Domů Procházet Nápověda
Registrovat se Přihlásit se
phyus
/
linux-vybrid_public
8
0
Rozštěpit 0
Soubory Úkoly 0 Pull Requesty 0 Wiki
Strom: 21c7075fa5
Větve Značky
linux-vybrid_pu...
/
arch
/
s390
/
kernel
/
reipl64.S

reipl64.S 3.2 KB
Historie Surový

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111 
  1. /*
    2. 

  2.  *    Copyright IBM Corp 2000,2009
    3. 

  3.  *    Author(s): Holger Smolinski <Holger.Smolinski@de.ibm.com>,
    4. 

  4.  *		 Denis Joseph Barrow,
    5. 

  5.  */
    6. 

  6. 

  7. #include <linux/linkage.h>
    8. 

  8. #include <asm/asm-offsets.h>
    9. 

  9. 

  10. #
    11. 

  11. # do_reipl_asm
    12. 

  12. # Parameter: r2 = schid of reipl device
    13. 

  13. #
    14. 

  14. 

  15. ENTRY(do_reipl_asm)
    16. 

  16. 		basr	%r13,0
    17. 

  17. .Lpg0:		lpswe	.Lnewpsw-.Lpg0(%r13)
    18. 

  18. .Lpg1:		# do store status of all registers
    19. 

  19. 

  20. 		stg	%r1,.Lregsave-.Lpg0(%r13)
    21. 

  21. 		lghi	%r1,0x1000
    22. 

  22. 		stmg	%r0,%r15,__LC_GPREGS_SAVE_AREA-0x1000(%r1)
    23. 

  23. 		lg	%r0,.Lregsave-.Lpg0(%r13)
    24. 

  24. 		stg	%r0,__LC_GPREGS_SAVE_AREA-0x1000+8(%r1)
    25. 

  25. 		stctg	%c0,%c15,__LC_CREGS_SAVE_AREA-0x1000(%r1)
    26. 

  26. 		stam	%a0,%a15,__LC_AREGS_SAVE_AREA-0x1000(%r1)
    27. 

  27. 		lg	%r10,.Ldump_pfx-.Lpg0(%r13)
    28. 

  28. 		mvc	__LC_PREFIX_SAVE_AREA-0x1000(4,%r1),0(%r10)
    29. 

  29. 		stfpc	__LC_FP_CREG_SAVE_AREA-0x1000(%r1)
    30. 

  30. 		stckc	.Lclkcmp-.Lpg0(%r13)
    31. 

  31. 		mvc	__LC_CLOCK_COMP_SAVE_AREA-0x1000(7,%r1),.Lclkcmp-.Lpg0(%r13)
    32. 

  32. 		stpt	__LC_CPU_TIMER_SAVE_AREA-0x1000(%r1)
    33. 

  33. 		stg	%r13, __LC_PSW_SAVE_AREA-0x1000+8(%r1)
    34. 

  34. 

  35. 		lctlg	%c6,%c6,.Lall-.Lpg0(%r13)
    36. 

  36. 		lgr	%r1,%r2
    37. 

  37. 		mvc	__LC_PGM_NEW_PSW(16),.Lpcnew-.Lpg0(%r13)
    38. 

  38. 		stsch	.Lschib-.Lpg0(%r13)
    39. 

  39. 		oi	.Lschib+5-.Lpg0(%r13),0x84
    40. 

  40. .Lecs:  	xi	.Lschib+27-.Lpg0(%r13),0x01
    41. 

  41. 		msch	.Lschib-.Lpg0(%r13)
    42. 

  42. 		lghi	%r0,5
    43. 

  43. .Lssch:		ssch	.Liplorb-.Lpg0(%r13)
    44. 

  44. 		jz	.L001
    45. 

  45. 		brct	%r0,.Lssch
    46. 

  46. 		bas	%r14,.Ldisab-.Lpg0(%r13)
    47. 

  47. .L001:		mvc	__LC_IO_NEW_PSW(16),.Lionew-.Lpg0(%r13)
    48. 

  48. .Ltpi:		lpswe	.Lwaitpsw-.Lpg0(%r13)
    49. 

  49. .Lcont:		c	%r1,__LC_SUBCHANNEL_ID
    50. 

  50. 		jnz	.Ltpi
    51. 

  51. 		clc	__LC_IO_INT_PARM(4),.Liplorb-.Lpg0(%r13)
    52. 

  52. 		jnz	.Ltpi
    53. 

  53. 		tsch	.Liplirb-.Lpg0(%r13)
    54. 

  54. 		tm	.Liplirb+9-.Lpg0(%r13),0xbf
    55. 

  55. 		jz	.L002
    56. 

  56. 		bas	%r14,.Ldisab-.Lpg0(%r13)
    57. 

  57. .L002:		tm	.Liplirb+8-.Lpg0(%r13),0xf3
    58. 

  58. 		jz	.L003
    59. 

  59. 		bas	%r14,.Ldisab-.Lpg0(%r13)
    60. 

  60. .L003:		st	%r1,__LC_SUBCHANNEL_ID
    61. 

  61. 		lhi	%r1,0		 # mode 0 = esa
    62. 

  62. 		slr	%r0,%r0 	 # set cpuid to zero
    63. 

  63. 		sigp	%r1,%r0,0x12	 # switch to esa mode
    64. 

  64. 		lpsw	0
    65. 

  65. .Ldisab:	sll	%r14,1
    66. 

  66. 		srl	%r14,1		 # need to kill hi bit to avoid specification exceptions.
    67. 

  67. 		st	%r14,.Ldispsw+12-.Lpg0(%r13)
    68. 

  68. 		lpswe	.Ldispsw-.Lpg0(%r13)
    69. 

  69. 		.align	8
    70. 

  70. .Lclkcmp:	.quad	0x0000000000000000
    71. 

  71. .Lall:		.quad	0x00000000ff000000
    72. 

  72. .Ldump_pfx:	.quad	dump_prefix_page
    73. 

  73. .Lregsave:	.quad	0x0000000000000000
    74. 

  74. 		.align	16
    75. 

  75. /*
    76. 

  76.  * These addresses have to be 31 bit otherwise
    77. 

  77.  * the sigp will throw a specifcation exception
    78. 

  78.  * when switching to ESA mode as bit 31 be set
    79. 

  79.  * in the ESA psw.
    80. 

  80.  * Bit 31 of the addresses has to be 0 for the
    81. 

  81.  * 31bit lpswe instruction a fact they appear to have
    82. 

  82.  * omitted from the pop.
    83. 

  83.  */
    84. 

  84. .Lnewpsw:	.quad	0x0000000080000000
    85. 

  85. 		.quad	.Lpg1
    86. 

  86. .Lpcnew:	.quad	0x0000000080000000
    87. 

  87. 		.quad	.Lecs
    88. 

  88. .Lionew:	.quad	0x0000000080000000
    89. 

  89. 		.quad	.Lcont
    90. 

  90. .Lwaitpsw:	.quad	0x0202000080000000
    91. 

  91. 		.quad	.Ltpi
    92. 

  92. .Ldispsw:	.quad	0x0002000080000000
    93. 

  93. 		.quad	0x0000000000000000
    94. 

  94. .Liplccws:	.long	0x02000000,0x60000018
    95. 

  95. 		.long	0x08000008,0x20000001
    96. 

  96. .Liplorb:	.long	0x0049504c,0x0040ff80
    97. 

  97. 		.long	0x00000000+.Liplccws
    98. 

  98. .Lschib:	.long	0x00000000,0x00000000
    99. 

  99. 		.long	0x00000000,0x00000000
    100. 

  100. 		.long	0x00000000,0x00000000
    101. 

  101. 		.long	0x00000000,0x00000000
    102. 

  102. 		.long	0x00000000,0x00000000
    103. 

  103. 		.long	0x00000000,0x00000000
    104. 

  104. .Liplirb:	.long	0x00000000,0x00000000
    105. 

  105. 		.long	0x00000000,0x00000000
    106. 

  106. 		.long	0x00000000,0x00000000
    107. 

  107. 		.long	0x00000000,0x00000000
    108. 

  108. 		.long	0x00000000,0x00000000
    109. 

  109. 		.long	0x00000000,0x00000000
    110. 

  110. 		.long	0x00000000,0x00000000
    111. 

  111. 		.long	0x00000000,0x00000000
    112.