rt2x00pci.c 12 KB

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  1. /*
  2. Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
  3. <http://rt2x00.serialmonkey.com>
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the
  14. Free Software Foundation, Inc.,
  15. 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  16. */
  17. /*
  18. Module: rt2x00pci
  19. Abstract: rt2x00 generic pci device routines.
  20. */
  21. #include <linux/dma-mapping.h>
  22. #include <linux/kernel.h>
  23. #include <linux/module.h>
  24. #include <linux/pci.h>
  25. #include "rt2x00.h"
  26. #include "rt2x00pci.h"
  27. /*
  28. * TX data handlers.
  29. */
  30. int rt2x00pci_write_tx_data(struct rt2x00_dev *rt2x00dev,
  31. struct data_queue *queue, struct sk_buff *skb,
  32. struct ieee80211_tx_control *control)
  33. {
  34. struct queue_entry *entry = rt2x00queue_get_entry(queue, Q_INDEX);
  35. struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
  36. struct skb_frame_desc *skbdesc;
  37. u32 word;
  38. if (rt2x00queue_full(queue))
  39. return -EINVAL;
  40. rt2x00_desc_read(priv_tx->desc, 0, &word);
  41. if (rt2x00_get_field32(word, TXD_ENTRY_OWNER_NIC) ||
  42. rt2x00_get_field32(word, TXD_ENTRY_VALID)) {
  43. ERROR(rt2x00dev,
  44. "Arrived at non-free entry in the non-full queue %d.\n"
  45. "Please file bug report to %s.\n",
  46. control->queue, DRV_PROJECT);
  47. return -EINVAL;
  48. }
  49. /*
  50. * Fill in skb descriptor
  51. */
  52. skbdesc = get_skb_frame_desc(skb);
  53. skbdesc->data = skb->data;
  54. skbdesc->data_len = skb->len;
  55. skbdesc->desc = priv_tx->desc;
  56. skbdesc->desc_len = queue->desc_size;
  57. skbdesc->entry = entry;
  58. memcpy(&priv_tx->control, control, sizeof(priv_tx->control));
  59. memcpy(priv_tx->data, skb->data, skb->len);
  60. rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
  61. rt2x00queue_index_inc(queue, Q_INDEX);
  62. return 0;
  63. }
  64. EXPORT_SYMBOL_GPL(rt2x00pci_write_tx_data);
  65. /*
  66. * TX/RX data handlers.
  67. */
  68. void rt2x00pci_rxdone(struct rt2x00_dev *rt2x00dev)
  69. {
  70. struct data_queue *queue = rt2x00dev->rx;
  71. struct queue_entry *entry;
  72. struct queue_entry_priv_pci_rx *priv_rx;
  73. struct ieee80211_hdr *hdr;
  74. struct skb_frame_desc *skbdesc;
  75. struct rxdone_entry_desc rxdesc;
  76. int header_size;
  77. int align;
  78. u32 word;
  79. while (1) {
  80. entry = rt2x00queue_get_entry(queue, Q_INDEX);
  81. priv_rx = entry->priv_data;
  82. rt2x00_desc_read(priv_rx->desc, 0, &word);
  83. if (rt2x00_get_field32(word, RXD_ENTRY_OWNER_NIC))
  84. break;
  85. memset(&rxdesc, 0, sizeof(rxdesc));
  86. rt2x00dev->ops->lib->fill_rxdone(entry, &rxdesc);
  87. hdr = (struct ieee80211_hdr *)priv_rx->data;
  88. header_size =
  89. ieee80211_get_hdrlen(le16_to_cpu(hdr->frame_control));
  90. /*
  91. * The data behind the ieee80211 header must be
  92. * aligned on a 4 byte boundary.
  93. */
  94. align = header_size % 4;
  95. /*
  96. * Allocate the sk_buffer, initialize it and copy
  97. * all data into it.
  98. */
  99. entry->skb = dev_alloc_skb(rxdesc.size + align);
  100. if (!entry->skb)
  101. return;
  102. skb_reserve(entry->skb, align);
  103. memcpy(skb_put(entry->skb, rxdesc.size),
  104. priv_rx->data, rxdesc.size);
  105. /*
  106. * Fill in skb descriptor
  107. */
  108. skbdesc = get_skb_frame_desc(entry->skb);
  109. memset(skbdesc, 0, sizeof(*skbdesc));
  110. skbdesc->data = entry->skb->data;
  111. skbdesc->data_len = entry->skb->len;
  112. skbdesc->desc = priv_rx->desc;
  113. skbdesc->desc_len = queue->desc_size;
  114. skbdesc->entry = entry;
  115. /*
  116. * Send the frame to rt2x00lib for further processing.
  117. */
  118. rt2x00lib_rxdone(entry, &rxdesc);
  119. if (test_bit(DEVICE_ENABLED_RADIO, &queue->rt2x00dev->flags)) {
  120. rt2x00_set_field32(&word, RXD_ENTRY_OWNER_NIC, 1);
  121. rt2x00_desc_write(priv_rx->desc, 0, word);
  122. }
  123. rt2x00queue_index_inc(queue, Q_INDEX);
  124. }
  125. }
  126. EXPORT_SYMBOL_GPL(rt2x00pci_rxdone);
  127. void rt2x00pci_txdone(struct rt2x00_dev *rt2x00dev, struct queue_entry *entry,
  128. struct txdone_entry_desc *txdesc)
  129. {
  130. struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
  131. u32 word;
  132. txdesc->control = &priv_tx->control;
  133. rt2x00lib_txdone(entry, txdesc);
  134. /*
  135. * Make this entry available for reuse.
  136. */
  137. entry->flags = 0;
  138. rt2x00_desc_read(priv_tx->desc, 0, &word);
  139. rt2x00_set_field32(&word, TXD_ENTRY_OWNER_NIC, 0);
  140. rt2x00_set_field32(&word, TXD_ENTRY_VALID, 0);
  141. rt2x00_desc_write(priv_tx->desc, 0, word);
  142. rt2x00queue_index_inc(entry->queue, Q_INDEX_DONE);
  143. /*
  144. * If the data queue was full before the txdone handler
  145. * we must make sure the packet queue in the mac80211 stack
  146. * is reenabled when the txdone handler has finished.
  147. */
  148. if (!rt2x00queue_full(entry->queue))
  149. ieee80211_wake_queue(rt2x00dev->hw, priv_tx->control.queue);
  150. }
  151. EXPORT_SYMBOL_GPL(rt2x00pci_txdone);
  152. /*
  153. * Device initialization handlers.
  154. */
  155. #define desc_size(__queue) \
  156. ({ \
  157. ((__queue)->limit * (__queue)->desc_size);\
  158. })
  159. #define data_size(__queue) \
  160. ({ \
  161. ((__queue)->limit * (__queue)->data_size);\
  162. })
  163. #define dma_size(__queue) \
  164. ({ \
  165. data_size(__queue) + desc_size(__queue);\
  166. })
  167. #define desc_offset(__queue, __base, __i) \
  168. ({ \
  169. (__base) + data_size(__queue) + \
  170. ((__i) * (__queue)->desc_size); \
  171. })
  172. #define data_offset(__queue, __base, __i) \
  173. ({ \
  174. (__base) + \
  175. ((__i) * (__queue)->data_size); \
  176. })
  177. static int rt2x00pci_alloc_queue_dma(struct rt2x00_dev *rt2x00dev,
  178. struct data_queue *queue)
  179. {
  180. struct pci_dev *pci_dev = rt2x00dev_pci(rt2x00dev);
  181. struct queue_entry_priv_pci_rx *priv_rx;
  182. struct queue_entry_priv_pci_tx *priv_tx;
  183. void *addr;
  184. dma_addr_t dma;
  185. void *desc_addr;
  186. dma_addr_t desc_dma;
  187. void *data_addr;
  188. dma_addr_t data_dma;
  189. unsigned int i;
  190. /*
  191. * Allocate DMA memory for descriptor and buffer.
  192. */
  193. addr = pci_alloc_consistent(pci_dev, dma_size(queue), &dma);
  194. if (!addr)
  195. return -ENOMEM;
  196. memset(addr, 0, dma_size(queue));
  197. /*
  198. * Initialize all queue entries to contain valid addresses.
  199. */
  200. for (i = 0; i < queue->limit; i++) {
  201. desc_addr = desc_offset(queue, addr, i);
  202. desc_dma = desc_offset(queue, dma, i);
  203. data_addr = data_offset(queue, addr, i);
  204. data_dma = data_offset(queue, dma, i);
  205. if (queue->qid == QID_RX) {
  206. priv_rx = queue->entries[i].priv_data;
  207. priv_rx->desc = desc_addr;
  208. priv_rx->desc_dma = desc_dma;
  209. priv_rx->data = data_addr;
  210. priv_rx->data_dma = data_dma;
  211. } else {
  212. priv_tx = queue->entries[i].priv_data;
  213. priv_tx->desc = desc_addr;
  214. priv_tx->desc_dma = desc_dma;
  215. priv_tx->data = data_addr;
  216. priv_tx->data_dma = data_dma;
  217. }
  218. }
  219. return 0;
  220. }
  221. static void rt2x00pci_free_queue_dma(struct rt2x00_dev *rt2x00dev,
  222. struct data_queue *queue)
  223. {
  224. struct pci_dev *pci_dev = rt2x00dev_pci(rt2x00dev);
  225. struct queue_entry_priv_pci_rx *priv_rx;
  226. struct queue_entry_priv_pci_tx *priv_tx;
  227. void *data_addr;
  228. dma_addr_t data_dma;
  229. if (queue->qid == QID_RX) {
  230. priv_rx = queue->entries[0].priv_data;
  231. data_addr = priv_rx->data;
  232. data_dma = priv_rx->data_dma;
  233. priv_rx->data = NULL;
  234. } else {
  235. priv_tx = queue->entries[0].priv_data;
  236. data_addr = priv_tx->data;
  237. data_dma = priv_tx->data_dma;
  238. priv_tx->data = NULL;
  239. }
  240. if (data_addr)
  241. pci_free_consistent(pci_dev, dma_size(queue),
  242. data_addr, data_dma);
  243. }
  244. int rt2x00pci_initialize(struct rt2x00_dev *rt2x00dev)
  245. {
  246. struct pci_dev *pci_dev = rt2x00dev_pci(rt2x00dev);
  247. struct data_queue *queue;
  248. int status;
  249. /*
  250. * Allocate DMA
  251. */
  252. queue_for_each(rt2x00dev, queue) {
  253. status = rt2x00pci_alloc_queue_dma(rt2x00dev, queue);
  254. if (status)
  255. goto exit;
  256. }
  257. /*
  258. * Register interrupt handler.
  259. */
  260. status = request_irq(pci_dev->irq, rt2x00dev->ops->lib->irq_handler,
  261. IRQF_SHARED, pci_name(pci_dev), rt2x00dev);
  262. if (status) {
  263. ERROR(rt2x00dev, "IRQ %d allocation failed (error %d).\n",
  264. pci_dev->irq, status);
  265. return status;
  266. }
  267. return 0;
  268. exit:
  269. rt2x00pci_uninitialize(rt2x00dev);
  270. return status;
  271. }
  272. EXPORT_SYMBOL_GPL(rt2x00pci_initialize);
  273. void rt2x00pci_uninitialize(struct rt2x00_dev *rt2x00dev)
  274. {
  275. struct data_queue *queue;
  276. /*
  277. * Free irq line.
  278. */
  279. free_irq(rt2x00dev_pci(rt2x00dev)->irq, rt2x00dev);
  280. /*
  281. * Free DMA
  282. */
  283. queue_for_each(rt2x00dev, queue)
  284. rt2x00pci_free_queue_dma(rt2x00dev, queue);
  285. }
  286. EXPORT_SYMBOL_GPL(rt2x00pci_uninitialize);
  287. /*
  288. * PCI driver handlers.
  289. */
  290. static void rt2x00pci_free_reg(struct rt2x00_dev *rt2x00dev)
  291. {
  292. kfree(rt2x00dev->rf);
  293. rt2x00dev->rf = NULL;
  294. kfree(rt2x00dev->eeprom);
  295. rt2x00dev->eeprom = NULL;
  296. if (rt2x00dev->csr.base) {
  297. iounmap(rt2x00dev->csr.base);
  298. rt2x00dev->csr.base = NULL;
  299. }
  300. }
  301. static int rt2x00pci_alloc_reg(struct rt2x00_dev *rt2x00dev)
  302. {
  303. struct pci_dev *pci_dev = rt2x00dev_pci(rt2x00dev);
  304. rt2x00dev->csr.base = ioremap(pci_resource_start(pci_dev, 0),
  305. pci_resource_len(pci_dev, 0));
  306. if (!rt2x00dev->csr.base)
  307. goto exit;
  308. rt2x00dev->eeprom = kzalloc(rt2x00dev->ops->eeprom_size, GFP_KERNEL);
  309. if (!rt2x00dev->eeprom)
  310. goto exit;
  311. rt2x00dev->rf = kzalloc(rt2x00dev->ops->rf_size, GFP_KERNEL);
  312. if (!rt2x00dev->rf)
  313. goto exit;
  314. return 0;
  315. exit:
  316. ERROR_PROBE("Failed to allocate registers.\n");
  317. rt2x00pci_free_reg(rt2x00dev);
  318. return -ENOMEM;
  319. }
  320. int rt2x00pci_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
  321. {
  322. struct rt2x00_ops *ops = (struct rt2x00_ops *)id->driver_data;
  323. struct ieee80211_hw *hw;
  324. struct rt2x00_dev *rt2x00dev;
  325. int retval;
  326. retval = pci_request_regions(pci_dev, pci_name(pci_dev));
  327. if (retval) {
  328. ERROR_PROBE("PCI request regions failed.\n");
  329. return retval;
  330. }
  331. retval = pci_enable_device(pci_dev);
  332. if (retval) {
  333. ERROR_PROBE("Enable device failed.\n");
  334. goto exit_release_regions;
  335. }
  336. pci_set_master(pci_dev);
  337. if (pci_set_mwi(pci_dev))
  338. ERROR_PROBE("MWI not available.\n");
  339. if (pci_set_dma_mask(pci_dev, DMA_64BIT_MASK) &&
  340. pci_set_dma_mask(pci_dev, DMA_32BIT_MASK)) {
  341. ERROR_PROBE("PCI DMA not supported.\n");
  342. retval = -EIO;
  343. goto exit_disable_device;
  344. }
  345. hw = ieee80211_alloc_hw(sizeof(struct rt2x00_dev), ops->hw);
  346. if (!hw) {
  347. ERROR_PROBE("Failed to allocate hardware.\n");
  348. retval = -ENOMEM;
  349. goto exit_disable_device;
  350. }
  351. pci_set_drvdata(pci_dev, hw);
  352. rt2x00dev = hw->priv;
  353. rt2x00dev->dev = pci_dev;
  354. rt2x00dev->ops = ops;
  355. rt2x00dev->hw = hw;
  356. retval = rt2x00pci_alloc_reg(rt2x00dev);
  357. if (retval)
  358. goto exit_free_device;
  359. retval = rt2x00lib_probe_dev(rt2x00dev);
  360. if (retval)
  361. goto exit_free_reg;
  362. return 0;
  363. exit_free_reg:
  364. rt2x00pci_free_reg(rt2x00dev);
  365. exit_free_device:
  366. ieee80211_free_hw(hw);
  367. exit_disable_device:
  368. if (retval != -EBUSY)
  369. pci_disable_device(pci_dev);
  370. exit_release_regions:
  371. pci_release_regions(pci_dev);
  372. pci_set_drvdata(pci_dev, NULL);
  373. return retval;
  374. }
  375. EXPORT_SYMBOL_GPL(rt2x00pci_probe);
  376. void rt2x00pci_remove(struct pci_dev *pci_dev)
  377. {
  378. struct ieee80211_hw *hw = pci_get_drvdata(pci_dev);
  379. struct rt2x00_dev *rt2x00dev = hw->priv;
  380. /*
  381. * Free all allocated data.
  382. */
  383. rt2x00lib_remove_dev(rt2x00dev);
  384. rt2x00pci_free_reg(rt2x00dev);
  385. ieee80211_free_hw(hw);
  386. /*
  387. * Free the PCI device data.
  388. */
  389. pci_set_drvdata(pci_dev, NULL);
  390. pci_disable_device(pci_dev);
  391. pci_release_regions(pci_dev);
  392. }
  393. EXPORT_SYMBOL_GPL(rt2x00pci_remove);
  394. #ifdef CONFIG_PM
  395. int rt2x00pci_suspend(struct pci_dev *pci_dev, pm_message_t state)
  396. {
  397. struct ieee80211_hw *hw = pci_get_drvdata(pci_dev);
  398. struct rt2x00_dev *rt2x00dev = hw->priv;
  399. int retval;
  400. retval = rt2x00lib_suspend(rt2x00dev, state);
  401. if (retval)
  402. return retval;
  403. rt2x00pci_free_reg(rt2x00dev);
  404. pci_save_state(pci_dev);
  405. pci_disable_device(pci_dev);
  406. return pci_set_power_state(pci_dev, pci_choose_state(pci_dev, state));
  407. }
  408. EXPORT_SYMBOL_GPL(rt2x00pci_suspend);
  409. int rt2x00pci_resume(struct pci_dev *pci_dev)
  410. {
  411. struct ieee80211_hw *hw = pci_get_drvdata(pci_dev);
  412. struct rt2x00_dev *rt2x00dev = hw->priv;
  413. int retval;
  414. if (pci_set_power_state(pci_dev, PCI_D0) ||
  415. pci_enable_device(pci_dev) ||
  416. pci_restore_state(pci_dev)) {
  417. ERROR(rt2x00dev, "Failed to resume device.\n");
  418. return -EIO;
  419. }
  420. retval = rt2x00pci_alloc_reg(rt2x00dev);
  421. if (retval)
  422. return retval;
  423. retval = rt2x00lib_resume(rt2x00dev);
  424. if (retval)
  425. goto exit_free_reg;
  426. return 0;
  427. exit_free_reg:
  428. rt2x00pci_free_reg(rt2x00dev);
  429. return retval;
  430. }
  431. EXPORT_SYMBOL_GPL(rt2x00pci_resume);
  432. #endif /* CONFIG_PM */
  433. /*
  434. * rt2x00pci module information.
  435. */
  436. MODULE_AUTHOR(DRV_PROJECT);
  437. MODULE_VERSION(DRV_VERSION);
  438. MODULE_DESCRIPTION("rt2x00 pci library");
  439. MODULE_LICENSE("GPL");