ak4642.c 13 KB

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  1. /*
  2. * ak4642.c -- AK4642/AK4643 ALSA Soc Audio driver
  3. *
  4. * Copyright (C) 2009 Renesas Solutions Corp.
  5. * Kuninori Morimoto <morimoto.kuninori@renesas.com>
  6. *
  7. * Based on wm8731.c by Richard Purdie
  8. * Based on ak4535.c by Richard Purdie
  9. * Based on wm8753.c by Liam Girdwood
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. */
  15. /* ** CAUTION **
  16. *
  17. * This is very simple driver.
  18. * It can use headphone output / stereo input only
  19. *
  20. * AK4642 is tested.
  21. * AK4643 is tested.
  22. * AK4648 is tested.
  23. */
  24. #include <linux/delay.h>
  25. #include <linux/i2c.h>
  26. #include <linux/slab.h>
  27. #include <linux/module.h>
  28. #include <sound/soc.h>
  29. #include <sound/initval.h>
  30. #include <sound/tlv.h>
  31. #define PW_MGMT1 0x00
  32. #define PW_MGMT2 0x01
  33. #define SG_SL1 0x02
  34. #define SG_SL2 0x03
  35. #define MD_CTL1 0x04
  36. #define MD_CTL2 0x05
  37. #define TIMER 0x06
  38. #define ALC_CTL1 0x07
  39. #define ALC_CTL2 0x08
  40. #define L_IVC 0x09
  41. #define L_DVC 0x0a
  42. #define ALC_CTL3 0x0b
  43. #define R_IVC 0x0c
  44. #define R_DVC 0x0d
  45. #define MD_CTL3 0x0e
  46. #define MD_CTL4 0x0f
  47. #define PW_MGMT3 0x10
  48. #define DF_S 0x11
  49. #define FIL3_0 0x12
  50. #define FIL3_1 0x13
  51. #define FIL3_2 0x14
  52. #define FIL3_3 0x15
  53. #define EQ_0 0x16
  54. #define EQ_1 0x17
  55. #define EQ_2 0x18
  56. #define EQ_3 0x19
  57. #define EQ_4 0x1a
  58. #define EQ_5 0x1b
  59. #define FIL1_0 0x1c
  60. #define FIL1_1 0x1d
  61. #define FIL1_2 0x1e
  62. #define FIL1_3 0x1f
  63. #define PW_MGMT4 0x20
  64. #define MD_CTL5 0x21
  65. #define LO_MS 0x22
  66. #define HP_MS 0x23
  67. #define SPK_MS 0x24
  68. /* PW_MGMT1*/
  69. #define PMVCM (1 << 6) /* VCOM Power Management */
  70. #define PMMIN (1 << 5) /* MIN Input Power Management */
  71. #define PMDAC (1 << 2) /* DAC Power Management */
  72. #define PMADL (1 << 0) /* MIC Amp Lch and ADC Lch Power Management */
  73. /* PW_MGMT2 */
  74. #define HPMTN (1 << 6)
  75. #define PMHPL (1 << 5)
  76. #define PMHPR (1 << 4)
  77. #define MS (1 << 3) /* master/slave select */
  78. #define MCKO (1 << 1)
  79. #define PMPLL (1 << 0)
  80. #define PMHP_MASK (PMHPL | PMHPR)
  81. #define PMHP PMHP_MASK
  82. /* PW_MGMT3 */
  83. #define PMADR (1 << 0) /* MIC L / ADC R Power Management */
  84. /* SG_SL1 */
  85. #define MINS (1 << 6) /* Switch from MIN to Speaker */
  86. #define DACL (1 << 4) /* Switch from DAC to Stereo or Receiver */
  87. #define PMMP (1 << 2) /* MPWR pin Power Management */
  88. #define MGAIN0 (1 << 0) /* MIC amp gain*/
  89. /* TIMER */
  90. #define ZTM(param) ((param & 0x3) << 4) /* ALC Zoro Crossing TimeOut */
  91. #define WTM(param) (((param & 0x4) << 4) | ((param & 0x3) << 2))
  92. /* ALC_CTL1 */
  93. #define ALC (1 << 5) /* ALC Enable */
  94. #define LMTH0 (1 << 0) /* ALC Limiter / Recovery Level */
  95. /* MD_CTL1 */
  96. #define PLL3 (1 << 7)
  97. #define PLL2 (1 << 6)
  98. #define PLL1 (1 << 5)
  99. #define PLL0 (1 << 4)
  100. #define PLL_MASK (PLL3 | PLL2 | PLL1 | PLL0)
  101. #define BCKO_MASK (1 << 3)
  102. #define BCKO_64 BCKO_MASK
  103. #define DIF_MASK (3 << 0)
  104. #define DSP (0 << 0)
  105. #define RIGHT_J (1 << 0)
  106. #define LEFT_J (2 << 0)
  107. #define I2S (3 << 0)
  108. /* MD_CTL2 */
  109. #define FS0 (1 << 0)
  110. #define FS1 (1 << 1)
  111. #define FS2 (1 << 2)
  112. #define FS3 (1 << 5)
  113. #define FS_MASK (FS0 | FS1 | FS2 | FS3)
  114. /* MD_CTL3 */
  115. #define BST1 (1 << 3)
  116. /* MD_CTL4 */
  117. #define DACH (1 << 0)
  118. /*
  119. * Playback Volume (table 39)
  120. *
  121. * max : 0x00 : +12.0 dB
  122. * ( 0.5 dB step )
  123. * min : 0xFE : -115.0 dB
  124. * mute: 0xFF
  125. */
  126. static const DECLARE_TLV_DB_SCALE(out_tlv, -11500, 50, 1);
  127. static const struct snd_kcontrol_new ak4642_snd_controls[] = {
  128. SOC_DOUBLE_R_TLV("Digital Playback Volume", L_DVC, R_DVC,
  129. 0, 0xFF, 1, out_tlv),
  130. };
  131. static const struct snd_kcontrol_new ak4642_headphone_control =
  132. SOC_DAPM_SINGLE("Switch", PW_MGMT2, 6, 1, 0);
  133. static const struct snd_kcontrol_new ak4642_lout_mixer_controls[] = {
  134. SOC_DAPM_SINGLE("DACL", SG_SL1, 4, 1, 0),
  135. };
  136. static const struct snd_soc_dapm_widget ak4642_dapm_widgets[] = {
  137. /* Outputs */
  138. SND_SOC_DAPM_OUTPUT("HPOUTL"),
  139. SND_SOC_DAPM_OUTPUT("HPOUTR"),
  140. SND_SOC_DAPM_OUTPUT("LINEOUT"),
  141. SND_SOC_DAPM_PGA("HPL Out", PW_MGMT2, 5, 0, NULL, 0),
  142. SND_SOC_DAPM_PGA("HPR Out", PW_MGMT2, 4, 0, NULL, 0),
  143. SND_SOC_DAPM_SWITCH("Headphone Enable", SND_SOC_NOPM, 0, 0,
  144. &ak4642_headphone_control),
  145. SND_SOC_DAPM_PGA("DACH", MD_CTL4, 0, 0, NULL, 0),
  146. SND_SOC_DAPM_MIXER("LINEOUT Mixer", PW_MGMT1, 3, 0,
  147. &ak4642_lout_mixer_controls[0],
  148. ARRAY_SIZE(ak4642_lout_mixer_controls)),
  149. /* DAC */
  150. SND_SOC_DAPM_DAC("DAC", "HiFi Playback", PW_MGMT1, 2, 0),
  151. };
  152. static const struct snd_soc_dapm_route ak4642_intercon[] = {
  153. /* Outputs */
  154. {"HPOUTL", NULL, "HPL Out"},
  155. {"HPOUTR", NULL, "HPR Out"},
  156. {"LINEOUT", NULL, "LINEOUT Mixer"},
  157. {"HPL Out", NULL, "Headphone Enable"},
  158. {"HPR Out", NULL, "Headphone Enable"},
  159. {"Headphone Enable", "Switch", "DACH"},
  160. {"DACH", NULL, "DAC"},
  161. {"LINEOUT Mixer", "DACL", "DAC"},
  162. };
  163. /* codec private data */
  164. struct ak4642_priv {
  165. unsigned int sysclk;
  166. enum snd_soc_control_type control_type;
  167. };
  168. /*
  169. * ak4642 register cache
  170. */
  171. static const u8 ak4642_reg[] = {
  172. 0x00, 0x00, 0x01, 0x00,
  173. 0x02, 0x00, 0x00, 0x00,
  174. 0xe1, 0xe1, 0x18, 0x00,
  175. 0xe1, 0x18, 0x11, 0x08,
  176. 0x00, 0x00, 0x00, 0x00,
  177. 0x00, 0x00, 0x00, 0x00,
  178. 0x00, 0x00, 0x00, 0x00,
  179. 0x00, 0x00, 0x00, 0x00,
  180. 0x00, 0x00, 0x00, 0x00,
  181. 0x00,
  182. };
  183. static const u8 ak4648_reg[] = {
  184. 0x00, 0x00, 0x01, 0x00,
  185. 0x02, 0x00, 0x00, 0x00,
  186. 0xe1, 0xe1, 0x18, 0x00,
  187. 0xe1, 0x18, 0x11, 0xb8,
  188. 0x00, 0x00, 0x00, 0x00,
  189. 0x00, 0x00, 0x00, 0x00,
  190. 0x00, 0x00, 0x00, 0x00,
  191. 0x00, 0x00, 0x00, 0x00,
  192. 0x00, 0x00, 0x00, 0x00,
  193. 0x00, 0x88, 0x88, 0x08,
  194. };
  195. static int ak4642_dai_startup(struct snd_pcm_substream *substream,
  196. struct snd_soc_dai *dai)
  197. {
  198. int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
  199. struct snd_soc_codec *codec = dai->codec;
  200. if (is_play) {
  201. /*
  202. * start headphone output
  203. *
  204. * PLL, Master Mode
  205. * Audio I/F Format :MSB justified (ADC & DAC)
  206. * Bass Boost Level : Middle
  207. *
  208. * This operation came from example code of
  209. * "ASAHI KASEI AK4642" (japanese) manual p97.
  210. */
  211. snd_soc_write(codec, L_IVC, 0x91); /* volume */
  212. snd_soc_write(codec, R_IVC, 0x91); /* volume */
  213. } else {
  214. /*
  215. * start stereo input
  216. *
  217. * PLL Master Mode
  218. * Audio I/F Format:MSB justified (ADC & DAC)
  219. * Pre MIC AMP:+20dB
  220. * MIC Power On
  221. * ALC setting:Refer to Table 35
  222. * ALC bit=“1”
  223. *
  224. * This operation came from example code of
  225. * "ASAHI KASEI AK4642" (japanese) manual p94.
  226. */
  227. snd_soc_write(codec, SG_SL1, PMMP | MGAIN0);
  228. snd_soc_write(codec, TIMER, ZTM(0x3) | WTM(0x3));
  229. snd_soc_write(codec, ALC_CTL1, ALC | LMTH0);
  230. snd_soc_update_bits(codec, PW_MGMT1, PMADL, PMADL);
  231. snd_soc_update_bits(codec, PW_MGMT3, PMADR, PMADR);
  232. }
  233. return 0;
  234. }
  235. static void ak4642_dai_shutdown(struct snd_pcm_substream *substream,
  236. struct snd_soc_dai *dai)
  237. {
  238. int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
  239. struct snd_soc_codec *codec = dai->codec;
  240. if (is_play) {
  241. } else {
  242. /* stop stereo input */
  243. snd_soc_update_bits(codec, PW_MGMT1, PMADL, 0);
  244. snd_soc_update_bits(codec, PW_MGMT3, PMADR, 0);
  245. snd_soc_update_bits(codec, ALC_CTL1, ALC, 0);
  246. }
  247. }
  248. static int ak4642_dai_set_sysclk(struct snd_soc_dai *codec_dai,
  249. int clk_id, unsigned int freq, int dir)
  250. {
  251. struct snd_soc_codec *codec = codec_dai->codec;
  252. u8 pll;
  253. switch (freq) {
  254. case 11289600:
  255. pll = PLL2;
  256. break;
  257. case 12288000:
  258. pll = PLL2 | PLL0;
  259. break;
  260. case 12000000:
  261. pll = PLL2 | PLL1;
  262. break;
  263. case 24000000:
  264. pll = PLL2 | PLL1 | PLL0;
  265. break;
  266. case 13500000:
  267. pll = PLL3 | PLL2;
  268. break;
  269. case 27000000:
  270. pll = PLL3 | PLL2 | PLL0;
  271. break;
  272. default:
  273. return -EINVAL;
  274. }
  275. snd_soc_update_bits(codec, MD_CTL1, PLL_MASK, pll);
  276. return 0;
  277. }
  278. static int ak4642_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  279. {
  280. struct snd_soc_codec *codec = dai->codec;
  281. u8 data;
  282. u8 bcko;
  283. data = MCKO | PMPLL; /* use MCKO */
  284. bcko = 0;
  285. /* set master/slave audio interface */
  286. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  287. case SND_SOC_DAIFMT_CBM_CFM:
  288. data |= MS;
  289. bcko = BCKO_64;
  290. break;
  291. case SND_SOC_DAIFMT_CBS_CFS:
  292. break;
  293. default:
  294. return -EINVAL;
  295. }
  296. snd_soc_update_bits(codec, PW_MGMT2, MS | MCKO | PMPLL, data);
  297. snd_soc_update_bits(codec, MD_CTL1, BCKO_MASK, bcko);
  298. /* format type */
  299. data = 0;
  300. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  301. case SND_SOC_DAIFMT_LEFT_J:
  302. data = LEFT_J;
  303. break;
  304. case SND_SOC_DAIFMT_I2S:
  305. data = I2S;
  306. break;
  307. /* FIXME
  308. * Please add RIGHT_J / DSP support here
  309. */
  310. default:
  311. return -EINVAL;
  312. break;
  313. }
  314. snd_soc_update_bits(codec, MD_CTL1, DIF_MASK, data);
  315. return 0;
  316. }
  317. static int ak4642_dai_hw_params(struct snd_pcm_substream *substream,
  318. struct snd_pcm_hw_params *params,
  319. struct snd_soc_dai *dai)
  320. {
  321. struct snd_soc_codec *codec = dai->codec;
  322. u8 rate;
  323. switch (params_rate(params)) {
  324. case 7350:
  325. rate = FS2;
  326. break;
  327. case 8000:
  328. rate = 0;
  329. break;
  330. case 11025:
  331. rate = FS2 | FS0;
  332. break;
  333. case 12000:
  334. rate = FS0;
  335. break;
  336. case 14700:
  337. rate = FS2 | FS1;
  338. break;
  339. case 16000:
  340. rate = FS1;
  341. break;
  342. case 22050:
  343. rate = FS2 | FS1 | FS0;
  344. break;
  345. case 24000:
  346. rate = FS1 | FS0;
  347. break;
  348. case 29400:
  349. rate = FS3 | FS2 | FS1;
  350. break;
  351. case 32000:
  352. rate = FS3 | FS1;
  353. break;
  354. case 44100:
  355. rate = FS3 | FS2 | FS1 | FS0;
  356. break;
  357. case 48000:
  358. rate = FS3 | FS1 | FS0;
  359. break;
  360. default:
  361. return -EINVAL;
  362. break;
  363. }
  364. snd_soc_update_bits(codec, MD_CTL2, FS_MASK, rate);
  365. return 0;
  366. }
  367. static int ak4642_set_bias_level(struct snd_soc_codec *codec,
  368. enum snd_soc_bias_level level)
  369. {
  370. switch (level) {
  371. case SND_SOC_BIAS_OFF:
  372. snd_soc_write(codec, PW_MGMT1, 0x00);
  373. break;
  374. default:
  375. snd_soc_update_bits(codec, PW_MGMT1, PMVCM, PMVCM);
  376. break;
  377. }
  378. codec->dapm.bias_level = level;
  379. return 0;
  380. }
  381. static const struct snd_soc_dai_ops ak4642_dai_ops = {
  382. .startup = ak4642_dai_startup,
  383. .shutdown = ak4642_dai_shutdown,
  384. .set_sysclk = ak4642_dai_set_sysclk,
  385. .set_fmt = ak4642_dai_set_fmt,
  386. .hw_params = ak4642_dai_hw_params,
  387. };
  388. static struct snd_soc_dai_driver ak4642_dai = {
  389. .name = "ak4642-hifi",
  390. .playback = {
  391. .stream_name = "Playback",
  392. .channels_min = 1,
  393. .channels_max = 2,
  394. .rates = SNDRV_PCM_RATE_8000_48000,
  395. .formats = SNDRV_PCM_FMTBIT_S16_LE },
  396. .capture = {
  397. .stream_name = "Capture",
  398. .channels_min = 1,
  399. .channels_max = 2,
  400. .rates = SNDRV_PCM_RATE_8000_48000,
  401. .formats = SNDRV_PCM_FMTBIT_S16_LE },
  402. .ops = &ak4642_dai_ops,
  403. .symmetric_rates = 1,
  404. };
  405. static int ak4642_resume(struct snd_soc_codec *codec)
  406. {
  407. snd_soc_cache_sync(codec);
  408. return 0;
  409. }
  410. static int ak4642_probe(struct snd_soc_codec *codec)
  411. {
  412. struct ak4642_priv *ak4642 = snd_soc_codec_get_drvdata(codec);
  413. int ret;
  414. ret = snd_soc_codec_set_cache_io(codec, 8, 8, ak4642->control_type);
  415. if (ret < 0) {
  416. dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
  417. return ret;
  418. }
  419. snd_soc_add_controls(codec, ak4642_snd_controls,
  420. ARRAY_SIZE(ak4642_snd_controls));
  421. ak4642_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  422. return 0;
  423. }
  424. static int ak4642_remove(struct snd_soc_codec *codec)
  425. {
  426. ak4642_set_bias_level(codec, SND_SOC_BIAS_OFF);
  427. return 0;
  428. }
  429. static struct snd_soc_codec_driver soc_codec_dev_ak4642 = {
  430. .probe = ak4642_probe,
  431. .remove = ak4642_remove,
  432. .resume = ak4642_resume,
  433. .set_bias_level = ak4642_set_bias_level,
  434. .reg_cache_default = ak4642_reg, /* ak4642 reg */
  435. .reg_cache_size = ARRAY_SIZE(ak4642_reg), /* ak4642 reg */
  436. .reg_word_size = sizeof(u8),
  437. .dapm_widgets = ak4642_dapm_widgets,
  438. .num_dapm_widgets = ARRAY_SIZE(ak4642_dapm_widgets),
  439. .dapm_routes = ak4642_intercon,
  440. .num_dapm_routes = ARRAY_SIZE(ak4642_intercon),
  441. };
  442. static struct snd_soc_codec_driver soc_codec_dev_ak4648 = {
  443. .probe = ak4642_probe,
  444. .remove = ak4642_remove,
  445. .resume = ak4642_resume,
  446. .set_bias_level = ak4642_set_bias_level,
  447. .reg_cache_default = ak4648_reg, /* ak4648 reg */
  448. .reg_cache_size = ARRAY_SIZE(ak4648_reg), /* ak4648 reg */
  449. .reg_word_size = sizeof(u8),
  450. .dapm_widgets = ak4642_dapm_widgets,
  451. .num_dapm_widgets = ARRAY_SIZE(ak4642_dapm_widgets),
  452. .dapm_routes = ak4642_intercon,
  453. .num_dapm_routes = ARRAY_SIZE(ak4642_intercon),
  454. };
  455. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  456. static __devinit int ak4642_i2c_probe(struct i2c_client *i2c,
  457. const struct i2c_device_id *id)
  458. {
  459. struct ak4642_priv *ak4642;
  460. int ret;
  461. ak4642 = devm_kzalloc(&i2c->dev, sizeof(struct ak4642_priv),
  462. GFP_KERNEL);
  463. if (!ak4642)
  464. return -ENOMEM;
  465. i2c_set_clientdata(i2c, ak4642);
  466. ak4642->control_type = SND_SOC_I2C;
  467. ret = snd_soc_register_codec(&i2c->dev,
  468. (struct snd_soc_codec_driver *)id->driver_data,
  469. &ak4642_dai, 1);
  470. return ret;
  471. }
  472. static __devexit int ak4642_i2c_remove(struct i2c_client *client)
  473. {
  474. snd_soc_unregister_codec(&client->dev);
  475. return 0;
  476. }
  477. static const struct i2c_device_id ak4642_i2c_id[] = {
  478. { "ak4642", (kernel_ulong_t)&soc_codec_dev_ak4642 },
  479. { "ak4643", (kernel_ulong_t)&soc_codec_dev_ak4642 },
  480. { "ak4648", (kernel_ulong_t)&soc_codec_dev_ak4648 },
  481. { }
  482. };
  483. MODULE_DEVICE_TABLE(i2c, ak4642_i2c_id);
  484. static struct i2c_driver ak4642_i2c_driver = {
  485. .driver = {
  486. .name = "ak4642-codec",
  487. .owner = THIS_MODULE,
  488. },
  489. .probe = ak4642_i2c_probe,
  490. .remove = __devexit_p(ak4642_i2c_remove),
  491. .id_table = ak4642_i2c_id,
  492. };
  493. #endif
  494. static int __init ak4642_modinit(void)
  495. {
  496. int ret = 0;
  497. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  498. ret = i2c_add_driver(&ak4642_i2c_driver);
  499. #endif
  500. return ret;
  501. }
  502. module_init(ak4642_modinit);
  503. static void __exit ak4642_exit(void)
  504. {
  505. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  506. i2c_del_driver(&ak4642_i2c_driver);
  507. #endif
  508. }
  509. module_exit(ak4642_exit);
  510. MODULE_DESCRIPTION("Soc AK4642 driver");
  511. MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
  512. MODULE_LICENSE("GPL");