mv_otg.c 22 KB

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  1. /*
  2. * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
  3. * Author: Chao Xie <chao.xie@marvell.com>
  4. * Neil Zhang <zhangwm@marvell.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. #include <linux/module.h>
  12. #include <linux/kernel.h>
  13. #include <linux/init.h>
  14. #include <linux/io.h>
  15. #include <linux/uaccess.h>
  16. #include <linux/device.h>
  17. #include <linux/proc_fs.h>
  18. #include <linux/clk.h>
  19. #include <linux/workqueue.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/usb.h>
  22. #include <linux/usb/ch9.h>
  23. #include <linux/usb/otg.h>
  24. #include <linux/usb/gadget.h>
  25. #include <linux/usb/hcd.h>
  26. #include <linux/platform_data/mv_usb.h>
  27. #include "mv_otg.h"
  28. #define DRIVER_DESC "Marvell USB OTG transceiver driver"
  29. #define DRIVER_VERSION "Jan 20, 2010"
  30. MODULE_DESCRIPTION(DRIVER_DESC);
  31. MODULE_VERSION(DRIVER_VERSION);
  32. MODULE_LICENSE("GPL");
  33. static const char driver_name[] = "mv-otg";
  34. static char *state_string[] = {
  35. "undefined",
  36. "b_idle",
  37. "b_srp_init",
  38. "b_peripheral",
  39. "b_wait_acon",
  40. "b_host",
  41. "a_idle",
  42. "a_wait_vrise",
  43. "a_wait_bcon",
  44. "a_host",
  45. "a_suspend",
  46. "a_peripheral",
  47. "a_wait_vfall",
  48. "a_vbus_err"
  49. };
  50. static int mv_otg_set_vbus(struct otg_transceiver *otg, bool on)
  51. {
  52. struct mv_otg *mvotg = container_of(otg, struct mv_otg, otg);
  53. if (mvotg->pdata->set_vbus == NULL)
  54. return -ENODEV;
  55. return mvotg->pdata->set_vbus(on);
  56. }
  57. static int mv_otg_set_host(struct otg_transceiver *otg,
  58. struct usb_bus *host)
  59. {
  60. otg->host = host;
  61. return 0;
  62. }
  63. static int mv_otg_set_peripheral(struct otg_transceiver *otg,
  64. struct usb_gadget *gadget)
  65. {
  66. otg->gadget = gadget;
  67. return 0;
  68. }
  69. static void mv_otg_run_state_machine(struct mv_otg *mvotg,
  70. unsigned long delay)
  71. {
  72. dev_dbg(&mvotg->pdev->dev, "transceiver is updated\n");
  73. if (!mvotg->qwork)
  74. return;
  75. queue_delayed_work(mvotg->qwork, &mvotg->work, delay);
  76. }
  77. static void mv_otg_timer_await_bcon(unsigned long data)
  78. {
  79. struct mv_otg *mvotg = (struct mv_otg *) data;
  80. mvotg->otg_ctrl.a_wait_bcon_timeout = 1;
  81. dev_info(&mvotg->pdev->dev, "B Device No Response!\n");
  82. if (spin_trylock(&mvotg->wq_lock)) {
  83. mv_otg_run_state_machine(mvotg, 0);
  84. spin_unlock(&mvotg->wq_lock);
  85. }
  86. }
  87. static int mv_otg_cancel_timer(struct mv_otg *mvotg, unsigned int id)
  88. {
  89. struct timer_list *timer;
  90. if (id >= OTG_TIMER_NUM)
  91. return -EINVAL;
  92. timer = &mvotg->otg_ctrl.timer[id];
  93. if (timer_pending(timer))
  94. del_timer(timer);
  95. return 0;
  96. }
  97. static int mv_otg_set_timer(struct mv_otg *mvotg, unsigned int id,
  98. unsigned long interval,
  99. void (*callback) (unsigned long))
  100. {
  101. struct timer_list *timer;
  102. if (id >= OTG_TIMER_NUM)
  103. return -EINVAL;
  104. timer = &mvotg->otg_ctrl.timer[id];
  105. if (timer_pending(timer)) {
  106. dev_err(&mvotg->pdev->dev, "Timer%d is already running\n", id);
  107. return -EBUSY;
  108. }
  109. init_timer(timer);
  110. timer->data = (unsigned long) mvotg;
  111. timer->function = callback;
  112. timer->expires = jiffies + interval;
  113. add_timer(timer);
  114. return 0;
  115. }
  116. static int mv_otg_reset(struct mv_otg *mvotg)
  117. {
  118. unsigned int loops;
  119. u32 tmp;
  120. /* Stop the controller */
  121. tmp = readl(&mvotg->op_regs->usbcmd);
  122. tmp &= ~USBCMD_RUN_STOP;
  123. writel(tmp, &mvotg->op_regs->usbcmd);
  124. /* Reset the controller to get default values */
  125. writel(USBCMD_CTRL_RESET, &mvotg->op_regs->usbcmd);
  126. loops = 500;
  127. while (readl(&mvotg->op_regs->usbcmd) & USBCMD_CTRL_RESET) {
  128. if (loops == 0) {
  129. dev_err(&mvotg->pdev->dev,
  130. "Wait for RESET completed TIMEOUT\n");
  131. return -ETIMEDOUT;
  132. }
  133. loops--;
  134. udelay(20);
  135. }
  136. writel(0x0, &mvotg->op_regs->usbintr);
  137. tmp = readl(&mvotg->op_regs->usbsts);
  138. writel(tmp, &mvotg->op_regs->usbsts);
  139. return 0;
  140. }
  141. static void mv_otg_init_irq(struct mv_otg *mvotg)
  142. {
  143. u32 otgsc;
  144. mvotg->irq_en = OTGSC_INTR_A_SESSION_VALID
  145. | OTGSC_INTR_A_VBUS_VALID;
  146. mvotg->irq_status = OTGSC_INTSTS_A_SESSION_VALID
  147. | OTGSC_INTSTS_A_VBUS_VALID;
  148. if (mvotg->pdata->vbus == NULL) {
  149. mvotg->irq_en |= OTGSC_INTR_B_SESSION_VALID
  150. | OTGSC_INTR_B_SESSION_END;
  151. mvotg->irq_status |= OTGSC_INTSTS_B_SESSION_VALID
  152. | OTGSC_INTSTS_B_SESSION_END;
  153. }
  154. if (mvotg->pdata->id == NULL) {
  155. mvotg->irq_en |= OTGSC_INTR_USB_ID;
  156. mvotg->irq_status |= OTGSC_INTSTS_USB_ID;
  157. }
  158. otgsc = readl(&mvotg->op_regs->otgsc);
  159. otgsc |= mvotg->irq_en;
  160. writel(otgsc, &mvotg->op_regs->otgsc);
  161. }
  162. static void mv_otg_start_host(struct mv_otg *mvotg, int on)
  163. {
  164. #ifdef CONFIG_USB
  165. struct otg_transceiver *otg = &mvotg->otg;
  166. struct usb_hcd *hcd;
  167. if (!otg->host)
  168. return;
  169. dev_info(&mvotg->pdev->dev, "%s host\n", on ? "start" : "stop");
  170. hcd = bus_to_hcd(otg->host);
  171. if (on)
  172. usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
  173. else
  174. usb_remove_hcd(hcd);
  175. #endif /* CONFIG_USB */
  176. }
  177. static void mv_otg_start_periphrals(struct mv_otg *mvotg, int on)
  178. {
  179. struct otg_transceiver *otg = &mvotg->otg;
  180. if (!otg->gadget)
  181. return;
  182. dev_info(otg->dev, "gadget %s\n", on ? "on" : "off");
  183. if (on)
  184. usb_gadget_vbus_connect(otg->gadget);
  185. else
  186. usb_gadget_vbus_disconnect(otg->gadget);
  187. }
  188. static void otg_clock_enable(struct mv_otg *mvotg)
  189. {
  190. unsigned int i;
  191. for (i = 0; i < mvotg->clknum; i++)
  192. clk_enable(mvotg->clk[i]);
  193. }
  194. static void otg_clock_disable(struct mv_otg *mvotg)
  195. {
  196. unsigned int i;
  197. for (i = 0; i < mvotg->clknum; i++)
  198. clk_disable(mvotg->clk[i]);
  199. }
  200. static int mv_otg_enable_internal(struct mv_otg *mvotg)
  201. {
  202. int retval = 0;
  203. if (mvotg->active)
  204. return 0;
  205. dev_dbg(&mvotg->pdev->dev, "otg enabled\n");
  206. otg_clock_enable(mvotg);
  207. if (mvotg->pdata->phy_init) {
  208. retval = mvotg->pdata->phy_init(mvotg->phy_regs);
  209. if (retval) {
  210. dev_err(&mvotg->pdev->dev,
  211. "init phy error %d\n", retval);
  212. otg_clock_disable(mvotg);
  213. return retval;
  214. }
  215. }
  216. mvotg->active = 1;
  217. return 0;
  218. }
  219. static int mv_otg_enable(struct mv_otg *mvotg)
  220. {
  221. if (mvotg->clock_gating)
  222. return mv_otg_enable_internal(mvotg);
  223. return 0;
  224. }
  225. static void mv_otg_disable_internal(struct mv_otg *mvotg)
  226. {
  227. if (mvotg->active) {
  228. dev_dbg(&mvotg->pdev->dev, "otg disabled\n");
  229. if (mvotg->pdata->phy_deinit)
  230. mvotg->pdata->phy_deinit(mvotg->phy_regs);
  231. otg_clock_disable(mvotg);
  232. mvotg->active = 0;
  233. }
  234. }
  235. static void mv_otg_disable(struct mv_otg *mvotg)
  236. {
  237. if (mvotg->clock_gating)
  238. mv_otg_disable_internal(mvotg);
  239. }
  240. static void mv_otg_update_inputs(struct mv_otg *mvotg)
  241. {
  242. struct mv_otg_ctrl *otg_ctrl = &mvotg->otg_ctrl;
  243. u32 otgsc;
  244. otgsc = readl(&mvotg->op_regs->otgsc);
  245. if (mvotg->pdata->vbus) {
  246. if (mvotg->pdata->vbus->poll() == VBUS_HIGH) {
  247. otg_ctrl->b_sess_vld = 1;
  248. otg_ctrl->b_sess_end = 0;
  249. } else {
  250. otg_ctrl->b_sess_vld = 0;
  251. otg_ctrl->b_sess_end = 1;
  252. }
  253. } else {
  254. otg_ctrl->b_sess_vld = !!(otgsc & OTGSC_STS_B_SESSION_VALID);
  255. otg_ctrl->b_sess_end = !!(otgsc & OTGSC_STS_B_SESSION_END);
  256. }
  257. if (mvotg->pdata->id)
  258. otg_ctrl->id = !!mvotg->pdata->id->poll();
  259. else
  260. otg_ctrl->id = !!(otgsc & OTGSC_STS_USB_ID);
  261. if (mvotg->pdata->otg_force_a_bus_req && !otg_ctrl->id)
  262. otg_ctrl->a_bus_req = 1;
  263. otg_ctrl->a_sess_vld = !!(otgsc & OTGSC_STS_A_SESSION_VALID);
  264. otg_ctrl->a_vbus_vld = !!(otgsc & OTGSC_STS_A_VBUS_VALID);
  265. dev_dbg(&mvotg->pdev->dev, "%s: ", __func__);
  266. dev_dbg(&mvotg->pdev->dev, "id %d\n", otg_ctrl->id);
  267. dev_dbg(&mvotg->pdev->dev, "b_sess_vld %d\n", otg_ctrl->b_sess_vld);
  268. dev_dbg(&mvotg->pdev->dev, "b_sess_end %d\n", otg_ctrl->b_sess_end);
  269. dev_dbg(&mvotg->pdev->dev, "a_vbus_vld %d\n", otg_ctrl->a_vbus_vld);
  270. dev_dbg(&mvotg->pdev->dev, "a_sess_vld %d\n", otg_ctrl->a_sess_vld);
  271. }
  272. static void mv_otg_update_state(struct mv_otg *mvotg)
  273. {
  274. struct mv_otg_ctrl *otg_ctrl = &mvotg->otg_ctrl;
  275. struct otg_transceiver *otg = &mvotg->otg;
  276. int old_state = otg->state;
  277. switch (old_state) {
  278. case OTG_STATE_UNDEFINED:
  279. otg->state = OTG_STATE_B_IDLE;
  280. /* FALL THROUGH */
  281. case OTG_STATE_B_IDLE:
  282. if (otg_ctrl->id == 0)
  283. otg->state = OTG_STATE_A_IDLE;
  284. else if (otg_ctrl->b_sess_vld)
  285. otg->state = OTG_STATE_B_PERIPHERAL;
  286. break;
  287. case OTG_STATE_B_PERIPHERAL:
  288. if (!otg_ctrl->b_sess_vld || otg_ctrl->id == 0)
  289. otg->state = OTG_STATE_B_IDLE;
  290. break;
  291. case OTG_STATE_A_IDLE:
  292. if (otg_ctrl->id)
  293. otg->state = OTG_STATE_B_IDLE;
  294. else if (!(otg_ctrl->a_bus_drop) &&
  295. (otg_ctrl->a_bus_req || otg_ctrl->a_srp_det))
  296. otg->state = OTG_STATE_A_WAIT_VRISE;
  297. break;
  298. case OTG_STATE_A_WAIT_VRISE:
  299. if (otg_ctrl->a_vbus_vld)
  300. otg->state = OTG_STATE_A_WAIT_BCON;
  301. break;
  302. case OTG_STATE_A_WAIT_BCON:
  303. if (otg_ctrl->id || otg_ctrl->a_bus_drop
  304. || otg_ctrl->a_wait_bcon_timeout) {
  305. mv_otg_cancel_timer(mvotg, A_WAIT_BCON_TIMER);
  306. mvotg->otg_ctrl.a_wait_bcon_timeout = 0;
  307. otg->state = OTG_STATE_A_WAIT_VFALL;
  308. otg_ctrl->a_bus_req = 0;
  309. } else if (!otg_ctrl->a_vbus_vld) {
  310. mv_otg_cancel_timer(mvotg, A_WAIT_BCON_TIMER);
  311. mvotg->otg_ctrl.a_wait_bcon_timeout = 0;
  312. otg->state = OTG_STATE_A_VBUS_ERR;
  313. } else if (otg_ctrl->b_conn) {
  314. mv_otg_cancel_timer(mvotg, A_WAIT_BCON_TIMER);
  315. mvotg->otg_ctrl.a_wait_bcon_timeout = 0;
  316. otg->state = OTG_STATE_A_HOST;
  317. }
  318. break;
  319. case OTG_STATE_A_HOST:
  320. if (otg_ctrl->id || !otg_ctrl->b_conn
  321. || otg_ctrl->a_bus_drop)
  322. otg->state = OTG_STATE_A_WAIT_BCON;
  323. else if (!otg_ctrl->a_vbus_vld)
  324. otg->state = OTG_STATE_A_VBUS_ERR;
  325. break;
  326. case OTG_STATE_A_WAIT_VFALL:
  327. if (otg_ctrl->id
  328. || (!otg_ctrl->b_conn && otg_ctrl->a_sess_vld)
  329. || otg_ctrl->a_bus_req)
  330. otg->state = OTG_STATE_A_IDLE;
  331. break;
  332. case OTG_STATE_A_VBUS_ERR:
  333. if (otg_ctrl->id || otg_ctrl->a_clr_err
  334. || otg_ctrl->a_bus_drop) {
  335. otg_ctrl->a_clr_err = 0;
  336. otg->state = OTG_STATE_A_WAIT_VFALL;
  337. }
  338. break;
  339. default:
  340. break;
  341. }
  342. }
  343. static void mv_otg_work(struct work_struct *work)
  344. {
  345. struct mv_otg *mvotg;
  346. struct otg_transceiver *otg;
  347. int old_state;
  348. mvotg = container_of((struct delayed_work *)work, struct mv_otg, work);
  349. run:
  350. /* work queue is single thread, or we need spin_lock to protect */
  351. otg = &mvotg->otg;
  352. old_state = otg->state;
  353. if (!mvotg->active)
  354. return;
  355. mv_otg_update_inputs(mvotg);
  356. mv_otg_update_state(mvotg);
  357. if (old_state != otg->state) {
  358. dev_info(&mvotg->pdev->dev, "change from state %s to %s\n",
  359. state_string[old_state],
  360. state_string[otg->state]);
  361. switch (otg->state) {
  362. case OTG_STATE_B_IDLE:
  363. mvotg->otg.default_a = 0;
  364. if (old_state == OTG_STATE_B_PERIPHERAL)
  365. mv_otg_start_periphrals(mvotg, 0);
  366. mv_otg_reset(mvotg);
  367. mv_otg_disable(mvotg);
  368. break;
  369. case OTG_STATE_B_PERIPHERAL:
  370. mv_otg_enable(mvotg);
  371. mv_otg_start_periphrals(mvotg, 1);
  372. break;
  373. case OTG_STATE_A_IDLE:
  374. mvotg->otg.default_a = 1;
  375. mv_otg_enable(mvotg);
  376. if (old_state == OTG_STATE_A_WAIT_VFALL)
  377. mv_otg_start_host(mvotg, 0);
  378. mv_otg_reset(mvotg);
  379. break;
  380. case OTG_STATE_A_WAIT_VRISE:
  381. mv_otg_set_vbus(&mvotg->otg, 1);
  382. break;
  383. case OTG_STATE_A_WAIT_BCON:
  384. if (old_state != OTG_STATE_A_HOST)
  385. mv_otg_start_host(mvotg, 1);
  386. mv_otg_set_timer(mvotg, A_WAIT_BCON_TIMER,
  387. T_A_WAIT_BCON,
  388. mv_otg_timer_await_bcon);
  389. /*
  390. * Now, we directly enter A_HOST. So set b_conn = 1
  391. * here. In fact, it need host driver to notify us.
  392. */
  393. mvotg->otg_ctrl.b_conn = 1;
  394. break;
  395. case OTG_STATE_A_HOST:
  396. break;
  397. case OTG_STATE_A_WAIT_VFALL:
  398. /*
  399. * Now, we has exited A_HOST. So set b_conn = 0
  400. * here. In fact, it need host driver to notify us.
  401. */
  402. mvotg->otg_ctrl.b_conn = 0;
  403. mv_otg_set_vbus(&mvotg->otg, 0);
  404. break;
  405. case OTG_STATE_A_VBUS_ERR:
  406. break;
  407. default:
  408. break;
  409. }
  410. goto run;
  411. }
  412. }
  413. static irqreturn_t mv_otg_irq(int irq, void *dev)
  414. {
  415. struct mv_otg *mvotg = dev;
  416. u32 otgsc;
  417. otgsc = readl(&mvotg->op_regs->otgsc);
  418. writel(otgsc, &mvotg->op_regs->otgsc);
  419. /*
  420. * if we have vbus, then the vbus detection for B-device
  421. * will be done by mv_otg_inputs_irq().
  422. */
  423. if (mvotg->pdata->vbus)
  424. if ((otgsc & OTGSC_STS_USB_ID) &&
  425. !(otgsc & OTGSC_INTSTS_USB_ID))
  426. return IRQ_NONE;
  427. if ((otgsc & mvotg->irq_status) == 0)
  428. return IRQ_NONE;
  429. mv_otg_run_state_machine(mvotg, 0);
  430. return IRQ_HANDLED;
  431. }
  432. static irqreturn_t mv_otg_inputs_irq(int irq, void *dev)
  433. {
  434. struct mv_otg *mvotg = dev;
  435. /* The clock may disabled at this time */
  436. if (!mvotg->active) {
  437. mv_otg_enable(mvotg);
  438. mv_otg_init_irq(mvotg);
  439. }
  440. mv_otg_run_state_machine(mvotg, 0);
  441. return IRQ_HANDLED;
  442. }
  443. static ssize_t
  444. get_a_bus_req(struct device *dev, struct device_attribute *attr, char *buf)
  445. {
  446. struct mv_otg *mvotg = dev_get_drvdata(dev);
  447. return scnprintf(buf, PAGE_SIZE, "%d\n",
  448. mvotg->otg_ctrl.a_bus_req);
  449. }
  450. static ssize_t
  451. set_a_bus_req(struct device *dev, struct device_attribute *attr,
  452. const char *buf, size_t count)
  453. {
  454. struct mv_otg *mvotg = dev_get_drvdata(dev);
  455. if (count > 2)
  456. return -1;
  457. /* We will use this interface to change to A device */
  458. if (mvotg->otg.state != OTG_STATE_B_IDLE
  459. && mvotg->otg.state != OTG_STATE_A_IDLE)
  460. return -1;
  461. /* The clock may disabled and we need to set irq for ID detected */
  462. mv_otg_enable(mvotg);
  463. mv_otg_init_irq(mvotg);
  464. if (buf[0] == '1') {
  465. mvotg->otg_ctrl.a_bus_req = 1;
  466. mvotg->otg_ctrl.a_bus_drop = 0;
  467. dev_dbg(&mvotg->pdev->dev,
  468. "User request: a_bus_req = 1\n");
  469. if (spin_trylock(&mvotg->wq_lock)) {
  470. mv_otg_run_state_machine(mvotg, 0);
  471. spin_unlock(&mvotg->wq_lock);
  472. }
  473. }
  474. return count;
  475. }
  476. static DEVICE_ATTR(a_bus_req, S_IRUGO | S_IWUSR, get_a_bus_req,
  477. set_a_bus_req);
  478. static ssize_t
  479. set_a_clr_err(struct device *dev, struct device_attribute *attr,
  480. const char *buf, size_t count)
  481. {
  482. struct mv_otg *mvotg = dev_get_drvdata(dev);
  483. if (!mvotg->otg.default_a)
  484. return -1;
  485. if (count > 2)
  486. return -1;
  487. if (buf[0] == '1') {
  488. mvotg->otg_ctrl.a_clr_err = 1;
  489. dev_dbg(&mvotg->pdev->dev,
  490. "User request: a_clr_err = 1\n");
  491. }
  492. if (spin_trylock(&mvotg->wq_lock)) {
  493. mv_otg_run_state_machine(mvotg, 0);
  494. spin_unlock(&mvotg->wq_lock);
  495. }
  496. return count;
  497. }
  498. static DEVICE_ATTR(a_clr_err, S_IWUSR, NULL, set_a_clr_err);
  499. static ssize_t
  500. get_a_bus_drop(struct device *dev, struct device_attribute *attr,
  501. char *buf)
  502. {
  503. struct mv_otg *mvotg = dev_get_drvdata(dev);
  504. return scnprintf(buf, PAGE_SIZE, "%d\n",
  505. mvotg->otg_ctrl.a_bus_drop);
  506. }
  507. static ssize_t
  508. set_a_bus_drop(struct device *dev, struct device_attribute *attr,
  509. const char *buf, size_t count)
  510. {
  511. struct mv_otg *mvotg = dev_get_drvdata(dev);
  512. if (!mvotg->otg.default_a)
  513. return -1;
  514. if (count > 2)
  515. return -1;
  516. if (buf[0] == '0') {
  517. mvotg->otg_ctrl.a_bus_drop = 0;
  518. dev_dbg(&mvotg->pdev->dev,
  519. "User request: a_bus_drop = 0\n");
  520. } else if (buf[0] == '1') {
  521. mvotg->otg_ctrl.a_bus_drop = 1;
  522. mvotg->otg_ctrl.a_bus_req = 0;
  523. dev_dbg(&mvotg->pdev->dev,
  524. "User request: a_bus_drop = 1\n");
  525. dev_dbg(&mvotg->pdev->dev,
  526. "User request: and a_bus_req = 0\n");
  527. }
  528. if (spin_trylock(&mvotg->wq_lock)) {
  529. mv_otg_run_state_machine(mvotg, 0);
  530. spin_unlock(&mvotg->wq_lock);
  531. }
  532. return count;
  533. }
  534. static DEVICE_ATTR(a_bus_drop, S_IRUGO | S_IWUSR,
  535. get_a_bus_drop, set_a_bus_drop);
  536. static struct attribute *inputs_attrs[] = {
  537. &dev_attr_a_bus_req.attr,
  538. &dev_attr_a_clr_err.attr,
  539. &dev_attr_a_bus_drop.attr,
  540. NULL,
  541. };
  542. static struct attribute_group inputs_attr_group = {
  543. .name = "inputs",
  544. .attrs = inputs_attrs,
  545. };
  546. int mv_otg_remove(struct platform_device *pdev)
  547. {
  548. struct mv_otg *mvotg = platform_get_drvdata(pdev);
  549. int clk_i;
  550. sysfs_remove_group(&mvotg->pdev->dev.kobj, &inputs_attr_group);
  551. if (mvotg->irq)
  552. free_irq(mvotg->irq, mvotg);
  553. if (mvotg->pdata->vbus)
  554. free_irq(mvotg->pdata->vbus->irq, mvotg);
  555. if (mvotg->pdata->id)
  556. free_irq(mvotg->pdata->id->irq, mvotg);
  557. if (mvotg->qwork) {
  558. flush_workqueue(mvotg->qwork);
  559. destroy_workqueue(mvotg->qwork);
  560. }
  561. mv_otg_disable(mvotg);
  562. if (mvotg->cap_regs)
  563. iounmap(mvotg->cap_regs);
  564. if (mvotg->phy_regs)
  565. iounmap(mvotg->phy_regs);
  566. for (clk_i = 0; clk_i <= mvotg->clknum; clk_i++)
  567. clk_put(mvotg->clk[clk_i]);
  568. otg_set_transceiver(NULL);
  569. platform_set_drvdata(pdev, NULL);
  570. kfree(mvotg);
  571. return 0;
  572. }
  573. static int mv_otg_probe(struct platform_device *pdev)
  574. {
  575. struct mv_usb_platform_data *pdata = pdev->dev.platform_data;
  576. struct mv_otg *mvotg;
  577. struct resource *r;
  578. int retval = 0, clk_i, i;
  579. size_t size;
  580. if (pdata == NULL) {
  581. dev_err(&pdev->dev, "failed to get platform data\n");
  582. return -ENODEV;
  583. }
  584. size = sizeof(*mvotg) + sizeof(struct clk *) * pdata->clknum;
  585. mvotg = kzalloc(size, GFP_KERNEL);
  586. if (!mvotg) {
  587. dev_err(&pdev->dev, "failed to allocate memory!\n");
  588. return -ENOMEM;
  589. }
  590. platform_set_drvdata(pdev, mvotg);
  591. mvotg->pdev = pdev;
  592. mvotg->pdata = pdata;
  593. mvotg->clknum = pdata->clknum;
  594. for (clk_i = 0; clk_i < mvotg->clknum; clk_i++) {
  595. mvotg->clk[clk_i] = clk_get(&pdev->dev, pdata->clkname[clk_i]);
  596. if (IS_ERR(mvotg->clk[clk_i])) {
  597. retval = PTR_ERR(mvotg->clk[clk_i]);
  598. goto err_put_clk;
  599. }
  600. }
  601. mvotg->qwork = create_singlethread_workqueue("mv_otg_queue");
  602. if (!mvotg->qwork) {
  603. dev_dbg(&pdev->dev, "cannot create workqueue for OTG\n");
  604. retval = -ENOMEM;
  605. goto err_put_clk;
  606. }
  607. INIT_DELAYED_WORK(&mvotg->work, mv_otg_work);
  608. /* OTG common part */
  609. mvotg->pdev = pdev;
  610. mvotg->otg.dev = &pdev->dev;
  611. mvotg->otg.label = driver_name;
  612. mvotg->otg.set_host = mv_otg_set_host;
  613. mvotg->otg.set_peripheral = mv_otg_set_peripheral;
  614. mvotg->otg.set_vbus = mv_otg_set_vbus;
  615. mvotg->otg.state = OTG_STATE_UNDEFINED;
  616. for (i = 0; i < OTG_TIMER_NUM; i++)
  617. init_timer(&mvotg->otg_ctrl.timer[i]);
  618. r = platform_get_resource_byname(mvotg->pdev,
  619. IORESOURCE_MEM, "phyregs");
  620. if (r == NULL) {
  621. dev_err(&pdev->dev, "no phy I/O memory resource defined\n");
  622. retval = -ENODEV;
  623. goto err_destroy_workqueue;
  624. }
  625. mvotg->phy_regs = ioremap(r->start, resource_size(r));
  626. if (mvotg->phy_regs == NULL) {
  627. dev_err(&pdev->dev, "failed to map phy I/O memory\n");
  628. retval = -EFAULT;
  629. goto err_destroy_workqueue;
  630. }
  631. r = platform_get_resource_byname(mvotg->pdev,
  632. IORESOURCE_MEM, "capregs");
  633. if (r == NULL) {
  634. dev_err(&pdev->dev, "no I/O memory resource defined\n");
  635. retval = -ENODEV;
  636. goto err_unmap_phyreg;
  637. }
  638. mvotg->cap_regs = ioremap(r->start, resource_size(r));
  639. if (mvotg->cap_regs == NULL) {
  640. dev_err(&pdev->dev, "failed to map I/O memory\n");
  641. retval = -EFAULT;
  642. goto err_unmap_phyreg;
  643. }
  644. /* we will acces controller register, so enable the udc controller */
  645. retval = mv_otg_enable_internal(mvotg);
  646. if (retval) {
  647. dev_err(&pdev->dev, "mv otg enable error %d\n", retval);
  648. goto err_unmap_capreg;
  649. }
  650. mvotg->op_regs =
  651. (struct mv_otg_regs __iomem *) ((unsigned long) mvotg->cap_regs
  652. + (readl(mvotg->cap_regs) & CAPLENGTH_MASK));
  653. if (pdata->id) {
  654. retval = request_threaded_irq(pdata->id->irq, NULL,
  655. mv_otg_inputs_irq,
  656. IRQF_ONESHOT, "id", mvotg);
  657. if (retval) {
  658. dev_info(&pdev->dev,
  659. "Failed to request irq for ID\n");
  660. pdata->id = NULL;
  661. }
  662. }
  663. if (pdata->vbus) {
  664. mvotg->clock_gating = 1;
  665. retval = request_threaded_irq(pdata->vbus->irq, NULL,
  666. mv_otg_inputs_irq,
  667. IRQF_ONESHOT, "vbus", mvotg);
  668. if (retval) {
  669. dev_info(&pdev->dev,
  670. "Failed to request irq for VBUS, "
  671. "disable clock gating\n");
  672. mvotg->clock_gating = 0;
  673. pdata->vbus = NULL;
  674. }
  675. }
  676. if (pdata->disable_otg_clock_gating)
  677. mvotg->clock_gating = 0;
  678. mv_otg_reset(mvotg);
  679. mv_otg_init_irq(mvotg);
  680. r = platform_get_resource(mvotg->pdev, IORESOURCE_IRQ, 0);
  681. if (r == NULL) {
  682. dev_err(&pdev->dev, "no IRQ resource defined\n");
  683. retval = -ENODEV;
  684. goto err_disable_clk;
  685. }
  686. mvotg->irq = r->start;
  687. if (request_irq(mvotg->irq, mv_otg_irq, IRQF_SHARED,
  688. driver_name, mvotg)) {
  689. dev_err(&pdev->dev, "Request irq %d for OTG failed\n",
  690. mvotg->irq);
  691. mvotg->irq = 0;
  692. retval = -ENODEV;
  693. goto err_disable_clk;
  694. }
  695. retval = otg_set_transceiver(&mvotg->otg);
  696. if (retval < 0) {
  697. dev_err(&pdev->dev, "can't register transceiver, %d\n",
  698. retval);
  699. goto err_free_irq;
  700. }
  701. retval = sysfs_create_group(&pdev->dev.kobj, &inputs_attr_group);
  702. if (retval < 0) {
  703. dev_dbg(&pdev->dev,
  704. "Can't register sysfs attr group: %d\n", retval);
  705. goto err_set_transceiver;
  706. }
  707. spin_lock_init(&mvotg->wq_lock);
  708. if (spin_trylock(&mvotg->wq_lock)) {
  709. mv_otg_run_state_machine(mvotg, 2 * HZ);
  710. spin_unlock(&mvotg->wq_lock);
  711. }
  712. dev_info(&pdev->dev,
  713. "successful probe OTG device %s clock gating.\n",
  714. mvotg->clock_gating ? "with" : "without");
  715. return 0;
  716. err_set_transceiver:
  717. otg_set_transceiver(NULL);
  718. err_free_irq:
  719. free_irq(mvotg->irq, mvotg);
  720. err_disable_clk:
  721. if (pdata->vbus)
  722. free_irq(pdata->vbus->irq, mvotg);
  723. if (pdata->id)
  724. free_irq(pdata->id->irq, mvotg);
  725. mv_otg_disable_internal(mvotg);
  726. err_unmap_capreg:
  727. iounmap(mvotg->cap_regs);
  728. err_unmap_phyreg:
  729. iounmap(mvotg->phy_regs);
  730. err_destroy_workqueue:
  731. flush_workqueue(mvotg->qwork);
  732. destroy_workqueue(mvotg->qwork);
  733. err_put_clk:
  734. for (clk_i--; clk_i >= 0; clk_i--)
  735. clk_put(mvotg->clk[clk_i]);
  736. platform_set_drvdata(pdev, NULL);
  737. kfree(mvotg);
  738. return retval;
  739. }
  740. #ifdef CONFIG_PM
  741. static int mv_otg_suspend(struct platform_device *pdev, pm_message_t state)
  742. {
  743. struct mv_otg *mvotg = platform_get_drvdata(pdev);
  744. if (mvotg->otg.state != OTG_STATE_B_IDLE) {
  745. dev_info(&pdev->dev,
  746. "OTG state is not B_IDLE, it is %d!\n",
  747. mvotg->otg.state);
  748. return -EAGAIN;
  749. }
  750. if (!mvotg->clock_gating)
  751. mv_otg_disable_internal(mvotg);
  752. return 0;
  753. }
  754. static int mv_otg_resume(struct platform_device *pdev)
  755. {
  756. struct mv_otg *mvotg = platform_get_drvdata(pdev);
  757. u32 otgsc;
  758. if (!mvotg->clock_gating) {
  759. mv_otg_enable_internal(mvotg);
  760. otgsc = readl(&mvotg->op_regs->otgsc);
  761. otgsc |= mvotg->irq_en;
  762. writel(otgsc, &mvotg->op_regs->otgsc);
  763. if (spin_trylock(&mvotg->wq_lock)) {
  764. mv_otg_run_state_machine(mvotg, 0);
  765. spin_unlock(&mvotg->wq_lock);
  766. }
  767. }
  768. return 0;
  769. }
  770. #endif
  771. static struct platform_driver mv_otg_driver = {
  772. .probe = mv_otg_probe,
  773. .remove = __exit_p(mv_otg_remove),
  774. .driver = {
  775. .owner = THIS_MODULE,
  776. .name = driver_name,
  777. },
  778. #ifdef CONFIG_PM
  779. .suspend = mv_otg_suspend,
  780. .resume = mv_otg_resume,
  781. #endif
  782. };
  783. static int __init mv_otg_init(void)
  784. {
  785. return platform_driver_register(&mv_otg_driver);
  786. }
  787. static void __exit mv_otg_exit(void)
  788. {
  789. platform_driver_unregister(&mv_otg_driver);
  790. }
  791. module_init(mv_otg_init);
  792. module_exit(mv_otg_exit);