davinci.c 17 KB

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  1. /*
  2. * Copyright (C) 2005-2006 by Texas Instruments
  3. *
  4. * This file is part of the Inventra Controller Driver for Linux.
  5. *
  6. * The Inventra Controller Driver for Linux is free software; you
  7. * can redistribute it and/or modify it under the terms of the GNU
  8. * General Public License version 2 as published by the Free Software
  9. * Foundation.
  10. *
  11. * The Inventra Controller Driver for Linux is distributed in
  12. * the hope that it will be useful, but WITHOUT ANY WARRANTY;
  13. * without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  15. * License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with The Inventra Controller Driver for Linux ; if not,
  19. * write to the Free Software Foundation, Inc., 59 Temple Place,
  20. * Suite 330, Boston, MA 02111-1307 USA
  21. *
  22. */
  23. #include <linux/module.h>
  24. #include <linux/kernel.h>
  25. #include <linux/sched.h>
  26. #include <linux/init.h>
  27. #include <linux/list.h>
  28. #include <linux/delay.h>
  29. #include <linux/clk.h>
  30. #include <linux/io.h>
  31. #include <linux/gpio.h>
  32. #include <linux/platform_device.h>
  33. #include <linux/dma-mapping.h>
  34. #include <mach/cputype.h>
  35. #include <asm/mach-types.h>
  36. #include "musb_core.h"
  37. #ifdef CONFIG_MACH_DAVINCI_EVM
  38. #define GPIO_nVBUS_DRV 160
  39. #endif
  40. #include "davinci.h"
  41. #include "cppi_dma.h"
  42. #define USB_PHY_CTRL IO_ADDRESS(USBPHY_CTL_PADDR)
  43. #define DM355_DEEPSLEEP IO_ADDRESS(DM355_DEEPSLEEP_PADDR)
  44. struct davinci_glue {
  45. struct device *dev;
  46. struct platform_device *musb;
  47. struct clk *clk;
  48. };
  49. /* REVISIT (PM) we should be able to keep the PHY in low power mode most
  50. * of the time (24 MHZ oscillator and PLL off, etc) by setting POWER.D0
  51. * and, when in host mode, autosuspending idle root ports... PHYPLLON
  52. * (overriding SUSPENDM?) then likely needs to stay off.
  53. */
  54. static inline void phy_on(void)
  55. {
  56. u32 phy_ctrl = __raw_readl(USB_PHY_CTRL);
  57. /* power everything up; start the on-chip PHY and its PLL */
  58. phy_ctrl &= ~(USBPHY_OSCPDWN | USBPHY_OTGPDWN | USBPHY_PHYPDWN);
  59. phy_ctrl |= USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON;
  60. __raw_writel(phy_ctrl, USB_PHY_CTRL);
  61. /* wait for PLL to lock before proceeding */
  62. while ((__raw_readl(USB_PHY_CTRL) & USBPHY_PHYCLKGD) == 0)
  63. cpu_relax();
  64. }
  65. static inline void phy_off(void)
  66. {
  67. u32 phy_ctrl = __raw_readl(USB_PHY_CTRL);
  68. /* powerdown the on-chip PHY, its PLL, and the OTG block */
  69. phy_ctrl &= ~(USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON);
  70. phy_ctrl |= USBPHY_OSCPDWN | USBPHY_OTGPDWN | USBPHY_PHYPDWN;
  71. __raw_writel(phy_ctrl, USB_PHY_CTRL);
  72. }
  73. static int dma_off = 1;
  74. static void davinci_musb_enable(struct musb *musb)
  75. {
  76. u32 tmp, old, val;
  77. /* workaround: setup irqs through both register sets */
  78. tmp = (musb->epmask & DAVINCI_USB_TX_ENDPTS_MASK)
  79. << DAVINCI_USB_TXINT_SHIFT;
  80. musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
  81. old = tmp;
  82. tmp = (musb->epmask & (0xfffe & DAVINCI_USB_RX_ENDPTS_MASK))
  83. << DAVINCI_USB_RXINT_SHIFT;
  84. musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
  85. tmp |= old;
  86. val = ~MUSB_INTR_SOF;
  87. tmp |= ((val & 0x01ff) << DAVINCI_USB_USBINT_SHIFT);
  88. musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
  89. if (is_dma_capable() && !dma_off)
  90. printk(KERN_WARNING "%s %s: dma not reactivated\n",
  91. __FILE__, __func__);
  92. else
  93. dma_off = 0;
  94. /* force a DRVVBUS irq so we can start polling for ID change */
  95. if (is_otg_enabled(musb))
  96. musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
  97. DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT);
  98. }
  99. /*
  100. * Disable the HDRC and flush interrupts
  101. */
  102. static void davinci_musb_disable(struct musb *musb)
  103. {
  104. /* because we don't set CTRLR.UINT, "important" to:
  105. * - not read/write INTRUSB/INTRUSBE
  106. * - (except during initial setup, as workaround)
  107. * - use INTSETR/INTCLRR instead
  108. */
  109. musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_CLR_REG,
  110. DAVINCI_USB_USBINT_MASK
  111. | DAVINCI_USB_TXINT_MASK
  112. | DAVINCI_USB_RXINT_MASK);
  113. musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
  114. musb_writel(musb->ctrl_base, DAVINCI_USB_EOI_REG, 0);
  115. if (is_dma_capable() && !dma_off)
  116. WARNING("dma still active\n");
  117. }
  118. #define portstate(stmt) stmt
  119. /*
  120. * VBUS SWITCHING IS BOARD-SPECIFIC ... at least for the DM6446 EVM,
  121. * which doesn't wire DRVVBUS to the FET that switches it. Unclear
  122. * if that's a problem with the DM6446 chip or just with that board.
  123. *
  124. * In either case, the DM355 EVM automates DRVVBUS the normal way,
  125. * when J10 is out, and TI documents it as handling OTG.
  126. */
  127. #ifdef CONFIG_MACH_DAVINCI_EVM
  128. static int vbus_state = -1;
  129. /* I2C operations are always synchronous, and require a task context.
  130. * With unloaded systems, using the shared workqueue seems to suffice
  131. * to satisfy the 100msec A_WAIT_VRISE timeout...
  132. */
  133. static void evm_deferred_drvvbus(struct work_struct *ignored)
  134. {
  135. gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state);
  136. vbus_state = !vbus_state;
  137. }
  138. #endif /* EVM */
  139. static void davinci_musb_source_power(struct musb *musb, int is_on, int immediate)
  140. {
  141. #ifdef CONFIG_MACH_DAVINCI_EVM
  142. if (is_on)
  143. is_on = 1;
  144. if (vbus_state == is_on)
  145. return;
  146. vbus_state = !is_on; /* 0/1 vs "-1 == unknown/init" */
  147. if (machine_is_davinci_evm()) {
  148. static DECLARE_WORK(evm_vbus_work, evm_deferred_drvvbus);
  149. if (immediate)
  150. gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state);
  151. else
  152. schedule_work(&evm_vbus_work);
  153. }
  154. if (immediate)
  155. vbus_state = is_on;
  156. #endif
  157. }
  158. static void davinci_musb_set_vbus(struct musb *musb, int is_on)
  159. {
  160. WARN_ON(is_on && is_peripheral_active(musb));
  161. davinci_musb_source_power(musb, is_on, 0);
  162. }
  163. #define POLL_SECONDS 2
  164. static struct timer_list otg_workaround;
  165. static void otg_timer(unsigned long _musb)
  166. {
  167. struct musb *musb = (void *)_musb;
  168. void __iomem *mregs = musb->mregs;
  169. u8 devctl;
  170. unsigned long flags;
  171. /* We poll because DaVinci's won't expose several OTG-critical
  172. * status change events (from the transceiver) otherwise.
  173. */
  174. devctl = musb_readb(mregs, MUSB_DEVCTL);
  175. dev_dbg(musb->controller, "poll devctl %02x (%s)\n", devctl,
  176. otg_state_string(musb->xceiv->state));
  177. spin_lock_irqsave(&musb->lock, flags);
  178. switch (musb->xceiv->state) {
  179. case OTG_STATE_A_WAIT_VFALL:
  180. /* Wait till VBUS falls below SessionEnd (~0.2V); the 1.3 RTL
  181. * seems to mis-handle session "start" otherwise (or in our
  182. * case "recover"), in routine "VBUS was valid by the time
  183. * VBUSERR got reported during enumeration" cases.
  184. */
  185. if (devctl & MUSB_DEVCTL_VBUS) {
  186. mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
  187. break;
  188. }
  189. musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
  190. musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
  191. MUSB_INTR_VBUSERROR << DAVINCI_USB_USBINT_SHIFT);
  192. break;
  193. case OTG_STATE_B_IDLE:
  194. if (!is_peripheral_enabled(musb))
  195. break;
  196. /* There's no ID-changed IRQ, so we have no good way to tell
  197. * when to switch to the A-Default state machine (by setting
  198. * the DEVCTL.SESSION flag).
  199. *
  200. * Workaround: whenever we're in B_IDLE, try setting the
  201. * session flag every few seconds. If it works, ID was
  202. * grounded and we're now in the A-Default state machine.
  203. *
  204. * NOTE setting the session flag is _supposed_ to trigger
  205. * SRP, but clearly it doesn't.
  206. */
  207. musb_writeb(mregs, MUSB_DEVCTL,
  208. devctl | MUSB_DEVCTL_SESSION);
  209. devctl = musb_readb(mregs, MUSB_DEVCTL);
  210. if (devctl & MUSB_DEVCTL_BDEVICE)
  211. mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
  212. else
  213. musb->xceiv->state = OTG_STATE_A_IDLE;
  214. break;
  215. default:
  216. break;
  217. }
  218. spin_unlock_irqrestore(&musb->lock, flags);
  219. }
  220. static irqreturn_t davinci_musb_interrupt(int irq, void *__hci)
  221. {
  222. unsigned long flags;
  223. irqreturn_t retval = IRQ_NONE;
  224. struct musb *musb = __hci;
  225. void __iomem *tibase = musb->ctrl_base;
  226. struct cppi *cppi;
  227. u32 tmp;
  228. spin_lock_irqsave(&musb->lock, flags);
  229. /* NOTE: DaVinci shadows the Mentor IRQs. Don't manage them through
  230. * the Mentor registers (except for setup), use the TI ones and EOI.
  231. *
  232. * Docs describe irq "vector" registers associated with the CPPI and
  233. * USB EOI registers. These hold a bitmask corresponding to the
  234. * current IRQ, not an irq handler address. Would using those bits
  235. * resolve some of the races observed in this dispatch code??
  236. */
  237. /* CPPI interrupts share the same IRQ line, but have their own
  238. * mask, state, "vector", and EOI registers.
  239. */
  240. cppi = container_of(musb->dma_controller, struct cppi, controller);
  241. if (is_cppi_enabled() && musb->dma_controller && !cppi->irq)
  242. retval = cppi_interrupt(irq, __hci);
  243. /* ack and handle non-CPPI interrupts */
  244. tmp = musb_readl(tibase, DAVINCI_USB_INT_SRC_MASKED_REG);
  245. musb_writel(tibase, DAVINCI_USB_INT_SRC_CLR_REG, tmp);
  246. dev_dbg(musb->controller, "IRQ %08x\n", tmp);
  247. musb->int_rx = (tmp & DAVINCI_USB_RXINT_MASK)
  248. >> DAVINCI_USB_RXINT_SHIFT;
  249. musb->int_tx = (tmp & DAVINCI_USB_TXINT_MASK)
  250. >> DAVINCI_USB_TXINT_SHIFT;
  251. musb->int_usb = (tmp & DAVINCI_USB_USBINT_MASK)
  252. >> DAVINCI_USB_USBINT_SHIFT;
  253. /* DRVVBUS irqs are the only proxy we have (a very poor one!) for
  254. * DaVinci's missing ID change IRQ. We need an ID change IRQ to
  255. * switch appropriately between halves of the OTG state machine.
  256. * Managing DEVCTL.SESSION per Mentor docs requires we know its
  257. * value, but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
  258. * Also, DRVVBUS pulses for SRP (but not at 5V) ...
  259. */
  260. if (tmp & (DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT)) {
  261. int drvvbus = musb_readl(tibase, DAVINCI_USB_STAT_REG);
  262. void __iomem *mregs = musb->mregs;
  263. u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
  264. int err = musb->int_usb & MUSB_INTR_VBUSERROR;
  265. err = is_host_enabled(musb)
  266. && (musb->int_usb & MUSB_INTR_VBUSERROR);
  267. if (err) {
  268. /* The Mentor core doesn't debounce VBUS as needed
  269. * to cope with device connect current spikes. This
  270. * means it's not uncommon for bus-powered devices
  271. * to get VBUS errors during enumeration.
  272. *
  273. * This is a workaround, but newer RTL from Mentor
  274. * seems to allow a better one: "re"starting sessions
  275. * without waiting (on EVM, a **long** time) for VBUS
  276. * to stop registering in devctl.
  277. */
  278. musb->int_usb &= ~MUSB_INTR_VBUSERROR;
  279. musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
  280. mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
  281. WARNING("VBUS error workaround (delay coming)\n");
  282. } else if (is_host_enabled(musb) && drvvbus) {
  283. MUSB_HST_MODE(musb);
  284. musb->xceiv->default_a = 1;
  285. musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
  286. portstate(musb->port1_status |= USB_PORT_STAT_POWER);
  287. del_timer(&otg_workaround);
  288. } else {
  289. musb->is_active = 0;
  290. MUSB_DEV_MODE(musb);
  291. musb->xceiv->default_a = 0;
  292. musb->xceiv->state = OTG_STATE_B_IDLE;
  293. portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
  294. }
  295. /* NOTE: this must complete poweron within 100 msec
  296. * (OTG_TIME_A_WAIT_VRISE) but we don't check for that.
  297. */
  298. davinci_musb_source_power(musb, drvvbus, 0);
  299. dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
  300. drvvbus ? "on" : "off",
  301. otg_state_string(musb->xceiv->state),
  302. err ? " ERROR" : "",
  303. devctl);
  304. retval = IRQ_HANDLED;
  305. }
  306. if (musb->int_tx || musb->int_rx || musb->int_usb)
  307. retval |= musb_interrupt(musb);
  308. /* irq stays asserted until EOI is written */
  309. musb_writel(tibase, DAVINCI_USB_EOI_REG, 0);
  310. /* poll for ID change */
  311. if (is_otg_enabled(musb)
  312. && musb->xceiv->state == OTG_STATE_B_IDLE)
  313. mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
  314. spin_unlock_irqrestore(&musb->lock, flags);
  315. return retval;
  316. }
  317. static int davinci_musb_set_mode(struct musb *musb, u8 mode)
  318. {
  319. /* EVM can't do this (right?) */
  320. return -EIO;
  321. }
  322. static int davinci_musb_init(struct musb *musb)
  323. {
  324. void __iomem *tibase = musb->ctrl_base;
  325. u32 revision;
  326. usb_nop_xceiv_register();
  327. musb->xceiv = otg_get_transceiver();
  328. if (!musb->xceiv)
  329. return -ENODEV;
  330. musb->mregs += DAVINCI_BASE_OFFSET;
  331. /* returns zero if e.g. not clocked */
  332. revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG);
  333. if (revision == 0)
  334. goto fail;
  335. if (is_host_enabled(musb))
  336. setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
  337. davinci_musb_source_power(musb, 0, 1);
  338. /* dm355 EVM swaps D+/D- for signal integrity, and
  339. * is clocked from the main 24 MHz crystal.
  340. */
  341. if (machine_is_davinci_dm355_evm()) {
  342. u32 phy_ctrl = __raw_readl(USB_PHY_CTRL);
  343. phy_ctrl &= ~(3 << 9);
  344. phy_ctrl |= USBPHY_DATAPOL;
  345. __raw_writel(phy_ctrl, USB_PHY_CTRL);
  346. }
  347. /* On dm355, the default-A state machine needs DRVVBUS control.
  348. * If we won't be a host, there's no need to turn it on.
  349. */
  350. if (cpu_is_davinci_dm355()) {
  351. u32 deepsleep = __raw_readl(DM355_DEEPSLEEP);
  352. if (is_host_enabled(musb)) {
  353. deepsleep &= ~DRVVBUS_OVERRIDE;
  354. } else {
  355. deepsleep &= ~DRVVBUS_FORCE;
  356. deepsleep |= DRVVBUS_OVERRIDE;
  357. }
  358. __raw_writel(deepsleep, DM355_DEEPSLEEP);
  359. }
  360. /* reset the controller */
  361. musb_writel(tibase, DAVINCI_USB_CTRL_REG, 0x1);
  362. /* start the on-chip PHY and its PLL */
  363. phy_on();
  364. msleep(5);
  365. /* NOTE: irqs are in mixed mode, not bypass to pure-musb */
  366. pr_debug("DaVinci OTG revision %08x phy %03x control %02x\n",
  367. revision, __raw_readl(USB_PHY_CTRL),
  368. musb_readb(tibase, DAVINCI_USB_CTRL_REG));
  369. musb->isr = davinci_musb_interrupt;
  370. return 0;
  371. fail:
  372. otg_put_transceiver(musb->xceiv);
  373. usb_nop_xceiv_unregister();
  374. return -ENODEV;
  375. }
  376. static int davinci_musb_exit(struct musb *musb)
  377. {
  378. if (is_host_enabled(musb))
  379. del_timer_sync(&otg_workaround);
  380. /* force VBUS off */
  381. if (cpu_is_davinci_dm355()) {
  382. u32 deepsleep = __raw_readl(DM355_DEEPSLEEP);
  383. deepsleep &= ~DRVVBUS_FORCE;
  384. deepsleep |= DRVVBUS_OVERRIDE;
  385. __raw_writel(deepsleep, DM355_DEEPSLEEP);
  386. }
  387. davinci_musb_source_power(musb, 0 /*off*/, 1);
  388. /* delay, to avoid problems with module reload */
  389. if (is_host_enabled(musb) && musb->xceiv->default_a) {
  390. int maxdelay = 30;
  391. u8 devctl, warn = 0;
  392. /* if there's no peripheral connected, this can take a
  393. * long time to fall, especially on EVM with huge C133.
  394. */
  395. do {
  396. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  397. if (!(devctl & MUSB_DEVCTL_VBUS))
  398. break;
  399. if ((devctl & MUSB_DEVCTL_VBUS) != warn) {
  400. warn = devctl & MUSB_DEVCTL_VBUS;
  401. dev_dbg(musb->controller, "VBUS %d\n",
  402. warn >> MUSB_DEVCTL_VBUS_SHIFT);
  403. }
  404. msleep(1000);
  405. maxdelay--;
  406. } while (maxdelay > 0);
  407. /* in OTG mode, another host might be connected */
  408. if (devctl & MUSB_DEVCTL_VBUS)
  409. dev_dbg(musb->controller, "VBUS off timeout (devctl %02x)\n", devctl);
  410. }
  411. phy_off();
  412. otg_put_transceiver(musb->xceiv);
  413. usb_nop_xceiv_unregister();
  414. return 0;
  415. }
  416. static const struct musb_platform_ops davinci_ops = {
  417. .init = davinci_musb_init,
  418. .exit = davinci_musb_exit,
  419. .enable = davinci_musb_enable,
  420. .disable = davinci_musb_disable,
  421. .set_mode = davinci_musb_set_mode,
  422. .set_vbus = davinci_musb_set_vbus,
  423. };
  424. static u64 davinci_dmamask = DMA_BIT_MASK(32);
  425. static int __init davinci_probe(struct platform_device *pdev)
  426. {
  427. struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
  428. struct platform_device *musb;
  429. struct davinci_glue *glue;
  430. struct clk *clk;
  431. int ret = -ENOMEM;
  432. glue = kzalloc(sizeof(*glue), GFP_KERNEL);
  433. if (!glue) {
  434. dev_err(&pdev->dev, "failed to allocate glue context\n");
  435. goto err0;
  436. }
  437. musb = platform_device_alloc("musb-hdrc", -1);
  438. if (!musb) {
  439. dev_err(&pdev->dev, "failed to allocate musb device\n");
  440. goto err1;
  441. }
  442. clk = clk_get(&pdev->dev, "usb");
  443. if (IS_ERR(clk)) {
  444. dev_err(&pdev->dev, "failed to get clock\n");
  445. ret = PTR_ERR(clk);
  446. goto err2;
  447. }
  448. ret = clk_enable(clk);
  449. if (ret) {
  450. dev_err(&pdev->dev, "failed to enable clock\n");
  451. goto err3;
  452. }
  453. musb->dev.parent = &pdev->dev;
  454. musb->dev.dma_mask = &davinci_dmamask;
  455. musb->dev.coherent_dma_mask = davinci_dmamask;
  456. glue->dev = &pdev->dev;
  457. glue->musb = musb;
  458. glue->clk = clk;
  459. pdata->platform_ops = &davinci_ops;
  460. platform_set_drvdata(pdev, glue);
  461. ret = platform_device_add_resources(musb, pdev->resource,
  462. pdev->num_resources);
  463. if (ret) {
  464. dev_err(&pdev->dev, "failed to add resources\n");
  465. goto err4;
  466. }
  467. ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
  468. if (ret) {
  469. dev_err(&pdev->dev, "failed to add platform_data\n");
  470. goto err4;
  471. }
  472. ret = platform_device_add(musb);
  473. if (ret) {
  474. dev_err(&pdev->dev, "failed to register musb device\n");
  475. goto err4;
  476. }
  477. return 0;
  478. err4:
  479. clk_disable(clk);
  480. err3:
  481. clk_put(clk);
  482. err2:
  483. platform_device_put(musb);
  484. err1:
  485. kfree(glue);
  486. err0:
  487. return ret;
  488. }
  489. static int __exit davinci_remove(struct platform_device *pdev)
  490. {
  491. struct davinci_glue *glue = platform_get_drvdata(pdev);
  492. platform_device_del(glue->musb);
  493. platform_device_put(glue->musb);
  494. clk_disable(glue->clk);
  495. clk_put(glue->clk);
  496. kfree(glue);
  497. return 0;
  498. }
  499. static struct platform_driver davinci_driver = {
  500. .remove = __exit_p(davinci_remove),
  501. .driver = {
  502. .name = "musb-davinci",
  503. },
  504. };
  505. MODULE_DESCRIPTION("DaVinci MUSB Glue Layer");
  506. MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
  507. MODULE_LICENSE("GPL v2");
  508. static int __init davinci_init(void)
  509. {
  510. return platform_driver_probe(&davinci_driver, davinci_probe);
  511. }
  512. subsys_initcall(davinci_init);
  513. static void __exit davinci_exit(void)
  514. {
  515. platform_driver_unregister(&davinci_driver);
  516. }
  517. module_exit(davinci_exit);