xhci-mem.c 71 KB

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  1. /*
  2. * xHCI host controller driver
  3. *
  4. * Copyright (C) 2008 Intel Corp.
  5. *
  6. * Author: Sarah Sharp
  7. * Some code borrowed from the Linux EHCI driver.
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope that it will be useful, but
  14. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  16. * for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software Foundation,
  20. * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21. */
  22. #include <linux/usb.h>
  23. #include <linux/pci.h>
  24. #include <linux/slab.h>
  25. #include <linux/dmapool.h>
  26. #include "xhci.h"
  27. /*
  28. * Allocates a generic ring segment from the ring pool, sets the dma address,
  29. * initializes the segment to zero, and sets the private next pointer to NULL.
  30. *
  31. * Section 4.11.1.1:
  32. * "All components of all Command and Transfer TRBs shall be initialized to '0'"
  33. */
  34. static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci, gfp_t flags)
  35. {
  36. struct xhci_segment *seg;
  37. dma_addr_t dma;
  38. seg = kzalloc(sizeof *seg, flags);
  39. if (!seg)
  40. return NULL;
  41. seg->trbs = dma_pool_alloc(xhci->segment_pool, flags, &dma);
  42. if (!seg->trbs) {
  43. kfree(seg);
  44. return NULL;
  45. }
  46. memset(seg->trbs, 0, SEGMENT_SIZE);
  47. seg->dma = dma;
  48. seg->next = NULL;
  49. return seg;
  50. }
  51. static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
  52. {
  53. if (seg->trbs) {
  54. dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
  55. seg->trbs = NULL;
  56. }
  57. kfree(seg);
  58. }
  59. /*
  60. * Make the prev segment point to the next segment.
  61. *
  62. * Change the last TRB in the prev segment to be a Link TRB which points to the
  63. * DMA address of the next segment. The caller needs to set any Link TRB
  64. * related flags, such as End TRB, Toggle Cycle, and no snoop.
  65. */
  66. static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev,
  67. struct xhci_segment *next, bool link_trbs, bool isoc)
  68. {
  69. u32 val;
  70. if (!prev || !next)
  71. return;
  72. prev->next = next;
  73. if (link_trbs) {
  74. prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr =
  75. cpu_to_le64(next->dma);
  76. /* Set the last TRB in the segment to have a TRB type ID of Link TRB */
  77. val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control);
  78. val &= ~TRB_TYPE_BITMASK;
  79. val |= TRB_TYPE(TRB_LINK);
  80. /* Always set the chain bit with 0.95 hardware */
  81. /* Set chain bit for isoc rings on AMD 0.96 host */
  82. if (xhci_link_trb_quirk(xhci) ||
  83. (isoc && (xhci->quirks & XHCI_AMD_0x96_HOST)))
  84. val |= TRB_CHAIN;
  85. prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val);
  86. }
  87. }
  88. /* XXX: Do we need the hcd structure in all these functions? */
  89. void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring)
  90. {
  91. struct xhci_segment *seg;
  92. struct xhci_segment *first_seg;
  93. if (!ring)
  94. return;
  95. if (ring->first_seg) {
  96. first_seg = ring->first_seg;
  97. seg = first_seg->next;
  98. while (seg != first_seg) {
  99. struct xhci_segment *next = seg->next;
  100. xhci_segment_free(xhci, seg);
  101. seg = next;
  102. }
  103. xhci_segment_free(xhci, first_seg);
  104. ring->first_seg = NULL;
  105. }
  106. kfree(ring);
  107. }
  108. static void xhci_initialize_ring_info(struct xhci_ring *ring)
  109. {
  110. /* The ring is empty, so the enqueue pointer == dequeue pointer */
  111. ring->enqueue = ring->first_seg->trbs;
  112. ring->enq_seg = ring->first_seg;
  113. ring->dequeue = ring->enqueue;
  114. ring->deq_seg = ring->first_seg;
  115. /* The ring is initialized to 0. The producer must write 1 to the cycle
  116. * bit to handover ownership of the TRB, so PCS = 1. The consumer must
  117. * compare CCS to the cycle bit to check ownership, so CCS = 1.
  118. */
  119. ring->cycle_state = 1;
  120. /* Not necessary for new rings, but needed for re-initialized rings */
  121. ring->enq_updates = 0;
  122. ring->deq_updates = 0;
  123. }
  124. /**
  125. * Create a new ring with zero or more segments.
  126. *
  127. * Link each segment together into a ring.
  128. * Set the end flag and the cycle toggle bit on the last segment.
  129. * See section 4.9.1 and figures 15 and 16.
  130. */
  131. static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
  132. unsigned int num_segs, bool link_trbs, bool isoc, gfp_t flags)
  133. {
  134. struct xhci_ring *ring;
  135. struct xhci_segment *prev;
  136. ring = kzalloc(sizeof *(ring), flags);
  137. if (!ring)
  138. return NULL;
  139. INIT_LIST_HEAD(&ring->td_list);
  140. if (num_segs == 0)
  141. return ring;
  142. ring->first_seg = xhci_segment_alloc(xhci, flags);
  143. if (!ring->first_seg)
  144. goto fail;
  145. num_segs--;
  146. prev = ring->first_seg;
  147. while (num_segs > 0) {
  148. struct xhci_segment *next;
  149. next = xhci_segment_alloc(xhci, flags);
  150. if (!next)
  151. goto fail;
  152. xhci_link_segments(xhci, prev, next, link_trbs, isoc);
  153. prev = next;
  154. num_segs--;
  155. }
  156. xhci_link_segments(xhci, prev, ring->first_seg, link_trbs, isoc);
  157. if (link_trbs) {
  158. /* See section 4.9.2.1 and 6.4.4.1 */
  159. prev->trbs[TRBS_PER_SEGMENT-1].link.control |=
  160. cpu_to_le32(LINK_TOGGLE);
  161. }
  162. xhci_initialize_ring_info(ring);
  163. return ring;
  164. fail:
  165. xhci_ring_free(xhci, ring);
  166. return NULL;
  167. }
  168. void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
  169. struct xhci_virt_device *virt_dev,
  170. unsigned int ep_index)
  171. {
  172. int rings_cached;
  173. rings_cached = virt_dev->num_rings_cached;
  174. if (rings_cached < XHCI_MAX_RINGS_CACHED) {
  175. virt_dev->ring_cache[rings_cached] =
  176. virt_dev->eps[ep_index].ring;
  177. virt_dev->num_rings_cached++;
  178. xhci_dbg(xhci, "Cached old ring, "
  179. "%d ring%s cached\n",
  180. virt_dev->num_rings_cached,
  181. (virt_dev->num_rings_cached > 1) ? "s" : "");
  182. } else {
  183. xhci_ring_free(xhci, virt_dev->eps[ep_index].ring);
  184. xhci_dbg(xhci, "Ring cache full (%d rings), "
  185. "freeing ring\n",
  186. virt_dev->num_rings_cached);
  187. }
  188. virt_dev->eps[ep_index].ring = NULL;
  189. }
  190. /* Zero an endpoint ring (except for link TRBs) and move the enqueue and dequeue
  191. * pointers to the beginning of the ring.
  192. */
  193. static void xhci_reinit_cached_ring(struct xhci_hcd *xhci,
  194. struct xhci_ring *ring, bool isoc)
  195. {
  196. struct xhci_segment *seg = ring->first_seg;
  197. do {
  198. memset(seg->trbs, 0,
  199. sizeof(union xhci_trb)*TRBS_PER_SEGMENT);
  200. /* All endpoint rings have link TRBs */
  201. xhci_link_segments(xhci, seg, seg->next, 1, isoc);
  202. seg = seg->next;
  203. } while (seg != ring->first_seg);
  204. xhci_initialize_ring_info(ring);
  205. /* td list should be empty since all URBs have been cancelled,
  206. * but just in case...
  207. */
  208. INIT_LIST_HEAD(&ring->td_list);
  209. }
  210. #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
  211. static struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
  212. int type, gfp_t flags)
  213. {
  214. struct xhci_container_ctx *ctx = kzalloc(sizeof(*ctx), flags);
  215. if (!ctx)
  216. return NULL;
  217. BUG_ON((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT));
  218. ctx->type = type;
  219. ctx->size = HCC_64BYTE_CONTEXT(xhci->hcc_params) ? 2048 : 1024;
  220. if (type == XHCI_CTX_TYPE_INPUT)
  221. ctx->size += CTX_SIZE(xhci->hcc_params);
  222. ctx->bytes = dma_pool_alloc(xhci->device_pool, flags, &ctx->dma);
  223. memset(ctx->bytes, 0, ctx->size);
  224. return ctx;
  225. }
  226. static void xhci_free_container_ctx(struct xhci_hcd *xhci,
  227. struct xhci_container_ctx *ctx)
  228. {
  229. if (!ctx)
  230. return;
  231. dma_pool_free(xhci->device_pool, ctx->bytes, ctx->dma);
  232. kfree(ctx);
  233. }
  234. struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci,
  235. struct xhci_container_ctx *ctx)
  236. {
  237. BUG_ON(ctx->type != XHCI_CTX_TYPE_INPUT);
  238. return (struct xhci_input_control_ctx *)ctx->bytes;
  239. }
  240. struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci,
  241. struct xhci_container_ctx *ctx)
  242. {
  243. if (ctx->type == XHCI_CTX_TYPE_DEVICE)
  244. return (struct xhci_slot_ctx *)ctx->bytes;
  245. return (struct xhci_slot_ctx *)
  246. (ctx->bytes + CTX_SIZE(xhci->hcc_params));
  247. }
  248. struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci,
  249. struct xhci_container_ctx *ctx,
  250. unsigned int ep_index)
  251. {
  252. /* increment ep index by offset of start of ep ctx array */
  253. ep_index++;
  254. if (ctx->type == XHCI_CTX_TYPE_INPUT)
  255. ep_index++;
  256. return (struct xhci_ep_ctx *)
  257. (ctx->bytes + (ep_index * CTX_SIZE(xhci->hcc_params)));
  258. }
  259. /***************** Streams structures manipulation *************************/
  260. static void xhci_free_stream_ctx(struct xhci_hcd *xhci,
  261. unsigned int num_stream_ctxs,
  262. struct xhci_stream_ctx *stream_ctx, dma_addr_t dma)
  263. {
  264. struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
  265. if (num_stream_ctxs > MEDIUM_STREAM_ARRAY_SIZE)
  266. dma_free_coherent(&pdev->dev,
  267. sizeof(struct xhci_stream_ctx)*num_stream_ctxs,
  268. stream_ctx, dma);
  269. else if (num_stream_ctxs <= SMALL_STREAM_ARRAY_SIZE)
  270. return dma_pool_free(xhci->small_streams_pool,
  271. stream_ctx, dma);
  272. else
  273. return dma_pool_free(xhci->medium_streams_pool,
  274. stream_ctx, dma);
  275. }
  276. /*
  277. * The stream context array for each endpoint with bulk streams enabled can
  278. * vary in size, based on:
  279. * - how many streams the endpoint supports,
  280. * - the maximum primary stream array size the host controller supports,
  281. * - and how many streams the device driver asks for.
  282. *
  283. * The stream context array must be a power of 2, and can be as small as
  284. * 64 bytes or as large as 1MB.
  285. */
  286. static struct xhci_stream_ctx *xhci_alloc_stream_ctx(struct xhci_hcd *xhci,
  287. unsigned int num_stream_ctxs, dma_addr_t *dma,
  288. gfp_t mem_flags)
  289. {
  290. struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
  291. if (num_stream_ctxs > MEDIUM_STREAM_ARRAY_SIZE)
  292. return dma_alloc_coherent(&pdev->dev,
  293. sizeof(struct xhci_stream_ctx)*num_stream_ctxs,
  294. dma, mem_flags);
  295. else if (num_stream_ctxs <= SMALL_STREAM_ARRAY_SIZE)
  296. return dma_pool_alloc(xhci->small_streams_pool,
  297. mem_flags, dma);
  298. else
  299. return dma_pool_alloc(xhci->medium_streams_pool,
  300. mem_flags, dma);
  301. }
  302. struct xhci_ring *xhci_dma_to_transfer_ring(
  303. struct xhci_virt_ep *ep,
  304. u64 address)
  305. {
  306. if (ep->ep_state & EP_HAS_STREAMS)
  307. return radix_tree_lookup(&ep->stream_info->trb_address_map,
  308. address >> SEGMENT_SHIFT);
  309. return ep->ring;
  310. }
  311. /* Only use this when you know stream_info is valid */
  312. #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
  313. static struct xhci_ring *dma_to_stream_ring(
  314. struct xhci_stream_info *stream_info,
  315. u64 address)
  316. {
  317. return radix_tree_lookup(&stream_info->trb_address_map,
  318. address >> SEGMENT_SHIFT);
  319. }
  320. #endif /* CONFIG_USB_XHCI_HCD_DEBUGGING */
  321. struct xhci_ring *xhci_stream_id_to_ring(
  322. struct xhci_virt_device *dev,
  323. unsigned int ep_index,
  324. unsigned int stream_id)
  325. {
  326. struct xhci_virt_ep *ep = &dev->eps[ep_index];
  327. if (stream_id == 0)
  328. return ep->ring;
  329. if (!ep->stream_info)
  330. return NULL;
  331. if (stream_id > ep->stream_info->num_streams)
  332. return NULL;
  333. return ep->stream_info->stream_rings[stream_id];
  334. }
  335. #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
  336. static int xhci_test_radix_tree(struct xhci_hcd *xhci,
  337. unsigned int num_streams,
  338. struct xhci_stream_info *stream_info)
  339. {
  340. u32 cur_stream;
  341. struct xhci_ring *cur_ring;
  342. u64 addr;
  343. for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
  344. struct xhci_ring *mapped_ring;
  345. int trb_size = sizeof(union xhci_trb);
  346. cur_ring = stream_info->stream_rings[cur_stream];
  347. for (addr = cur_ring->first_seg->dma;
  348. addr < cur_ring->first_seg->dma + SEGMENT_SIZE;
  349. addr += trb_size) {
  350. mapped_ring = dma_to_stream_ring(stream_info, addr);
  351. if (cur_ring != mapped_ring) {
  352. xhci_warn(xhci, "WARN: DMA address 0x%08llx "
  353. "didn't map to stream ID %u; "
  354. "mapped to ring %p\n",
  355. (unsigned long long) addr,
  356. cur_stream,
  357. mapped_ring);
  358. return -EINVAL;
  359. }
  360. }
  361. /* One TRB after the end of the ring segment shouldn't return a
  362. * pointer to the current ring (although it may be a part of a
  363. * different ring).
  364. */
  365. mapped_ring = dma_to_stream_ring(stream_info, addr);
  366. if (mapped_ring != cur_ring) {
  367. /* One TRB before should also fail */
  368. addr = cur_ring->first_seg->dma - trb_size;
  369. mapped_ring = dma_to_stream_ring(stream_info, addr);
  370. }
  371. if (mapped_ring == cur_ring) {
  372. xhci_warn(xhci, "WARN: Bad DMA address 0x%08llx "
  373. "mapped to valid stream ID %u; "
  374. "mapped ring = %p\n",
  375. (unsigned long long) addr,
  376. cur_stream,
  377. mapped_ring);
  378. return -EINVAL;
  379. }
  380. }
  381. return 0;
  382. }
  383. #endif /* CONFIG_USB_XHCI_HCD_DEBUGGING */
  384. /*
  385. * Change an endpoint's internal structure so it supports stream IDs. The
  386. * number of requested streams includes stream 0, which cannot be used by device
  387. * drivers.
  388. *
  389. * The number of stream contexts in the stream context array may be bigger than
  390. * the number of streams the driver wants to use. This is because the number of
  391. * stream context array entries must be a power of two.
  392. *
  393. * We need a radix tree for mapping physical addresses of TRBs to which stream
  394. * ID they belong to. We need to do this because the host controller won't tell
  395. * us which stream ring the TRB came from. We could store the stream ID in an
  396. * event data TRB, but that doesn't help us for the cancellation case, since the
  397. * endpoint may stop before it reaches that event data TRB.
  398. *
  399. * The radix tree maps the upper portion of the TRB DMA address to a ring
  400. * segment that has the same upper portion of DMA addresses. For example, say I
  401. * have segments of size 1KB, that are always 64-byte aligned. A segment may
  402. * start at 0x10c91000 and end at 0x10c913f0. If I use the upper 10 bits, the
  403. * key to the stream ID is 0x43244. I can use the DMA address of the TRB to
  404. * pass the radix tree a key to get the right stream ID:
  405. *
  406. * 0x10c90fff >> 10 = 0x43243
  407. * 0x10c912c0 >> 10 = 0x43244
  408. * 0x10c91400 >> 10 = 0x43245
  409. *
  410. * Obviously, only those TRBs with DMA addresses that are within the segment
  411. * will make the radix tree return the stream ID for that ring.
  412. *
  413. * Caveats for the radix tree:
  414. *
  415. * The radix tree uses an unsigned long as a key pair. On 32-bit systems, an
  416. * unsigned long will be 32-bits; on a 64-bit system an unsigned long will be
  417. * 64-bits. Since we only request 32-bit DMA addresses, we can use that as the
  418. * key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit
  419. * PCI DMA addresses on a 64-bit system). There might be a problem on 32-bit
  420. * extended systems (where the DMA address can be bigger than 32-bits),
  421. * if we allow the PCI dma mask to be bigger than 32-bits. So don't do that.
  422. */
  423. struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
  424. unsigned int num_stream_ctxs,
  425. unsigned int num_streams, gfp_t mem_flags)
  426. {
  427. struct xhci_stream_info *stream_info;
  428. u32 cur_stream;
  429. struct xhci_ring *cur_ring;
  430. unsigned long key;
  431. u64 addr;
  432. int ret;
  433. xhci_dbg(xhci, "Allocating %u streams and %u "
  434. "stream context array entries.\n",
  435. num_streams, num_stream_ctxs);
  436. if (xhci->cmd_ring_reserved_trbs == MAX_RSVD_CMD_TRBS) {
  437. xhci_dbg(xhci, "Command ring has no reserved TRBs available\n");
  438. return NULL;
  439. }
  440. xhci->cmd_ring_reserved_trbs++;
  441. stream_info = kzalloc(sizeof(struct xhci_stream_info), mem_flags);
  442. if (!stream_info)
  443. goto cleanup_trbs;
  444. stream_info->num_streams = num_streams;
  445. stream_info->num_stream_ctxs = num_stream_ctxs;
  446. /* Initialize the array of virtual pointers to stream rings. */
  447. stream_info->stream_rings = kzalloc(
  448. sizeof(struct xhci_ring *)*num_streams,
  449. mem_flags);
  450. if (!stream_info->stream_rings)
  451. goto cleanup_info;
  452. /* Initialize the array of DMA addresses for stream rings for the HW. */
  453. stream_info->stream_ctx_array = xhci_alloc_stream_ctx(xhci,
  454. num_stream_ctxs, &stream_info->ctx_array_dma,
  455. mem_flags);
  456. if (!stream_info->stream_ctx_array)
  457. goto cleanup_ctx;
  458. memset(stream_info->stream_ctx_array, 0,
  459. sizeof(struct xhci_stream_ctx)*num_stream_ctxs);
  460. /* Allocate everything needed to free the stream rings later */
  461. stream_info->free_streams_command =
  462. xhci_alloc_command(xhci, true, true, mem_flags);
  463. if (!stream_info->free_streams_command)
  464. goto cleanup_ctx;
  465. INIT_RADIX_TREE(&stream_info->trb_address_map, GFP_ATOMIC);
  466. /* Allocate rings for all the streams that the driver will use,
  467. * and add their segment DMA addresses to the radix tree.
  468. * Stream 0 is reserved.
  469. */
  470. for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
  471. stream_info->stream_rings[cur_stream] =
  472. xhci_ring_alloc(xhci, 1, true, false, mem_flags);
  473. cur_ring = stream_info->stream_rings[cur_stream];
  474. if (!cur_ring)
  475. goto cleanup_rings;
  476. cur_ring->stream_id = cur_stream;
  477. /* Set deq ptr, cycle bit, and stream context type */
  478. addr = cur_ring->first_seg->dma |
  479. SCT_FOR_CTX(SCT_PRI_TR) |
  480. cur_ring->cycle_state;
  481. stream_info->stream_ctx_array[cur_stream].stream_ring =
  482. cpu_to_le64(addr);
  483. xhci_dbg(xhci, "Setting stream %d ring ptr to 0x%08llx\n",
  484. cur_stream, (unsigned long long) addr);
  485. key = (unsigned long)
  486. (cur_ring->first_seg->dma >> SEGMENT_SHIFT);
  487. ret = radix_tree_insert(&stream_info->trb_address_map,
  488. key, cur_ring);
  489. if (ret) {
  490. xhci_ring_free(xhci, cur_ring);
  491. stream_info->stream_rings[cur_stream] = NULL;
  492. goto cleanup_rings;
  493. }
  494. }
  495. /* Leave the other unused stream ring pointers in the stream context
  496. * array initialized to zero. This will cause the xHC to give us an
  497. * error if the device asks for a stream ID we don't have setup (if it
  498. * was any other way, the host controller would assume the ring is
  499. * "empty" and wait forever for data to be queued to that stream ID).
  500. */
  501. #if XHCI_DEBUG
  502. /* Do a little test on the radix tree to make sure it returns the
  503. * correct values.
  504. */
  505. if (xhci_test_radix_tree(xhci, num_streams, stream_info))
  506. goto cleanup_rings;
  507. #endif
  508. return stream_info;
  509. cleanup_rings:
  510. for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
  511. cur_ring = stream_info->stream_rings[cur_stream];
  512. if (cur_ring) {
  513. addr = cur_ring->first_seg->dma;
  514. radix_tree_delete(&stream_info->trb_address_map,
  515. addr >> SEGMENT_SHIFT);
  516. xhci_ring_free(xhci, cur_ring);
  517. stream_info->stream_rings[cur_stream] = NULL;
  518. }
  519. }
  520. xhci_free_command(xhci, stream_info->free_streams_command);
  521. cleanup_ctx:
  522. kfree(stream_info->stream_rings);
  523. cleanup_info:
  524. kfree(stream_info);
  525. cleanup_trbs:
  526. xhci->cmd_ring_reserved_trbs--;
  527. return NULL;
  528. }
  529. /*
  530. * Sets the MaxPStreams field and the Linear Stream Array field.
  531. * Sets the dequeue pointer to the stream context array.
  532. */
  533. void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
  534. struct xhci_ep_ctx *ep_ctx,
  535. struct xhci_stream_info *stream_info)
  536. {
  537. u32 max_primary_streams;
  538. /* MaxPStreams is the number of stream context array entries, not the
  539. * number we're actually using. Must be in 2^(MaxPstreams + 1) format.
  540. * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc.
  541. */
  542. max_primary_streams = fls(stream_info->num_stream_ctxs) - 2;
  543. xhci_dbg(xhci, "Setting number of stream ctx array entries to %u\n",
  544. 1 << (max_primary_streams + 1));
  545. ep_ctx->ep_info &= cpu_to_le32(~EP_MAXPSTREAMS_MASK);
  546. ep_ctx->ep_info |= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams)
  547. | EP_HAS_LSA);
  548. ep_ctx->deq = cpu_to_le64(stream_info->ctx_array_dma);
  549. }
  550. /*
  551. * Sets the MaxPStreams field and the Linear Stream Array field to 0.
  552. * Reinstalls the "normal" endpoint ring (at its previous dequeue mark,
  553. * not at the beginning of the ring).
  554. */
  555. void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci,
  556. struct xhci_ep_ctx *ep_ctx,
  557. struct xhci_virt_ep *ep)
  558. {
  559. dma_addr_t addr;
  560. ep_ctx->ep_info &= cpu_to_le32(~(EP_MAXPSTREAMS_MASK | EP_HAS_LSA));
  561. addr = xhci_trb_virt_to_dma(ep->ring->deq_seg, ep->ring->dequeue);
  562. ep_ctx->deq = cpu_to_le64(addr | ep->ring->cycle_state);
  563. }
  564. /* Frees all stream contexts associated with the endpoint,
  565. *
  566. * Caller should fix the endpoint context streams fields.
  567. */
  568. void xhci_free_stream_info(struct xhci_hcd *xhci,
  569. struct xhci_stream_info *stream_info)
  570. {
  571. int cur_stream;
  572. struct xhci_ring *cur_ring;
  573. dma_addr_t addr;
  574. if (!stream_info)
  575. return;
  576. for (cur_stream = 1; cur_stream < stream_info->num_streams;
  577. cur_stream++) {
  578. cur_ring = stream_info->stream_rings[cur_stream];
  579. if (cur_ring) {
  580. addr = cur_ring->first_seg->dma;
  581. radix_tree_delete(&stream_info->trb_address_map,
  582. addr >> SEGMENT_SHIFT);
  583. xhci_ring_free(xhci, cur_ring);
  584. stream_info->stream_rings[cur_stream] = NULL;
  585. }
  586. }
  587. xhci_free_command(xhci, stream_info->free_streams_command);
  588. xhci->cmd_ring_reserved_trbs--;
  589. if (stream_info->stream_ctx_array)
  590. xhci_free_stream_ctx(xhci,
  591. stream_info->num_stream_ctxs,
  592. stream_info->stream_ctx_array,
  593. stream_info->ctx_array_dma);
  594. if (stream_info)
  595. kfree(stream_info->stream_rings);
  596. kfree(stream_info);
  597. }
  598. /***************** Device context manipulation *************************/
  599. static void xhci_init_endpoint_timer(struct xhci_hcd *xhci,
  600. struct xhci_virt_ep *ep)
  601. {
  602. init_timer(&ep->stop_cmd_timer);
  603. ep->stop_cmd_timer.data = (unsigned long) ep;
  604. ep->stop_cmd_timer.function = xhci_stop_endpoint_command_watchdog;
  605. ep->xhci = xhci;
  606. }
  607. static void xhci_free_tt_info(struct xhci_hcd *xhci,
  608. struct xhci_virt_device *virt_dev,
  609. int slot_id)
  610. {
  611. struct list_head *tt;
  612. struct list_head *tt_list_head;
  613. struct list_head *tt_next;
  614. struct xhci_tt_bw_info *tt_info;
  615. /* If the device never made it past the Set Address stage,
  616. * it may not have the real_port set correctly.
  617. */
  618. if (virt_dev->real_port == 0 ||
  619. virt_dev->real_port > HCS_MAX_PORTS(xhci->hcs_params1)) {
  620. xhci_dbg(xhci, "Bad real port.\n");
  621. return;
  622. }
  623. tt_list_head = &(xhci->rh_bw[virt_dev->real_port - 1].tts);
  624. if (list_empty(tt_list_head))
  625. return;
  626. list_for_each(tt, tt_list_head) {
  627. tt_info = list_entry(tt, struct xhci_tt_bw_info, tt_list);
  628. if (tt_info->slot_id == slot_id)
  629. break;
  630. }
  631. /* Cautionary measure in case the hub was disconnected before we
  632. * stored the TT information.
  633. */
  634. if (tt_info->slot_id != slot_id)
  635. return;
  636. tt_next = tt->next;
  637. tt_info = list_entry(tt, struct xhci_tt_bw_info,
  638. tt_list);
  639. /* Multi-TT hubs will have more than one entry */
  640. do {
  641. list_del(tt);
  642. kfree(tt_info);
  643. tt = tt_next;
  644. if (list_empty(tt_list_head))
  645. break;
  646. tt_next = tt->next;
  647. tt_info = list_entry(tt, struct xhci_tt_bw_info,
  648. tt_list);
  649. } while (tt_info->slot_id == slot_id);
  650. }
  651. int xhci_alloc_tt_info(struct xhci_hcd *xhci,
  652. struct xhci_virt_device *virt_dev,
  653. struct usb_device *hdev,
  654. struct usb_tt *tt, gfp_t mem_flags)
  655. {
  656. struct xhci_tt_bw_info *tt_info;
  657. unsigned int num_ports;
  658. int i, j;
  659. if (!tt->multi)
  660. num_ports = 1;
  661. else
  662. num_ports = hdev->maxchild;
  663. for (i = 0; i < num_ports; i++, tt_info++) {
  664. struct xhci_interval_bw_table *bw_table;
  665. tt_info = kzalloc(sizeof(*tt_info), mem_flags);
  666. if (!tt_info)
  667. goto free_tts;
  668. INIT_LIST_HEAD(&tt_info->tt_list);
  669. list_add(&tt_info->tt_list,
  670. &xhci->rh_bw[virt_dev->real_port - 1].tts);
  671. tt_info->slot_id = virt_dev->udev->slot_id;
  672. if (tt->multi)
  673. tt_info->ttport = i+1;
  674. bw_table = &tt_info->bw_table;
  675. for (j = 0; j < XHCI_MAX_INTERVAL; j++)
  676. INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
  677. }
  678. return 0;
  679. free_tts:
  680. xhci_free_tt_info(xhci, virt_dev, virt_dev->udev->slot_id);
  681. return -ENOMEM;
  682. }
  683. /* All the xhci_tds in the ring's TD list should be freed at this point.
  684. * Should be called with xhci->lock held if there is any chance the TT lists
  685. * will be manipulated by the configure endpoint, allocate device, or update
  686. * hub functions while this function is removing the TT entries from the list.
  687. */
  688. void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id)
  689. {
  690. struct xhci_virt_device *dev;
  691. int i;
  692. int old_active_eps = 0;
  693. /* Slot ID 0 is reserved */
  694. if (slot_id == 0 || !xhci->devs[slot_id])
  695. return;
  696. dev = xhci->devs[slot_id];
  697. xhci->dcbaa->dev_context_ptrs[slot_id] = 0;
  698. if (!dev)
  699. return;
  700. if (dev->tt_info)
  701. old_active_eps = dev->tt_info->active_eps;
  702. for (i = 0; i < 31; ++i) {
  703. if (dev->eps[i].ring)
  704. xhci_ring_free(xhci, dev->eps[i].ring);
  705. if (dev->eps[i].stream_info)
  706. xhci_free_stream_info(xhci,
  707. dev->eps[i].stream_info);
  708. /* Endpoints on the TT/root port lists should have been removed
  709. * when usb_disable_device() was called for the device.
  710. * We can't drop them anyway, because the udev might have gone
  711. * away by this point, and we can't tell what speed it was.
  712. */
  713. if (!list_empty(&dev->eps[i].bw_endpoint_list))
  714. xhci_warn(xhci, "Slot %u endpoint %u "
  715. "not removed from BW list!\n",
  716. slot_id, i);
  717. }
  718. /* If this is a hub, free the TT(s) from the TT list */
  719. xhci_free_tt_info(xhci, dev, slot_id);
  720. /* If necessary, update the number of active TTs on this root port */
  721. xhci_update_tt_active_eps(xhci, dev, old_active_eps);
  722. if (dev->ring_cache) {
  723. for (i = 0; i < dev->num_rings_cached; i++)
  724. xhci_ring_free(xhci, dev->ring_cache[i]);
  725. kfree(dev->ring_cache);
  726. }
  727. if (dev->in_ctx)
  728. xhci_free_container_ctx(xhci, dev->in_ctx);
  729. if (dev->out_ctx)
  730. xhci_free_container_ctx(xhci, dev->out_ctx);
  731. kfree(xhci->devs[slot_id]);
  732. xhci->devs[slot_id] = NULL;
  733. }
  734. int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id,
  735. struct usb_device *udev, gfp_t flags)
  736. {
  737. struct xhci_virt_device *dev;
  738. int i;
  739. /* Slot ID 0 is reserved */
  740. if (slot_id == 0 || xhci->devs[slot_id]) {
  741. xhci_warn(xhci, "Bad Slot ID %d\n", slot_id);
  742. return 0;
  743. }
  744. xhci->devs[slot_id] = kzalloc(sizeof(*xhci->devs[slot_id]), flags);
  745. if (!xhci->devs[slot_id])
  746. return 0;
  747. dev = xhci->devs[slot_id];
  748. /* Allocate the (output) device context that will be used in the HC. */
  749. dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags);
  750. if (!dev->out_ctx)
  751. goto fail;
  752. xhci_dbg(xhci, "Slot %d output ctx = 0x%llx (dma)\n", slot_id,
  753. (unsigned long long)dev->out_ctx->dma);
  754. /* Allocate the (input) device context for address device command */
  755. dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags);
  756. if (!dev->in_ctx)
  757. goto fail;
  758. xhci_dbg(xhci, "Slot %d input ctx = 0x%llx (dma)\n", slot_id,
  759. (unsigned long long)dev->in_ctx->dma);
  760. /* Initialize the cancellation list and watchdog timers for each ep */
  761. for (i = 0; i < 31; i++) {
  762. xhci_init_endpoint_timer(xhci, &dev->eps[i]);
  763. INIT_LIST_HEAD(&dev->eps[i].cancelled_td_list);
  764. INIT_LIST_HEAD(&dev->eps[i].bw_endpoint_list);
  765. }
  766. /* Allocate endpoint 0 ring */
  767. dev->eps[0].ring = xhci_ring_alloc(xhci, 1, true, false, flags);
  768. if (!dev->eps[0].ring)
  769. goto fail;
  770. /* Allocate pointers to the ring cache */
  771. dev->ring_cache = kzalloc(
  772. sizeof(struct xhci_ring *)*XHCI_MAX_RINGS_CACHED,
  773. flags);
  774. if (!dev->ring_cache)
  775. goto fail;
  776. dev->num_rings_cached = 0;
  777. init_completion(&dev->cmd_completion);
  778. INIT_LIST_HEAD(&dev->cmd_list);
  779. dev->udev = udev;
  780. /* Point to output device context in dcbaa. */
  781. xhci->dcbaa->dev_context_ptrs[slot_id] = cpu_to_le64(dev->out_ctx->dma);
  782. xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n",
  783. slot_id,
  784. &xhci->dcbaa->dev_context_ptrs[slot_id],
  785. le64_to_cpu(xhci->dcbaa->dev_context_ptrs[slot_id]));
  786. return 1;
  787. fail:
  788. xhci_free_virt_device(xhci, slot_id);
  789. return 0;
  790. }
  791. void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
  792. struct usb_device *udev)
  793. {
  794. struct xhci_virt_device *virt_dev;
  795. struct xhci_ep_ctx *ep0_ctx;
  796. struct xhci_ring *ep_ring;
  797. virt_dev = xhci->devs[udev->slot_id];
  798. ep0_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, 0);
  799. ep_ring = virt_dev->eps[0].ring;
  800. /*
  801. * FIXME we don't keep track of the dequeue pointer very well after a
  802. * Set TR dequeue pointer, so we're setting the dequeue pointer of the
  803. * host to our enqueue pointer. This should only be called after a
  804. * configured device has reset, so all control transfers should have
  805. * been completed or cancelled before the reset.
  806. */
  807. ep0_ctx->deq = cpu_to_le64(xhci_trb_virt_to_dma(ep_ring->enq_seg,
  808. ep_ring->enqueue)
  809. | ep_ring->cycle_state);
  810. }
  811. /*
  812. * The xHCI roothub may have ports of differing speeds in any order in the port
  813. * status registers. xhci->port_array provides an array of the port speed for
  814. * each offset into the port status registers.
  815. *
  816. * The xHCI hardware wants to know the roothub port number that the USB device
  817. * is attached to (or the roothub port its ancestor hub is attached to). All we
  818. * know is the index of that port under either the USB 2.0 or the USB 3.0
  819. * roothub, but that doesn't give us the real index into the HW port status
  820. * registers. Scan through the xHCI roothub port array, looking for the Nth
  821. * entry of the correct port speed. Return the port number of that entry.
  822. */
  823. static u32 xhci_find_real_port_number(struct xhci_hcd *xhci,
  824. struct usb_device *udev)
  825. {
  826. struct usb_device *top_dev;
  827. unsigned int num_similar_speed_ports;
  828. unsigned int faked_port_num;
  829. int i;
  830. for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
  831. top_dev = top_dev->parent)
  832. /* Found device below root hub */;
  833. faked_port_num = top_dev->portnum;
  834. for (i = 0, num_similar_speed_ports = 0;
  835. i < HCS_MAX_PORTS(xhci->hcs_params1); i++) {
  836. u8 port_speed = xhci->port_array[i];
  837. /*
  838. * Skip ports that don't have known speeds, or have duplicate
  839. * Extended Capabilities port speed entries.
  840. */
  841. if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
  842. continue;
  843. /*
  844. * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
  845. * 1.1 ports are under the USB 2.0 hub. If the port speed
  846. * matches the device speed, it's a similar speed port.
  847. */
  848. if ((port_speed == 0x03) == (udev->speed == USB_SPEED_SUPER))
  849. num_similar_speed_ports++;
  850. if (num_similar_speed_ports == faked_port_num)
  851. /* Roothub ports are numbered from 1 to N */
  852. return i+1;
  853. }
  854. return 0;
  855. }
  856. /* Setup an xHCI virtual device for a Set Address command */
  857. int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev)
  858. {
  859. struct xhci_virt_device *dev;
  860. struct xhci_ep_ctx *ep0_ctx;
  861. struct xhci_slot_ctx *slot_ctx;
  862. u32 port_num;
  863. struct usb_device *top_dev;
  864. dev = xhci->devs[udev->slot_id];
  865. /* Slot ID 0 is reserved */
  866. if (udev->slot_id == 0 || !dev) {
  867. xhci_warn(xhci, "Slot ID %d is not assigned to this device\n",
  868. udev->slot_id);
  869. return -EINVAL;
  870. }
  871. ep0_ctx = xhci_get_ep_ctx(xhci, dev->in_ctx, 0);
  872. slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx);
  873. /* 3) Only the control endpoint is valid - one endpoint context */
  874. slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1) | udev->route);
  875. switch (udev->speed) {
  876. case USB_SPEED_SUPER:
  877. slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SS);
  878. break;
  879. case USB_SPEED_HIGH:
  880. slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_HS);
  881. break;
  882. case USB_SPEED_FULL:
  883. slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_FS);
  884. break;
  885. case USB_SPEED_LOW:
  886. slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_LS);
  887. break;
  888. case USB_SPEED_WIRELESS:
  889. xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
  890. return -EINVAL;
  891. break;
  892. default:
  893. /* Speed was set earlier, this shouldn't happen. */
  894. BUG();
  895. }
  896. /* Find the root hub port this device is under */
  897. port_num = xhci_find_real_port_number(xhci, udev);
  898. if (!port_num)
  899. return -EINVAL;
  900. slot_ctx->dev_info2 |= cpu_to_le32(ROOT_HUB_PORT(port_num));
  901. /* Set the port number in the virtual_device to the faked port number */
  902. for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
  903. top_dev = top_dev->parent)
  904. /* Found device below root hub */;
  905. dev->fake_port = top_dev->portnum;
  906. dev->real_port = port_num;
  907. xhci_dbg(xhci, "Set root hub portnum to %d\n", port_num);
  908. xhci_dbg(xhci, "Set fake root hub portnum to %d\n", dev->fake_port);
  909. /* Find the right bandwidth table that this device will be a part of.
  910. * If this is a full speed device attached directly to a root port (or a
  911. * decendent of one), it counts as a primary bandwidth domain, not a
  912. * secondary bandwidth domain under a TT. An xhci_tt_info structure
  913. * will never be created for the HS root hub.
  914. */
  915. if (!udev->tt || !udev->tt->hub->parent) {
  916. dev->bw_table = &xhci->rh_bw[port_num - 1].bw_table;
  917. } else {
  918. struct xhci_root_port_bw_info *rh_bw;
  919. struct xhci_tt_bw_info *tt_bw;
  920. rh_bw = &xhci->rh_bw[port_num - 1];
  921. /* Find the right TT. */
  922. list_for_each_entry(tt_bw, &rh_bw->tts, tt_list) {
  923. if (tt_bw->slot_id != udev->tt->hub->slot_id)
  924. continue;
  925. if (!dev->udev->tt->multi ||
  926. (udev->tt->multi &&
  927. tt_bw->ttport == dev->udev->ttport)) {
  928. dev->bw_table = &tt_bw->bw_table;
  929. dev->tt_info = tt_bw;
  930. break;
  931. }
  932. }
  933. if (!dev->tt_info)
  934. xhci_warn(xhci, "WARN: Didn't find a matching TT\n");
  935. }
  936. /* Is this a LS/FS device under an external HS hub? */
  937. if (udev->tt && udev->tt->hub->parent) {
  938. slot_ctx->tt_info = cpu_to_le32(udev->tt->hub->slot_id |
  939. (udev->ttport << 8));
  940. if (udev->tt->multi)
  941. slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
  942. }
  943. xhci_dbg(xhci, "udev->tt = %p\n", udev->tt);
  944. xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport);
  945. /* Step 4 - ring already allocated */
  946. /* Step 5 */
  947. ep0_ctx->ep_info2 = cpu_to_le32(EP_TYPE(CTRL_EP));
  948. /*
  949. * XXX: Not sure about wireless USB devices.
  950. */
  951. switch (udev->speed) {
  952. case USB_SPEED_SUPER:
  953. ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(512));
  954. break;
  955. case USB_SPEED_HIGH:
  956. /* USB core guesses at a 64-byte max packet first for FS devices */
  957. case USB_SPEED_FULL:
  958. ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(64));
  959. break;
  960. case USB_SPEED_LOW:
  961. ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(8));
  962. break;
  963. case USB_SPEED_WIRELESS:
  964. xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
  965. return -EINVAL;
  966. break;
  967. default:
  968. /* New speed? */
  969. BUG();
  970. }
  971. /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
  972. ep0_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3));
  973. ep0_ctx->deq = cpu_to_le64(dev->eps[0].ring->first_seg->dma |
  974. dev->eps[0].ring->cycle_state);
  975. /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
  976. return 0;
  977. }
  978. /*
  979. * Convert interval expressed as 2^(bInterval - 1) == interval into
  980. * straight exponent value 2^n == interval.
  981. *
  982. */
  983. static unsigned int xhci_parse_exponent_interval(struct usb_device *udev,
  984. struct usb_host_endpoint *ep)
  985. {
  986. unsigned int interval;
  987. interval = clamp_val(ep->desc.bInterval, 1, 16) - 1;
  988. if (interval != ep->desc.bInterval - 1)
  989. dev_warn(&udev->dev,
  990. "ep %#x - rounding interval to %d %sframes\n",
  991. ep->desc.bEndpointAddress,
  992. 1 << interval,
  993. udev->speed == USB_SPEED_FULL ? "" : "micro");
  994. if (udev->speed == USB_SPEED_FULL) {
  995. /*
  996. * Full speed isoc endpoints specify interval in frames,
  997. * not microframes. We are using microframes everywhere,
  998. * so adjust accordingly.
  999. */
  1000. interval += 3; /* 1 frame = 2^3 uframes */
  1001. }
  1002. return interval;
  1003. }
  1004. /*
  1005. * Convert bInterval expressed in microframes (in 1-255 range) to exponent of
  1006. * microframes, rounded down to nearest power of 2.
  1007. */
  1008. static unsigned int xhci_microframes_to_exponent(struct usb_device *udev,
  1009. struct usb_host_endpoint *ep, unsigned int desc_interval,
  1010. unsigned int min_exponent, unsigned int max_exponent)
  1011. {
  1012. unsigned int interval;
  1013. interval = fls(desc_interval) - 1;
  1014. interval = clamp_val(interval, min_exponent, max_exponent);
  1015. if ((1 << interval) != desc_interval)
  1016. dev_warn(&udev->dev,
  1017. "ep %#x - rounding interval to %d microframes, ep desc says %d microframes\n",
  1018. ep->desc.bEndpointAddress,
  1019. 1 << interval,
  1020. desc_interval);
  1021. return interval;
  1022. }
  1023. static unsigned int xhci_parse_microframe_interval(struct usb_device *udev,
  1024. struct usb_host_endpoint *ep)
  1025. {
  1026. return xhci_microframes_to_exponent(udev, ep,
  1027. ep->desc.bInterval, 0, 15);
  1028. }
  1029. static unsigned int xhci_parse_frame_interval(struct usb_device *udev,
  1030. struct usb_host_endpoint *ep)
  1031. {
  1032. return xhci_microframes_to_exponent(udev, ep,
  1033. ep->desc.bInterval * 8, 3, 10);
  1034. }
  1035. /* Return the polling or NAK interval.
  1036. *
  1037. * The polling interval is expressed in "microframes". If xHCI's Interval field
  1038. * is set to N, it will service the endpoint every 2^(Interval)*125us.
  1039. *
  1040. * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
  1041. * is set to 0.
  1042. */
  1043. static unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
  1044. struct usb_host_endpoint *ep)
  1045. {
  1046. unsigned int interval = 0;
  1047. switch (udev->speed) {
  1048. case USB_SPEED_HIGH:
  1049. /* Max NAK rate */
  1050. if (usb_endpoint_xfer_control(&ep->desc) ||
  1051. usb_endpoint_xfer_bulk(&ep->desc)) {
  1052. interval = xhci_parse_microframe_interval(udev, ep);
  1053. break;
  1054. }
  1055. /* Fall through - SS and HS isoc/int have same decoding */
  1056. case USB_SPEED_SUPER:
  1057. if (usb_endpoint_xfer_int(&ep->desc) ||
  1058. usb_endpoint_xfer_isoc(&ep->desc)) {
  1059. interval = xhci_parse_exponent_interval(udev, ep);
  1060. }
  1061. break;
  1062. case USB_SPEED_FULL:
  1063. if (usb_endpoint_xfer_isoc(&ep->desc)) {
  1064. interval = xhci_parse_exponent_interval(udev, ep);
  1065. break;
  1066. }
  1067. /*
  1068. * Fall through for interrupt endpoint interval decoding
  1069. * since it uses the same rules as low speed interrupt
  1070. * endpoints.
  1071. */
  1072. case USB_SPEED_LOW:
  1073. if (usb_endpoint_xfer_int(&ep->desc) ||
  1074. usb_endpoint_xfer_isoc(&ep->desc)) {
  1075. interval = xhci_parse_frame_interval(udev, ep);
  1076. }
  1077. break;
  1078. default:
  1079. BUG();
  1080. }
  1081. return EP_INTERVAL(interval);
  1082. }
  1083. /* The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
  1084. * High speed endpoint descriptors can define "the number of additional
  1085. * transaction opportunities per microframe", but that goes in the Max Burst
  1086. * endpoint context field.
  1087. */
  1088. static u32 xhci_get_endpoint_mult(struct usb_device *udev,
  1089. struct usb_host_endpoint *ep)
  1090. {
  1091. if (udev->speed != USB_SPEED_SUPER ||
  1092. !usb_endpoint_xfer_isoc(&ep->desc))
  1093. return 0;
  1094. return ep->ss_ep_comp.bmAttributes;
  1095. }
  1096. static u32 xhci_get_endpoint_type(struct usb_device *udev,
  1097. struct usb_host_endpoint *ep)
  1098. {
  1099. int in;
  1100. u32 type;
  1101. in = usb_endpoint_dir_in(&ep->desc);
  1102. if (usb_endpoint_xfer_control(&ep->desc)) {
  1103. type = EP_TYPE(CTRL_EP);
  1104. } else if (usb_endpoint_xfer_bulk(&ep->desc)) {
  1105. if (in)
  1106. type = EP_TYPE(BULK_IN_EP);
  1107. else
  1108. type = EP_TYPE(BULK_OUT_EP);
  1109. } else if (usb_endpoint_xfer_isoc(&ep->desc)) {
  1110. if (in)
  1111. type = EP_TYPE(ISOC_IN_EP);
  1112. else
  1113. type = EP_TYPE(ISOC_OUT_EP);
  1114. } else if (usb_endpoint_xfer_int(&ep->desc)) {
  1115. if (in)
  1116. type = EP_TYPE(INT_IN_EP);
  1117. else
  1118. type = EP_TYPE(INT_OUT_EP);
  1119. } else {
  1120. BUG();
  1121. }
  1122. return type;
  1123. }
  1124. /* Return the maximum endpoint service interval time (ESIT) payload.
  1125. * Basically, this is the maxpacket size, multiplied by the burst size
  1126. * and mult size.
  1127. */
  1128. static u32 xhci_get_max_esit_payload(struct xhci_hcd *xhci,
  1129. struct usb_device *udev,
  1130. struct usb_host_endpoint *ep)
  1131. {
  1132. int max_burst;
  1133. int max_packet;
  1134. /* Only applies for interrupt or isochronous endpoints */
  1135. if (usb_endpoint_xfer_control(&ep->desc) ||
  1136. usb_endpoint_xfer_bulk(&ep->desc))
  1137. return 0;
  1138. if (udev->speed == USB_SPEED_SUPER)
  1139. return le16_to_cpu(ep->ss_ep_comp.wBytesPerInterval);
  1140. max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc));
  1141. max_burst = (usb_endpoint_maxp(&ep->desc) & 0x1800) >> 11;
  1142. /* A 0 in max burst means 1 transfer per ESIT */
  1143. return max_packet * (max_burst + 1);
  1144. }
  1145. /* Set up an endpoint with one ring segment. Do not allocate stream rings.
  1146. * Drivers will have to call usb_alloc_streams() to do that.
  1147. */
  1148. int xhci_endpoint_init(struct xhci_hcd *xhci,
  1149. struct xhci_virt_device *virt_dev,
  1150. struct usb_device *udev,
  1151. struct usb_host_endpoint *ep,
  1152. gfp_t mem_flags)
  1153. {
  1154. unsigned int ep_index;
  1155. struct xhci_ep_ctx *ep_ctx;
  1156. struct xhci_ring *ep_ring;
  1157. unsigned int max_packet;
  1158. unsigned int max_burst;
  1159. u32 max_esit_payload;
  1160. ep_index = xhci_get_endpoint_index(&ep->desc);
  1161. ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
  1162. /* Set up the endpoint ring */
  1163. /*
  1164. * Isochronous endpoint ring needs bigger size because one isoc URB
  1165. * carries multiple packets and it will insert multiple tds to the
  1166. * ring.
  1167. * This should be replaced with dynamic ring resizing in the future.
  1168. */
  1169. if (usb_endpoint_xfer_isoc(&ep->desc))
  1170. virt_dev->eps[ep_index].new_ring =
  1171. xhci_ring_alloc(xhci, 8, true, true, mem_flags);
  1172. else
  1173. virt_dev->eps[ep_index].new_ring =
  1174. xhci_ring_alloc(xhci, 1, true, false, mem_flags);
  1175. if (!virt_dev->eps[ep_index].new_ring) {
  1176. /* Attempt to use the ring cache */
  1177. if (virt_dev->num_rings_cached == 0)
  1178. return -ENOMEM;
  1179. virt_dev->eps[ep_index].new_ring =
  1180. virt_dev->ring_cache[virt_dev->num_rings_cached];
  1181. virt_dev->ring_cache[virt_dev->num_rings_cached] = NULL;
  1182. virt_dev->num_rings_cached--;
  1183. xhci_reinit_cached_ring(xhci, virt_dev->eps[ep_index].new_ring,
  1184. usb_endpoint_xfer_isoc(&ep->desc) ? true : false);
  1185. }
  1186. virt_dev->eps[ep_index].skip = false;
  1187. ep_ring = virt_dev->eps[ep_index].new_ring;
  1188. ep_ctx->deq = cpu_to_le64(ep_ring->first_seg->dma | ep_ring->cycle_state);
  1189. ep_ctx->ep_info = cpu_to_le32(xhci_get_endpoint_interval(udev, ep)
  1190. | EP_MULT(xhci_get_endpoint_mult(udev, ep)));
  1191. /* FIXME dig Mult and streams info out of ep companion desc */
  1192. /* Allow 3 retries for everything but isoc;
  1193. * CErr shall be set to 0 for Isoch endpoints.
  1194. */
  1195. if (!usb_endpoint_xfer_isoc(&ep->desc))
  1196. ep_ctx->ep_info2 = cpu_to_le32(ERROR_COUNT(3));
  1197. else
  1198. ep_ctx->ep_info2 = cpu_to_le32(ERROR_COUNT(0));
  1199. ep_ctx->ep_info2 |= cpu_to_le32(xhci_get_endpoint_type(udev, ep));
  1200. /* Set the max packet size and max burst */
  1201. switch (udev->speed) {
  1202. case USB_SPEED_SUPER:
  1203. max_packet = usb_endpoint_maxp(&ep->desc);
  1204. ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet));
  1205. /* dig out max burst from ep companion desc */
  1206. max_packet = ep->ss_ep_comp.bMaxBurst;
  1207. ep_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(max_packet));
  1208. break;
  1209. case USB_SPEED_HIGH:
  1210. /* bits 11:12 specify the number of additional transaction
  1211. * opportunities per microframe (USB 2.0, section 9.6.6)
  1212. */
  1213. if (usb_endpoint_xfer_isoc(&ep->desc) ||
  1214. usb_endpoint_xfer_int(&ep->desc)) {
  1215. max_burst = (usb_endpoint_maxp(&ep->desc)
  1216. & 0x1800) >> 11;
  1217. ep_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(max_burst));
  1218. }
  1219. /* Fall through */
  1220. case USB_SPEED_FULL:
  1221. case USB_SPEED_LOW:
  1222. max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc));
  1223. ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet));
  1224. break;
  1225. default:
  1226. BUG();
  1227. }
  1228. max_esit_payload = xhci_get_max_esit_payload(xhci, udev, ep);
  1229. ep_ctx->tx_info = cpu_to_le32(MAX_ESIT_PAYLOAD_FOR_EP(max_esit_payload));
  1230. /*
  1231. * XXX no idea how to calculate the average TRB buffer length for bulk
  1232. * endpoints, as the driver gives us no clue how big each scatter gather
  1233. * list entry (or buffer) is going to be.
  1234. *
  1235. * For isochronous and interrupt endpoints, we set it to the max
  1236. * available, until we have new API in the USB core to allow drivers to
  1237. * declare how much bandwidth they actually need.
  1238. *
  1239. * Normally, it would be calculated by taking the total of the buffer
  1240. * lengths in the TD and then dividing by the number of TRBs in a TD,
  1241. * including link TRBs, No-op TRBs, and Event data TRBs. Since we don't
  1242. * use Event Data TRBs, and we don't chain in a link TRB on short
  1243. * transfers, we're basically dividing by 1.
  1244. *
  1245. * xHCI 1.0 specification indicates that the Average TRB Length should
  1246. * be set to 8 for control endpoints.
  1247. */
  1248. if (usb_endpoint_xfer_control(&ep->desc) && xhci->hci_version == 0x100)
  1249. ep_ctx->tx_info |= cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(8));
  1250. else
  1251. ep_ctx->tx_info |=
  1252. cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(max_esit_payload));
  1253. /* FIXME Debug endpoint context */
  1254. return 0;
  1255. }
  1256. void xhci_endpoint_zero(struct xhci_hcd *xhci,
  1257. struct xhci_virt_device *virt_dev,
  1258. struct usb_host_endpoint *ep)
  1259. {
  1260. unsigned int ep_index;
  1261. struct xhci_ep_ctx *ep_ctx;
  1262. ep_index = xhci_get_endpoint_index(&ep->desc);
  1263. ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
  1264. ep_ctx->ep_info = 0;
  1265. ep_ctx->ep_info2 = 0;
  1266. ep_ctx->deq = 0;
  1267. ep_ctx->tx_info = 0;
  1268. /* Don't free the endpoint ring until the set interface or configuration
  1269. * request succeeds.
  1270. */
  1271. }
  1272. void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info)
  1273. {
  1274. bw_info->ep_interval = 0;
  1275. bw_info->mult = 0;
  1276. bw_info->num_packets = 0;
  1277. bw_info->max_packet_size = 0;
  1278. bw_info->type = 0;
  1279. bw_info->max_esit_payload = 0;
  1280. }
  1281. void xhci_update_bw_info(struct xhci_hcd *xhci,
  1282. struct xhci_container_ctx *in_ctx,
  1283. struct xhci_input_control_ctx *ctrl_ctx,
  1284. struct xhci_virt_device *virt_dev)
  1285. {
  1286. struct xhci_bw_info *bw_info;
  1287. struct xhci_ep_ctx *ep_ctx;
  1288. unsigned int ep_type;
  1289. int i;
  1290. for (i = 1; i < 31; ++i) {
  1291. bw_info = &virt_dev->eps[i].bw_info;
  1292. /* We can't tell what endpoint type is being dropped, but
  1293. * unconditionally clearing the bandwidth info for non-periodic
  1294. * endpoints should be harmless because the info will never be
  1295. * set in the first place.
  1296. */
  1297. if (!EP_IS_ADDED(ctrl_ctx, i) && EP_IS_DROPPED(ctrl_ctx, i)) {
  1298. /* Dropped endpoint */
  1299. xhci_clear_endpoint_bw_info(bw_info);
  1300. continue;
  1301. }
  1302. if (EP_IS_ADDED(ctrl_ctx, i)) {
  1303. ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, i);
  1304. ep_type = CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx->ep_info2));
  1305. /* Ignore non-periodic endpoints */
  1306. if (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
  1307. ep_type != ISOC_IN_EP &&
  1308. ep_type != INT_IN_EP)
  1309. continue;
  1310. /* Added or changed endpoint */
  1311. bw_info->ep_interval = CTX_TO_EP_INTERVAL(
  1312. le32_to_cpu(ep_ctx->ep_info));
  1313. /* Number of packets and mult are zero-based in the
  1314. * input context, but we want one-based for the
  1315. * interval table.
  1316. */
  1317. bw_info->mult = CTX_TO_EP_MULT(
  1318. le32_to_cpu(ep_ctx->ep_info)) + 1;
  1319. bw_info->num_packets = CTX_TO_MAX_BURST(
  1320. le32_to_cpu(ep_ctx->ep_info2)) + 1;
  1321. bw_info->max_packet_size = MAX_PACKET_DECODED(
  1322. le32_to_cpu(ep_ctx->ep_info2));
  1323. bw_info->type = ep_type;
  1324. bw_info->max_esit_payload = CTX_TO_MAX_ESIT_PAYLOAD(
  1325. le32_to_cpu(ep_ctx->tx_info));
  1326. }
  1327. }
  1328. }
  1329. /* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
  1330. * Useful when you want to change one particular aspect of the endpoint and then
  1331. * issue a configure endpoint command.
  1332. */
  1333. void xhci_endpoint_copy(struct xhci_hcd *xhci,
  1334. struct xhci_container_ctx *in_ctx,
  1335. struct xhci_container_ctx *out_ctx,
  1336. unsigned int ep_index)
  1337. {
  1338. struct xhci_ep_ctx *out_ep_ctx;
  1339. struct xhci_ep_ctx *in_ep_ctx;
  1340. out_ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
  1341. in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
  1342. in_ep_ctx->ep_info = out_ep_ctx->ep_info;
  1343. in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2;
  1344. in_ep_ctx->deq = out_ep_ctx->deq;
  1345. in_ep_ctx->tx_info = out_ep_ctx->tx_info;
  1346. }
  1347. /* Copy output xhci_slot_ctx to the input xhci_slot_ctx.
  1348. * Useful when you want to change one particular aspect of the endpoint and then
  1349. * issue a configure endpoint command. Only the context entries field matters,
  1350. * but we'll copy the whole thing anyway.
  1351. */
  1352. void xhci_slot_copy(struct xhci_hcd *xhci,
  1353. struct xhci_container_ctx *in_ctx,
  1354. struct xhci_container_ctx *out_ctx)
  1355. {
  1356. struct xhci_slot_ctx *in_slot_ctx;
  1357. struct xhci_slot_ctx *out_slot_ctx;
  1358. in_slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
  1359. out_slot_ctx = xhci_get_slot_ctx(xhci, out_ctx);
  1360. in_slot_ctx->dev_info = out_slot_ctx->dev_info;
  1361. in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2;
  1362. in_slot_ctx->tt_info = out_slot_ctx->tt_info;
  1363. in_slot_ctx->dev_state = out_slot_ctx->dev_state;
  1364. }
  1365. /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
  1366. static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags)
  1367. {
  1368. int i;
  1369. struct device *dev = xhci_to_hcd(xhci)->self.controller;
  1370. int num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
  1371. xhci_dbg(xhci, "Allocating %d scratchpad buffers\n", num_sp);
  1372. if (!num_sp)
  1373. return 0;
  1374. xhci->scratchpad = kzalloc(sizeof(*xhci->scratchpad), flags);
  1375. if (!xhci->scratchpad)
  1376. goto fail_sp;
  1377. xhci->scratchpad->sp_array = dma_alloc_coherent(dev,
  1378. num_sp * sizeof(u64),
  1379. &xhci->scratchpad->sp_dma, flags);
  1380. if (!xhci->scratchpad->sp_array)
  1381. goto fail_sp2;
  1382. xhci->scratchpad->sp_buffers = kzalloc(sizeof(void *) * num_sp, flags);
  1383. if (!xhci->scratchpad->sp_buffers)
  1384. goto fail_sp3;
  1385. xhci->scratchpad->sp_dma_buffers =
  1386. kzalloc(sizeof(dma_addr_t) * num_sp, flags);
  1387. if (!xhci->scratchpad->sp_dma_buffers)
  1388. goto fail_sp4;
  1389. xhci->dcbaa->dev_context_ptrs[0] = cpu_to_le64(xhci->scratchpad->sp_dma);
  1390. for (i = 0; i < num_sp; i++) {
  1391. dma_addr_t dma;
  1392. void *buf = dma_alloc_coherent(dev, xhci->page_size, &dma,
  1393. flags);
  1394. if (!buf)
  1395. goto fail_sp5;
  1396. xhci->scratchpad->sp_array[i] = dma;
  1397. xhci->scratchpad->sp_buffers[i] = buf;
  1398. xhci->scratchpad->sp_dma_buffers[i] = dma;
  1399. }
  1400. return 0;
  1401. fail_sp5:
  1402. for (i = i - 1; i >= 0; i--) {
  1403. dma_free_coherent(dev, xhci->page_size,
  1404. xhci->scratchpad->sp_buffers[i],
  1405. xhci->scratchpad->sp_dma_buffers[i]);
  1406. }
  1407. kfree(xhci->scratchpad->sp_dma_buffers);
  1408. fail_sp4:
  1409. kfree(xhci->scratchpad->sp_buffers);
  1410. fail_sp3:
  1411. dma_free_coherent(dev, num_sp * sizeof(u64),
  1412. xhci->scratchpad->sp_array,
  1413. xhci->scratchpad->sp_dma);
  1414. fail_sp2:
  1415. kfree(xhci->scratchpad);
  1416. xhci->scratchpad = NULL;
  1417. fail_sp:
  1418. return -ENOMEM;
  1419. }
  1420. static void scratchpad_free(struct xhci_hcd *xhci)
  1421. {
  1422. int num_sp;
  1423. int i;
  1424. struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
  1425. if (!xhci->scratchpad)
  1426. return;
  1427. num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
  1428. for (i = 0; i < num_sp; i++) {
  1429. dma_free_coherent(&pdev->dev, xhci->page_size,
  1430. xhci->scratchpad->sp_buffers[i],
  1431. xhci->scratchpad->sp_dma_buffers[i]);
  1432. }
  1433. kfree(xhci->scratchpad->sp_dma_buffers);
  1434. kfree(xhci->scratchpad->sp_buffers);
  1435. dma_free_coherent(&pdev->dev, num_sp * sizeof(u64),
  1436. xhci->scratchpad->sp_array,
  1437. xhci->scratchpad->sp_dma);
  1438. kfree(xhci->scratchpad);
  1439. xhci->scratchpad = NULL;
  1440. }
  1441. struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
  1442. bool allocate_in_ctx, bool allocate_completion,
  1443. gfp_t mem_flags)
  1444. {
  1445. struct xhci_command *command;
  1446. command = kzalloc(sizeof(*command), mem_flags);
  1447. if (!command)
  1448. return NULL;
  1449. if (allocate_in_ctx) {
  1450. command->in_ctx =
  1451. xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT,
  1452. mem_flags);
  1453. if (!command->in_ctx) {
  1454. kfree(command);
  1455. return NULL;
  1456. }
  1457. }
  1458. if (allocate_completion) {
  1459. command->completion =
  1460. kzalloc(sizeof(struct completion), mem_flags);
  1461. if (!command->completion) {
  1462. xhci_free_container_ctx(xhci, command->in_ctx);
  1463. kfree(command);
  1464. return NULL;
  1465. }
  1466. init_completion(command->completion);
  1467. }
  1468. command->status = 0;
  1469. INIT_LIST_HEAD(&command->cmd_list);
  1470. return command;
  1471. }
  1472. void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv)
  1473. {
  1474. if (urb_priv) {
  1475. kfree(urb_priv->td[0]);
  1476. kfree(urb_priv);
  1477. }
  1478. }
  1479. void xhci_free_command(struct xhci_hcd *xhci,
  1480. struct xhci_command *command)
  1481. {
  1482. xhci_free_container_ctx(xhci,
  1483. command->in_ctx);
  1484. kfree(command->completion);
  1485. kfree(command);
  1486. }
  1487. void xhci_mem_cleanup(struct xhci_hcd *xhci)
  1488. {
  1489. struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
  1490. struct dev_info *dev_info, *next;
  1491. unsigned long flags;
  1492. int size;
  1493. int i;
  1494. /* Free the Event Ring Segment Table and the actual Event Ring */
  1495. if (xhci->ir_set) {
  1496. xhci_writel(xhci, 0, &xhci->ir_set->erst_size);
  1497. xhci_write_64(xhci, 0, &xhci->ir_set->erst_base);
  1498. xhci_write_64(xhci, 0, &xhci->ir_set->erst_dequeue);
  1499. }
  1500. size = sizeof(struct xhci_erst_entry)*(xhci->erst.num_entries);
  1501. if (xhci->erst.entries)
  1502. dma_free_coherent(&pdev->dev, size,
  1503. xhci->erst.entries, xhci->erst.erst_dma_addr);
  1504. xhci->erst.entries = NULL;
  1505. xhci_dbg(xhci, "Freed ERST\n");
  1506. if (xhci->event_ring)
  1507. xhci_ring_free(xhci, xhci->event_ring);
  1508. xhci->event_ring = NULL;
  1509. xhci_dbg(xhci, "Freed event ring\n");
  1510. xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
  1511. if (xhci->cmd_ring)
  1512. xhci_ring_free(xhci, xhci->cmd_ring);
  1513. xhci->cmd_ring = NULL;
  1514. xhci_dbg(xhci, "Freed command ring\n");
  1515. for (i = 1; i < MAX_HC_SLOTS; ++i)
  1516. xhci_free_virt_device(xhci, i);
  1517. if (xhci->segment_pool)
  1518. dma_pool_destroy(xhci->segment_pool);
  1519. xhci->segment_pool = NULL;
  1520. xhci_dbg(xhci, "Freed segment pool\n");
  1521. if (xhci->device_pool)
  1522. dma_pool_destroy(xhci->device_pool);
  1523. xhci->device_pool = NULL;
  1524. xhci_dbg(xhci, "Freed device context pool\n");
  1525. if (xhci->small_streams_pool)
  1526. dma_pool_destroy(xhci->small_streams_pool);
  1527. xhci->small_streams_pool = NULL;
  1528. xhci_dbg(xhci, "Freed small stream array pool\n");
  1529. if (xhci->medium_streams_pool)
  1530. dma_pool_destroy(xhci->medium_streams_pool);
  1531. xhci->medium_streams_pool = NULL;
  1532. xhci_dbg(xhci, "Freed medium stream array pool\n");
  1533. xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
  1534. if (xhci->dcbaa)
  1535. dma_free_coherent(&pdev->dev, sizeof(*xhci->dcbaa),
  1536. xhci->dcbaa, xhci->dcbaa->dma);
  1537. xhci->dcbaa = NULL;
  1538. scratchpad_free(xhci);
  1539. spin_lock_irqsave(&xhci->lock, flags);
  1540. list_for_each_entry_safe(dev_info, next, &xhci->lpm_failed_devs, list) {
  1541. list_del(&dev_info->list);
  1542. kfree(dev_info);
  1543. }
  1544. spin_unlock_irqrestore(&xhci->lock, flags);
  1545. xhci->num_usb2_ports = 0;
  1546. xhci->num_usb3_ports = 0;
  1547. kfree(xhci->usb2_ports);
  1548. kfree(xhci->usb3_ports);
  1549. kfree(xhci->port_array);
  1550. kfree(xhci->rh_bw);
  1551. xhci->page_size = 0;
  1552. xhci->page_shift = 0;
  1553. xhci->bus_state[0].bus_suspended = 0;
  1554. xhci->bus_state[1].bus_suspended = 0;
  1555. }
  1556. static int xhci_test_trb_in_td(struct xhci_hcd *xhci,
  1557. struct xhci_segment *input_seg,
  1558. union xhci_trb *start_trb,
  1559. union xhci_trb *end_trb,
  1560. dma_addr_t input_dma,
  1561. struct xhci_segment *result_seg,
  1562. char *test_name, int test_number)
  1563. {
  1564. unsigned long long start_dma;
  1565. unsigned long long end_dma;
  1566. struct xhci_segment *seg;
  1567. start_dma = xhci_trb_virt_to_dma(input_seg, start_trb);
  1568. end_dma = xhci_trb_virt_to_dma(input_seg, end_trb);
  1569. seg = trb_in_td(input_seg, start_trb, end_trb, input_dma);
  1570. if (seg != result_seg) {
  1571. xhci_warn(xhci, "WARN: %s TRB math test %d failed!\n",
  1572. test_name, test_number);
  1573. xhci_warn(xhci, "Tested TRB math w/ seg %p and "
  1574. "input DMA 0x%llx\n",
  1575. input_seg,
  1576. (unsigned long long) input_dma);
  1577. xhci_warn(xhci, "starting TRB %p (0x%llx DMA), "
  1578. "ending TRB %p (0x%llx DMA)\n",
  1579. start_trb, start_dma,
  1580. end_trb, end_dma);
  1581. xhci_warn(xhci, "Expected seg %p, got seg %p\n",
  1582. result_seg, seg);
  1583. return -1;
  1584. }
  1585. return 0;
  1586. }
  1587. /* TRB math checks for xhci_trb_in_td(), using the command and event rings. */
  1588. static int xhci_check_trb_in_td_math(struct xhci_hcd *xhci, gfp_t mem_flags)
  1589. {
  1590. struct {
  1591. dma_addr_t input_dma;
  1592. struct xhci_segment *result_seg;
  1593. } simple_test_vector [] = {
  1594. /* A zeroed DMA field should fail */
  1595. { 0, NULL },
  1596. /* One TRB before the ring start should fail */
  1597. { xhci->event_ring->first_seg->dma - 16, NULL },
  1598. /* One byte before the ring start should fail */
  1599. { xhci->event_ring->first_seg->dma - 1, NULL },
  1600. /* Starting TRB should succeed */
  1601. { xhci->event_ring->first_seg->dma, xhci->event_ring->first_seg },
  1602. /* Ending TRB should succeed */
  1603. { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16,
  1604. xhci->event_ring->first_seg },
  1605. /* One byte after the ring end should fail */
  1606. { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16 + 1, NULL },
  1607. /* One TRB after the ring end should fail */
  1608. { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT)*16, NULL },
  1609. /* An address of all ones should fail */
  1610. { (dma_addr_t) (~0), NULL },
  1611. };
  1612. struct {
  1613. struct xhci_segment *input_seg;
  1614. union xhci_trb *start_trb;
  1615. union xhci_trb *end_trb;
  1616. dma_addr_t input_dma;
  1617. struct xhci_segment *result_seg;
  1618. } complex_test_vector [] = {
  1619. /* Test feeding a valid DMA address from a different ring */
  1620. { .input_seg = xhci->event_ring->first_seg,
  1621. .start_trb = xhci->event_ring->first_seg->trbs,
  1622. .end_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
  1623. .input_dma = xhci->cmd_ring->first_seg->dma,
  1624. .result_seg = NULL,
  1625. },
  1626. /* Test feeding a valid end TRB from a different ring */
  1627. { .input_seg = xhci->event_ring->first_seg,
  1628. .start_trb = xhci->event_ring->first_seg->trbs,
  1629. .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
  1630. .input_dma = xhci->cmd_ring->first_seg->dma,
  1631. .result_seg = NULL,
  1632. },
  1633. /* Test feeding a valid start and end TRB from a different ring */
  1634. { .input_seg = xhci->event_ring->first_seg,
  1635. .start_trb = xhci->cmd_ring->first_seg->trbs,
  1636. .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
  1637. .input_dma = xhci->cmd_ring->first_seg->dma,
  1638. .result_seg = NULL,
  1639. },
  1640. /* TRB in this ring, but after this TD */
  1641. { .input_seg = xhci->event_ring->first_seg,
  1642. .start_trb = &xhci->event_ring->first_seg->trbs[0],
  1643. .end_trb = &xhci->event_ring->first_seg->trbs[3],
  1644. .input_dma = xhci->event_ring->first_seg->dma + 4*16,
  1645. .result_seg = NULL,
  1646. },
  1647. /* TRB in this ring, but before this TD */
  1648. { .input_seg = xhci->event_ring->first_seg,
  1649. .start_trb = &xhci->event_ring->first_seg->trbs[3],
  1650. .end_trb = &xhci->event_ring->first_seg->trbs[6],
  1651. .input_dma = xhci->event_ring->first_seg->dma + 2*16,
  1652. .result_seg = NULL,
  1653. },
  1654. /* TRB in this ring, but after this wrapped TD */
  1655. { .input_seg = xhci->event_ring->first_seg,
  1656. .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
  1657. .end_trb = &xhci->event_ring->first_seg->trbs[1],
  1658. .input_dma = xhci->event_ring->first_seg->dma + 2*16,
  1659. .result_seg = NULL,
  1660. },
  1661. /* TRB in this ring, but before this wrapped TD */
  1662. { .input_seg = xhci->event_ring->first_seg,
  1663. .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
  1664. .end_trb = &xhci->event_ring->first_seg->trbs[1],
  1665. .input_dma = xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 4)*16,
  1666. .result_seg = NULL,
  1667. },
  1668. /* TRB not in this ring, and we have a wrapped TD */
  1669. { .input_seg = xhci->event_ring->first_seg,
  1670. .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
  1671. .end_trb = &xhci->event_ring->first_seg->trbs[1],
  1672. .input_dma = xhci->cmd_ring->first_seg->dma + 2*16,
  1673. .result_seg = NULL,
  1674. },
  1675. };
  1676. unsigned int num_tests;
  1677. int i, ret;
  1678. num_tests = ARRAY_SIZE(simple_test_vector);
  1679. for (i = 0; i < num_tests; i++) {
  1680. ret = xhci_test_trb_in_td(xhci,
  1681. xhci->event_ring->first_seg,
  1682. xhci->event_ring->first_seg->trbs,
  1683. &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
  1684. simple_test_vector[i].input_dma,
  1685. simple_test_vector[i].result_seg,
  1686. "Simple", i);
  1687. if (ret < 0)
  1688. return ret;
  1689. }
  1690. num_tests = ARRAY_SIZE(complex_test_vector);
  1691. for (i = 0; i < num_tests; i++) {
  1692. ret = xhci_test_trb_in_td(xhci,
  1693. complex_test_vector[i].input_seg,
  1694. complex_test_vector[i].start_trb,
  1695. complex_test_vector[i].end_trb,
  1696. complex_test_vector[i].input_dma,
  1697. complex_test_vector[i].result_seg,
  1698. "Complex", i);
  1699. if (ret < 0)
  1700. return ret;
  1701. }
  1702. xhci_dbg(xhci, "TRB math tests passed.\n");
  1703. return 0;
  1704. }
  1705. static void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
  1706. {
  1707. u64 temp;
  1708. dma_addr_t deq;
  1709. deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
  1710. xhci->event_ring->dequeue);
  1711. if (deq == 0 && !in_interrupt())
  1712. xhci_warn(xhci, "WARN something wrong with SW event ring "
  1713. "dequeue ptr.\n");
  1714. /* Update HC event ring dequeue pointer */
  1715. temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
  1716. temp &= ERST_PTR_MASK;
  1717. /* Don't clear the EHB bit (which is RW1C) because
  1718. * there might be more events to service.
  1719. */
  1720. temp &= ~ERST_EHB;
  1721. xhci_dbg(xhci, "// Write event ring dequeue pointer, "
  1722. "preserving EHB bit\n");
  1723. xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
  1724. &xhci->ir_set->erst_dequeue);
  1725. }
  1726. static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
  1727. __le32 __iomem *addr, u8 major_revision)
  1728. {
  1729. u32 temp, port_offset, port_count;
  1730. int i;
  1731. if (major_revision > 0x03) {
  1732. xhci_warn(xhci, "Ignoring unknown port speed, "
  1733. "Ext Cap %p, revision = 0x%x\n",
  1734. addr, major_revision);
  1735. /* Ignoring port protocol we can't understand. FIXME */
  1736. return;
  1737. }
  1738. /* Port offset and count in the third dword, see section 7.2 */
  1739. temp = xhci_readl(xhci, addr + 2);
  1740. port_offset = XHCI_EXT_PORT_OFF(temp);
  1741. port_count = XHCI_EXT_PORT_COUNT(temp);
  1742. xhci_dbg(xhci, "Ext Cap %p, port offset = %u, "
  1743. "count = %u, revision = 0x%x\n",
  1744. addr, port_offset, port_count, major_revision);
  1745. /* Port count includes the current port offset */
  1746. if (port_offset == 0 || (port_offset + port_count - 1) > num_ports)
  1747. /* WTF? "Valid values are ‘1’ to MaxPorts" */
  1748. return;
  1749. /* Check the host's USB2 LPM capability */
  1750. if ((xhci->hci_version == 0x96) && (major_revision != 0x03) &&
  1751. (temp & XHCI_L1C)) {
  1752. xhci_dbg(xhci, "xHCI 0.96: support USB2 software lpm\n");
  1753. xhci->sw_lpm_support = 1;
  1754. }
  1755. if ((xhci->hci_version >= 0x100) && (major_revision != 0x03)) {
  1756. xhci_dbg(xhci, "xHCI 1.0: support USB2 software lpm\n");
  1757. xhci->sw_lpm_support = 1;
  1758. if (temp & XHCI_HLC) {
  1759. xhci_dbg(xhci, "xHCI 1.0: support USB2 hardware lpm\n");
  1760. xhci->hw_lpm_support = 1;
  1761. }
  1762. }
  1763. port_offset--;
  1764. for (i = port_offset; i < (port_offset + port_count); i++) {
  1765. /* Duplicate entry. Ignore the port if the revisions differ. */
  1766. if (xhci->port_array[i] != 0) {
  1767. xhci_warn(xhci, "Duplicate port entry, Ext Cap %p,"
  1768. " port %u\n", addr, i);
  1769. xhci_warn(xhci, "Port was marked as USB %u, "
  1770. "duplicated as USB %u\n",
  1771. xhci->port_array[i], major_revision);
  1772. /* Only adjust the roothub port counts if we haven't
  1773. * found a similar duplicate.
  1774. */
  1775. if (xhci->port_array[i] != major_revision &&
  1776. xhci->port_array[i] != DUPLICATE_ENTRY) {
  1777. if (xhci->port_array[i] == 0x03)
  1778. xhci->num_usb3_ports--;
  1779. else
  1780. xhci->num_usb2_ports--;
  1781. xhci->port_array[i] = DUPLICATE_ENTRY;
  1782. }
  1783. /* FIXME: Should we disable the port? */
  1784. continue;
  1785. }
  1786. xhci->port_array[i] = major_revision;
  1787. if (major_revision == 0x03)
  1788. xhci->num_usb3_ports++;
  1789. else
  1790. xhci->num_usb2_ports++;
  1791. }
  1792. /* FIXME: Should we disable ports not in the Extended Capabilities? */
  1793. }
  1794. /*
  1795. * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that
  1796. * specify what speeds each port is supposed to be. We can't count on the port
  1797. * speed bits in the PORTSC register being correct until a device is connected,
  1798. * but we need to set up the two fake roothubs with the correct number of USB
  1799. * 3.0 and USB 2.0 ports at host controller initialization time.
  1800. */
  1801. static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags)
  1802. {
  1803. __le32 __iomem *addr;
  1804. u32 offset;
  1805. unsigned int num_ports;
  1806. int i, j, port_index;
  1807. addr = &xhci->cap_regs->hcc_params;
  1808. offset = XHCI_HCC_EXT_CAPS(xhci_readl(xhci, addr));
  1809. if (offset == 0) {
  1810. xhci_err(xhci, "No Extended Capability registers, "
  1811. "unable to set up roothub.\n");
  1812. return -ENODEV;
  1813. }
  1814. num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
  1815. xhci->port_array = kzalloc(sizeof(*xhci->port_array)*num_ports, flags);
  1816. if (!xhci->port_array)
  1817. return -ENOMEM;
  1818. xhci->rh_bw = kzalloc(sizeof(*xhci->rh_bw)*num_ports, flags);
  1819. if (!xhci->rh_bw)
  1820. return -ENOMEM;
  1821. for (i = 0; i < num_ports; i++) {
  1822. struct xhci_interval_bw_table *bw_table;
  1823. INIT_LIST_HEAD(&xhci->rh_bw[i].tts);
  1824. bw_table = &xhci->rh_bw[i].bw_table;
  1825. for (j = 0; j < XHCI_MAX_INTERVAL; j++)
  1826. INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
  1827. }
  1828. /*
  1829. * For whatever reason, the first capability offset is from the
  1830. * capability register base, not from the HCCPARAMS register.
  1831. * See section 5.3.6 for offset calculation.
  1832. */
  1833. addr = &xhci->cap_regs->hc_capbase + offset;
  1834. while (1) {
  1835. u32 cap_id;
  1836. cap_id = xhci_readl(xhci, addr);
  1837. if (XHCI_EXT_CAPS_ID(cap_id) == XHCI_EXT_CAPS_PROTOCOL)
  1838. xhci_add_in_port(xhci, num_ports, addr,
  1839. (u8) XHCI_EXT_PORT_MAJOR(cap_id));
  1840. offset = XHCI_EXT_CAPS_NEXT(cap_id);
  1841. if (!offset || (xhci->num_usb2_ports + xhci->num_usb3_ports)
  1842. == num_ports)
  1843. break;
  1844. /*
  1845. * Once you're into the Extended Capabilities, the offset is
  1846. * always relative to the register holding the offset.
  1847. */
  1848. addr += offset;
  1849. }
  1850. if (xhci->num_usb2_ports == 0 && xhci->num_usb3_ports == 0) {
  1851. xhci_warn(xhci, "No ports on the roothubs?\n");
  1852. return -ENODEV;
  1853. }
  1854. xhci_dbg(xhci, "Found %u USB 2.0 ports and %u USB 3.0 ports.\n",
  1855. xhci->num_usb2_ports, xhci->num_usb3_ports);
  1856. /* Place limits on the number of roothub ports so that the hub
  1857. * descriptors aren't longer than the USB core will allocate.
  1858. */
  1859. if (xhci->num_usb3_ports > 15) {
  1860. xhci_dbg(xhci, "Limiting USB 3.0 roothub ports to 15.\n");
  1861. xhci->num_usb3_ports = 15;
  1862. }
  1863. if (xhci->num_usb2_ports > USB_MAXCHILDREN) {
  1864. xhci_dbg(xhci, "Limiting USB 2.0 roothub ports to %u.\n",
  1865. USB_MAXCHILDREN);
  1866. xhci->num_usb2_ports = USB_MAXCHILDREN;
  1867. }
  1868. /*
  1869. * Note we could have all USB 3.0 ports, or all USB 2.0 ports.
  1870. * Not sure how the USB core will handle a hub with no ports...
  1871. */
  1872. if (xhci->num_usb2_ports) {
  1873. xhci->usb2_ports = kmalloc(sizeof(*xhci->usb2_ports)*
  1874. xhci->num_usb2_ports, flags);
  1875. if (!xhci->usb2_ports)
  1876. return -ENOMEM;
  1877. port_index = 0;
  1878. for (i = 0; i < num_ports; i++) {
  1879. if (xhci->port_array[i] == 0x03 ||
  1880. xhci->port_array[i] == 0 ||
  1881. xhci->port_array[i] == DUPLICATE_ENTRY)
  1882. continue;
  1883. xhci->usb2_ports[port_index] =
  1884. &xhci->op_regs->port_status_base +
  1885. NUM_PORT_REGS*i;
  1886. xhci_dbg(xhci, "USB 2.0 port at index %u, "
  1887. "addr = %p\n", i,
  1888. xhci->usb2_ports[port_index]);
  1889. port_index++;
  1890. if (port_index == xhci->num_usb2_ports)
  1891. break;
  1892. }
  1893. }
  1894. if (xhci->num_usb3_ports) {
  1895. xhci->usb3_ports = kmalloc(sizeof(*xhci->usb3_ports)*
  1896. xhci->num_usb3_ports, flags);
  1897. if (!xhci->usb3_ports)
  1898. return -ENOMEM;
  1899. port_index = 0;
  1900. for (i = 0; i < num_ports; i++)
  1901. if (xhci->port_array[i] == 0x03) {
  1902. xhci->usb3_ports[port_index] =
  1903. &xhci->op_regs->port_status_base +
  1904. NUM_PORT_REGS*i;
  1905. xhci_dbg(xhci, "USB 3.0 port at index %u, "
  1906. "addr = %p\n", i,
  1907. xhci->usb3_ports[port_index]);
  1908. port_index++;
  1909. if (port_index == xhci->num_usb3_ports)
  1910. break;
  1911. }
  1912. }
  1913. return 0;
  1914. }
  1915. int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
  1916. {
  1917. dma_addr_t dma;
  1918. struct device *dev = xhci_to_hcd(xhci)->self.controller;
  1919. unsigned int val, val2;
  1920. u64 val_64;
  1921. struct xhci_segment *seg;
  1922. u32 page_size;
  1923. int i;
  1924. page_size = xhci_readl(xhci, &xhci->op_regs->page_size);
  1925. xhci_dbg(xhci, "Supported page size register = 0x%x\n", page_size);
  1926. for (i = 0; i < 16; i++) {
  1927. if ((0x1 & page_size) != 0)
  1928. break;
  1929. page_size = page_size >> 1;
  1930. }
  1931. if (i < 16)
  1932. xhci_dbg(xhci, "Supported page size of %iK\n", (1 << (i+12)) / 1024);
  1933. else
  1934. xhci_warn(xhci, "WARN: no supported page size\n");
  1935. /* Use 4K pages, since that's common and the minimum the HC supports */
  1936. xhci->page_shift = 12;
  1937. xhci->page_size = 1 << xhci->page_shift;
  1938. xhci_dbg(xhci, "HCD page size set to %iK\n", xhci->page_size / 1024);
  1939. /*
  1940. * Program the Number of Device Slots Enabled field in the CONFIG
  1941. * register with the max value of slots the HC can handle.
  1942. */
  1943. val = HCS_MAX_SLOTS(xhci_readl(xhci, &xhci->cap_regs->hcs_params1));
  1944. xhci_dbg(xhci, "// xHC can handle at most %d device slots.\n",
  1945. (unsigned int) val);
  1946. val2 = xhci_readl(xhci, &xhci->op_regs->config_reg);
  1947. val |= (val2 & ~HCS_SLOTS_MASK);
  1948. xhci_dbg(xhci, "// Setting Max device slots reg = 0x%x.\n",
  1949. (unsigned int) val);
  1950. xhci_writel(xhci, val, &xhci->op_regs->config_reg);
  1951. /*
  1952. * Section 5.4.8 - doorbell array must be
  1953. * "physically contiguous and 64-byte (cache line) aligned".
  1954. */
  1955. xhci->dcbaa = dma_alloc_coherent(dev, sizeof(*xhci->dcbaa), &dma,
  1956. GFP_KERNEL);
  1957. if (!xhci->dcbaa)
  1958. goto fail;
  1959. memset(xhci->dcbaa, 0, sizeof *(xhci->dcbaa));
  1960. xhci->dcbaa->dma = dma;
  1961. xhci_dbg(xhci, "// Device context base array address = 0x%llx (DMA), %p (virt)\n",
  1962. (unsigned long long)xhci->dcbaa->dma, xhci->dcbaa);
  1963. xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr);
  1964. /*
  1965. * Initialize the ring segment pool. The ring must be a contiguous
  1966. * structure comprised of TRBs. The TRBs must be 16 byte aligned,
  1967. * however, the command ring segment needs 64-byte aligned segments,
  1968. * so we pick the greater alignment need.
  1969. */
  1970. xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
  1971. SEGMENT_SIZE, 64, xhci->page_size);
  1972. /* See Table 46 and Note on Figure 55 */
  1973. xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev,
  1974. 2112, 64, xhci->page_size);
  1975. if (!xhci->segment_pool || !xhci->device_pool)
  1976. goto fail;
  1977. /* Linear stream context arrays don't have any boundary restrictions,
  1978. * and only need to be 16-byte aligned.
  1979. */
  1980. xhci->small_streams_pool =
  1981. dma_pool_create("xHCI 256 byte stream ctx arrays",
  1982. dev, SMALL_STREAM_ARRAY_SIZE, 16, 0);
  1983. xhci->medium_streams_pool =
  1984. dma_pool_create("xHCI 1KB stream ctx arrays",
  1985. dev, MEDIUM_STREAM_ARRAY_SIZE, 16, 0);
  1986. /* Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE
  1987. * will be allocated with dma_alloc_coherent()
  1988. */
  1989. if (!xhci->small_streams_pool || !xhci->medium_streams_pool)
  1990. goto fail;
  1991. /* Set up the command ring to have one segments for now. */
  1992. xhci->cmd_ring = xhci_ring_alloc(xhci, 1, true, false, flags);
  1993. if (!xhci->cmd_ring)
  1994. goto fail;
  1995. xhci_dbg(xhci, "Allocated command ring at %p\n", xhci->cmd_ring);
  1996. xhci_dbg(xhci, "First segment DMA is 0x%llx\n",
  1997. (unsigned long long)xhci->cmd_ring->first_seg->dma);
  1998. /* Set the address in the Command Ring Control register */
  1999. val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
  2000. val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
  2001. (xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) |
  2002. xhci->cmd_ring->cycle_state;
  2003. xhci_dbg(xhci, "// Setting command ring address to 0x%x\n", val);
  2004. xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
  2005. xhci_dbg_cmd_ptrs(xhci);
  2006. val = xhci_readl(xhci, &xhci->cap_regs->db_off);
  2007. val &= DBOFF_MASK;
  2008. xhci_dbg(xhci, "// Doorbell array is located at offset 0x%x"
  2009. " from cap regs base addr\n", val);
  2010. xhci->dba = (void __iomem *) xhci->cap_regs + val;
  2011. xhci_dbg_regs(xhci);
  2012. xhci_print_run_regs(xhci);
  2013. /* Set ir_set to interrupt register set 0 */
  2014. xhci->ir_set = &xhci->run_regs->ir_set[0];
  2015. /*
  2016. * Event ring setup: Allocate a normal ring, but also setup
  2017. * the event ring segment table (ERST). Section 4.9.3.
  2018. */
  2019. xhci_dbg(xhci, "// Allocating event ring\n");
  2020. xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, false, false,
  2021. flags);
  2022. if (!xhci->event_ring)
  2023. goto fail;
  2024. if (xhci_check_trb_in_td_math(xhci, flags) < 0)
  2025. goto fail;
  2026. xhci->erst.entries = dma_alloc_coherent(dev,
  2027. sizeof(struct xhci_erst_entry) * ERST_NUM_SEGS, &dma,
  2028. GFP_KERNEL);
  2029. if (!xhci->erst.entries)
  2030. goto fail;
  2031. xhci_dbg(xhci, "// Allocated event ring segment table at 0x%llx\n",
  2032. (unsigned long long)dma);
  2033. memset(xhci->erst.entries, 0, sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS);
  2034. xhci->erst.num_entries = ERST_NUM_SEGS;
  2035. xhci->erst.erst_dma_addr = dma;
  2036. xhci_dbg(xhci, "Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx\n",
  2037. xhci->erst.num_entries,
  2038. xhci->erst.entries,
  2039. (unsigned long long)xhci->erst.erst_dma_addr);
  2040. /* set ring base address and size for each segment table entry */
  2041. for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) {
  2042. struct xhci_erst_entry *entry = &xhci->erst.entries[val];
  2043. entry->seg_addr = cpu_to_le64(seg->dma);
  2044. entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT);
  2045. entry->rsvd = 0;
  2046. seg = seg->next;
  2047. }
  2048. /* set ERST count with the number of entries in the segment table */
  2049. val = xhci_readl(xhci, &xhci->ir_set->erst_size);
  2050. val &= ERST_SIZE_MASK;
  2051. val |= ERST_NUM_SEGS;
  2052. xhci_dbg(xhci, "// Write ERST size = %i to ir_set 0 (some bits preserved)\n",
  2053. val);
  2054. xhci_writel(xhci, val, &xhci->ir_set->erst_size);
  2055. xhci_dbg(xhci, "// Set ERST entries to point to event ring.\n");
  2056. /* set the segment table base address */
  2057. xhci_dbg(xhci, "// Set ERST base address for ir_set 0 = 0x%llx\n",
  2058. (unsigned long long)xhci->erst.erst_dma_addr);
  2059. val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base);
  2060. val_64 &= ERST_PTR_MASK;
  2061. val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK);
  2062. xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base);
  2063. /* Set the event ring dequeue address */
  2064. xhci_set_hc_event_deq(xhci);
  2065. xhci_dbg(xhci, "Wrote ERST address to ir_set 0.\n");
  2066. xhci_print_ir_set(xhci, 0);
  2067. /*
  2068. * XXX: Might need to set the Interrupter Moderation Register to
  2069. * something other than the default (~1ms minimum between interrupts).
  2070. * See section 5.5.1.2.
  2071. */
  2072. init_completion(&xhci->addr_dev);
  2073. for (i = 0; i < MAX_HC_SLOTS; ++i)
  2074. xhci->devs[i] = NULL;
  2075. for (i = 0; i < USB_MAXCHILDREN; ++i) {
  2076. xhci->bus_state[0].resume_done[i] = 0;
  2077. xhci->bus_state[1].resume_done[i] = 0;
  2078. }
  2079. if (scratchpad_alloc(xhci, flags))
  2080. goto fail;
  2081. if (xhci_setup_port_arrays(xhci, flags))
  2082. goto fail;
  2083. INIT_LIST_HEAD(&xhci->lpm_failed_devs);
  2084. return 0;
  2085. fail:
  2086. xhci_warn(xhci, "Couldn't initialize memory\n");
  2087. xhci_mem_cleanup(xhci);
  2088. return -ENOMEM;
  2089. }