langwell_udc.c 86 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084308530863087308830893090309130923093309430953096309730983099310031013102310331043105310631073108310931103111311231133114311531163117311831193120312131223123312431253126312731283129313031313132313331343135313631373138313931403141314231433144314531463147314831493150315131523153315431553156315731583159316031613162316331643165316631673168316931703171317231733174317531763177317831793180318131823183318431853186318731883189319031913192319331943195319631973198319932003201320232033204320532063207320832093210321132123213321432153216321732183219322032213222322332243225322632273228322932303231323232333234323532363237323832393240324132423243324432453246324732483249325032513252325332543255325632573258325932603261326232633264326532663267326832693270327132723273327432753276327732783279328032813282328332843285328632873288328932903291329232933294329532963297329832993300330133023303330433053306330733083309331033113312331333143315331633173318331933203321332233233324332533263327332833293330333133323333333433353336333733383339334033413342334333443345334633473348334933503351335233533354335533563357335833593360336133623363336433653366336733683369337033713372337333743375337633773378337933803381338233833384338533863387338833893390339133923393339433953396339733983399340034013402340334043405340634073408340934103411341234133414341534163417341834193420342134223423342434253426342734283429343034313432343334343435343634373438343934403441344234433444344534463447344834493450345134523453345434553456345734583459346034613462346334643465
  1. /*
  2. * Intel Langwell USB Device Controller driver
  3. * Copyright (C) 2008-2009, Intel Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. */
  9. /* #undef DEBUG */
  10. /* #undef VERBOSE_DEBUG */
  11. #include <linux/module.h>
  12. #include <linux/pci.h>
  13. #include <linux/dma-mapping.h>
  14. #include <linux/kernel.h>
  15. #include <linux/delay.h>
  16. #include <linux/ioport.h>
  17. #include <linux/sched.h>
  18. #include <linux/slab.h>
  19. #include <linux/errno.h>
  20. #include <linux/init.h>
  21. #include <linux/timer.h>
  22. #include <linux/list.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/moduleparam.h>
  25. #include <linux/device.h>
  26. #include <linux/usb/ch9.h>
  27. #include <linux/usb/gadget.h>
  28. #include <linux/usb/otg.h>
  29. #include <linux/pm.h>
  30. #include <linux/io.h>
  31. #include <linux/irq.h>
  32. #include <asm/system.h>
  33. #include <asm/unaligned.h>
  34. #include "langwell_udc.h"
  35. #define DRIVER_DESC "Intel Langwell USB Device Controller driver"
  36. #define DRIVER_VERSION "16 May 2009"
  37. static const char driver_name[] = "langwell_udc";
  38. static const char driver_desc[] = DRIVER_DESC;
  39. /* for endpoint 0 operations */
  40. static const struct usb_endpoint_descriptor
  41. langwell_ep0_desc = {
  42. .bLength = USB_DT_ENDPOINT_SIZE,
  43. .bDescriptorType = USB_DT_ENDPOINT,
  44. .bEndpointAddress = 0,
  45. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  46. .wMaxPacketSize = EP0_MAX_PKT_SIZE,
  47. };
  48. /*-------------------------------------------------------------------------*/
  49. /* debugging */
  50. #ifdef VERBOSE_DEBUG
  51. static inline void print_all_registers(struct langwell_udc *dev)
  52. {
  53. int i;
  54. /* Capability Registers */
  55. dev_dbg(&dev->pdev->dev,
  56. "Capability Registers (offset: 0x%04x, length: 0x%08x)\n",
  57. CAP_REG_OFFSET, (u32)sizeof(struct langwell_cap_regs));
  58. dev_dbg(&dev->pdev->dev, "caplength=0x%02x\n",
  59. readb(&dev->cap_regs->caplength));
  60. dev_dbg(&dev->pdev->dev, "hciversion=0x%04x\n",
  61. readw(&dev->cap_regs->hciversion));
  62. dev_dbg(&dev->pdev->dev, "hcsparams=0x%08x\n",
  63. readl(&dev->cap_regs->hcsparams));
  64. dev_dbg(&dev->pdev->dev, "hccparams=0x%08x\n",
  65. readl(&dev->cap_regs->hccparams));
  66. dev_dbg(&dev->pdev->dev, "dciversion=0x%04x\n",
  67. readw(&dev->cap_regs->dciversion));
  68. dev_dbg(&dev->pdev->dev, "dccparams=0x%08x\n",
  69. readl(&dev->cap_regs->dccparams));
  70. /* Operational Registers */
  71. dev_dbg(&dev->pdev->dev,
  72. "Operational Registers (offset: 0x%04x, length: 0x%08x)\n",
  73. OP_REG_OFFSET, (u32)sizeof(struct langwell_op_regs));
  74. dev_dbg(&dev->pdev->dev, "extsts=0x%08x\n",
  75. readl(&dev->op_regs->extsts));
  76. dev_dbg(&dev->pdev->dev, "extintr=0x%08x\n",
  77. readl(&dev->op_regs->extintr));
  78. dev_dbg(&dev->pdev->dev, "usbcmd=0x%08x\n",
  79. readl(&dev->op_regs->usbcmd));
  80. dev_dbg(&dev->pdev->dev, "usbsts=0x%08x\n",
  81. readl(&dev->op_regs->usbsts));
  82. dev_dbg(&dev->pdev->dev, "usbintr=0x%08x\n",
  83. readl(&dev->op_regs->usbintr));
  84. dev_dbg(&dev->pdev->dev, "frindex=0x%08x\n",
  85. readl(&dev->op_regs->frindex));
  86. dev_dbg(&dev->pdev->dev, "ctrldssegment=0x%08x\n",
  87. readl(&dev->op_regs->ctrldssegment));
  88. dev_dbg(&dev->pdev->dev, "deviceaddr=0x%08x\n",
  89. readl(&dev->op_regs->deviceaddr));
  90. dev_dbg(&dev->pdev->dev, "endpointlistaddr=0x%08x\n",
  91. readl(&dev->op_regs->endpointlistaddr));
  92. dev_dbg(&dev->pdev->dev, "ttctrl=0x%08x\n",
  93. readl(&dev->op_regs->ttctrl));
  94. dev_dbg(&dev->pdev->dev, "burstsize=0x%08x\n",
  95. readl(&dev->op_regs->burstsize));
  96. dev_dbg(&dev->pdev->dev, "txfilltuning=0x%08x\n",
  97. readl(&dev->op_regs->txfilltuning));
  98. dev_dbg(&dev->pdev->dev, "txttfilltuning=0x%08x\n",
  99. readl(&dev->op_regs->txttfilltuning));
  100. dev_dbg(&dev->pdev->dev, "ic_usb=0x%08x\n",
  101. readl(&dev->op_regs->ic_usb));
  102. dev_dbg(&dev->pdev->dev, "ulpi_viewport=0x%08x\n",
  103. readl(&dev->op_regs->ulpi_viewport));
  104. dev_dbg(&dev->pdev->dev, "configflag=0x%08x\n",
  105. readl(&dev->op_regs->configflag));
  106. dev_dbg(&dev->pdev->dev, "portsc1=0x%08x\n",
  107. readl(&dev->op_regs->portsc1));
  108. dev_dbg(&dev->pdev->dev, "devlc=0x%08x\n",
  109. readl(&dev->op_regs->devlc));
  110. dev_dbg(&dev->pdev->dev, "otgsc=0x%08x\n",
  111. readl(&dev->op_regs->otgsc));
  112. dev_dbg(&dev->pdev->dev, "usbmode=0x%08x\n",
  113. readl(&dev->op_regs->usbmode));
  114. dev_dbg(&dev->pdev->dev, "endptnak=0x%08x\n",
  115. readl(&dev->op_regs->endptnak));
  116. dev_dbg(&dev->pdev->dev, "endptnaken=0x%08x\n",
  117. readl(&dev->op_regs->endptnaken));
  118. dev_dbg(&dev->pdev->dev, "endptsetupstat=0x%08x\n",
  119. readl(&dev->op_regs->endptsetupstat));
  120. dev_dbg(&dev->pdev->dev, "endptprime=0x%08x\n",
  121. readl(&dev->op_regs->endptprime));
  122. dev_dbg(&dev->pdev->dev, "endptflush=0x%08x\n",
  123. readl(&dev->op_regs->endptflush));
  124. dev_dbg(&dev->pdev->dev, "endptstat=0x%08x\n",
  125. readl(&dev->op_regs->endptstat));
  126. dev_dbg(&dev->pdev->dev, "endptcomplete=0x%08x\n",
  127. readl(&dev->op_regs->endptcomplete));
  128. for (i = 0; i < dev->ep_max / 2; i++) {
  129. dev_dbg(&dev->pdev->dev, "endptctrl[%d]=0x%08x\n",
  130. i, readl(&dev->op_regs->endptctrl[i]));
  131. }
  132. }
  133. #else
  134. #define print_all_registers(dev) do { } while (0)
  135. #endif /* VERBOSE_DEBUG */
  136. /*-------------------------------------------------------------------------*/
  137. #define is_in(ep) (((ep)->ep_num == 0) ? ((ep)->dev->ep0_dir == \
  138. USB_DIR_IN) : (usb_endpoint_dir_in((ep)->desc)))
  139. #define DIR_STRING(ep) (is_in(ep) ? "in" : "out")
  140. static char *type_string(const struct usb_endpoint_descriptor *desc)
  141. {
  142. switch (usb_endpoint_type(desc)) {
  143. case USB_ENDPOINT_XFER_BULK:
  144. return "bulk";
  145. case USB_ENDPOINT_XFER_ISOC:
  146. return "iso";
  147. case USB_ENDPOINT_XFER_INT:
  148. return "int";
  149. };
  150. return "control";
  151. }
  152. /* configure endpoint control registers */
  153. static void ep_reset(struct langwell_ep *ep, unsigned char ep_num,
  154. unsigned char is_in, unsigned char ep_type)
  155. {
  156. struct langwell_udc *dev;
  157. u32 endptctrl;
  158. dev = ep->dev;
  159. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  160. endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
  161. if (is_in) { /* TX */
  162. if (ep_num)
  163. endptctrl |= EPCTRL_TXR;
  164. endptctrl |= EPCTRL_TXE;
  165. endptctrl |= ep_type << EPCTRL_TXT_SHIFT;
  166. } else { /* RX */
  167. if (ep_num)
  168. endptctrl |= EPCTRL_RXR;
  169. endptctrl |= EPCTRL_RXE;
  170. endptctrl |= ep_type << EPCTRL_RXT_SHIFT;
  171. }
  172. writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
  173. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  174. }
  175. /* reset ep0 dQH and endptctrl */
  176. static void ep0_reset(struct langwell_udc *dev)
  177. {
  178. struct langwell_ep *ep;
  179. int i;
  180. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  181. /* ep0 in and out */
  182. for (i = 0; i < 2; i++) {
  183. ep = &dev->ep[i];
  184. ep->dev = dev;
  185. /* ep0 dQH */
  186. ep->dqh = &dev->ep_dqh[i];
  187. /* configure ep0 endpoint capabilities in dQH */
  188. ep->dqh->dqh_ios = 1;
  189. ep->dqh->dqh_mpl = EP0_MAX_PKT_SIZE;
  190. /* enable ep0-in HW zero length termination select */
  191. if (is_in(ep))
  192. ep->dqh->dqh_zlt = 0;
  193. ep->dqh->dqh_mult = 0;
  194. ep->dqh->dtd_next = DTD_TERM;
  195. /* configure ep0 control registers */
  196. ep_reset(&dev->ep[0], 0, i, USB_ENDPOINT_XFER_CONTROL);
  197. }
  198. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  199. }
  200. /*-------------------------------------------------------------------------*/
  201. /* endpoints operations */
  202. /* configure endpoint, making it usable */
  203. static int langwell_ep_enable(struct usb_ep *_ep,
  204. const struct usb_endpoint_descriptor *desc)
  205. {
  206. struct langwell_udc *dev;
  207. struct langwell_ep *ep;
  208. u16 max = 0;
  209. unsigned long flags;
  210. int i, retval = 0;
  211. unsigned char zlt, ios = 0, mult = 0;
  212. ep = container_of(_ep, struct langwell_ep, ep);
  213. dev = ep->dev;
  214. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  215. if (!_ep || !desc || ep->desc
  216. || desc->bDescriptorType != USB_DT_ENDPOINT)
  217. return -EINVAL;
  218. if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
  219. return -ESHUTDOWN;
  220. max = usb_endpoint_maxp(desc);
  221. /*
  222. * disable HW zero length termination select
  223. * driver handles zero length packet through req->req.zero
  224. */
  225. zlt = 1;
  226. /*
  227. * sanity check type, direction, address, and then
  228. * initialize the endpoint capabilities fields in dQH
  229. */
  230. switch (usb_endpoint_type(desc)) {
  231. case USB_ENDPOINT_XFER_CONTROL:
  232. ios = 1;
  233. break;
  234. case USB_ENDPOINT_XFER_BULK:
  235. if ((dev->gadget.speed == USB_SPEED_HIGH
  236. && max != 512)
  237. || (dev->gadget.speed == USB_SPEED_FULL
  238. && max > 64)) {
  239. goto done;
  240. }
  241. break;
  242. case USB_ENDPOINT_XFER_INT:
  243. if (strstr(ep->ep.name, "-iso")) /* bulk is ok */
  244. goto done;
  245. switch (dev->gadget.speed) {
  246. case USB_SPEED_HIGH:
  247. if (max <= 1024)
  248. break;
  249. case USB_SPEED_FULL:
  250. if (max <= 64)
  251. break;
  252. default:
  253. if (max <= 8)
  254. break;
  255. goto done;
  256. }
  257. break;
  258. case USB_ENDPOINT_XFER_ISOC:
  259. if (strstr(ep->ep.name, "-bulk")
  260. || strstr(ep->ep.name, "-int"))
  261. goto done;
  262. switch (dev->gadget.speed) {
  263. case USB_SPEED_HIGH:
  264. if (max <= 1024)
  265. break;
  266. case USB_SPEED_FULL:
  267. if (max <= 1023)
  268. break;
  269. default:
  270. goto done;
  271. }
  272. /*
  273. * FIXME:
  274. * calculate transactions needed for high bandwidth iso
  275. */
  276. mult = (unsigned char)(1 + ((max >> 11) & 0x03));
  277. max = max & 0x8ff; /* bit 0~10 */
  278. /* 3 transactions at most */
  279. if (mult > 3)
  280. goto done;
  281. break;
  282. default:
  283. goto done;
  284. }
  285. spin_lock_irqsave(&dev->lock, flags);
  286. ep->ep.maxpacket = max;
  287. ep->desc = desc;
  288. ep->stopped = 0;
  289. ep->ep_num = usb_endpoint_num(desc);
  290. /* ep_type */
  291. ep->ep_type = usb_endpoint_type(desc);
  292. /* configure endpoint control registers */
  293. ep_reset(ep, ep->ep_num, is_in(ep), ep->ep_type);
  294. /* configure endpoint capabilities in dQH */
  295. i = ep->ep_num * 2 + is_in(ep);
  296. ep->dqh = &dev->ep_dqh[i];
  297. ep->dqh->dqh_ios = ios;
  298. ep->dqh->dqh_mpl = cpu_to_le16(max);
  299. ep->dqh->dqh_zlt = zlt;
  300. ep->dqh->dqh_mult = mult;
  301. ep->dqh->dtd_next = DTD_TERM;
  302. dev_dbg(&dev->pdev->dev, "enabled %s (ep%d%s-%s), max %04x\n",
  303. _ep->name,
  304. ep->ep_num,
  305. DIR_STRING(ep),
  306. type_string(desc),
  307. max);
  308. spin_unlock_irqrestore(&dev->lock, flags);
  309. done:
  310. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  311. return retval;
  312. }
  313. /*-------------------------------------------------------------------------*/
  314. /* retire a request */
  315. static void done(struct langwell_ep *ep, struct langwell_request *req,
  316. int status)
  317. {
  318. struct langwell_udc *dev = ep->dev;
  319. unsigned stopped = ep->stopped;
  320. struct langwell_dtd *curr_dtd, *next_dtd;
  321. int i;
  322. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  323. /* remove the req from ep->queue */
  324. list_del_init(&req->queue);
  325. if (req->req.status == -EINPROGRESS)
  326. req->req.status = status;
  327. else
  328. status = req->req.status;
  329. /* free dTD for the request */
  330. next_dtd = req->head;
  331. for (i = 0; i < req->dtd_count; i++) {
  332. curr_dtd = next_dtd;
  333. if (i != req->dtd_count - 1)
  334. next_dtd = curr_dtd->next_dtd_virt;
  335. dma_pool_free(dev->dtd_pool, curr_dtd, curr_dtd->dtd_dma);
  336. }
  337. if (req->mapped) {
  338. dma_unmap_single(&dev->pdev->dev,
  339. req->req.dma, req->req.length,
  340. is_in(ep) ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  341. req->req.dma = DMA_ADDR_INVALID;
  342. req->mapped = 0;
  343. } else
  344. dma_sync_single_for_cpu(&dev->pdev->dev, req->req.dma,
  345. req->req.length,
  346. is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  347. if (status != -ESHUTDOWN)
  348. dev_dbg(&dev->pdev->dev,
  349. "complete %s, req %p, stat %d, len %u/%u\n",
  350. ep->ep.name, &req->req, status,
  351. req->req.actual, req->req.length);
  352. /* don't modify queue heads during completion callback */
  353. ep->stopped = 1;
  354. spin_unlock(&dev->lock);
  355. /* complete routine from gadget driver */
  356. if (req->req.complete)
  357. req->req.complete(&ep->ep, &req->req);
  358. spin_lock(&dev->lock);
  359. ep->stopped = stopped;
  360. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  361. }
  362. static void langwell_ep_fifo_flush(struct usb_ep *_ep);
  363. /* delete all endpoint requests, called with spinlock held */
  364. static void nuke(struct langwell_ep *ep, int status)
  365. {
  366. /* called with spinlock held */
  367. ep->stopped = 1;
  368. /* endpoint fifo flush */
  369. if (&ep->ep && ep->desc)
  370. langwell_ep_fifo_flush(&ep->ep);
  371. while (!list_empty(&ep->queue)) {
  372. struct langwell_request *req = NULL;
  373. req = list_entry(ep->queue.next, struct langwell_request,
  374. queue);
  375. done(ep, req, status);
  376. }
  377. }
  378. /*-------------------------------------------------------------------------*/
  379. /* endpoint is no longer usable */
  380. static int langwell_ep_disable(struct usb_ep *_ep)
  381. {
  382. struct langwell_ep *ep;
  383. unsigned long flags;
  384. struct langwell_udc *dev;
  385. int ep_num;
  386. u32 endptctrl;
  387. ep = container_of(_ep, struct langwell_ep, ep);
  388. dev = ep->dev;
  389. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  390. if (!_ep || !ep->desc)
  391. return -EINVAL;
  392. spin_lock_irqsave(&dev->lock, flags);
  393. /* disable endpoint control register */
  394. ep_num = ep->ep_num;
  395. endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
  396. if (is_in(ep))
  397. endptctrl &= ~EPCTRL_TXE;
  398. else
  399. endptctrl &= ~EPCTRL_RXE;
  400. writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
  401. /* nuke all pending requests (does flush) */
  402. nuke(ep, -ESHUTDOWN);
  403. ep->desc = NULL;
  404. ep->stopped = 1;
  405. spin_unlock_irqrestore(&dev->lock, flags);
  406. dev_dbg(&dev->pdev->dev, "disabled %s\n", _ep->name);
  407. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  408. return 0;
  409. }
  410. /* allocate a request object to use with this endpoint */
  411. static struct usb_request *langwell_alloc_request(struct usb_ep *_ep,
  412. gfp_t gfp_flags)
  413. {
  414. struct langwell_ep *ep;
  415. struct langwell_udc *dev;
  416. struct langwell_request *req = NULL;
  417. if (!_ep)
  418. return NULL;
  419. ep = container_of(_ep, struct langwell_ep, ep);
  420. dev = ep->dev;
  421. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  422. req = kzalloc(sizeof(*req), gfp_flags);
  423. if (!req)
  424. return NULL;
  425. req->req.dma = DMA_ADDR_INVALID;
  426. INIT_LIST_HEAD(&req->queue);
  427. dev_vdbg(&dev->pdev->dev, "alloc request for %s\n", _ep->name);
  428. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  429. return &req->req;
  430. }
  431. /* free a request object */
  432. static void langwell_free_request(struct usb_ep *_ep,
  433. struct usb_request *_req)
  434. {
  435. struct langwell_ep *ep;
  436. struct langwell_udc *dev;
  437. struct langwell_request *req = NULL;
  438. ep = container_of(_ep, struct langwell_ep, ep);
  439. dev = ep->dev;
  440. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  441. if (!_ep || !_req)
  442. return;
  443. req = container_of(_req, struct langwell_request, req);
  444. WARN_ON(!list_empty(&req->queue));
  445. if (_req)
  446. kfree(req);
  447. dev_vdbg(&dev->pdev->dev, "free request for %s\n", _ep->name);
  448. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  449. }
  450. /*-------------------------------------------------------------------------*/
  451. /* queue dTD and PRIME endpoint */
  452. static int queue_dtd(struct langwell_ep *ep, struct langwell_request *req)
  453. {
  454. u32 bit_mask, usbcmd, endptstat, dtd_dma;
  455. u8 dtd_status;
  456. int i;
  457. struct langwell_dqh *dqh;
  458. struct langwell_udc *dev;
  459. dev = ep->dev;
  460. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  461. i = ep->ep_num * 2 + is_in(ep);
  462. dqh = &dev->ep_dqh[i];
  463. if (ep->ep_num)
  464. dev_vdbg(&dev->pdev->dev, "%s\n", ep->name);
  465. else
  466. /* ep0 */
  467. dev_vdbg(&dev->pdev->dev, "%s-%s\n", ep->name, DIR_STRING(ep));
  468. dev_vdbg(&dev->pdev->dev, "ep_dqh[%d] addr: 0x%p\n",
  469. i, &(dev->ep_dqh[i]));
  470. bit_mask = is_in(ep) ?
  471. (1 << (ep->ep_num + 16)) : (1 << (ep->ep_num));
  472. dev_vdbg(&dev->pdev->dev, "bit_mask = 0x%08x\n", bit_mask);
  473. /* check if the pipe is empty */
  474. if (!(list_empty(&ep->queue))) {
  475. /* add dTD to the end of linked list */
  476. struct langwell_request *lastreq;
  477. lastreq = list_entry(ep->queue.prev,
  478. struct langwell_request, queue);
  479. lastreq->tail->dtd_next =
  480. cpu_to_le32(req->head->dtd_dma & DTD_NEXT_MASK);
  481. /* read prime bit, if 1 goto out */
  482. if (readl(&dev->op_regs->endptprime) & bit_mask)
  483. goto out;
  484. do {
  485. /* set ATDTW bit in USBCMD */
  486. usbcmd = readl(&dev->op_regs->usbcmd);
  487. writel(usbcmd | CMD_ATDTW, &dev->op_regs->usbcmd);
  488. /* read correct status bit */
  489. endptstat = readl(&dev->op_regs->endptstat) & bit_mask;
  490. } while (!(readl(&dev->op_regs->usbcmd) & CMD_ATDTW));
  491. /* write ATDTW bit to 0 */
  492. usbcmd = readl(&dev->op_regs->usbcmd);
  493. writel(usbcmd & ~CMD_ATDTW, &dev->op_regs->usbcmd);
  494. if (endptstat)
  495. goto out;
  496. }
  497. /* write dQH next pointer and terminate bit to 0 */
  498. dtd_dma = req->head->dtd_dma & DTD_NEXT_MASK;
  499. dqh->dtd_next = cpu_to_le32(dtd_dma);
  500. /* clear active and halt bit */
  501. dtd_status = (u8) ~(DTD_STS_ACTIVE | DTD_STS_HALTED);
  502. dqh->dtd_status &= dtd_status;
  503. dev_vdbg(&dev->pdev->dev, "dqh->dtd_status = 0x%x\n", dqh->dtd_status);
  504. /* ensure that updates to the dQH will occur before priming */
  505. wmb();
  506. /* write 1 to endptprime register to PRIME endpoint */
  507. bit_mask = is_in(ep) ? (1 << (ep->ep_num + 16)) : (1 << ep->ep_num);
  508. dev_vdbg(&dev->pdev->dev, "endprime bit_mask = 0x%08x\n", bit_mask);
  509. writel(bit_mask, &dev->op_regs->endptprime);
  510. out:
  511. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  512. return 0;
  513. }
  514. /* fill in the dTD structure to build a transfer descriptor */
  515. static struct langwell_dtd *build_dtd(struct langwell_request *req,
  516. unsigned *length, dma_addr_t *dma, int *is_last)
  517. {
  518. u32 buf_ptr;
  519. struct langwell_dtd *dtd;
  520. struct langwell_udc *dev;
  521. int i;
  522. dev = req->ep->dev;
  523. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  524. /* the maximum transfer length, up to 16k bytes */
  525. *length = min(req->req.length - req->req.actual,
  526. (unsigned)DTD_MAX_TRANSFER_LENGTH);
  527. /* create dTD dma_pool resource */
  528. dtd = dma_pool_alloc(dev->dtd_pool, GFP_KERNEL, dma);
  529. if (dtd == NULL)
  530. return dtd;
  531. dtd->dtd_dma = *dma;
  532. /* initialize buffer page pointers */
  533. buf_ptr = (u32)(req->req.dma + req->req.actual);
  534. for (i = 0; i < 5; i++)
  535. dtd->dtd_buf[i] = cpu_to_le32(buf_ptr + i * PAGE_SIZE);
  536. req->req.actual += *length;
  537. /* fill in total bytes with transfer size */
  538. dtd->dtd_total = cpu_to_le16(*length);
  539. dev_vdbg(&dev->pdev->dev, "dtd->dtd_total = %d\n", dtd->dtd_total);
  540. /* set is_last flag if req->req.zero is set or not */
  541. if (req->req.zero) {
  542. if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
  543. *is_last = 1;
  544. else
  545. *is_last = 0;
  546. } else if (req->req.length == req->req.actual) {
  547. *is_last = 1;
  548. } else
  549. *is_last = 0;
  550. if (*is_last == 0)
  551. dev_vdbg(&dev->pdev->dev, "multi-dtd request!\n");
  552. /* set interrupt on complete bit for the last dTD */
  553. if (*is_last && !req->req.no_interrupt)
  554. dtd->dtd_ioc = 1;
  555. /* set multiplier override 0 for non-ISO and non-TX endpoint */
  556. dtd->dtd_multo = 0;
  557. /* set the active bit of status field to 1 */
  558. dtd->dtd_status = DTD_STS_ACTIVE;
  559. dev_vdbg(&dev->pdev->dev, "dtd->dtd_status = 0x%02x\n",
  560. dtd->dtd_status);
  561. dev_vdbg(&dev->pdev->dev, "length = %d, dma addr= 0x%08x\n",
  562. *length, (int)*dma);
  563. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  564. return dtd;
  565. }
  566. /* generate dTD linked list for a request */
  567. static int req_to_dtd(struct langwell_request *req)
  568. {
  569. unsigned count;
  570. int is_last, is_first = 1;
  571. struct langwell_dtd *dtd, *last_dtd = NULL;
  572. struct langwell_udc *dev;
  573. dma_addr_t dma;
  574. dev = req->ep->dev;
  575. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  576. do {
  577. dtd = build_dtd(req, &count, &dma, &is_last);
  578. if (dtd == NULL)
  579. return -ENOMEM;
  580. if (is_first) {
  581. is_first = 0;
  582. req->head = dtd;
  583. } else {
  584. last_dtd->dtd_next = cpu_to_le32(dma);
  585. last_dtd->next_dtd_virt = dtd;
  586. }
  587. last_dtd = dtd;
  588. req->dtd_count++;
  589. } while (!is_last);
  590. /* set terminate bit to 1 for the last dTD */
  591. dtd->dtd_next = DTD_TERM;
  592. req->tail = dtd;
  593. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  594. return 0;
  595. }
  596. /*-------------------------------------------------------------------------*/
  597. /* queue (submits) an I/O requests to an endpoint */
  598. static int langwell_ep_queue(struct usb_ep *_ep, struct usb_request *_req,
  599. gfp_t gfp_flags)
  600. {
  601. struct langwell_request *req;
  602. struct langwell_ep *ep;
  603. struct langwell_udc *dev;
  604. unsigned long flags;
  605. int is_iso = 0, zlflag = 0;
  606. /* always require a cpu-view buffer */
  607. req = container_of(_req, struct langwell_request, req);
  608. ep = container_of(_ep, struct langwell_ep, ep);
  609. if (!_req || !_req->complete || !_req->buf
  610. || !list_empty(&req->queue)) {
  611. return -EINVAL;
  612. }
  613. if (unlikely(!_ep || !ep->desc))
  614. return -EINVAL;
  615. dev = ep->dev;
  616. req->ep = ep;
  617. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  618. if (usb_endpoint_xfer_isoc(ep->desc)) {
  619. if (req->req.length > ep->ep.maxpacket)
  620. return -EMSGSIZE;
  621. is_iso = 1;
  622. }
  623. if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN))
  624. return -ESHUTDOWN;
  625. /* set up dma mapping in case the caller didn't */
  626. if (_req->dma == DMA_ADDR_INVALID) {
  627. /* WORKAROUND: WARN_ON(size == 0) */
  628. if (_req->length == 0) {
  629. dev_vdbg(&dev->pdev->dev, "req->length: 0->1\n");
  630. zlflag = 1;
  631. _req->length++;
  632. }
  633. _req->dma = dma_map_single(&dev->pdev->dev,
  634. _req->buf, _req->length,
  635. is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  636. if (zlflag && (_req->length == 1)) {
  637. dev_vdbg(&dev->pdev->dev, "req->length: 1->0\n");
  638. zlflag = 0;
  639. _req->length = 0;
  640. }
  641. req->mapped = 1;
  642. dev_vdbg(&dev->pdev->dev, "req->mapped = 1\n");
  643. } else {
  644. dma_sync_single_for_device(&dev->pdev->dev,
  645. _req->dma, _req->length,
  646. is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  647. req->mapped = 0;
  648. dev_vdbg(&dev->pdev->dev, "req->mapped = 0\n");
  649. }
  650. dev_dbg(&dev->pdev->dev,
  651. "%s queue req %p, len %u, buf %p, dma 0x%08x\n",
  652. _ep->name,
  653. _req, _req->length, _req->buf, (int)_req->dma);
  654. _req->status = -EINPROGRESS;
  655. _req->actual = 0;
  656. req->dtd_count = 0;
  657. spin_lock_irqsave(&dev->lock, flags);
  658. /* build and put dTDs to endpoint queue */
  659. if (!req_to_dtd(req)) {
  660. queue_dtd(ep, req);
  661. } else {
  662. spin_unlock_irqrestore(&dev->lock, flags);
  663. return -ENOMEM;
  664. }
  665. /* update ep0 state */
  666. if (ep->ep_num == 0)
  667. dev->ep0_state = DATA_STATE_XMIT;
  668. if (likely(req != NULL)) {
  669. list_add_tail(&req->queue, &ep->queue);
  670. dev_vdbg(&dev->pdev->dev, "list_add_tail()\n");
  671. }
  672. spin_unlock_irqrestore(&dev->lock, flags);
  673. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  674. return 0;
  675. }
  676. /* dequeue (cancels, unlinks) an I/O request from an endpoint */
  677. static int langwell_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  678. {
  679. struct langwell_ep *ep;
  680. struct langwell_udc *dev;
  681. struct langwell_request *req;
  682. unsigned long flags;
  683. int stopped, ep_num, retval = 0;
  684. u32 endptctrl;
  685. ep = container_of(_ep, struct langwell_ep, ep);
  686. dev = ep->dev;
  687. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  688. if (!_ep || !ep->desc || !_req)
  689. return -EINVAL;
  690. if (!dev->driver)
  691. return -ESHUTDOWN;
  692. spin_lock_irqsave(&dev->lock, flags);
  693. stopped = ep->stopped;
  694. /* quiesce dma while we patch the queue */
  695. ep->stopped = 1;
  696. ep_num = ep->ep_num;
  697. /* disable endpoint control register */
  698. endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
  699. if (is_in(ep))
  700. endptctrl &= ~EPCTRL_TXE;
  701. else
  702. endptctrl &= ~EPCTRL_RXE;
  703. writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
  704. /* make sure it's still queued on this endpoint */
  705. list_for_each_entry(req, &ep->queue, queue) {
  706. if (&req->req == _req)
  707. break;
  708. }
  709. if (&req->req != _req) {
  710. retval = -EINVAL;
  711. goto done;
  712. }
  713. /* queue head may be partially complete. */
  714. if (ep->queue.next == &req->queue) {
  715. dev_dbg(&dev->pdev->dev, "unlink (%s) dma\n", _ep->name);
  716. _req->status = -ECONNRESET;
  717. langwell_ep_fifo_flush(&ep->ep);
  718. /* not the last request in endpoint queue */
  719. if (likely(ep->queue.next == &req->queue)) {
  720. struct langwell_dqh *dqh;
  721. struct langwell_request *next_req;
  722. dqh = ep->dqh;
  723. next_req = list_entry(req->queue.next,
  724. struct langwell_request, queue);
  725. /* point the dQH to the first dTD of next request */
  726. writel((u32) next_req->head, &dqh->dqh_current);
  727. }
  728. } else {
  729. struct langwell_request *prev_req;
  730. prev_req = list_entry(req->queue.prev,
  731. struct langwell_request, queue);
  732. writel(readl(&req->tail->dtd_next),
  733. &prev_req->tail->dtd_next);
  734. }
  735. done(ep, req, -ECONNRESET);
  736. done:
  737. /* enable endpoint again */
  738. endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
  739. if (is_in(ep))
  740. endptctrl |= EPCTRL_TXE;
  741. else
  742. endptctrl |= EPCTRL_RXE;
  743. writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
  744. ep->stopped = stopped;
  745. spin_unlock_irqrestore(&dev->lock, flags);
  746. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  747. return retval;
  748. }
  749. /*-------------------------------------------------------------------------*/
  750. /* endpoint set/clear halt */
  751. static void ep_set_halt(struct langwell_ep *ep, int value)
  752. {
  753. u32 endptctrl = 0;
  754. int ep_num;
  755. struct langwell_udc *dev = ep->dev;
  756. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  757. ep_num = ep->ep_num;
  758. endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
  759. /* value: 1 - set halt, 0 - clear halt */
  760. if (value) {
  761. /* set the stall bit */
  762. if (is_in(ep))
  763. endptctrl |= EPCTRL_TXS;
  764. else
  765. endptctrl |= EPCTRL_RXS;
  766. } else {
  767. /* clear the stall bit and reset data toggle */
  768. if (is_in(ep)) {
  769. endptctrl &= ~EPCTRL_TXS;
  770. endptctrl |= EPCTRL_TXR;
  771. } else {
  772. endptctrl &= ~EPCTRL_RXS;
  773. endptctrl |= EPCTRL_RXR;
  774. }
  775. }
  776. writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
  777. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  778. }
  779. /* set the endpoint halt feature */
  780. static int langwell_ep_set_halt(struct usb_ep *_ep, int value)
  781. {
  782. struct langwell_ep *ep;
  783. struct langwell_udc *dev;
  784. unsigned long flags;
  785. int retval = 0;
  786. ep = container_of(_ep, struct langwell_ep, ep);
  787. dev = ep->dev;
  788. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  789. if (!_ep || !ep->desc)
  790. return -EINVAL;
  791. if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
  792. return -ESHUTDOWN;
  793. if (usb_endpoint_xfer_isoc(ep->desc))
  794. return -EOPNOTSUPP;
  795. spin_lock_irqsave(&dev->lock, flags);
  796. /*
  797. * attempt to halt IN ep will fail if any transfer requests
  798. * are still queue
  799. */
  800. if (!list_empty(&ep->queue) && is_in(ep) && value) {
  801. /* IN endpoint FIFO holds bytes */
  802. dev_dbg(&dev->pdev->dev, "%s FIFO holds bytes\n", _ep->name);
  803. retval = -EAGAIN;
  804. goto done;
  805. }
  806. /* endpoint set/clear halt */
  807. if (ep->ep_num) {
  808. ep_set_halt(ep, value);
  809. } else { /* endpoint 0 */
  810. dev->ep0_state = WAIT_FOR_SETUP;
  811. dev->ep0_dir = USB_DIR_OUT;
  812. }
  813. done:
  814. spin_unlock_irqrestore(&dev->lock, flags);
  815. dev_dbg(&dev->pdev->dev, "%s %s halt\n",
  816. _ep->name, value ? "set" : "clear");
  817. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  818. return retval;
  819. }
  820. /* set the halt feature and ignores clear requests */
  821. static int langwell_ep_set_wedge(struct usb_ep *_ep)
  822. {
  823. struct langwell_ep *ep;
  824. struct langwell_udc *dev;
  825. ep = container_of(_ep, struct langwell_ep, ep);
  826. dev = ep->dev;
  827. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  828. if (!_ep || !ep->desc)
  829. return -EINVAL;
  830. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  831. return usb_ep_set_halt(_ep);
  832. }
  833. /* flush contents of a fifo */
  834. static void langwell_ep_fifo_flush(struct usb_ep *_ep)
  835. {
  836. struct langwell_ep *ep;
  837. struct langwell_udc *dev;
  838. u32 flush_bit;
  839. unsigned long timeout;
  840. ep = container_of(_ep, struct langwell_ep, ep);
  841. dev = ep->dev;
  842. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  843. if (!_ep || !ep->desc) {
  844. dev_vdbg(&dev->pdev->dev, "ep or ep->desc is NULL\n");
  845. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  846. return;
  847. }
  848. dev_vdbg(&dev->pdev->dev, "%s-%s fifo flush\n",
  849. _ep->name, DIR_STRING(ep));
  850. /* flush endpoint buffer */
  851. if (ep->ep_num == 0)
  852. flush_bit = (1 << 16) | 1;
  853. else if (is_in(ep))
  854. flush_bit = 1 << (ep->ep_num + 16); /* TX */
  855. else
  856. flush_bit = 1 << ep->ep_num; /* RX */
  857. /* wait until flush complete */
  858. timeout = jiffies + FLUSH_TIMEOUT;
  859. do {
  860. writel(flush_bit, &dev->op_regs->endptflush);
  861. while (readl(&dev->op_regs->endptflush)) {
  862. if (time_after(jiffies, timeout)) {
  863. dev_err(&dev->pdev->dev, "ep flush timeout\n");
  864. goto done;
  865. }
  866. cpu_relax();
  867. }
  868. } while (readl(&dev->op_regs->endptstat) & flush_bit);
  869. done:
  870. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  871. }
  872. /* endpoints operations structure */
  873. static const struct usb_ep_ops langwell_ep_ops = {
  874. /* configure endpoint, making it usable */
  875. .enable = langwell_ep_enable,
  876. /* endpoint is no longer usable */
  877. .disable = langwell_ep_disable,
  878. /* allocate a request object to use with this endpoint */
  879. .alloc_request = langwell_alloc_request,
  880. /* free a request object */
  881. .free_request = langwell_free_request,
  882. /* queue (submits) an I/O requests to an endpoint */
  883. .queue = langwell_ep_queue,
  884. /* dequeue (cancels, unlinks) an I/O request from an endpoint */
  885. .dequeue = langwell_ep_dequeue,
  886. /* set the endpoint halt feature */
  887. .set_halt = langwell_ep_set_halt,
  888. /* set the halt feature and ignores clear requests */
  889. .set_wedge = langwell_ep_set_wedge,
  890. /* flush contents of a fifo */
  891. .fifo_flush = langwell_ep_fifo_flush,
  892. };
  893. /*-------------------------------------------------------------------------*/
  894. /* device controller usb_gadget_ops structure */
  895. /* returns the current frame number */
  896. static int langwell_get_frame(struct usb_gadget *_gadget)
  897. {
  898. struct langwell_udc *dev;
  899. u16 retval;
  900. if (!_gadget)
  901. return -ENODEV;
  902. dev = container_of(_gadget, struct langwell_udc, gadget);
  903. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  904. retval = readl(&dev->op_regs->frindex) & FRINDEX_MASK;
  905. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  906. return retval;
  907. }
  908. /* enter or exit PHY low power state */
  909. static void langwell_phy_low_power(struct langwell_udc *dev, bool flag)
  910. {
  911. u32 devlc;
  912. u8 devlc_byte2;
  913. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  914. devlc = readl(&dev->op_regs->devlc);
  915. dev_vdbg(&dev->pdev->dev, "devlc = 0x%08x\n", devlc);
  916. if (flag)
  917. devlc |= LPM_PHCD;
  918. else
  919. devlc &= ~LPM_PHCD;
  920. /* FIXME: workaround for Langwell A1/A2/A3 sighting */
  921. devlc_byte2 = (devlc >> 16) & 0xff;
  922. writeb(devlc_byte2, (u8 *)&dev->op_regs->devlc + 2);
  923. devlc = readl(&dev->op_regs->devlc);
  924. dev_vdbg(&dev->pdev->dev,
  925. "%s PHY low power suspend, devlc = 0x%08x\n",
  926. flag ? "enter" : "exit", devlc);
  927. }
  928. /* tries to wake up the host connected to this gadget */
  929. static int langwell_wakeup(struct usb_gadget *_gadget)
  930. {
  931. struct langwell_udc *dev;
  932. u32 portsc1;
  933. unsigned long flags;
  934. if (!_gadget)
  935. return 0;
  936. dev = container_of(_gadget, struct langwell_udc, gadget);
  937. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  938. /* remote wakeup feature not enabled by host */
  939. if (!dev->remote_wakeup) {
  940. dev_info(&dev->pdev->dev, "remote wakeup is disabled\n");
  941. return -ENOTSUPP;
  942. }
  943. spin_lock_irqsave(&dev->lock, flags);
  944. portsc1 = readl(&dev->op_regs->portsc1);
  945. if (!(portsc1 & PORTS_SUSP)) {
  946. spin_unlock_irqrestore(&dev->lock, flags);
  947. return 0;
  948. }
  949. /* LPM L1 to L0 or legacy remote wakeup */
  950. if (dev->lpm && dev->lpm_state == LPM_L1)
  951. dev_info(&dev->pdev->dev, "LPM L1 to L0 remote wakeup\n");
  952. else
  953. dev_info(&dev->pdev->dev, "device remote wakeup\n");
  954. /* exit PHY low power suspend */
  955. if (dev->pdev->device != 0x0829)
  956. langwell_phy_low_power(dev, 0);
  957. /* force port resume */
  958. portsc1 |= PORTS_FPR;
  959. writel(portsc1, &dev->op_regs->portsc1);
  960. spin_unlock_irqrestore(&dev->lock, flags);
  961. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  962. return 0;
  963. }
  964. /* notify controller that VBUS is powered or not */
  965. static int langwell_vbus_session(struct usb_gadget *_gadget, int is_active)
  966. {
  967. struct langwell_udc *dev;
  968. unsigned long flags;
  969. u32 usbcmd;
  970. if (!_gadget)
  971. return -ENODEV;
  972. dev = container_of(_gadget, struct langwell_udc, gadget);
  973. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  974. spin_lock_irqsave(&dev->lock, flags);
  975. dev_vdbg(&dev->pdev->dev, "VBUS status: %s\n",
  976. is_active ? "on" : "off");
  977. dev->vbus_active = (is_active != 0);
  978. if (dev->driver && dev->softconnected && dev->vbus_active) {
  979. usbcmd = readl(&dev->op_regs->usbcmd);
  980. usbcmd |= CMD_RUNSTOP;
  981. writel(usbcmd, &dev->op_regs->usbcmd);
  982. } else {
  983. usbcmd = readl(&dev->op_regs->usbcmd);
  984. usbcmd &= ~CMD_RUNSTOP;
  985. writel(usbcmd, &dev->op_regs->usbcmd);
  986. }
  987. spin_unlock_irqrestore(&dev->lock, flags);
  988. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  989. return 0;
  990. }
  991. /* constrain controller's VBUS power usage */
  992. static int langwell_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
  993. {
  994. struct langwell_udc *dev;
  995. if (!_gadget)
  996. return -ENODEV;
  997. dev = container_of(_gadget, struct langwell_udc, gadget);
  998. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  999. if (dev->transceiver) {
  1000. dev_vdbg(&dev->pdev->dev, "otg_set_power\n");
  1001. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1002. return otg_set_power(dev->transceiver, mA);
  1003. }
  1004. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1005. return -ENOTSUPP;
  1006. }
  1007. /* D+ pullup, software-controlled connect/disconnect to USB host */
  1008. static int langwell_pullup(struct usb_gadget *_gadget, int is_on)
  1009. {
  1010. struct langwell_udc *dev;
  1011. u32 usbcmd;
  1012. unsigned long flags;
  1013. if (!_gadget)
  1014. return -ENODEV;
  1015. dev = container_of(_gadget, struct langwell_udc, gadget);
  1016. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1017. spin_lock_irqsave(&dev->lock, flags);
  1018. dev->softconnected = (is_on != 0);
  1019. if (dev->driver && dev->softconnected && dev->vbus_active) {
  1020. usbcmd = readl(&dev->op_regs->usbcmd);
  1021. usbcmd |= CMD_RUNSTOP;
  1022. writel(usbcmd, &dev->op_regs->usbcmd);
  1023. } else {
  1024. usbcmd = readl(&dev->op_regs->usbcmd);
  1025. usbcmd &= ~CMD_RUNSTOP;
  1026. writel(usbcmd, &dev->op_regs->usbcmd);
  1027. }
  1028. spin_unlock_irqrestore(&dev->lock, flags);
  1029. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1030. return 0;
  1031. }
  1032. static int langwell_start(struct usb_gadget *g,
  1033. struct usb_gadget_driver *driver);
  1034. static int langwell_stop(struct usb_gadget *g,
  1035. struct usb_gadget_driver *driver);
  1036. /* device controller usb_gadget_ops structure */
  1037. static const struct usb_gadget_ops langwell_ops = {
  1038. /* returns the current frame number */
  1039. .get_frame = langwell_get_frame,
  1040. /* tries to wake up the host connected to this gadget */
  1041. .wakeup = langwell_wakeup,
  1042. /* set the device selfpowered feature, always selfpowered */
  1043. /* .set_selfpowered = langwell_set_selfpowered, */
  1044. /* notify controller that VBUS is powered or not */
  1045. .vbus_session = langwell_vbus_session,
  1046. /* constrain controller's VBUS power usage */
  1047. .vbus_draw = langwell_vbus_draw,
  1048. /* D+ pullup, software-controlled connect/disconnect to USB host */
  1049. .pullup = langwell_pullup,
  1050. .udc_start = langwell_start,
  1051. .udc_stop = langwell_stop,
  1052. };
  1053. /*-------------------------------------------------------------------------*/
  1054. /* device controller operations */
  1055. /* reset device controller */
  1056. static int langwell_udc_reset(struct langwell_udc *dev)
  1057. {
  1058. u32 usbcmd, usbmode, devlc, endpointlistaddr;
  1059. u8 devlc_byte0, devlc_byte2;
  1060. unsigned long timeout;
  1061. if (!dev)
  1062. return -EINVAL;
  1063. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1064. /* set controller to stop state */
  1065. usbcmd = readl(&dev->op_regs->usbcmd);
  1066. usbcmd &= ~CMD_RUNSTOP;
  1067. writel(usbcmd, &dev->op_regs->usbcmd);
  1068. /* reset device controller */
  1069. usbcmd = readl(&dev->op_regs->usbcmd);
  1070. usbcmd |= CMD_RST;
  1071. writel(usbcmd, &dev->op_regs->usbcmd);
  1072. /* wait for reset to complete */
  1073. timeout = jiffies + RESET_TIMEOUT;
  1074. while (readl(&dev->op_regs->usbcmd) & CMD_RST) {
  1075. if (time_after(jiffies, timeout)) {
  1076. dev_err(&dev->pdev->dev, "device reset timeout\n");
  1077. return -ETIMEDOUT;
  1078. }
  1079. cpu_relax();
  1080. }
  1081. /* set controller to device mode */
  1082. usbmode = readl(&dev->op_regs->usbmode);
  1083. usbmode |= MODE_DEVICE;
  1084. /* turn setup lockout off, require setup tripwire in usbcmd */
  1085. usbmode |= MODE_SLOM;
  1086. writel(usbmode, &dev->op_regs->usbmode);
  1087. usbmode = readl(&dev->op_regs->usbmode);
  1088. dev_vdbg(&dev->pdev->dev, "usbmode=0x%08x\n", usbmode);
  1089. /* Write-Clear setup status */
  1090. writel(0, &dev->op_regs->usbsts);
  1091. /* if support USB LPM, ACK all LPM token */
  1092. if (dev->lpm) {
  1093. devlc = readl(&dev->op_regs->devlc);
  1094. dev_vdbg(&dev->pdev->dev, "devlc = 0x%08x\n", devlc);
  1095. /* FIXME: workaround for Langwell A1/A2/A3 sighting */
  1096. devlc &= ~LPM_STL; /* don't STALL LPM token */
  1097. devlc &= ~LPM_NYT_ACK; /* ACK LPM token */
  1098. devlc_byte0 = devlc & 0xff;
  1099. devlc_byte2 = (devlc >> 16) & 0xff;
  1100. writeb(devlc_byte0, (u8 *)&dev->op_regs->devlc);
  1101. writeb(devlc_byte2, (u8 *)&dev->op_regs->devlc + 2);
  1102. devlc = readl(&dev->op_regs->devlc);
  1103. dev_vdbg(&dev->pdev->dev,
  1104. "ACK LPM token, devlc = 0x%08x\n", devlc);
  1105. }
  1106. /* fill endpointlistaddr register */
  1107. endpointlistaddr = dev->ep_dqh_dma;
  1108. endpointlistaddr &= ENDPOINTLISTADDR_MASK;
  1109. writel(endpointlistaddr, &dev->op_regs->endpointlistaddr);
  1110. dev_vdbg(&dev->pdev->dev,
  1111. "dQH base (vir: %p, phy: 0x%08x), endpointlistaddr=0x%08x\n",
  1112. dev->ep_dqh, endpointlistaddr,
  1113. readl(&dev->op_regs->endpointlistaddr));
  1114. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1115. return 0;
  1116. }
  1117. /* reinitialize device controller endpoints */
  1118. static int eps_reinit(struct langwell_udc *dev)
  1119. {
  1120. struct langwell_ep *ep;
  1121. char name[14];
  1122. int i;
  1123. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1124. /* initialize ep0 */
  1125. ep = &dev->ep[0];
  1126. ep->dev = dev;
  1127. strncpy(ep->name, "ep0", sizeof(ep->name));
  1128. ep->ep.name = ep->name;
  1129. ep->ep.ops = &langwell_ep_ops;
  1130. ep->stopped = 0;
  1131. ep->ep.maxpacket = EP0_MAX_PKT_SIZE;
  1132. ep->ep_num = 0;
  1133. ep->desc = &langwell_ep0_desc;
  1134. INIT_LIST_HEAD(&ep->queue);
  1135. ep->ep_type = USB_ENDPOINT_XFER_CONTROL;
  1136. /* initialize other endpoints */
  1137. for (i = 2; i < dev->ep_max; i++) {
  1138. ep = &dev->ep[i];
  1139. if (i % 2)
  1140. snprintf(name, sizeof(name), "ep%din", i / 2);
  1141. else
  1142. snprintf(name, sizeof(name), "ep%dout", i / 2);
  1143. ep->dev = dev;
  1144. strncpy(ep->name, name, sizeof(ep->name));
  1145. ep->ep.name = ep->name;
  1146. ep->ep.ops = &langwell_ep_ops;
  1147. ep->stopped = 0;
  1148. ep->ep.maxpacket = (unsigned short) ~0;
  1149. ep->ep_num = i / 2;
  1150. INIT_LIST_HEAD(&ep->queue);
  1151. list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
  1152. }
  1153. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1154. return 0;
  1155. }
  1156. /* enable interrupt and set controller to run state */
  1157. static void langwell_udc_start(struct langwell_udc *dev)
  1158. {
  1159. u32 usbintr, usbcmd;
  1160. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1161. /* enable interrupts */
  1162. usbintr = INTR_ULPIE /* ULPI */
  1163. | INTR_SLE /* suspend */
  1164. /* | INTR_SRE SOF received */
  1165. | INTR_URE /* USB reset */
  1166. | INTR_AAE /* async advance */
  1167. | INTR_SEE /* system error */
  1168. | INTR_FRE /* frame list rollover */
  1169. | INTR_PCE /* port change detect */
  1170. | INTR_UEE /* USB error interrupt */
  1171. | INTR_UE; /* USB interrupt */
  1172. writel(usbintr, &dev->op_regs->usbintr);
  1173. /* clear stopped bit */
  1174. dev->stopped = 0;
  1175. /* set controller to run */
  1176. usbcmd = readl(&dev->op_regs->usbcmd);
  1177. usbcmd |= CMD_RUNSTOP;
  1178. writel(usbcmd, &dev->op_regs->usbcmd);
  1179. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1180. }
  1181. /* disable interrupt and set controller to stop state */
  1182. static void langwell_udc_stop(struct langwell_udc *dev)
  1183. {
  1184. u32 usbcmd;
  1185. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1186. /* disable all interrupts */
  1187. writel(0, &dev->op_regs->usbintr);
  1188. /* set stopped bit */
  1189. dev->stopped = 1;
  1190. /* set controller to stop state */
  1191. usbcmd = readl(&dev->op_regs->usbcmd);
  1192. usbcmd &= ~CMD_RUNSTOP;
  1193. writel(usbcmd, &dev->op_regs->usbcmd);
  1194. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1195. }
  1196. /* stop all USB activities */
  1197. static void stop_activity(struct langwell_udc *dev)
  1198. {
  1199. struct langwell_ep *ep;
  1200. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1201. nuke(&dev->ep[0], -ESHUTDOWN);
  1202. list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) {
  1203. nuke(ep, -ESHUTDOWN);
  1204. }
  1205. /* report disconnect; the driver is already quiesced */
  1206. if (dev->driver) {
  1207. spin_unlock(&dev->lock);
  1208. dev->driver->disconnect(&dev->gadget);
  1209. spin_lock(&dev->lock);
  1210. }
  1211. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1212. }
  1213. /*-------------------------------------------------------------------------*/
  1214. /* device "function" sysfs attribute file */
  1215. static ssize_t show_function(struct device *_dev,
  1216. struct device_attribute *attr, char *buf)
  1217. {
  1218. struct langwell_udc *dev = dev_get_drvdata(_dev);
  1219. if (!dev->driver || !dev->driver->function
  1220. || strlen(dev->driver->function) > PAGE_SIZE)
  1221. return 0;
  1222. return scnprintf(buf, PAGE_SIZE, "%s\n", dev->driver->function);
  1223. }
  1224. static DEVICE_ATTR(function, S_IRUGO, show_function, NULL);
  1225. static inline enum usb_device_speed lpm_device_speed(u32 reg)
  1226. {
  1227. switch (LPM_PSPD(reg)) {
  1228. case LPM_SPEED_HIGH:
  1229. return USB_SPEED_HIGH;
  1230. case LPM_SPEED_FULL:
  1231. return USB_SPEED_FULL;
  1232. case LPM_SPEED_LOW:
  1233. return USB_SPEED_LOW;
  1234. default:
  1235. return USB_SPEED_UNKNOWN;
  1236. }
  1237. }
  1238. /* device "langwell_udc" sysfs attribute file */
  1239. static ssize_t show_langwell_udc(struct device *_dev,
  1240. struct device_attribute *attr, char *buf)
  1241. {
  1242. struct langwell_udc *dev = dev_get_drvdata(_dev);
  1243. struct langwell_request *req;
  1244. struct langwell_ep *ep = NULL;
  1245. char *next;
  1246. unsigned size;
  1247. unsigned t;
  1248. unsigned i;
  1249. unsigned long flags;
  1250. u32 tmp_reg;
  1251. next = buf;
  1252. size = PAGE_SIZE;
  1253. spin_lock_irqsave(&dev->lock, flags);
  1254. /* driver basic information */
  1255. t = scnprintf(next, size,
  1256. DRIVER_DESC "\n"
  1257. "%s version: %s\n"
  1258. "Gadget driver: %s\n\n",
  1259. driver_name, DRIVER_VERSION,
  1260. dev->driver ? dev->driver->driver.name : "(none)");
  1261. size -= t;
  1262. next += t;
  1263. /* device registers */
  1264. tmp_reg = readl(&dev->op_regs->usbcmd);
  1265. t = scnprintf(next, size,
  1266. "USBCMD reg:\n"
  1267. "SetupTW: %d\n"
  1268. "Run/Stop: %s\n\n",
  1269. (tmp_reg & CMD_SUTW) ? 1 : 0,
  1270. (tmp_reg & CMD_RUNSTOP) ? "Run" : "Stop");
  1271. size -= t;
  1272. next += t;
  1273. tmp_reg = readl(&dev->op_regs->usbsts);
  1274. t = scnprintf(next, size,
  1275. "USB Status Reg:\n"
  1276. "Device Suspend: %d\n"
  1277. "Reset Received: %d\n"
  1278. "System Error: %s\n"
  1279. "USB Error Interrupt: %s\n\n",
  1280. (tmp_reg & STS_SLI) ? 1 : 0,
  1281. (tmp_reg & STS_URI) ? 1 : 0,
  1282. (tmp_reg & STS_SEI) ? "Error" : "No error",
  1283. (tmp_reg & STS_UEI) ? "Error detected" : "No error");
  1284. size -= t;
  1285. next += t;
  1286. tmp_reg = readl(&dev->op_regs->usbintr);
  1287. t = scnprintf(next, size,
  1288. "USB Intrrupt Enable Reg:\n"
  1289. "Sleep Enable: %d\n"
  1290. "SOF Received Enable: %d\n"
  1291. "Reset Enable: %d\n"
  1292. "System Error Enable: %d\n"
  1293. "Port Change Dectected Enable: %d\n"
  1294. "USB Error Intr Enable: %d\n"
  1295. "USB Intr Enable: %d\n\n",
  1296. (tmp_reg & INTR_SLE) ? 1 : 0,
  1297. (tmp_reg & INTR_SRE) ? 1 : 0,
  1298. (tmp_reg & INTR_URE) ? 1 : 0,
  1299. (tmp_reg & INTR_SEE) ? 1 : 0,
  1300. (tmp_reg & INTR_PCE) ? 1 : 0,
  1301. (tmp_reg & INTR_UEE) ? 1 : 0,
  1302. (tmp_reg & INTR_UE) ? 1 : 0);
  1303. size -= t;
  1304. next += t;
  1305. tmp_reg = readl(&dev->op_regs->frindex);
  1306. t = scnprintf(next, size,
  1307. "USB Frame Index Reg:\n"
  1308. "Frame Number is 0x%08x\n\n",
  1309. (tmp_reg & FRINDEX_MASK));
  1310. size -= t;
  1311. next += t;
  1312. tmp_reg = readl(&dev->op_regs->deviceaddr);
  1313. t = scnprintf(next, size,
  1314. "USB Device Address Reg:\n"
  1315. "Device Addr is 0x%x\n\n",
  1316. USBADR(tmp_reg));
  1317. size -= t;
  1318. next += t;
  1319. tmp_reg = readl(&dev->op_regs->endpointlistaddr);
  1320. t = scnprintf(next, size,
  1321. "USB Endpoint List Address Reg:\n"
  1322. "Endpoint List Pointer is 0x%x\n\n",
  1323. EPBASE(tmp_reg));
  1324. size -= t;
  1325. next += t;
  1326. tmp_reg = readl(&dev->op_regs->portsc1);
  1327. t = scnprintf(next, size,
  1328. "USB Port Status & Control Reg:\n"
  1329. "Port Reset: %s\n"
  1330. "Port Suspend Mode: %s\n"
  1331. "Over-current Change: %s\n"
  1332. "Port Enable/Disable Change: %s\n"
  1333. "Port Enabled/Disabled: %s\n"
  1334. "Current Connect Status: %s\n"
  1335. "LPM Suspend Status: %s\n\n",
  1336. (tmp_reg & PORTS_PR) ? "Reset" : "Not Reset",
  1337. (tmp_reg & PORTS_SUSP) ? "Suspend " : "Not Suspend",
  1338. (tmp_reg & PORTS_OCC) ? "Detected" : "No",
  1339. (tmp_reg & PORTS_PEC) ? "Changed" : "Not Changed",
  1340. (tmp_reg & PORTS_PE) ? "Enable" : "Not Correct",
  1341. (tmp_reg & PORTS_CCS) ? "Attached" : "Not Attached",
  1342. (tmp_reg & PORTS_SLP) ? "LPM L1" : "LPM L0");
  1343. size -= t;
  1344. next += t;
  1345. tmp_reg = readl(&dev->op_regs->devlc);
  1346. t = scnprintf(next, size,
  1347. "Device LPM Control Reg:\n"
  1348. "Parallel Transceiver : %d\n"
  1349. "Serial Transceiver : %d\n"
  1350. "Port Speed: %s\n"
  1351. "Port Force Full Speed Connenct: %s\n"
  1352. "PHY Low Power Suspend Clock: %s\n"
  1353. "BmAttributes: %d\n\n",
  1354. LPM_PTS(tmp_reg),
  1355. (tmp_reg & LPM_STS) ? 1 : 0,
  1356. usb_speed_string(lpm_device_speed(tmp_reg)),
  1357. (tmp_reg & LPM_PFSC) ? "Force Full Speed" : "Not Force",
  1358. (tmp_reg & LPM_PHCD) ? "Disabled" : "Enabled",
  1359. LPM_BA(tmp_reg));
  1360. size -= t;
  1361. next += t;
  1362. tmp_reg = readl(&dev->op_regs->usbmode);
  1363. t = scnprintf(next, size,
  1364. "USB Mode Reg:\n"
  1365. "Controller Mode is : %s\n\n", ({
  1366. char *s;
  1367. switch (MODE_CM(tmp_reg)) {
  1368. case MODE_IDLE:
  1369. s = "Idle"; break;
  1370. case MODE_DEVICE:
  1371. s = "Device Controller"; break;
  1372. case MODE_HOST:
  1373. s = "Host Controller"; break;
  1374. default:
  1375. s = "None"; break;
  1376. }
  1377. s;
  1378. }));
  1379. size -= t;
  1380. next += t;
  1381. tmp_reg = readl(&dev->op_regs->endptsetupstat);
  1382. t = scnprintf(next, size,
  1383. "Endpoint Setup Status Reg:\n"
  1384. "SETUP on ep 0x%04x\n\n",
  1385. tmp_reg & SETUPSTAT_MASK);
  1386. size -= t;
  1387. next += t;
  1388. for (i = 0; i < dev->ep_max / 2; i++) {
  1389. tmp_reg = readl(&dev->op_regs->endptctrl[i]);
  1390. t = scnprintf(next, size, "EP Ctrl Reg [%d]: 0x%08x\n",
  1391. i, tmp_reg);
  1392. size -= t;
  1393. next += t;
  1394. }
  1395. tmp_reg = readl(&dev->op_regs->endptprime);
  1396. t = scnprintf(next, size, "EP Prime Reg: 0x%08x\n\n", tmp_reg);
  1397. size -= t;
  1398. next += t;
  1399. /* langwell_udc, langwell_ep, langwell_request structure information */
  1400. ep = &dev->ep[0];
  1401. t = scnprintf(next, size, "%s MaxPacketSize: 0x%x, ep_num: %d\n",
  1402. ep->ep.name, ep->ep.maxpacket, ep->ep_num);
  1403. size -= t;
  1404. next += t;
  1405. if (list_empty(&ep->queue)) {
  1406. t = scnprintf(next, size, "its req queue is empty\n\n");
  1407. size -= t;
  1408. next += t;
  1409. } else {
  1410. list_for_each_entry(req, &ep->queue, queue) {
  1411. t = scnprintf(next, size,
  1412. "req %p actual 0x%x length 0x%x buf %p\n",
  1413. &req->req, req->req.actual,
  1414. req->req.length, req->req.buf);
  1415. size -= t;
  1416. next += t;
  1417. }
  1418. }
  1419. /* other gadget->eplist ep */
  1420. list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) {
  1421. if (ep->desc) {
  1422. t = scnprintf(next, size,
  1423. "\n%s MaxPacketSize: 0x%x, "
  1424. "ep_num: %d\n",
  1425. ep->ep.name, ep->ep.maxpacket,
  1426. ep->ep_num);
  1427. size -= t;
  1428. next += t;
  1429. if (list_empty(&ep->queue)) {
  1430. t = scnprintf(next, size,
  1431. "its req queue is empty\n\n");
  1432. size -= t;
  1433. next += t;
  1434. } else {
  1435. list_for_each_entry(req, &ep->queue, queue) {
  1436. t = scnprintf(next, size,
  1437. "req %p actual 0x%x length "
  1438. "0x%x buf %p\n",
  1439. &req->req, req->req.actual,
  1440. req->req.length, req->req.buf);
  1441. size -= t;
  1442. next += t;
  1443. }
  1444. }
  1445. }
  1446. }
  1447. spin_unlock_irqrestore(&dev->lock, flags);
  1448. return PAGE_SIZE - size;
  1449. }
  1450. static DEVICE_ATTR(langwell_udc, S_IRUGO, show_langwell_udc, NULL);
  1451. /* device "remote_wakeup" sysfs attribute file */
  1452. static ssize_t store_remote_wakeup(struct device *_dev,
  1453. struct device_attribute *attr, const char *buf, size_t count)
  1454. {
  1455. struct langwell_udc *dev = dev_get_drvdata(_dev);
  1456. unsigned long flags;
  1457. ssize_t rc = count;
  1458. if (count > 2)
  1459. return -EINVAL;
  1460. if (count > 0 && buf[count-1] == '\n')
  1461. ((char *) buf)[count-1] = 0;
  1462. if (buf[0] != '1')
  1463. return -EINVAL;
  1464. /* force remote wakeup enabled in case gadget driver doesn't support */
  1465. spin_lock_irqsave(&dev->lock, flags);
  1466. dev->remote_wakeup = 1;
  1467. dev->dev_status |= (1 << USB_DEVICE_REMOTE_WAKEUP);
  1468. spin_unlock_irqrestore(&dev->lock, flags);
  1469. langwell_wakeup(&dev->gadget);
  1470. return rc;
  1471. }
  1472. static DEVICE_ATTR(remote_wakeup, S_IWUSR, NULL, store_remote_wakeup);
  1473. /*-------------------------------------------------------------------------*/
  1474. /*
  1475. * when a driver is successfully registered, it will receive
  1476. * control requests including set_configuration(), which enables
  1477. * non-control requests. then usb traffic follows until a
  1478. * disconnect is reported. then a host may connect again, or
  1479. * the driver might get unbound.
  1480. */
  1481. static int langwell_start(struct usb_gadget *g,
  1482. struct usb_gadget_driver *driver)
  1483. {
  1484. struct langwell_udc *dev = gadget_to_langwell(g);
  1485. unsigned long flags;
  1486. int retval;
  1487. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1488. spin_lock_irqsave(&dev->lock, flags);
  1489. /* hook up the driver ... */
  1490. driver->driver.bus = NULL;
  1491. dev->driver = driver;
  1492. dev->gadget.dev.driver = &driver->driver;
  1493. spin_unlock_irqrestore(&dev->lock, flags);
  1494. retval = device_create_file(&dev->pdev->dev, &dev_attr_function);
  1495. if (retval)
  1496. goto err;
  1497. dev->usb_state = USB_STATE_ATTACHED;
  1498. dev->ep0_state = WAIT_FOR_SETUP;
  1499. dev->ep0_dir = USB_DIR_OUT;
  1500. /* enable interrupt and set controller to run state */
  1501. if (dev->got_irq)
  1502. langwell_udc_start(dev);
  1503. dev_vdbg(&dev->pdev->dev,
  1504. "After langwell_udc_start(), print all registers:\n");
  1505. print_all_registers(dev);
  1506. dev_info(&dev->pdev->dev, "register driver: %s\n",
  1507. driver->driver.name);
  1508. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1509. return 0;
  1510. err:
  1511. dev->gadget.dev.driver = NULL;
  1512. dev->driver = NULL;
  1513. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1514. return retval;
  1515. }
  1516. /* unregister gadget driver */
  1517. static int langwell_stop(struct usb_gadget *g,
  1518. struct usb_gadget_driver *driver)
  1519. {
  1520. struct langwell_udc *dev = gadget_to_langwell(g);
  1521. unsigned long flags;
  1522. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1523. /* exit PHY low power suspend */
  1524. if (dev->pdev->device != 0x0829)
  1525. langwell_phy_low_power(dev, 0);
  1526. /* unbind OTG transceiver */
  1527. if (dev->transceiver)
  1528. (void)otg_set_peripheral(dev->transceiver, 0);
  1529. /* disable interrupt and set controller to stop state */
  1530. langwell_udc_stop(dev);
  1531. dev->usb_state = USB_STATE_ATTACHED;
  1532. dev->ep0_state = WAIT_FOR_SETUP;
  1533. dev->ep0_dir = USB_DIR_OUT;
  1534. spin_lock_irqsave(&dev->lock, flags);
  1535. /* stop all usb activities */
  1536. dev->gadget.speed = USB_SPEED_UNKNOWN;
  1537. dev->gadget.dev.driver = NULL;
  1538. dev->driver = NULL;
  1539. stop_activity(dev);
  1540. spin_unlock_irqrestore(&dev->lock, flags);
  1541. device_remove_file(&dev->pdev->dev, &dev_attr_function);
  1542. dev_info(&dev->pdev->dev, "unregistered driver '%s'\n",
  1543. driver->driver.name);
  1544. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1545. return 0;
  1546. }
  1547. /*-------------------------------------------------------------------------*/
  1548. /*
  1549. * setup tripwire is used as a semaphore to ensure that the setup data
  1550. * payload is extracted from a dQH without being corrupted
  1551. */
  1552. static void setup_tripwire(struct langwell_udc *dev)
  1553. {
  1554. u32 usbcmd,
  1555. endptsetupstat;
  1556. unsigned long timeout;
  1557. struct langwell_dqh *dqh;
  1558. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1559. /* ep0 OUT dQH */
  1560. dqh = &dev->ep_dqh[EP_DIR_OUT];
  1561. /* Write-Clear endptsetupstat */
  1562. endptsetupstat = readl(&dev->op_regs->endptsetupstat);
  1563. writel(endptsetupstat, &dev->op_regs->endptsetupstat);
  1564. /* wait until endptsetupstat is cleared */
  1565. timeout = jiffies + SETUPSTAT_TIMEOUT;
  1566. while (readl(&dev->op_regs->endptsetupstat)) {
  1567. if (time_after(jiffies, timeout)) {
  1568. dev_err(&dev->pdev->dev, "setup_tripwire timeout\n");
  1569. break;
  1570. }
  1571. cpu_relax();
  1572. }
  1573. /* while a hazard exists when setup packet arrives */
  1574. do {
  1575. /* set setup tripwire bit */
  1576. usbcmd = readl(&dev->op_regs->usbcmd);
  1577. writel(usbcmd | CMD_SUTW, &dev->op_regs->usbcmd);
  1578. /* copy the setup packet to local buffer */
  1579. memcpy(&dev->local_setup_buff, &dqh->dqh_setup, 8);
  1580. } while (!(readl(&dev->op_regs->usbcmd) & CMD_SUTW));
  1581. /* Write-Clear setup tripwire bit */
  1582. usbcmd = readl(&dev->op_regs->usbcmd);
  1583. writel(usbcmd & ~CMD_SUTW, &dev->op_regs->usbcmd);
  1584. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1585. }
  1586. /* protocol ep0 stall, will automatically be cleared on new transaction */
  1587. static void ep0_stall(struct langwell_udc *dev)
  1588. {
  1589. u32 endptctrl;
  1590. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1591. /* set TX and RX to stall */
  1592. endptctrl = readl(&dev->op_regs->endptctrl[0]);
  1593. endptctrl |= EPCTRL_TXS | EPCTRL_RXS;
  1594. writel(endptctrl, &dev->op_regs->endptctrl[0]);
  1595. /* update ep0 state */
  1596. dev->ep0_state = WAIT_FOR_SETUP;
  1597. dev->ep0_dir = USB_DIR_OUT;
  1598. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1599. }
  1600. /* PRIME a status phase for ep0 */
  1601. static int prime_status_phase(struct langwell_udc *dev, int dir)
  1602. {
  1603. struct langwell_request *req;
  1604. struct langwell_ep *ep;
  1605. int status = 0;
  1606. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1607. if (dir == EP_DIR_IN)
  1608. dev->ep0_dir = USB_DIR_IN;
  1609. else
  1610. dev->ep0_dir = USB_DIR_OUT;
  1611. ep = &dev->ep[0];
  1612. dev->ep0_state = WAIT_FOR_OUT_STATUS;
  1613. req = dev->status_req;
  1614. req->ep = ep;
  1615. req->req.length = 0;
  1616. req->req.status = -EINPROGRESS;
  1617. req->req.actual = 0;
  1618. req->req.complete = NULL;
  1619. req->dtd_count = 0;
  1620. if (!req_to_dtd(req))
  1621. status = queue_dtd(ep, req);
  1622. else
  1623. return -ENOMEM;
  1624. if (status)
  1625. dev_err(&dev->pdev->dev, "can't queue ep0 status request\n");
  1626. list_add_tail(&req->queue, &ep->queue);
  1627. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1628. return status;
  1629. }
  1630. /* SET_ADDRESS request routine */
  1631. static void set_address(struct langwell_udc *dev, u16 value,
  1632. u16 index, u16 length)
  1633. {
  1634. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1635. /* save the new address to device struct */
  1636. dev->dev_addr = (u8) value;
  1637. dev_vdbg(&dev->pdev->dev, "dev->dev_addr = %d\n", dev->dev_addr);
  1638. /* update usb state */
  1639. dev->usb_state = USB_STATE_ADDRESS;
  1640. /* STATUS phase */
  1641. if (prime_status_phase(dev, EP_DIR_IN))
  1642. ep0_stall(dev);
  1643. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1644. }
  1645. /* return endpoint by windex */
  1646. static struct langwell_ep *get_ep_by_windex(struct langwell_udc *dev,
  1647. u16 wIndex)
  1648. {
  1649. struct langwell_ep *ep;
  1650. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1651. if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0)
  1652. return &dev->ep[0];
  1653. list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) {
  1654. u8 bEndpointAddress;
  1655. if (!ep->desc)
  1656. continue;
  1657. bEndpointAddress = ep->desc->bEndpointAddress;
  1658. if ((wIndex ^ bEndpointAddress) & USB_DIR_IN)
  1659. continue;
  1660. if ((wIndex & USB_ENDPOINT_NUMBER_MASK)
  1661. == (bEndpointAddress & USB_ENDPOINT_NUMBER_MASK))
  1662. return ep;
  1663. }
  1664. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1665. return NULL;
  1666. }
  1667. /* return whether endpoint is stalled, 0: not stalled; 1: stalled */
  1668. static int ep_is_stall(struct langwell_ep *ep)
  1669. {
  1670. struct langwell_udc *dev = ep->dev;
  1671. u32 endptctrl;
  1672. int retval;
  1673. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1674. endptctrl = readl(&dev->op_regs->endptctrl[ep->ep_num]);
  1675. if (is_in(ep))
  1676. retval = endptctrl & EPCTRL_TXS ? 1 : 0;
  1677. else
  1678. retval = endptctrl & EPCTRL_RXS ? 1 : 0;
  1679. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1680. return retval;
  1681. }
  1682. /* GET_STATUS request routine */
  1683. static void get_status(struct langwell_udc *dev, u8 request_type, u16 value,
  1684. u16 index, u16 length)
  1685. {
  1686. struct langwell_request *req;
  1687. struct langwell_ep *ep;
  1688. u16 status_data = 0; /* 16 bits cpu view status data */
  1689. int status = 0;
  1690. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1691. ep = &dev->ep[0];
  1692. if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
  1693. /* get device status */
  1694. status_data = dev->dev_status;
  1695. } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
  1696. /* get interface status */
  1697. status_data = 0;
  1698. } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
  1699. /* get endpoint status */
  1700. struct langwell_ep *epn;
  1701. epn = get_ep_by_windex(dev, index);
  1702. /* stall if endpoint doesn't exist */
  1703. if (!epn)
  1704. goto stall;
  1705. status_data = ep_is_stall(epn) << USB_ENDPOINT_HALT;
  1706. }
  1707. dev_dbg(&dev->pdev->dev, "get status data: 0x%04x\n", status_data);
  1708. dev->ep0_dir = USB_DIR_IN;
  1709. /* borrow the per device status_req */
  1710. req = dev->status_req;
  1711. /* fill in the reqest structure */
  1712. *((u16 *) req->req.buf) = cpu_to_le16(status_data);
  1713. req->ep = ep;
  1714. req->req.length = 2;
  1715. req->req.status = -EINPROGRESS;
  1716. req->req.actual = 0;
  1717. req->req.complete = NULL;
  1718. req->dtd_count = 0;
  1719. /* prime the data phase */
  1720. if (!req_to_dtd(req))
  1721. status = queue_dtd(ep, req);
  1722. else /* no mem */
  1723. goto stall;
  1724. if (status) {
  1725. dev_err(&dev->pdev->dev,
  1726. "response error on GET_STATUS request\n");
  1727. goto stall;
  1728. }
  1729. list_add_tail(&req->queue, &ep->queue);
  1730. dev->ep0_state = DATA_STATE_XMIT;
  1731. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1732. return;
  1733. stall:
  1734. ep0_stall(dev);
  1735. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1736. }
  1737. /* setup packet interrupt handler */
  1738. static void handle_setup_packet(struct langwell_udc *dev,
  1739. struct usb_ctrlrequest *setup)
  1740. {
  1741. u16 wValue = le16_to_cpu(setup->wValue);
  1742. u16 wIndex = le16_to_cpu(setup->wIndex);
  1743. u16 wLength = le16_to_cpu(setup->wLength);
  1744. u32 portsc1;
  1745. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1746. /* ep0 fifo flush */
  1747. nuke(&dev->ep[0], -ESHUTDOWN);
  1748. dev_dbg(&dev->pdev->dev, "SETUP %02x.%02x v%04x i%04x l%04x\n",
  1749. setup->bRequestType, setup->bRequest,
  1750. wValue, wIndex, wLength);
  1751. /* RNDIS gadget delegate */
  1752. if ((setup->bRequestType == 0x21) && (setup->bRequest == 0x00)) {
  1753. /* USB_CDC_SEND_ENCAPSULATED_COMMAND */
  1754. goto delegate;
  1755. }
  1756. /* USB_CDC_GET_ENCAPSULATED_RESPONSE */
  1757. if ((setup->bRequestType == 0xa1) && (setup->bRequest == 0x01)) {
  1758. /* USB_CDC_GET_ENCAPSULATED_RESPONSE */
  1759. goto delegate;
  1760. }
  1761. /* We process some stardard setup requests here */
  1762. switch (setup->bRequest) {
  1763. case USB_REQ_GET_STATUS:
  1764. dev_dbg(&dev->pdev->dev, "SETUP: USB_REQ_GET_STATUS\n");
  1765. /* get status, DATA and STATUS phase */
  1766. if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
  1767. != (USB_DIR_IN | USB_TYPE_STANDARD))
  1768. break;
  1769. get_status(dev, setup->bRequestType, wValue, wIndex, wLength);
  1770. goto end;
  1771. case USB_REQ_SET_ADDRESS:
  1772. dev_dbg(&dev->pdev->dev, "SETUP: USB_REQ_SET_ADDRESS\n");
  1773. /* STATUS phase */
  1774. if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
  1775. | USB_RECIP_DEVICE))
  1776. break;
  1777. set_address(dev, wValue, wIndex, wLength);
  1778. goto end;
  1779. case USB_REQ_CLEAR_FEATURE:
  1780. case USB_REQ_SET_FEATURE:
  1781. /* STATUS phase */
  1782. {
  1783. int rc = -EOPNOTSUPP;
  1784. if (setup->bRequest == USB_REQ_SET_FEATURE)
  1785. dev_dbg(&dev->pdev->dev,
  1786. "SETUP: USB_REQ_SET_FEATURE\n");
  1787. else if (setup->bRequest == USB_REQ_CLEAR_FEATURE)
  1788. dev_dbg(&dev->pdev->dev,
  1789. "SETUP: USB_REQ_CLEAR_FEATURE\n");
  1790. if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
  1791. == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
  1792. struct langwell_ep *epn;
  1793. epn = get_ep_by_windex(dev, wIndex);
  1794. /* stall if endpoint doesn't exist */
  1795. if (!epn) {
  1796. ep0_stall(dev);
  1797. goto end;
  1798. }
  1799. if (wValue != 0 || wLength != 0
  1800. || epn->ep_num > dev->ep_max)
  1801. break;
  1802. spin_unlock(&dev->lock);
  1803. rc = langwell_ep_set_halt(&epn->ep,
  1804. (setup->bRequest == USB_REQ_SET_FEATURE)
  1805. ? 1 : 0);
  1806. spin_lock(&dev->lock);
  1807. } else if ((setup->bRequestType & (USB_RECIP_MASK
  1808. | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
  1809. | USB_TYPE_STANDARD)) {
  1810. rc = 0;
  1811. switch (wValue) {
  1812. case USB_DEVICE_REMOTE_WAKEUP:
  1813. if (setup->bRequest == USB_REQ_SET_FEATURE) {
  1814. dev->remote_wakeup = 1;
  1815. dev->dev_status |= (1 << wValue);
  1816. } else {
  1817. dev->remote_wakeup = 0;
  1818. dev->dev_status &= ~(1 << wValue);
  1819. }
  1820. break;
  1821. case USB_DEVICE_TEST_MODE:
  1822. dev_dbg(&dev->pdev->dev, "SETUP: TEST MODE\n");
  1823. if ((wIndex & 0xff) ||
  1824. (dev->gadget.speed != USB_SPEED_HIGH))
  1825. ep0_stall(dev);
  1826. switch (wIndex >> 8) {
  1827. case TEST_J:
  1828. case TEST_K:
  1829. case TEST_SE0_NAK:
  1830. case TEST_PACKET:
  1831. case TEST_FORCE_EN:
  1832. if (prime_status_phase(dev, EP_DIR_IN))
  1833. ep0_stall(dev);
  1834. portsc1 = readl(&dev->op_regs->portsc1);
  1835. portsc1 |= (wIndex & 0xf00) << 8;
  1836. writel(portsc1, &dev->op_regs->portsc1);
  1837. goto end;
  1838. default:
  1839. rc = -EOPNOTSUPP;
  1840. }
  1841. break;
  1842. default:
  1843. rc = -EOPNOTSUPP;
  1844. break;
  1845. }
  1846. if (!gadget_is_otg(&dev->gadget))
  1847. break;
  1848. else if (setup->bRequest == USB_DEVICE_B_HNP_ENABLE)
  1849. dev->gadget.b_hnp_enable = 1;
  1850. else if (setup->bRequest == USB_DEVICE_A_HNP_SUPPORT)
  1851. dev->gadget.a_hnp_support = 1;
  1852. else if (setup->bRequest ==
  1853. USB_DEVICE_A_ALT_HNP_SUPPORT)
  1854. dev->gadget.a_alt_hnp_support = 1;
  1855. else
  1856. break;
  1857. } else
  1858. break;
  1859. if (rc == 0) {
  1860. if (prime_status_phase(dev, EP_DIR_IN))
  1861. ep0_stall(dev);
  1862. }
  1863. goto end;
  1864. }
  1865. case USB_REQ_GET_DESCRIPTOR:
  1866. dev_dbg(&dev->pdev->dev,
  1867. "SETUP: USB_REQ_GET_DESCRIPTOR\n");
  1868. goto delegate;
  1869. case USB_REQ_SET_DESCRIPTOR:
  1870. dev_dbg(&dev->pdev->dev,
  1871. "SETUP: USB_REQ_SET_DESCRIPTOR unsupported\n");
  1872. goto delegate;
  1873. case USB_REQ_GET_CONFIGURATION:
  1874. dev_dbg(&dev->pdev->dev,
  1875. "SETUP: USB_REQ_GET_CONFIGURATION\n");
  1876. goto delegate;
  1877. case USB_REQ_SET_CONFIGURATION:
  1878. dev_dbg(&dev->pdev->dev,
  1879. "SETUP: USB_REQ_SET_CONFIGURATION\n");
  1880. goto delegate;
  1881. case USB_REQ_GET_INTERFACE:
  1882. dev_dbg(&dev->pdev->dev,
  1883. "SETUP: USB_REQ_GET_INTERFACE\n");
  1884. goto delegate;
  1885. case USB_REQ_SET_INTERFACE:
  1886. dev_dbg(&dev->pdev->dev,
  1887. "SETUP: USB_REQ_SET_INTERFACE\n");
  1888. goto delegate;
  1889. case USB_REQ_SYNCH_FRAME:
  1890. dev_dbg(&dev->pdev->dev,
  1891. "SETUP: USB_REQ_SYNCH_FRAME unsupported\n");
  1892. goto delegate;
  1893. default:
  1894. /* delegate USB standard requests to the gadget driver */
  1895. goto delegate;
  1896. delegate:
  1897. /* USB requests handled by gadget */
  1898. if (wLength) {
  1899. /* DATA phase from gadget, STATUS phase from udc */
  1900. dev->ep0_dir = (setup->bRequestType & USB_DIR_IN)
  1901. ? USB_DIR_IN : USB_DIR_OUT;
  1902. dev_vdbg(&dev->pdev->dev,
  1903. "dev->ep0_dir = 0x%x, wLength = %d\n",
  1904. dev->ep0_dir, wLength);
  1905. spin_unlock(&dev->lock);
  1906. if (dev->driver->setup(&dev->gadget,
  1907. &dev->local_setup_buff) < 0)
  1908. ep0_stall(dev);
  1909. spin_lock(&dev->lock);
  1910. dev->ep0_state = (setup->bRequestType & USB_DIR_IN)
  1911. ? DATA_STATE_XMIT : DATA_STATE_RECV;
  1912. } else {
  1913. /* no DATA phase, IN STATUS phase from gadget */
  1914. dev->ep0_dir = USB_DIR_IN;
  1915. dev_vdbg(&dev->pdev->dev,
  1916. "dev->ep0_dir = 0x%x, wLength = %d\n",
  1917. dev->ep0_dir, wLength);
  1918. spin_unlock(&dev->lock);
  1919. if (dev->driver->setup(&dev->gadget,
  1920. &dev->local_setup_buff) < 0)
  1921. ep0_stall(dev);
  1922. spin_lock(&dev->lock);
  1923. dev->ep0_state = WAIT_FOR_OUT_STATUS;
  1924. }
  1925. break;
  1926. }
  1927. end:
  1928. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1929. }
  1930. /* transfer completion, process endpoint request and free the completed dTDs
  1931. * for this request
  1932. */
  1933. static int process_ep_req(struct langwell_udc *dev, int index,
  1934. struct langwell_request *curr_req)
  1935. {
  1936. struct langwell_dtd *curr_dtd;
  1937. struct langwell_dqh *curr_dqh;
  1938. int td_complete, actual, remaining_length;
  1939. int i, dir;
  1940. u8 dtd_status = 0;
  1941. int retval = 0;
  1942. curr_dqh = &dev->ep_dqh[index];
  1943. dir = index % 2;
  1944. curr_dtd = curr_req->head;
  1945. td_complete = 0;
  1946. actual = curr_req->req.length;
  1947. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1948. for (i = 0; i < curr_req->dtd_count; i++) {
  1949. /* command execution states by dTD */
  1950. dtd_status = curr_dtd->dtd_status;
  1951. barrier();
  1952. remaining_length = le16_to_cpu(curr_dtd->dtd_total);
  1953. actual -= remaining_length;
  1954. if (!dtd_status) {
  1955. /* transfers completed successfully */
  1956. if (!remaining_length) {
  1957. td_complete++;
  1958. dev_vdbg(&dev->pdev->dev,
  1959. "dTD transmitted successfully\n");
  1960. } else {
  1961. if (dir) {
  1962. dev_vdbg(&dev->pdev->dev,
  1963. "TX dTD remains data\n");
  1964. retval = -EPROTO;
  1965. break;
  1966. } else {
  1967. td_complete++;
  1968. break;
  1969. }
  1970. }
  1971. } else {
  1972. /* transfers completed with errors */
  1973. if (dtd_status & DTD_STS_ACTIVE) {
  1974. dev_dbg(&dev->pdev->dev,
  1975. "dTD status ACTIVE dQH[%d]\n", index);
  1976. retval = 1;
  1977. return retval;
  1978. } else if (dtd_status & DTD_STS_HALTED) {
  1979. dev_err(&dev->pdev->dev,
  1980. "dTD error %08x dQH[%d]\n",
  1981. dtd_status, index);
  1982. /* clear the errors and halt condition */
  1983. curr_dqh->dtd_status = 0;
  1984. retval = -EPIPE;
  1985. break;
  1986. } else if (dtd_status & DTD_STS_DBE) {
  1987. dev_dbg(&dev->pdev->dev,
  1988. "data buffer (overflow) error\n");
  1989. retval = -EPROTO;
  1990. break;
  1991. } else if (dtd_status & DTD_STS_TRE) {
  1992. dev_dbg(&dev->pdev->dev,
  1993. "transaction(ISO) error\n");
  1994. retval = -EILSEQ;
  1995. break;
  1996. } else
  1997. dev_err(&dev->pdev->dev,
  1998. "unknown error (0x%x)!\n",
  1999. dtd_status);
  2000. }
  2001. if (i != curr_req->dtd_count - 1)
  2002. curr_dtd = (struct langwell_dtd *)
  2003. curr_dtd->next_dtd_virt;
  2004. }
  2005. if (retval)
  2006. return retval;
  2007. curr_req->req.actual = actual;
  2008. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2009. return 0;
  2010. }
  2011. /* complete DATA or STATUS phase of ep0 prime status phase if needed */
  2012. static void ep0_req_complete(struct langwell_udc *dev,
  2013. struct langwell_ep *ep0, struct langwell_request *req)
  2014. {
  2015. u32 new_addr;
  2016. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2017. if (dev->usb_state == USB_STATE_ADDRESS) {
  2018. /* set the new address */
  2019. new_addr = (u32)dev->dev_addr;
  2020. writel(new_addr << USBADR_SHIFT, &dev->op_regs->deviceaddr);
  2021. new_addr = USBADR(readl(&dev->op_regs->deviceaddr));
  2022. dev_vdbg(&dev->pdev->dev, "new_addr = %d\n", new_addr);
  2023. }
  2024. done(ep0, req, 0);
  2025. switch (dev->ep0_state) {
  2026. case DATA_STATE_XMIT:
  2027. /* receive status phase */
  2028. if (prime_status_phase(dev, EP_DIR_OUT))
  2029. ep0_stall(dev);
  2030. break;
  2031. case DATA_STATE_RECV:
  2032. /* send status phase */
  2033. if (prime_status_phase(dev, EP_DIR_IN))
  2034. ep0_stall(dev);
  2035. break;
  2036. case WAIT_FOR_OUT_STATUS:
  2037. dev->ep0_state = WAIT_FOR_SETUP;
  2038. break;
  2039. case WAIT_FOR_SETUP:
  2040. dev_err(&dev->pdev->dev, "unexpect ep0 packets\n");
  2041. break;
  2042. default:
  2043. ep0_stall(dev);
  2044. break;
  2045. }
  2046. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2047. }
  2048. /* USB transfer completion interrupt */
  2049. static void handle_trans_complete(struct langwell_udc *dev)
  2050. {
  2051. u32 complete_bits;
  2052. int i, ep_num, dir, bit_mask, status;
  2053. struct langwell_ep *epn;
  2054. struct langwell_request *curr_req, *temp_req;
  2055. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2056. complete_bits = readl(&dev->op_regs->endptcomplete);
  2057. dev_vdbg(&dev->pdev->dev, "endptcomplete register: 0x%08x\n",
  2058. complete_bits);
  2059. /* Write-Clear the bits in endptcomplete register */
  2060. writel(complete_bits, &dev->op_regs->endptcomplete);
  2061. if (!complete_bits) {
  2062. dev_dbg(&dev->pdev->dev, "complete_bits = 0\n");
  2063. goto done;
  2064. }
  2065. for (i = 0; i < dev->ep_max; i++) {
  2066. ep_num = i / 2;
  2067. dir = i % 2;
  2068. bit_mask = 1 << (ep_num + 16 * dir);
  2069. if (!(complete_bits & bit_mask))
  2070. continue;
  2071. /* ep0 */
  2072. if (i == 1)
  2073. epn = &dev->ep[0];
  2074. else
  2075. epn = &dev->ep[i];
  2076. if (epn->name == NULL) {
  2077. dev_warn(&dev->pdev->dev, "invalid endpoint\n");
  2078. continue;
  2079. }
  2080. if (i < 2)
  2081. /* ep0 in and out */
  2082. dev_dbg(&dev->pdev->dev, "%s-%s transfer completed\n",
  2083. epn->name,
  2084. is_in(epn) ? "in" : "out");
  2085. else
  2086. dev_dbg(&dev->pdev->dev, "%s transfer completed\n",
  2087. epn->name);
  2088. /* process the req queue until an uncomplete request */
  2089. list_for_each_entry_safe(curr_req, temp_req,
  2090. &epn->queue, queue) {
  2091. status = process_ep_req(dev, i, curr_req);
  2092. dev_vdbg(&dev->pdev->dev, "%s req status: %d\n",
  2093. epn->name, status);
  2094. if (status)
  2095. break;
  2096. /* write back status to req */
  2097. curr_req->req.status = status;
  2098. /* ep0 request completion */
  2099. if (ep_num == 0) {
  2100. ep0_req_complete(dev, epn, curr_req);
  2101. break;
  2102. } else {
  2103. done(epn, curr_req, status);
  2104. }
  2105. }
  2106. }
  2107. done:
  2108. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2109. }
  2110. /* port change detect interrupt handler */
  2111. static void handle_port_change(struct langwell_udc *dev)
  2112. {
  2113. u32 portsc1, devlc;
  2114. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2115. if (dev->bus_reset)
  2116. dev->bus_reset = 0;
  2117. portsc1 = readl(&dev->op_regs->portsc1);
  2118. devlc = readl(&dev->op_regs->devlc);
  2119. dev_vdbg(&dev->pdev->dev, "portsc1 = 0x%08x, devlc = 0x%08x\n",
  2120. portsc1, devlc);
  2121. /* bus reset is finished */
  2122. if (!(portsc1 & PORTS_PR)) {
  2123. /* get the speed */
  2124. dev->gadget.speed = lpm_device_speed(devlc);
  2125. dev_vdbg(&dev->pdev->dev, "dev->gadget.speed = %d\n",
  2126. dev->gadget.speed);
  2127. }
  2128. /* LPM L0 to L1 */
  2129. if (dev->lpm && dev->lpm_state == LPM_L0)
  2130. if (portsc1 & PORTS_SUSP && portsc1 & PORTS_SLP) {
  2131. dev_info(&dev->pdev->dev, "LPM L0 to L1\n");
  2132. dev->lpm_state = LPM_L1;
  2133. }
  2134. /* LPM L1 to L0, force resume or remote wakeup finished */
  2135. if (dev->lpm && dev->lpm_state == LPM_L1)
  2136. if (!(portsc1 & PORTS_SUSP)) {
  2137. dev_info(&dev->pdev->dev, "LPM L1 to L0\n");
  2138. dev->lpm_state = LPM_L0;
  2139. }
  2140. /* update USB state */
  2141. if (!dev->resume_state)
  2142. dev->usb_state = USB_STATE_DEFAULT;
  2143. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2144. }
  2145. /* USB reset interrupt handler */
  2146. static void handle_usb_reset(struct langwell_udc *dev)
  2147. {
  2148. u32 deviceaddr,
  2149. endptsetupstat,
  2150. endptcomplete;
  2151. unsigned long timeout;
  2152. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2153. /* Write-Clear the device address */
  2154. deviceaddr = readl(&dev->op_regs->deviceaddr);
  2155. writel(deviceaddr & ~USBADR_MASK, &dev->op_regs->deviceaddr);
  2156. dev->dev_addr = 0;
  2157. /* clear usb state */
  2158. dev->resume_state = 0;
  2159. /* LPM L1 to L0, reset */
  2160. if (dev->lpm)
  2161. dev->lpm_state = LPM_L0;
  2162. dev->ep0_dir = USB_DIR_OUT;
  2163. dev->ep0_state = WAIT_FOR_SETUP;
  2164. /* remote wakeup reset to 0 when the device is reset */
  2165. dev->remote_wakeup = 0;
  2166. dev->dev_status = 1 << USB_DEVICE_SELF_POWERED;
  2167. dev->gadget.b_hnp_enable = 0;
  2168. dev->gadget.a_hnp_support = 0;
  2169. dev->gadget.a_alt_hnp_support = 0;
  2170. /* Write-Clear all the setup token semaphores */
  2171. endptsetupstat = readl(&dev->op_regs->endptsetupstat);
  2172. writel(endptsetupstat, &dev->op_regs->endptsetupstat);
  2173. /* Write-Clear all the endpoint complete status bits */
  2174. endptcomplete = readl(&dev->op_regs->endptcomplete);
  2175. writel(endptcomplete, &dev->op_regs->endptcomplete);
  2176. /* wait until all endptprime bits cleared */
  2177. timeout = jiffies + PRIME_TIMEOUT;
  2178. while (readl(&dev->op_regs->endptprime)) {
  2179. if (time_after(jiffies, timeout)) {
  2180. dev_err(&dev->pdev->dev, "USB reset timeout\n");
  2181. break;
  2182. }
  2183. cpu_relax();
  2184. }
  2185. /* write 1s to endptflush register to clear any primed buffers */
  2186. writel((u32) ~0, &dev->op_regs->endptflush);
  2187. if (readl(&dev->op_regs->portsc1) & PORTS_PR) {
  2188. dev_vdbg(&dev->pdev->dev, "USB bus reset\n");
  2189. /* bus is reseting */
  2190. dev->bus_reset = 1;
  2191. /* reset all the queues, stop all USB activities */
  2192. stop_activity(dev);
  2193. dev->usb_state = USB_STATE_DEFAULT;
  2194. } else {
  2195. dev_vdbg(&dev->pdev->dev, "device controller reset\n");
  2196. /* controller reset */
  2197. langwell_udc_reset(dev);
  2198. /* reset all the queues, stop all USB activities */
  2199. stop_activity(dev);
  2200. /* reset ep0 dQH and endptctrl */
  2201. ep0_reset(dev);
  2202. /* enable interrupt and set controller to run state */
  2203. langwell_udc_start(dev);
  2204. dev->usb_state = USB_STATE_ATTACHED;
  2205. }
  2206. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2207. }
  2208. /* USB bus suspend/resume interrupt */
  2209. static void handle_bus_suspend(struct langwell_udc *dev)
  2210. {
  2211. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2212. dev->resume_state = dev->usb_state;
  2213. dev->usb_state = USB_STATE_SUSPENDED;
  2214. /* report suspend to the driver */
  2215. if (dev->driver) {
  2216. if (dev->driver->suspend) {
  2217. spin_unlock(&dev->lock);
  2218. dev->driver->suspend(&dev->gadget);
  2219. spin_lock(&dev->lock);
  2220. dev_dbg(&dev->pdev->dev, "suspend %s\n",
  2221. dev->driver->driver.name);
  2222. }
  2223. }
  2224. /* enter PHY low power suspend */
  2225. if (dev->pdev->device != 0x0829)
  2226. langwell_phy_low_power(dev, 0);
  2227. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2228. }
  2229. static void handle_bus_resume(struct langwell_udc *dev)
  2230. {
  2231. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2232. dev->usb_state = dev->resume_state;
  2233. dev->resume_state = 0;
  2234. /* exit PHY low power suspend */
  2235. if (dev->pdev->device != 0x0829)
  2236. langwell_phy_low_power(dev, 0);
  2237. /* report resume to the driver */
  2238. if (dev->driver) {
  2239. if (dev->driver->resume) {
  2240. spin_unlock(&dev->lock);
  2241. dev->driver->resume(&dev->gadget);
  2242. spin_lock(&dev->lock);
  2243. dev_dbg(&dev->pdev->dev, "resume %s\n",
  2244. dev->driver->driver.name);
  2245. }
  2246. }
  2247. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2248. }
  2249. /* USB device controller interrupt handler */
  2250. static irqreturn_t langwell_irq(int irq, void *_dev)
  2251. {
  2252. struct langwell_udc *dev = _dev;
  2253. u32 usbsts,
  2254. usbintr,
  2255. irq_sts,
  2256. portsc1;
  2257. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2258. if (dev->stopped) {
  2259. dev_vdbg(&dev->pdev->dev, "handle IRQ_NONE\n");
  2260. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2261. return IRQ_NONE;
  2262. }
  2263. spin_lock(&dev->lock);
  2264. /* USB status */
  2265. usbsts = readl(&dev->op_regs->usbsts);
  2266. /* USB interrupt enable */
  2267. usbintr = readl(&dev->op_regs->usbintr);
  2268. irq_sts = usbsts & usbintr;
  2269. dev_vdbg(&dev->pdev->dev,
  2270. "usbsts = 0x%08x, usbintr = 0x%08x, irq_sts = 0x%08x\n",
  2271. usbsts, usbintr, irq_sts);
  2272. if (!irq_sts) {
  2273. dev_vdbg(&dev->pdev->dev, "handle IRQ_NONE\n");
  2274. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2275. spin_unlock(&dev->lock);
  2276. return IRQ_NONE;
  2277. }
  2278. /* Write-Clear interrupt status bits */
  2279. writel(irq_sts, &dev->op_regs->usbsts);
  2280. /* resume from suspend */
  2281. portsc1 = readl(&dev->op_regs->portsc1);
  2282. if (dev->usb_state == USB_STATE_SUSPENDED)
  2283. if (!(portsc1 & PORTS_SUSP))
  2284. handle_bus_resume(dev);
  2285. /* USB interrupt */
  2286. if (irq_sts & STS_UI) {
  2287. dev_vdbg(&dev->pdev->dev, "USB interrupt\n");
  2288. /* setup packet received from ep0 */
  2289. if (readl(&dev->op_regs->endptsetupstat)
  2290. & EP0SETUPSTAT_MASK) {
  2291. dev_vdbg(&dev->pdev->dev,
  2292. "USB SETUP packet received interrupt\n");
  2293. /* setup tripwire semaphone */
  2294. setup_tripwire(dev);
  2295. handle_setup_packet(dev, &dev->local_setup_buff);
  2296. }
  2297. /* USB transfer completion */
  2298. if (readl(&dev->op_regs->endptcomplete)) {
  2299. dev_vdbg(&dev->pdev->dev,
  2300. "USB transfer completion interrupt\n");
  2301. handle_trans_complete(dev);
  2302. }
  2303. }
  2304. /* SOF received interrupt (for ISO transfer) */
  2305. if (irq_sts & STS_SRI) {
  2306. /* FIXME */
  2307. /* dev_vdbg(&dev->pdev->dev, "SOF received interrupt\n"); */
  2308. }
  2309. /* port change detect interrupt */
  2310. if (irq_sts & STS_PCI) {
  2311. dev_vdbg(&dev->pdev->dev, "port change detect interrupt\n");
  2312. handle_port_change(dev);
  2313. }
  2314. /* suspend interrupt */
  2315. if (irq_sts & STS_SLI) {
  2316. dev_vdbg(&dev->pdev->dev, "suspend interrupt\n");
  2317. handle_bus_suspend(dev);
  2318. }
  2319. /* USB reset interrupt */
  2320. if (irq_sts & STS_URI) {
  2321. dev_vdbg(&dev->pdev->dev, "USB reset interrupt\n");
  2322. handle_usb_reset(dev);
  2323. }
  2324. /* USB error or system error interrupt */
  2325. if (irq_sts & (STS_UEI | STS_SEI)) {
  2326. /* FIXME */
  2327. dev_warn(&dev->pdev->dev, "error IRQ, irq_sts: %x\n", irq_sts);
  2328. }
  2329. spin_unlock(&dev->lock);
  2330. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2331. return IRQ_HANDLED;
  2332. }
  2333. /*-------------------------------------------------------------------------*/
  2334. /* release device structure */
  2335. static void gadget_release(struct device *_dev)
  2336. {
  2337. struct langwell_udc *dev = dev_get_drvdata(_dev);
  2338. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2339. complete(dev->done);
  2340. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2341. kfree(dev);
  2342. }
  2343. /* enable SRAM caching if SRAM detected */
  2344. static void sram_init(struct langwell_udc *dev)
  2345. {
  2346. struct pci_dev *pdev = dev->pdev;
  2347. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2348. dev->sram_addr = pci_resource_start(pdev, 1);
  2349. dev->sram_size = pci_resource_len(pdev, 1);
  2350. dev_info(&dev->pdev->dev, "Found private SRAM at %x size:%x\n",
  2351. dev->sram_addr, dev->sram_size);
  2352. dev->got_sram = 1;
  2353. if (pci_request_region(pdev, 1, kobject_name(&pdev->dev.kobj))) {
  2354. dev_warn(&dev->pdev->dev, "SRAM request failed\n");
  2355. dev->got_sram = 0;
  2356. } else if (!dma_declare_coherent_memory(&pdev->dev, dev->sram_addr,
  2357. dev->sram_addr, dev->sram_size, DMA_MEMORY_MAP)) {
  2358. dev_warn(&dev->pdev->dev, "SRAM DMA declare failed\n");
  2359. pci_release_region(pdev, 1);
  2360. dev->got_sram = 0;
  2361. }
  2362. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2363. }
  2364. /* release SRAM caching */
  2365. static void sram_deinit(struct langwell_udc *dev)
  2366. {
  2367. struct pci_dev *pdev = dev->pdev;
  2368. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2369. dma_release_declared_memory(&pdev->dev);
  2370. pci_release_region(pdev, 1);
  2371. dev->got_sram = 0;
  2372. dev_info(&dev->pdev->dev, "release SRAM caching\n");
  2373. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2374. }
  2375. /* tear down the binding between this driver and the pci device */
  2376. static void langwell_udc_remove(struct pci_dev *pdev)
  2377. {
  2378. struct langwell_udc *dev = pci_get_drvdata(pdev);
  2379. DECLARE_COMPLETION(done);
  2380. BUG_ON(dev->driver);
  2381. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2382. dev->done = &done;
  2383. /* free dTD dma_pool and dQH */
  2384. if (dev->dtd_pool)
  2385. dma_pool_destroy(dev->dtd_pool);
  2386. if (dev->ep_dqh)
  2387. dma_free_coherent(&pdev->dev, dev->ep_dqh_size,
  2388. dev->ep_dqh, dev->ep_dqh_dma);
  2389. /* release SRAM caching */
  2390. if (dev->has_sram && dev->got_sram)
  2391. sram_deinit(dev);
  2392. if (dev->status_req) {
  2393. kfree(dev->status_req->req.buf);
  2394. kfree(dev->status_req);
  2395. }
  2396. kfree(dev->ep);
  2397. /* disable IRQ handler */
  2398. if (dev->got_irq)
  2399. free_irq(pdev->irq, dev);
  2400. if (dev->cap_regs)
  2401. iounmap(dev->cap_regs);
  2402. if (dev->region)
  2403. release_mem_region(pci_resource_start(pdev, 0),
  2404. pci_resource_len(pdev, 0));
  2405. if (dev->enabled)
  2406. pci_disable_device(pdev);
  2407. dev->cap_regs = NULL;
  2408. dev_info(&dev->pdev->dev, "unbind\n");
  2409. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2410. device_unregister(&dev->gadget.dev);
  2411. device_remove_file(&pdev->dev, &dev_attr_langwell_udc);
  2412. device_remove_file(&pdev->dev, &dev_attr_remote_wakeup);
  2413. pci_set_drvdata(pdev, NULL);
  2414. /* free dev, wait for the release() finished */
  2415. wait_for_completion(&done);
  2416. }
  2417. /*
  2418. * wrap this driver around the specified device, but
  2419. * don't respond over USB until a gadget driver binds to us.
  2420. */
  2421. static int langwell_udc_probe(struct pci_dev *pdev,
  2422. const struct pci_device_id *id)
  2423. {
  2424. struct langwell_udc *dev;
  2425. unsigned long resource, len;
  2426. void __iomem *base = NULL;
  2427. size_t size;
  2428. int retval;
  2429. /* alloc, and start init */
  2430. dev = kzalloc(sizeof *dev, GFP_KERNEL);
  2431. if (dev == NULL) {
  2432. retval = -ENOMEM;
  2433. goto error;
  2434. }
  2435. /* initialize device spinlock */
  2436. spin_lock_init(&dev->lock);
  2437. dev->pdev = pdev;
  2438. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2439. pci_set_drvdata(pdev, dev);
  2440. /* now all the pci goodies ... */
  2441. if (pci_enable_device(pdev) < 0) {
  2442. retval = -ENODEV;
  2443. goto error;
  2444. }
  2445. dev->enabled = 1;
  2446. /* control register: BAR 0 */
  2447. resource = pci_resource_start(pdev, 0);
  2448. len = pci_resource_len(pdev, 0);
  2449. if (!request_mem_region(resource, len, driver_name)) {
  2450. dev_err(&dev->pdev->dev, "controller already in use\n");
  2451. retval = -EBUSY;
  2452. goto error;
  2453. }
  2454. dev->region = 1;
  2455. base = ioremap_nocache(resource, len);
  2456. if (base == NULL) {
  2457. dev_err(&dev->pdev->dev, "can't map memory\n");
  2458. retval = -EFAULT;
  2459. goto error;
  2460. }
  2461. dev->cap_regs = (struct langwell_cap_regs __iomem *) base;
  2462. dev_vdbg(&dev->pdev->dev, "dev->cap_regs: %p\n", dev->cap_regs);
  2463. dev->op_regs = (struct langwell_op_regs __iomem *)
  2464. (base + OP_REG_OFFSET);
  2465. dev_vdbg(&dev->pdev->dev, "dev->op_regs: %p\n", dev->op_regs);
  2466. /* irq setup after old hardware is cleaned up */
  2467. if (!pdev->irq) {
  2468. dev_err(&dev->pdev->dev, "No IRQ. Check PCI setup!\n");
  2469. retval = -ENODEV;
  2470. goto error;
  2471. }
  2472. dev->has_sram = 1;
  2473. dev->got_sram = 0;
  2474. dev_vdbg(&dev->pdev->dev, "dev->has_sram: %d\n", dev->has_sram);
  2475. /* enable SRAM caching if detected */
  2476. if (dev->has_sram && !dev->got_sram)
  2477. sram_init(dev);
  2478. dev_info(&dev->pdev->dev,
  2479. "irq %d, io mem: 0x%08lx, len: 0x%08lx, pci mem 0x%p\n",
  2480. pdev->irq, resource, len, base);
  2481. /* enables bus-mastering for device dev */
  2482. pci_set_master(pdev);
  2483. if (request_irq(pdev->irq, langwell_irq, IRQF_SHARED,
  2484. driver_name, dev) != 0) {
  2485. dev_err(&dev->pdev->dev,
  2486. "request interrupt %d failed\n", pdev->irq);
  2487. retval = -EBUSY;
  2488. goto error;
  2489. }
  2490. dev->got_irq = 1;
  2491. /* set stopped bit */
  2492. dev->stopped = 1;
  2493. /* capabilities and endpoint number */
  2494. dev->lpm = (readl(&dev->cap_regs->hccparams) & HCC_LEN) ? 1 : 0;
  2495. dev->dciversion = readw(&dev->cap_regs->dciversion);
  2496. dev->devcap = (readl(&dev->cap_regs->dccparams) & DEVCAP) ? 1 : 0;
  2497. dev_vdbg(&dev->pdev->dev, "dev->lpm: %d\n", dev->lpm);
  2498. dev_vdbg(&dev->pdev->dev, "dev->dciversion: 0x%04x\n",
  2499. dev->dciversion);
  2500. dev_vdbg(&dev->pdev->dev, "dccparams: 0x%08x\n",
  2501. readl(&dev->cap_regs->dccparams));
  2502. dev_vdbg(&dev->pdev->dev, "dev->devcap: %d\n", dev->devcap);
  2503. if (!dev->devcap) {
  2504. dev_err(&dev->pdev->dev, "can't support device mode\n");
  2505. retval = -ENODEV;
  2506. goto error;
  2507. }
  2508. /* a pair of endpoints (out/in) for each address */
  2509. dev->ep_max = DEN(readl(&dev->cap_regs->dccparams)) * 2;
  2510. dev_vdbg(&dev->pdev->dev, "dev->ep_max: %d\n", dev->ep_max);
  2511. /* allocate endpoints memory */
  2512. dev->ep = kzalloc(sizeof(struct langwell_ep) * dev->ep_max,
  2513. GFP_KERNEL);
  2514. if (!dev->ep) {
  2515. dev_err(&dev->pdev->dev, "allocate endpoints memory failed\n");
  2516. retval = -ENOMEM;
  2517. goto error;
  2518. }
  2519. /* allocate device dQH memory */
  2520. size = dev->ep_max * sizeof(struct langwell_dqh);
  2521. dev_vdbg(&dev->pdev->dev, "orig size = %zd\n", size);
  2522. if (size < DQH_ALIGNMENT)
  2523. size = DQH_ALIGNMENT;
  2524. else if ((size % DQH_ALIGNMENT) != 0) {
  2525. size += DQH_ALIGNMENT + 1;
  2526. size &= ~(DQH_ALIGNMENT - 1);
  2527. }
  2528. dev->ep_dqh = dma_alloc_coherent(&pdev->dev, size,
  2529. &dev->ep_dqh_dma, GFP_KERNEL);
  2530. if (!dev->ep_dqh) {
  2531. dev_err(&dev->pdev->dev, "allocate dQH memory failed\n");
  2532. retval = -ENOMEM;
  2533. goto error;
  2534. }
  2535. dev->ep_dqh_size = size;
  2536. dev_vdbg(&dev->pdev->dev, "ep_dqh_size = %zd\n", dev->ep_dqh_size);
  2537. /* initialize ep0 status request structure */
  2538. dev->status_req = kzalloc(sizeof(struct langwell_request), GFP_KERNEL);
  2539. if (!dev->status_req) {
  2540. dev_err(&dev->pdev->dev,
  2541. "allocate status_req memory failed\n");
  2542. retval = -ENOMEM;
  2543. goto error;
  2544. }
  2545. INIT_LIST_HEAD(&dev->status_req->queue);
  2546. /* allocate a small amount of memory to get valid address */
  2547. dev->status_req->req.buf = kmalloc(8, GFP_KERNEL);
  2548. dev->status_req->req.dma = virt_to_phys(dev->status_req->req.buf);
  2549. dev->resume_state = USB_STATE_NOTATTACHED;
  2550. dev->usb_state = USB_STATE_POWERED;
  2551. dev->ep0_dir = USB_DIR_OUT;
  2552. /* remote wakeup reset to 0 when the device is reset */
  2553. dev->remote_wakeup = 0;
  2554. dev->dev_status = 1 << USB_DEVICE_SELF_POWERED;
  2555. /* reset device controller */
  2556. langwell_udc_reset(dev);
  2557. /* initialize gadget structure */
  2558. dev->gadget.ops = &langwell_ops; /* usb_gadget_ops */
  2559. dev->gadget.ep0 = &dev->ep[0].ep; /* gadget ep0 */
  2560. INIT_LIST_HEAD(&dev->gadget.ep_list); /* ep_list */
  2561. dev->gadget.speed = USB_SPEED_UNKNOWN; /* speed */
  2562. dev->gadget.max_speed = USB_SPEED_HIGH; /* support dual speed */
  2563. /* the "gadget" abstracts/virtualizes the controller */
  2564. dev_set_name(&dev->gadget.dev, "gadget");
  2565. dev->gadget.dev.parent = &pdev->dev;
  2566. dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
  2567. dev->gadget.dev.release = gadget_release;
  2568. dev->gadget.name = driver_name; /* gadget name */
  2569. /* controller endpoints reinit */
  2570. eps_reinit(dev);
  2571. /* reset ep0 dQH and endptctrl */
  2572. ep0_reset(dev);
  2573. /* create dTD dma_pool resource */
  2574. dev->dtd_pool = dma_pool_create("langwell_dtd",
  2575. &dev->pdev->dev,
  2576. sizeof(struct langwell_dtd),
  2577. DTD_ALIGNMENT,
  2578. DMA_BOUNDARY);
  2579. if (!dev->dtd_pool) {
  2580. retval = -ENOMEM;
  2581. goto error;
  2582. }
  2583. /* done */
  2584. dev_info(&dev->pdev->dev, "%s\n", driver_desc);
  2585. dev_info(&dev->pdev->dev, "irq %d, pci mem %p\n", pdev->irq, base);
  2586. dev_info(&dev->pdev->dev, "Driver version: " DRIVER_VERSION "\n");
  2587. dev_info(&dev->pdev->dev, "Support (max) %d endpoints\n", dev->ep_max);
  2588. dev_info(&dev->pdev->dev, "Device interface version: 0x%04x\n",
  2589. dev->dciversion);
  2590. dev_info(&dev->pdev->dev, "Controller mode: %s\n",
  2591. dev->devcap ? "Device" : "Host");
  2592. dev_info(&dev->pdev->dev, "Support USB LPM: %s\n",
  2593. dev->lpm ? "Yes" : "No");
  2594. dev_vdbg(&dev->pdev->dev,
  2595. "After langwell_udc_probe(), print all registers:\n");
  2596. print_all_registers(dev);
  2597. retval = device_register(&dev->gadget.dev);
  2598. if (retval)
  2599. goto error;
  2600. retval = usb_add_gadget_udc(&pdev->dev, &dev->gadget);
  2601. if (retval)
  2602. goto error;
  2603. retval = device_create_file(&pdev->dev, &dev_attr_langwell_udc);
  2604. if (retval)
  2605. goto error;
  2606. retval = device_create_file(&pdev->dev, &dev_attr_remote_wakeup);
  2607. if (retval)
  2608. goto error_attr1;
  2609. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2610. return 0;
  2611. error_attr1:
  2612. device_remove_file(&pdev->dev, &dev_attr_langwell_udc);
  2613. error:
  2614. if (dev) {
  2615. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2616. langwell_udc_remove(pdev);
  2617. }
  2618. return retval;
  2619. }
  2620. /* device controller suspend */
  2621. static int langwell_udc_suspend(struct pci_dev *pdev, pm_message_t state)
  2622. {
  2623. struct langwell_udc *dev = pci_get_drvdata(pdev);
  2624. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2625. usb_del_gadget_udc(&dev->gadget);
  2626. /* disable interrupt and set controller to stop state */
  2627. langwell_udc_stop(dev);
  2628. /* disable IRQ handler */
  2629. if (dev->got_irq)
  2630. free_irq(pdev->irq, dev);
  2631. dev->got_irq = 0;
  2632. /* save PCI state */
  2633. pci_save_state(pdev);
  2634. spin_lock_irq(&dev->lock);
  2635. /* stop all usb activities */
  2636. stop_activity(dev);
  2637. spin_unlock_irq(&dev->lock);
  2638. /* free dTD dma_pool and dQH */
  2639. if (dev->dtd_pool)
  2640. dma_pool_destroy(dev->dtd_pool);
  2641. if (dev->ep_dqh)
  2642. dma_free_coherent(&pdev->dev, dev->ep_dqh_size,
  2643. dev->ep_dqh, dev->ep_dqh_dma);
  2644. /* release SRAM caching */
  2645. if (dev->has_sram && dev->got_sram)
  2646. sram_deinit(dev);
  2647. /* set device power state */
  2648. pci_set_power_state(pdev, PCI_D3hot);
  2649. /* enter PHY low power suspend */
  2650. if (dev->pdev->device != 0x0829)
  2651. langwell_phy_low_power(dev, 1);
  2652. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2653. return 0;
  2654. }
  2655. /* device controller resume */
  2656. static int langwell_udc_resume(struct pci_dev *pdev)
  2657. {
  2658. struct langwell_udc *dev = pci_get_drvdata(pdev);
  2659. size_t size;
  2660. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2661. /* exit PHY low power suspend */
  2662. if (dev->pdev->device != 0x0829)
  2663. langwell_phy_low_power(dev, 0);
  2664. /* set device D0 power state */
  2665. pci_set_power_state(pdev, PCI_D0);
  2666. /* enable SRAM caching if detected */
  2667. if (dev->has_sram && !dev->got_sram)
  2668. sram_init(dev);
  2669. /* allocate device dQH memory */
  2670. size = dev->ep_max * sizeof(struct langwell_dqh);
  2671. dev_vdbg(&dev->pdev->dev, "orig size = %zd\n", size);
  2672. if (size < DQH_ALIGNMENT)
  2673. size = DQH_ALIGNMENT;
  2674. else if ((size % DQH_ALIGNMENT) != 0) {
  2675. size += DQH_ALIGNMENT + 1;
  2676. size &= ~(DQH_ALIGNMENT - 1);
  2677. }
  2678. dev->ep_dqh = dma_alloc_coherent(&pdev->dev, size,
  2679. &dev->ep_dqh_dma, GFP_KERNEL);
  2680. if (!dev->ep_dqh) {
  2681. dev_err(&dev->pdev->dev, "allocate dQH memory failed\n");
  2682. return -ENOMEM;
  2683. }
  2684. dev->ep_dqh_size = size;
  2685. dev_vdbg(&dev->pdev->dev, "ep_dqh_size = %zd\n", dev->ep_dqh_size);
  2686. /* create dTD dma_pool resource */
  2687. dev->dtd_pool = dma_pool_create("langwell_dtd",
  2688. &dev->pdev->dev,
  2689. sizeof(struct langwell_dtd),
  2690. DTD_ALIGNMENT,
  2691. DMA_BOUNDARY);
  2692. if (!dev->dtd_pool)
  2693. return -ENOMEM;
  2694. /* restore PCI state */
  2695. pci_restore_state(pdev);
  2696. /* enable IRQ handler */
  2697. if (request_irq(pdev->irq, langwell_irq, IRQF_SHARED,
  2698. driver_name, dev) != 0) {
  2699. dev_err(&dev->pdev->dev, "request interrupt %d failed\n",
  2700. pdev->irq);
  2701. return -EBUSY;
  2702. }
  2703. dev->got_irq = 1;
  2704. /* reset and start controller to run state */
  2705. if (dev->stopped) {
  2706. /* reset device controller */
  2707. langwell_udc_reset(dev);
  2708. /* reset ep0 dQH and endptctrl */
  2709. ep0_reset(dev);
  2710. /* start device if gadget is loaded */
  2711. if (dev->driver)
  2712. langwell_udc_start(dev);
  2713. }
  2714. /* reset USB status */
  2715. dev->usb_state = USB_STATE_ATTACHED;
  2716. dev->ep0_state = WAIT_FOR_SETUP;
  2717. dev->ep0_dir = USB_DIR_OUT;
  2718. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2719. return 0;
  2720. }
  2721. /* pci driver shutdown */
  2722. static void langwell_udc_shutdown(struct pci_dev *pdev)
  2723. {
  2724. struct langwell_udc *dev = pci_get_drvdata(pdev);
  2725. u32 usbmode;
  2726. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2727. /* reset controller mode to IDLE */
  2728. usbmode = readl(&dev->op_regs->usbmode);
  2729. dev_dbg(&dev->pdev->dev, "usbmode = 0x%08x\n", usbmode);
  2730. usbmode &= (~3 | MODE_IDLE);
  2731. writel(usbmode, &dev->op_regs->usbmode);
  2732. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2733. }
  2734. /*-------------------------------------------------------------------------*/
  2735. static const struct pci_device_id pci_ids[] = { {
  2736. .class = ((PCI_CLASS_SERIAL_USB << 8) | 0xfe),
  2737. .class_mask = ~0,
  2738. .vendor = 0x8086,
  2739. .device = 0x0811,
  2740. .subvendor = PCI_ANY_ID,
  2741. .subdevice = PCI_ANY_ID,
  2742. }, { /* end: all zeroes */ }
  2743. };
  2744. MODULE_DEVICE_TABLE(pci, pci_ids);
  2745. static struct pci_driver langwell_pci_driver = {
  2746. .name = (char *) driver_name,
  2747. .id_table = pci_ids,
  2748. .probe = langwell_udc_probe,
  2749. .remove = langwell_udc_remove,
  2750. /* device controller suspend/resume */
  2751. .suspend = langwell_udc_suspend,
  2752. .resume = langwell_udc_resume,
  2753. .shutdown = langwell_udc_shutdown,
  2754. };
  2755. static int __init init(void)
  2756. {
  2757. return pci_register_driver(&langwell_pci_driver);
  2758. }
  2759. module_init(init);
  2760. static void __exit cleanup(void)
  2761. {
  2762. pci_unregister_driver(&langwell_pci_driver);
  2763. }
  2764. module_exit(cleanup);
  2765. MODULE_DESCRIPTION(DRIVER_DESC);
  2766. MODULE_AUTHOR("Xiaochen Shen <xiaochen.shen@intel.com>");
  2767. MODULE_VERSION(DRIVER_VERSION);
  2768. MODULE_LICENSE("GPL");