qla_mbx.c 106 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2011 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include <linux/delay.h>
  9. #include <linux/gfp.h>
  10. /*
  11. * qla2x00_mailbox_command
  12. * Issue mailbox command and waits for completion.
  13. *
  14. * Input:
  15. * ha = adapter block pointer.
  16. * mcp = driver internal mbx struct pointer.
  17. *
  18. * Output:
  19. * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data.
  20. *
  21. * Returns:
  22. * 0 : QLA_SUCCESS = cmd performed success
  23. * 1 : QLA_FUNCTION_FAILED (error encountered)
  24. * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered)
  25. *
  26. * Context:
  27. * Kernel context.
  28. */
  29. static int
  30. qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp)
  31. {
  32. int rval;
  33. unsigned long flags = 0;
  34. device_reg_t __iomem *reg;
  35. uint8_t abort_active;
  36. uint8_t io_lock_on;
  37. uint16_t command = 0;
  38. uint16_t *iptr;
  39. uint16_t __iomem *optr;
  40. uint32_t cnt;
  41. uint32_t mboxes;
  42. unsigned long wait_time;
  43. struct qla_hw_data *ha = vha->hw;
  44. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  45. ql_dbg(ql_dbg_mbx, base_vha, 0x1000, "Entered %s.\n", __func__);
  46. if (ha->pdev->error_state > pci_channel_io_frozen) {
  47. ql_log(ql_log_warn, base_vha, 0x1001,
  48. "error_state is greater than pci_channel_io_frozen, "
  49. "exiting.\n");
  50. return QLA_FUNCTION_TIMEOUT;
  51. }
  52. if (vha->device_flags & DFLG_DEV_FAILED) {
  53. ql_log(ql_log_warn, base_vha, 0x1002,
  54. "Device in failed state, exiting.\n");
  55. return QLA_FUNCTION_TIMEOUT;
  56. }
  57. reg = ha->iobase;
  58. io_lock_on = base_vha->flags.init_done;
  59. rval = QLA_SUCCESS;
  60. abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  61. if (ha->flags.pci_channel_io_perm_failure) {
  62. ql_log(ql_log_warn, base_vha, 0x1003,
  63. "Perm failure on EEH timeout MBX, exiting.\n");
  64. return QLA_FUNCTION_TIMEOUT;
  65. }
  66. if (ha->flags.isp82xx_fw_hung) {
  67. /* Setting Link-Down error */
  68. mcp->mb[0] = MBS_LINK_DOWN_ERROR;
  69. ql_log(ql_log_warn, base_vha, 0x1004,
  70. "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
  71. return QLA_FUNCTION_TIMEOUT;
  72. }
  73. /*
  74. * Wait for active mailbox commands to finish by waiting at most tov
  75. * seconds. This is to serialize actual issuing of mailbox cmds during
  76. * non ISP abort time.
  77. */
  78. if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) {
  79. /* Timeout occurred. Return error. */
  80. ql_log(ql_log_warn, base_vha, 0x1005,
  81. "Cmd access timeout, Exiting.\n");
  82. return QLA_FUNCTION_TIMEOUT;
  83. }
  84. ha->flags.mbox_busy = 1;
  85. /* Save mailbox command for debug */
  86. ha->mcp = mcp;
  87. ql_dbg(ql_dbg_mbx, base_vha, 0x1006,
  88. "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]);
  89. spin_lock_irqsave(&ha->hardware_lock, flags);
  90. /* Load mailbox registers. */
  91. if (IS_QLA82XX(ha))
  92. optr = (uint16_t __iomem *)&reg->isp82.mailbox_in[0];
  93. else if (IS_FWI2_CAPABLE(ha) && !IS_QLA82XX(ha))
  94. optr = (uint16_t __iomem *)&reg->isp24.mailbox0;
  95. else
  96. optr = (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 0);
  97. iptr = mcp->mb;
  98. command = mcp->mb[0];
  99. mboxes = mcp->out_mb;
  100. for (cnt = 0; cnt < ha->mbx_count; cnt++) {
  101. if (IS_QLA2200(ha) && cnt == 8)
  102. optr =
  103. (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 8);
  104. if (mboxes & BIT_0)
  105. WRT_REG_WORD(optr, *iptr);
  106. mboxes >>= 1;
  107. optr++;
  108. iptr++;
  109. }
  110. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x1111,
  111. "Loaded MBX registers (displayed in bytes) =.\n");
  112. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x1112,
  113. (uint8_t *)mcp->mb, 16);
  114. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x1113,
  115. ".\n");
  116. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x1114,
  117. ((uint8_t *)mcp->mb + 0x10), 16);
  118. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x1115,
  119. ".\n");
  120. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x1116,
  121. ((uint8_t *)mcp->mb + 0x20), 8);
  122. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x1117,
  123. "I/O Address = %p.\n", optr);
  124. ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x100e);
  125. /* Issue set host interrupt command to send cmd out. */
  126. ha->flags.mbox_int = 0;
  127. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  128. /* Unlock mbx registers and wait for interrupt */
  129. ql_dbg(ql_dbg_mbx, base_vha, 0x100f,
  130. "Going to unlock irq & waiting for interrupts. "
  131. "jiffies=%lx.\n", jiffies);
  132. /* Wait for mbx cmd completion until timeout */
  133. if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
  134. set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
  135. if (IS_QLA82XX(ha)) {
  136. if (RD_REG_DWORD(&reg->isp82.hint) &
  137. HINT_MBX_INT_PENDING) {
  138. spin_unlock_irqrestore(&ha->hardware_lock,
  139. flags);
  140. ha->flags.mbox_busy = 0;
  141. ql_dbg(ql_dbg_mbx, base_vha, 0x1010,
  142. "Pending mailbox timeout, exiting.\n");
  143. rval = QLA_FUNCTION_TIMEOUT;
  144. goto premature_exit;
  145. }
  146. WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
  147. } else if (IS_FWI2_CAPABLE(ha))
  148. WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
  149. else
  150. WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
  151. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  152. wait_for_completion_timeout(&ha->mbx_intr_comp, mcp->tov * HZ);
  153. clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
  154. } else {
  155. ql_dbg(ql_dbg_mbx, base_vha, 0x1011,
  156. "Cmd=%x Polling Mode.\n", command);
  157. if (IS_QLA82XX(ha)) {
  158. if (RD_REG_DWORD(&reg->isp82.hint) &
  159. HINT_MBX_INT_PENDING) {
  160. spin_unlock_irqrestore(&ha->hardware_lock,
  161. flags);
  162. ha->flags.mbox_busy = 0;
  163. ql_dbg(ql_dbg_mbx, base_vha, 0x1012,
  164. "Pending mailbox timeout, exiting.\n");
  165. rval = QLA_FUNCTION_TIMEOUT;
  166. goto premature_exit;
  167. }
  168. WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
  169. } else if (IS_FWI2_CAPABLE(ha))
  170. WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
  171. else
  172. WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
  173. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  174. wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */
  175. while (!ha->flags.mbox_int) {
  176. if (time_after(jiffies, wait_time))
  177. break;
  178. /* Check for pending interrupts. */
  179. qla2x00_poll(ha->rsp_q_map[0]);
  180. if (!ha->flags.mbox_int &&
  181. !(IS_QLA2200(ha) &&
  182. command == MBC_LOAD_RISC_RAM_EXTENDED))
  183. msleep(10);
  184. } /* while */
  185. ql_dbg(ql_dbg_mbx, base_vha, 0x1013,
  186. "Waited %d sec.\n",
  187. (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
  188. }
  189. /* Check whether we timed out */
  190. if (ha->flags.mbox_int) {
  191. uint16_t *iptr2;
  192. ql_dbg(ql_dbg_mbx, base_vha, 0x1014,
  193. "Cmd=%x completed.\n", command);
  194. /* Got interrupt. Clear the flag. */
  195. ha->flags.mbox_int = 0;
  196. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  197. if (ha->flags.isp82xx_fw_hung) {
  198. ha->flags.mbox_busy = 0;
  199. /* Setting Link-Down error */
  200. mcp->mb[0] = MBS_LINK_DOWN_ERROR;
  201. ha->mcp = NULL;
  202. rval = QLA_FUNCTION_FAILED;
  203. ql_log(ql_log_warn, base_vha, 0x1015,
  204. "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
  205. goto premature_exit;
  206. }
  207. if (ha->mailbox_out[0] != MBS_COMMAND_COMPLETE)
  208. rval = QLA_FUNCTION_FAILED;
  209. /* Load return mailbox registers. */
  210. iptr2 = mcp->mb;
  211. iptr = (uint16_t *)&ha->mailbox_out[0];
  212. mboxes = mcp->in_mb;
  213. for (cnt = 0; cnt < ha->mbx_count; cnt++) {
  214. if (mboxes & BIT_0)
  215. *iptr2 = *iptr;
  216. mboxes >>= 1;
  217. iptr2++;
  218. iptr++;
  219. }
  220. } else {
  221. uint16_t mb0;
  222. uint32_t ictrl;
  223. if (IS_FWI2_CAPABLE(ha)) {
  224. mb0 = RD_REG_WORD(&reg->isp24.mailbox0);
  225. ictrl = RD_REG_DWORD(&reg->isp24.ictrl);
  226. } else {
  227. mb0 = RD_MAILBOX_REG(ha, &reg->isp, 0);
  228. ictrl = RD_REG_WORD(&reg->isp.ictrl);
  229. }
  230. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x1119,
  231. "MBX Command timeout for cmd %x.\n", command);
  232. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x111a,
  233. "iocontrol=%x jiffies=%lx.\n", ictrl, jiffies);
  234. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x111b,
  235. "mb[0] = 0x%x.\n", mb0);
  236. ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x1019);
  237. rval = QLA_FUNCTION_TIMEOUT;
  238. }
  239. ha->flags.mbox_busy = 0;
  240. /* Clean up */
  241. ha->mcp = NULL;
  242. if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) {
  243. ql_dbg(ql_dbg_mbx, base_vha, 0x101a,
  244. "Checking for additional resp interrupt.\n");
  245. /* polling mode for non isp_abort commands. */
  246. qla2x00_poll(ha->rsp_q_map[0]);
  247. }
  248. if (rval == QLA_FUNCTION_TIMEOUT &&
  249. mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) {
  250. if (!io_lock_on || (mcp->flags & IOCTL_CMD) ||
  251. ha->flags.eeh_busy) {
  252. /* not in dpc. schedule it for dpc to take over. */
  253. ql_dbg(ql_dbg_mbx, base_vha, 0x101b,
  254. "Timeout, schedule isp_abort_needed.\n");
  255. if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
  256. !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
  257. !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  258. if (IS_QLA82XX(ha)) {
  259. ql_dbg(ql_dbg_mbx, vha, 0x112a,
  260. "disabling pause transmit on port "
  261. "0 & 1.\n");
  262. qla82xx_wr_32(ha,
  263. QLA82XX_CRB_NIU + 0x98,
  264. CRB_NIU_XG_PAUSE_CTL_P0|
  265. CRB_NIU_XG_PAUSE_CTL_P1);
  266. }
  267. ql_log(ql_log_info, base_vha, 0x101c,
  268. "Mailbox cmd timeout occured. "
  269. "Scheduling ISP abort eeh_busy=0x%x.\n",
  270. ha->flags.eeh_busy);
  271. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  272. qla2xxx_wake_dpc(vha);
  273. }
  274. } else if (!abort_active) {
  275. /* call abort directly since we are in the DPC thread */
  276. ql_dbg(ql_dbg_mbx, base_vha, 0x101d,
  277. "Timeout, calling abort_isp.\n");
  278. if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
  279. !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
  280. !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  281. if (IS_QLA82XX(ha)) {
  282. ql_dbg(ql_dbg_mbx, vha, 0x112b,
  283. "disabling pause transmit on port "
  284. "0 & 1.\n");
  285. qla82xx_wr_32(ha,
  286. QLA82XX_CRB_NIU + 0x98,
  287. CRB_NIU_XG_PAUSE_CTL_P0|
  288. CRB_NIU_XG_PAUSE_CTL_P1);
  289. }
  290. ql_log(ql_log_info, base_vha, 0x101e,
  291. "Mailbox cmd timeout occured. "
  292. "Scheduling ISP abort.\n");
  293. set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
  294. clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  295. /* Allow next mbx cmd to come in. */
  296. complete(&ha->mbx_cmd_comp);
  297. if (ha->isp_ops->abort_isp(vha)) {
  298. /* Failed. retry later. */
  299. set_bit(ISP_ABORT_NEEDED,
  300. &vha->dpc_flags);
  301. }
  302. clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
  303. ql_dbg(ql_dbg_mbx, base_vha, 0x101f,
  304. "Finished abort_isp.\n");
  305. goto mbx_done;
  306. }
  307. }
  308. }
  309. premature_exit:
  310. /* Allow next mbx cmd to come in. */
  311. complete(&ha->mbx_cmd_comp);
  312. mbx_done:
  313. if (rval) {
  314. ql_dbg(ql_dbg_mbx, base_vha, 0x1020,
  315. "**** Failed mbx[0]=%x, mb[1]=%x, mb[2]=%x, cmd=%x ****.\n",
  316. mcp->mb[0], mcp->mb[1], mcp->mb[2], command);
  317. } else {
  318. ql_dbg(ql_dbg_mbx, base_vha, 0x1021, "Done %s.\n", __func__);
  319. }
  320. return rval;
  321. }
  322. int
  323. qla2x00_load_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t risc_addr,
  324. uint32_t risc_code_size)
  325. {
  326. int rval;
  327. struct qla_hw_data *ha = vha->hw;
  328. mbx_cmd_t mc;
  329. mbx_cmd_t *mcp = &mc;
  330. ql_dbg(ql_dbg_mbx, vha, 0x1022, "Entered %s.\n", __func__);
  331. if (MSW(risc_addr) || IS_FWI2_CAPABLE(ha)) {
  332. mcp->mb[0] = MBC_LOAD_RISC_RAM_EXTENDED;
  333. mcp->mb[8] = MSW(risc_addr);
  334. mcp->out_mb = MBX_8|MBX_0;
  335. } else {
  336. mcp->mb[0] = MBC_LOAD_RISC_RAM;
  337. mcp->out_mb = MBX_0;
  338. }
  339. mcp->mb[1] = LSW(risc_addr);
  340. mcp->mb[2] = MSW(req_dma);
  341. mcp->mb[3] = LSW(req_dma);
  342. mcp->mb[6] = MSW(MSD(req_dma));
  343. mcp->mb[7] = LSW(MSD(req_dma));
  344. mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
  345. if (IS_FWI2_CAPABLE(ha)) {
  346. mcp->mb[4] = MSW(risc_code_size);
  347. mcp->mb[5] = LSW(risc_code_size);
  348. mcp->out_mb |= MBX_5|MBX_4;
  349. } else {
  350. mcp->mb[4] = LSW(risc_code_size);
  351. mcp->out_mb |= MBX_4;
  352. }
  353. mcp->in_mb = MBX_0;
  354. mcp->tov = MBX_TOV_SECONDS;
  355. mcp->flags = 0;
  356. rval = qla2x00_mailbox_command(vha, mcp);
  357. if (rval != QLA_SUCCESS) {
  358. ql_dbg(ql_dbg_mbx, vha, 0x1023,
  359. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  360. } else {
  361. ql_dbg(ql_dbg_mbx, vha, 0x1024, "Done %s.\n", __func__);
  362. }
  363. return rval;
  364. }
  365. #define EXTENDED_BB_CREDITS BIT_0
  366. /*
  367. * qla2x00_execute_fw
  368. * Start adapter firmware.
  369. *
  370. * Input:
  371. * ha = adapter block pointer.
  372. * TARGET_QUEUE_LOCK must be released.
  373. * ADAPTER_STATE_LOCK must be released.
  374. *
  375. * Returns:
  376. * qla2x00 local function return status code.
  377. *
  378. * Context:
  379. * Kernel context.
  380. */
  381. int
  382. qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr)
  383. {
  384. int rval;
  385. struct qla_hw_data *ha = vha->hw;
  386. mbx_cmd_t mc;
  387. mbx_cmd_t *mcp = &mc;
  388. ql_dbg(ql_dbg_mbx, vha, 0x1025, "Entered %s.\n", __func__);
  389. mcp->mb[0] = MBC_EXECUTE_FIRMWARE;
  390. mcp->out_mb = MBX_0;
  391. mcp->in_mb = MBX_0;
  392. if (IS_FWI2_CAPABLE(ha)) {
  393. mcp->mb[1] = MSW(risc_addr);
  394. mcp->mb[2] = LSW(risc_addr);
  395. mcp->mb[3] = 0;
  396. if (IS_QLA81XX(ha)) {
  397. struct nvram_81xx *nv = ha->nvram;
  398. mcp->mb[4] = (nv->enhanced_features &
  399. EXTENDED_BB_CREDITS);
  400. } else
  401. mcp->mb[4] = 0;
  402. mcp->out_mb |= MBX_4|MBX_3|MBX_2|MBX_1;
  403. mcp->in_mb |= MBX_1;
  404. } else {
  405. mcp->mb[1] = LSW(risc_addr);
  406. mcp->out_mb |= MBX_1;
  407. if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
  408. mcp->mb[2] = 0;
  409. mcp->out_mb |= MBX_2;
  410. }
  411. }
  412. mcp->tov = MBX_TOV_SECONDS;
  413. mcp->flags = 0;
  414. rval = qla2x00_mailbox_command(vha, mcp);
  415. if (rval != QLA_SUCCESS) {
  416. ql_dbg(ql_dbg_mbx, vha, 0x1026,
  417. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  418. } else {
  419. if (IS_FWI2_CAPABLE(ha)) {
  420. ql_dbg(ql_dbg_mbx, vha, 0x1027,
  421. "Done exchanges=%x.\n", mcp->mb[1]);
  422. } else {
  423. ql_dbg(ql_dbg_mbx, vha, 0x1028, "Done %s.\n", __func__);
  424. }
  425. }
  426. return rval;
  427. }
  428. /*
  429. * qla2x00_get_fw_version
  430. * Get firmware version.
  431. *
  432. * Input:
  433. * ha: adapter state pointer.
  434. * major: pointer for major number.
  435. * minor: pointer for minor number.
  436. * subminor: pointer for subminor number.
  437. *
  438. * Returns:
  439. * qla2x00 local function return status code.
  440. *
  441. * Context:
  442. * Kernel context.
  443. */
  444. int
  445. qla2x00_get_fw_version(scsi_qla_host_t *vha, uint16_t *major, uint16_t *minor,
  446. uint16_t *subminor, uint16_t *attributes, uint32_t *memory, uint8_t *mpi,
  447. uint32_t *mpi_caps, uint8_t *phy)
  448. {
  449. int rval;
  450. mbx_cmd_t mc;
  451. mbx_cmd_t *mcp = &mc;
  452. ql_dbg(ql_dbg_mbx, vha, 0x1029, "Entered %s.\n", __func__);
  453. mcp->mb[0] = MBC_GET_FIRMWARE_VERSION;
  454. mcp->out_mb = MBX_0;
  455. mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  456. if (IS_QLA81XX(vha->hw))
  457. mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8;
  458. mcp->flags = 0;
  459. mcp->tov = MBX_TOV_SECONDS;
  460. rval = qla2x00_mailbox_command(vha, mcp);
  461. if (rval != QLA_SUCCESS)
  462. goto failed;
  463. /* Return mailbox data. */
  464. *major = mcp->mb[1];
  465. *minor = mcp->mb[2];
  466. *subminor = mcp->mb[3];
  467. *attributes = mcp->mb[6];
  468. if (IS_QLA2100(vha->hw) || IS_QLA2200(vha->hw))
  469. *memory = 0x1FFFF; /* Defaults to 128KB. */
  470. else
  471. *memory = (mcp->mb[5] << 16) | mcp->mb[4];
  472. if (IS_QLA81XX(vha->hw)) {
  473. mpi[0] = mcp->mb[10] & 0xff;
  474. mpi[1] = mcp->mb[11] >> 8;
  475. mpi[2] = mcp->mb[11] & 0xff;
  476. *mpi_caps = (mcp->mb[12] << 16) | mcp->mb[13];
  477. phy[0] = mcp->mb[8] & 0xff;
  478. phy[1] = mcp->mb[9] >> 8;
  479. phy[2] = mcp->mb[9] & 0xff;
  480. }
  481. failed:
  482. if (rval != QLA_SUCCESS) {
  483. /*EMPTY*/
  484. ql_dbg(ql_dbg_mbx, vha, 0x102a, "Failed=%x.\n", rval);
  485. } else {
  486. /*EMPTY*/
  487. ql_dbg(ql_dbg_mbx, vha, 0x102b, "Done %s.\n", __func__);
  488. }
  489. return rval;
  490. }
  491. /*
  492. * qla2x00_get_fw_options
  493. * Set firmware options.
  494. *
  495. * Input:
  496. * ha = adapter block pointer.
  497. * fwopt = pointer for firmware options.
  498. *
  499. * Returns:
  500. * qla2x00 local function return status code.
  501. *
  502. * Context:
  503. * Kernel context.
  504. */
  505. int
  506. qla2x00_get_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
  507. {
  508. int rval;
  509. mbx_cmd_t mc;
  510. mbx_cmd_t *mcp = &mc;
  511. ql_dbg(ql_dbg_mbx, vha, 0x102c, "Entered %s.\n", __func__);
  512. mcp->mb[0] = MBC_GET_FIRMWARE_OPTION;
  513. mcp->out_mb = MBX_0;
  514. mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  515. mcp->tov = MBX_TOV_SECONDS;
  516. mcp->flags = 0;
  517. rval = qla2x00_mailbox_command(vha, mcp);
  518. if (rval != QLA_SUCCESS) {
  519. /*EMPTY*/
  520. ql_dbg(ql_dbg_mbx, vha, 0x102d, "Failed=%x.\n", rval);
  521. } else {
  522. fwopts[0] = mcp->mb[0];
  523. fwopts[1] = mcp->mb[1];
  524. fwopts[2] = mcp->mb[2];
  525. fwopts[3] = mcp->mb[3];
  526. ql_dbg(ql_dbg_mbx, vha, 0x102e, "Done %s.\n", __func__);
  527. }
  528. return rval;
  529. }
  530. /*
  531. * qla2x00_set_fw_options
  532. * Set firmware options.
  533. *
  534. * Input:
  535. * ha = adapter block pointer.
  536. * fwopt = pointer for firmware options.
  537. *
  538. * Returns:
  539. * qla2x00 local function return status code.
  540. *
  541. * Context:
  542. * Kernel context.
  543. */
  544. int
  545. qla2x00_set_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
  546. {
  547. int rval;
  548. mbx_cmd_t mc;
  549. mbx_cmd_t *mcp = &mc;
  550. ql_dbg(ql_dbg_mbx, vha, 0x102f, "Entered %s.\n", __func__);
  551. mcp->mb[0] = MBC_SET_FIRMWARE_OPTION;
  552. mcp->mb[1] = fwopts[1];
  553. mcp->mb[2] = fwopts[2];
  554. mcp->mb[3] = fwopts[3];
  555. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  556. mcp->in_mb = MBX_0;
  557. if (IS_FWI2_CAPABLE(vha->hw)) {
  558. mcp->in_mb |= MBX_1;
  559. } else {
  560. mcp->mb[10] = fwopts[10];
  561. mcp->mb[11] = fwopts[11];
  562. mcp->mb[12] = 0; /* Undocumented, but used */
  563. mcp->out_mb |= MBX_12|MBX_11|MBX_10;
  564. }
  565. mcp->tov = MBX_TOV_SECONDS;
  566. mcp->flags = 0;
  567. rval = qla2x00_mailbox_command(vha, mcp);
  568. fwopts[0] = mcp->mb[0];
  569. if (rval != QLA_SUCCESS) {
  570. /*EMPTY*/
  571. ql_dbg(ql_dbg_mbx, vha, 0x1030,
  572. "Failed=%x (%x/%x).\n", rval, mcp->mb[0], mcp->mb[1]);
  573. } else {
  574. /*EMPTY*/
  575. ql_dbg(ql_dbg_mbx, vha, 0x1031, "Done %s.\n", __func__);
  576. }
  577. return rval;
  578. }
  579. /*
  580. * qla2x00_mbx_reg_test
  581. * Mailbox register wrap test.
  582. *
  583. * Input:
  584. * ha = adapter block pointer.
  585. * TARGET_QUEUE_LOCK must be released.
  586. * ADAPTER_STATE_LOCK must be released.
  587. *
  588. * Returns:
  589. * qla2x00 local function return status code.
  590. *
  591. * Context:
  592. * Kernel context.
  593. */
  594. int
  595. qla2x00_mbx_reg_test(scsi_qla_host_t *vha)
  596. {
  597. int rval;
  598. mbx_cmd_t mc;
  599. mbx_cmd_t *mcp = &mc;
  600. ql_dbg(ql_dbg_mbx, vha, 0x1032, "Entered %s.\n", __func__);
  601. mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST;
  602. mcp->mb[1] = 0xAAAA;
  603. mcp->mb[2] = 0x5555;
  604. mcp->mb[3] = 0xAA55;
  605. mcp->mb[4] = 0x55AA;
  606. mcp->mb[5] = 0xA5A5;
  607. mcp->mb[6] = 0x5A5A;
  608. mcp->mb[7] = 0x2525;
  609. mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  610. mcp->in_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  611. mcp->tov = MBX_TOV_SECONDS;
  612. mcp->flags = 0;
  613. rval = qla2x00_mailbox_command(vha, mcp);
  614. if (rval == QLA_SUCCESS) {
  615. if (mcp->mb[1] != 0xAAAA || mcp->mb[2] != 0x5555 ||
  616. mcp->mb[3] != 0xAA55 || mcp->mb[4] != 0x55AA)
  617. rval = QLA_FUNCTION_FAILED;
  618. if (mcp->mb[5] != 0xA5A5 || mcp->mb[6] != 0x5A5A ||
  619. mcp->mb[7] != 0x2525)
  620. rval = QLA_FUNCTION_FAILED;
  621. }
  622. if (rval != QLA_SUCCESS) {
  623. /*EMPTY*/
  624. ql_dbg(ql_dbg_mbx, vha, 0x1033, "Failed=%x.\n", rval);
  625. } else {
  626. /*EMPTY*/
  627. ql_dbg(ql_dbg_mbx, vha, 0x1034, "Done %s.\n", __func__);
  628. }
  629. return rval;
  630. }
  631. /*
  632. * qla2x00_verify_checksum
  633. * Verify firmware checksum.
  634. *
  635. * Input:
  636. * ha = adapter block pointer.
  637. * TARGET_QUEUE_LOCK must be released.
  638. * ADAPTER_STATE_LOCK must be released.
  639. *
  640. * Returns:
  641. * qla2x00 local function return status code.
  642. *
  643. * Context:
  644. * Kernel context.
  645. */
  646. int
  647. qla2x00_verify_checksum(scsi_qla_host_t *vha, uint32_t risc_addr)
  648. {
  649. int rval;
  650. mbx_cmd_t mc;
  651. mbx_cmd_t *mcp = &mc;
  652. ql_dbg(ql_dbg_mbx, vha, 0x1035, "Entered %s.\n", __func__);
  653. mcp->mb[0] = MBC_VERIFY_CHECKSUM;
  654. mcp->out_mb = MBX_0;
  655. mcp->in_mb = MBX_0;
  656. if (IS_FWI2_CAPABLE(vha->hw)) {
  657. mcp->mb[1] = MSW(risc_addr);
  658. mcp->mb[2] = LSW(risc_addr);
  659. mcp->out_mb |= MBX_2|MBX_1;
  660. mcp->in_mb |= MBX_2|MBX_1;
  661. } else {
  662. mcp->mb[1] = LSW(risc_addr);
  663. mcp->out_mb |= MBX_1;
  664. mcp->in_mb |= MBX_1;
  665. }
  666. mcp->tov = MBX_TOV_SECONDS;
  667. mcp->flags = 0;
  668. rval = qla2x00_mailbox_command(vha, mcp);
  669. if (rval != QLA_SUCCESS) {
  670. ql_dbg(ql_dbg_mbx, vha, 0x1036,
  671. "Failed=%x chm sum=%x.\n", rval, IS_FWI2_CAPABLE(vha->hw) ?
  672. (mcp->mb[2] << 16) | mcp->mb[1] : mcp->mb[1]);
  673. } else {
  674. ql_dbg(ql_dbg_mbx, vha, 0x1037, "Done %s.\n", __func__);
  675. }
  676. return rval;
  677. }
  678. /*
  679. * qla2x00_issue_iocb
  680. * Issue IOCB using mailbox command
  681. *
  682. * Input:
  683. * ha = adapter state pointer.
  684. * buffer = buffer pointer.
  685. * phys_addr = physical address of buffer.
  686. * size = size of buffer.
  687. * TARGET_QUEUE_LOCK must be released.
  688. * ADAPTER_STATE_LOCK must be released.
  689. *
  690. * Returns:
  691. * qla2x00 local function return status code.
  692. *
  693. * Context:
  694. * Kernel context.
  695. */
  696. int
  697. qla2x00_issue_iocb_timeout(scsi_qla_host_t *vha, void *buffer,
  698. dma_addr_t phys_addr, size_t size, uint32_t tov)
  699. {
  700. int rval;
  701. mbx_cmd_t mc;
  702. mbx_cmd_t *mcp = &mc;
  703. ql_dbg(ql_dbg_mbx, vha, 0x1038, "Entered %s.\n", __func__);
  704. mcp->mb[0] = MBC_IOCB_COMMAND_A64;
  705. mcp->mb[1] = 0;
  706. mcp->mb[2] = MSW(phys_addr);
  707. mcp->mb[3] = LSW(phys_addr);
  708. mcp->mb[6] = MSW(MSD(phys_addr));
  709. mcp->mb[7] = LSW(MSD(phys_addr));
  710. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  711. mcp->in_mb = MBX_2|MBX_0;
  712. mcp->tov = tov;
  713. mcp->flags = 0;
  714. rval = qla2x00_mailbox_command(vha, mcp);
  715. if (rval != QLA_SUCCESS) {
  716. /*EMPTY*/
  717. ql_dbg(ql_dbg_mbx, vha, 0x1039, "Failed=%x.\n", rval);
  718. } else {
  719. sts_entry_t *sts_entry = (sts_entry_t *) buffer;
  720. /* Mask reserved bits. */
  721. sts_entry->entry_status &=
  722. IS_FWI2_CAPABLE(vha->hw) ? RF_MASK_24XX : RF_MASK;
  723. ql_dbg(ql_dbg_mbx, vha, 0x103a, "Done %s.\n", __func__);
  724. }
  725. return rval;
  726. }
  727. int
  728. qla2x00_issue_iocb(scsi_qla_host_t *vha, void *buffer, dma_addr_t phys_addr,
  729. size_t size)
  730. {
  731. return qla2x00_issue_iocb_timeout(vha, buffer, phys_addr, size,
  732. MBX_TOV_SECONDS);
  733. }
  734. /*
  735. * qla2x00_abort_command
  736. * Abort command aborts a specified IOCB.
  737. *
  738. * Input:
  739. * ha = adapter block pointer.
  740. * sp = SB structure pointer.
  741. *
  742. * Returns:
  743. * qla2x00 local function return status code.
  744. *
  745. * Context:
  746. * Kernel context.
  747. */
  748. int
  749. qla2x00_abort_command(srb_t *sp)
  750. {
  751. unsigned long flags = 0;
  752. int rval;
  753. uint32_t handle = 0;
  754. mbx_cmd_t mc;
  755. mbx_cmd_t *mcp = &mc;
  756. fc_port_t *fcport = sp->fcport;
  757. scsi_qla_host_t *vha = fcport->vha;
  758. struct qla_hw_data *ha = vha->hw;
  759. struct req_que *req = vha->req;
  760. ql_dbg(ql_dbg_mbx, vha, 0x103b, "Entered %s.\n", __func__);
  761. spin_lock_irqsave(&ha->hardware_lock, flags);
  762. for (handle = 1; handle < MAX_OUTSTANDING_COMMANDS; handle++) {
  763. if (req->outstanding_cmds[handle] == sp)
  764. break;
  765. }
  766. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  767. if (handle == MAX_OUTSTANDING_COMMANDS) {
  768. /* command not found */
  769. return QLA_FUNCTION_FAILED;
  770. }
  771. mcp->mb[0] = MBC_ABORT_COMMAND;
  772. if (HAS_EXTENDED_IDS(ha))
  773. mcp->mb[1] = fcport->loop_id;
  774. else
  775. mcp->mb[1] = fcport->loop_id << 8;
  776. mcp->mb[2] = (uint16_t)handle;
  777. mcp->mb[3] = (uint16_t)(handle >> 16);
  778. mcp->mb[6] = (uint16_t)sp->cmd->device->lun;
  779. mcp->out_mb = MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  780. mcp->in_mb = MBX_0;
  781. mcp->tov = MBX_TOV_SECONDS;
  782. mcp->flags = 0;
  783. rval = qla2x00_mailbox_command(vha, mcp);
  784. if (rval != QLA_SUCCESS) {
  785. ql_dbg(ql_dbg_mbx, vha, 0x103c, "Failed=%x.\n", rval);
  786. } else {
  787. ql_dbg(ql_dbg_mbx, vha, 0x103d, "Done %s.\n", __func__);
  788. }
  789. return rval;
  790. }
  791. int
  792. qla2x00_abort_target(struct fc_port *fcport, unsigned int l, int tag)
  793. {
  794. int rval, rval2;
  795. mbx_cmd_t mc;
  796. mbx_cmd_t *mcp = &mc;
  797. scsi_qla_host_t *vha;
  798. struct req_que *req;
  799. struct rsp_que *rsp;
  800. l = l;
  801. vha = fcport->vha;
  802. ql_dbg(ql_dbg_mbx, vha, 0x103e, "Entered %s.\n", __func__);
  803. req = vha->hw->req_q_map[0];
  804. rsp = req->rsp;
  805. mcp->mb[0] = MBC_ABORT_TARGET;
  806. mcp->out_mb = MBX_9|MBX_2|MBX_1|MBX_0;
  807. if (HAS_EXTENDED_IDS(vha->hw)) {
  808. mcp->mb[1] = fcport->loop_id;
  809. mcp->mb[10] = 0;
  810. mcp->out_mb |= MBX_10;
  811. } else {
  812. mcp->mb[1] = fcport->loop_id << 8;
  813. }
  814. mcp->mb[2] = vha->hw->loop_reset_delay;
  815. mcp->mb[9] = vha->vp_idx;
  816. mcp->in_mb = MBX_0;
  817. mcp->tov = MBX_TOV_SECONDS;
  818. mcp->flags = 0;
  819. rval = qla2x00_mailbox_command(vha, mcp);
  820. if (rval != QLA_SUCCESS) {
  821. ql_dbg(ql_dbg_mbx, vha, 0x103f, "Failed=%x.\n", rval);
  822. }
  823. /* Issue marker IOCB. */
  824. rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, 0,
  825. MK_SYNC_ID);
  826. if (rval2 != QLA_SUCCESS) {
  827. ql_dbg(ql_dbg_mbx, vha, 0x1040,
  828. "Failed to issue marker IOCB (%x).\n", rval2);
  829. } else {
  830. ql_dbg(ql_dbg_mbx, vha, 0x1041, "Done %s.\n", __func__);
  831. }
  832. return rval;
  833. }
  834. int
  835. qla2x00_lun_reset(struct fc_port *fcport, unsigned int l, int tag)
  836. {
  837. int rval, rval2;
  838. mbx_cmd_t mc;
  839. mbx_cmd_t *mcp = &mc;
  840. scsi_qla_host_t *vha;
  841. struct req_que *req;
  842. struct rsp_que *rsp;
  843. vha = fcport->vha;
  844. ql_dbg(ql_dbg_mbx, vha, 0x1042, "Entered %s.\n", __func__);
  845. req = vha->hw->req_q_map[0];
  846. rsp = req->rsp;
  847. mcp->mb[0] = MBC_LUN_RESET;
  848. mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
  849. if (HAS_EXTENDED_IDS(vha->hw))
  850. mcp->mb[1] = fcport->loop_id;
  851. else
  852. mcp->mb[1] = fcport->loop_id << 8;
  853. mcp->mb[2] = l;
  854. mcp->mb[3] = 0;
  855. mcp->mb[9] = vha->vp_idx;
  856. mcp->in_mb = MBX_0;
  857. mcp->tov = MBX_TOV_SECONDS;
  858. mcp->flags = 0;
  859. rval = qla2x00_mailbox_command(vha, mcp);
  860. if (rval != QLA_SUCCESS) {
  861. ql_dbg(ql_dbg_mbx, vha, 0x1043, "Failed=%x.\n", rval);
  862. }
  863. /* Issue marker IOCB. */
  864. rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
  865. MK_SYNC_ID_LUN);
  866. if (rval2 != QLA_SUCCESS) {
  867. ql_dbg(ql_dbg_mbx, vha, 0x1044,
  868. "Failed to issue marker IOCB (%x).\n", rval2);
  869. } else {
  870. ql_dbg(ql_dbg_mbx, vha, 0x1045, "Done %s.\n", __func__);
  871. }
  872. return rval;
  873. }
  874. /*
  875. * qla2x00_get_adapter_id
  876. * Get adapter ID and topology.
  877. *
  878. * Input:
  879. * ha = adapter block pointer.
  880. * id = pointer for loop ID.
  881. * al_pa = pointer for AL_PA.
  882. * area = pointer for area.
  883. * domain = pointer for domain.
  884. * top = pointer for topology.
  885. * TARGET_QUEUE_LOCK must be released.
  886. * ADAPTER_STATE_LOCK must be released.
  887. *
  888. * Returns:
  889. * qla2x00 local function return status code.
  890. *
  891. * Context:
  892. * Kernel context.
  893. */
  894. int
  895. qla2x00_get_adapter_id(scsi_qla_host_t *vha, uint16_t *id, uint8_t *al_pa,
  896. uint8_t *area, uint8_t *domain, uint16_t *top, uint16_t *sw_cap)
  897. {
  898. int rval;
  899. mbx_cmd_t mc;
  900. mbx_cmd_t *mcp = &mc;
  901. ql_dbg(ql_dbg_mbx, vha, 0x1046, "Entered %s.\n", __func__);
  902. mcp->mb[0] = MBC_GET_ADAPTER_LOOP_ID;
  903. mcp->mb[9] = vha->vp_idx;
  904. mcp->out_mb = MBX_9|MBX_0;
  905. mcp->in_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  906. if (IS_QLA8XXX_TYPE(vha->hw))
  907. mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10;
  908. mcp->tov = MBX_TOV_SECONDS;
  909. mcp->flags = 0;
  910. rval = qla2x00_mailbox_command(vha, mcp);
  911. if (mcp->mb[0] == MBS_COMMAND_ERROR)
  912. rval = QLA_COMMAND_ERROR;
  913. else if (mcp->mb[0] == MBS_INVALID_COMMAND)
  914. rval = QLA_INVALID_COMMAND;
  915. /* Return data. */
  916. *id = mcp->mb[1];
  917. *al_pa = LSB(mcp->mb[2]);
  918. *area = MSB(mcp->mb[2]);
  919. *domain = LSB(mcp->mb[3]);
  920. *top = mcp->mb[6];
  921. *sw_cap = mcp->mb[7];
  922. if (rval != QLA_SUCCESS) {
  923. /*EMPTY*/
  924. ql_dbg(ql_dbg_mbx, vha, 0x1047, "Failed=%x.\n", rval);
  925. } else {
  926. ql_dbg(ql_dbg_mbx, vha, 0x1048, "Done %s.\n", __func__);
  927. if (IS_QLA8XXX_TYPE(vha->hw)) {
  928. vha->fcoe_vlan_id = mcp->mb[9] & 0xfff;
  929. vha->fcoe_fcf_idx = mcp->mb[10];
  930. vha->fcoe_vn_port_mac[5] = mcp->mb[11] >> 8;
  931. vha->fcoe_vn_port_mac[4] = mcp->mb[11] & 0xff;
  932. vha->fcoe_vn_port_mac[3] = mcp->mb[12] >> 8;
  933. vha->fcoe_vn_port_mac[2] = mcp->mb[12] & 0xff;
  934. vha->fcoe_vn_port_mac[1] = mcp->mb[13] >> 8;
  935. vha->fcoe_vn_port_mac[0] = mcp->mb[13] & 0xff;
  936. }
  937. }
  938. return rval;
  939. }
  940. /*
  941. * qla2x00_get_retry_cnt
  942. * Get current firmware login retry count and delay.
  943. *
  944. * Input:
  945. * ha = adapter block pointer.
  946. * retry_cnt = pointer to login retry count.
  947. * tov = pointer to login timeout value.
  948. *
  949. * Returns:
  950. * qla2x00 local function return status code.
  951. *
  952. * Context:
  953. * Kernel context.
  954. */
  955. int
  956. qla2x00_get_retry_cnt(scsi_qla_host_t *vha, uint8_t *retry_cnt, uint8_t *tov,
  957. uint16_t *r_a_tov)
  958. {
  959. int rval;
  960. uint16_t ratov;
  961. mbx_cmd_t mc;
  962. mbx_cmd_t *mcp = &mc;
  963. ql_dbg(ql_dbg_mbx, vha, 0x1049, "Entered %s.\n", __func__);
  964. mcp->mb[0] = MBC_GET_RETRY_COUNT;
  965. mcp->out_mb = MBX_0;
  966. mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  967. mcp->tov = MBX_TOV_SECONDS;
  968. mcp->flags = 0;
  969. rval = qla2x00_mailbox_command(vha, mcp);
  970. if (rval != QLA_SUCCESS) {
  971. /*EMPTY*/
  972. ql_dbg(ql_dbg_mbx, vha, 0x104a,
  973. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  974. } else {
  975. /* Convert returned data and check our values. */
  976. *r_a_tov = mcp->mb[3] / 2;
  977. ratov = (mcp->mb[3]/2) / 10; /* mb[3] value is in 100ms */
  978. if (mcp->mb[1] * ratov > (*retry_cnt) * (*tov)) {
  979. /* Update to the larger values */
  980. *retry_cnt = (uint8_t)mcp->mb[1];
  981. *tov = ratov;
  982. }
  983. ql_dbg(ql_dbg_mbx, vha, 0x104b,
  984. "Done %s mb3=%d ratov=%d.\n", __func__, mcp->mb[3], ratov);
  985. }
  986. return rval;
  987. }
  988. /*
  989. * qla2x00_init_firmware
  990. * Initialize adapter firmware.
  991. *
  992. * Input:
  993. * ha = adapter block pointer.
  994. * dptr = Initialization control block pointer.
  995. * size = size of initialization control block.
  996. * TARGET_QUEUE_LOCK must be released.
  997. * ADAPTER_STATE_LOCK must be released.
  998. *
  999. * Returns:
  1000. * qla2x00 local function return status code.
  1001. *
  1002. * Context:
  1003. * Kernel context.
  1004. */
  1005. int
  1006. qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
  1007. {
  1008. int rval;
  1009. mbx_cmd_t mc;
  1010. mbx_cmd_t *mcp = &mc;
  1011. struct qla_hw_data *ha = vha->hw;
  1012. ql_dbg(ql_dbg_mbx, vha, 0x104c, "Entered %s.\n", __func__);
  1013. if (IS_QLA82XX(ha) && ql2xdbwr)
  1014. qla82xx_wr_32(ha, ha->nxdb_wr_ptr,
  1015. (0x04 | (ha->portnum << 5) | (0 << 8) | (0 << 16)));
  1016. if (ha->flags.npiv_supported)
  1017. mcp->mb[0] = MBC_MID_INITIALIZE_FIRMWARE;
  1018. else
  1019. mcp->mb[0] = MBC_INITIALIZE_FIRMWARE;
  1020. mcp->mb[1] = 0;
  1021. mcp->mb[2] = MSW(ha->init_cb_dma);
  1022. mcp->mb[3] = LSW(ha->init_cb_dma);
  1023. mcp->mb[6] = MSW(MSD(ha->init_cb_dma));
  1024. mcp->mb[7] = LSW(MSD(ha->init_cb_dma));
  1025. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  1026. if (IS_QLA81XX(ha) && ha->ex_init_cb->ex_version) {
  1027. mcp->mb[1] = BIT_0;
  1028. mcp->mb[10] = MSW(ha->ex_init_cb_dma);
  1029. mcp->mb[11] = LSW(ha->ex_init_cb_dma);
  1030. mcp->mb[12] = MSW(MSD(ha->ex_init_cb_dma));
  1031. mcp->mb[13] = LSW(MSD(ha->ex_init_cb_dma));
  1032. mcp->mb[14] = sizeof(*ha->ex_init_cb);
  1033. mcp->out_mb |= MBX_14|MBX_13|MBX_12|MBX_11|MBX_10;
  1034. }
  1035. mcp->in_mb = MBX_0;
  1036. mcp->buf_size = size;
  1037. mcp->flags = MBX_DMA_OUT;
  1038. mcp->tov = MBX_TOV_SECONDS;
  1039. rval = qla2x00_mailbox_command(vha, mcp);
  1040. if (rval != QLA_SUCCESS) {
  1041. /*EMPTY*/
  1042. ql_dbg(ql_dbg_mbx, vha, 0x104d,
  1043. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  1044. } else {
  1045. /*EMPTY*/
  1046. ql_dbg(ql_dbg_mbx, vha, 0x104e, "Done %s.\n", __func__);
  1047. }
  1048. return rval;
  1049. }
  1050. /*
  1051. * qla2x00_get_port_database
  1052. * Issue normal/enhanced get port database mailbox command
  1053. * and copy device name as necessary.
  1054. *
  1055. * Input:
  1056. * ha = adapter state pointer.
  1057. * dev = structure pointer.
  1058. * opt = enhanced cmd option byte.
  1059. *
  1060. * Returns:
  1061. * qla2x00 local function return status code.
  1062. *
  1063. * Context:
  1064. * Kernel context.
  1065. */
  1066. int
  1067. qla2x00_get_port_database(scsi_qla_host_t *vha, fc_port_t *fcport, uint8_t opt)
  1068. {
  1069. int rval;
  1070. mbx_cmd_t mc;
  1071. mbx_cmd_t *mcp = &mc;
  1072. port_database_t *pd;
  1073. struct port_database_24xx *pd24;
  1074. dma_addr_t pd_dma;
  1075. struct qla_hw_data *ha = vha->hw;
  1076. ql_dbg(ql_dbg_mbx, vha, 0x104f, "Entered %s.\n", __func__);
  1077. pd24 = NULL;
  1078. pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
  1079. if (pd == NULL) {
  1080. ql_log(ql_log_warn, vha, 0x1050,
  1081. "Failed to allocate port database structure.\n");
  1082. return QLA_MEMORY_ALLOC_FAILED;
  1083. }
  1084. memset(pd, 0, max(PORT_DATABASE_SIZE, PORT_DATABASE_24XX_SIZE));
  1085. mcp->mb[0] = MBC_GET_PORT_DATABASE;
  1086. if (opt != 0 && !IS_FWI2_CAPABLE(ha))
  1087. mcp->mb[0] = MBC_ENHANCED_GET_PORT_DATABASE;
  1088. mcp->mb[2] = MSW(pd_dma);
  1089. mcp->mb[3] = LSW(pd_dma);
  1090. mcp->mb[6] = MSW(MSD(pd_dma));
  1091. mcp->mb[7] = LSW(MSD(pd_dma));
  1092. mcp->mb[9] = vha->vp_idx;
  1093. mcp->out_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  1094. mcp->in_mb = MBX_0;
  1095. if (IS_FWI2_CAPABLE(ha)) {
  1096. mcp->mb[1] = fcport->loop_id;
  1097. mcp->mb[10] = opt;
  1098. mcp->out_mb |= MBX_10|MBX_1;
  1099. mcp->in_mb |= MBX_1;
  1100. } else if (HAS_EXTENDED_IDS(ha)) {
  1101. mcp->mb[1] = fcport->loop_id;
  1102. mcp->mb[10] = opt;
  1103. mcp->out_mb |= MBX_10|MBX_1;
  1104. } else {
  1105. mcp->mb[1] = fcport->loop_id << 8 | opt;
  1106. mcp->out_mb |= MBX_1;
  1107. }
  1108. mcp->buf_size = IS_FWI2_CAPABLE(ha) ?
  1109. PORT_DATABASE_24XX_SIZE : PORT_DATABASE_SIZE;
  1110. mcp->flags = MBX_DMA_IN;
  1111. mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
  1112. rval = qla2x00_mailbox_command(vha, mcp);
  1113. if (rval != QLA_SUCCESS)
  1114. goto gpd_error_out;
  1115. if (IS_FWI2_CAPABLE(ha)) {
  1116. pd24 = (struct port_database_24xx *) pd;
  1117. /* Check for logged in state. */
  1118. if (pd24->current_login_state != PDS_PRLI_COMPLETE &&
  1119. pd24->last_login_state != PDS_PRLI_COMPLETE) {
  1120. ql_dbg(ql_dbg_mbx, vha, 0x1051,
  1121. "Unable to verify login-state (%x/%x) for "
  1122. "loop_id %x.\n", pd24->current_login_state,
  1123. pd24->last_login_state, fcport->loop_id);
  1124. rval = QLA_FUNCTION_FAILED;
  1125. goto gpd_error_out;
  1126. }
  1127. /* Names are little-endian. */
  1128. memcpy(fcport->node_name, pd24->node_name, WWN_SIZE);
  1129. memcpy(fcport->port_name, pd24->port_name, WWN_SIZE);
  1130. /* Get port_id of device. */
  1131. fcport->d_id.b.domain = pd24->port_id[0];
  1132. fcport->d_id.b.area = pd24->port_id[1];
  1133. fcport->d_id.b.al_pa = pd24->port_id[2];
  1134. fcport->d_id.b.rsvd_1 = 0;
  1135. /* If not target must be initiator or unknown type. */
  1136. if ((pd24->prli_svc_param_word_3[0] & BIT_4) == 0)
  1137. fcport->port_type = FCT_INITIATOR;
  1138. else
  1139. fcport->port_type = FCT_TARGET;
  1140. } else {
  1141. /* Check for logged in state. */
  1142. if (pd->master_state != PD_STATE_PORT_LOGGED_IN &&
  1143. pd->slave_state != PD_STATE_PORT_LOGGED_IN) {
  1144. ql_dbg(ql_dbg_mbx, vha, 0x100a,
  1145. "Unable to verify login-state (%x/%x) - "
  1146. "portid=%02x%02x%02x.\n", pd->master_state,
  1147. pd->slave_state, fcport->d_id.b.domain,
  1148. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  1149. rval = QLA_FUNCTION_FAILED;
  1150. goto gpd_error_out;
  1151. }
  1152. /* Names are little-endian. */
  1153. memcpy(fcport->node_name, pd->node_name, WWN_SIZE);
  1154. memcpy(fcport->port_name, pd->port_name, WWN_SIZE);
  1155. /* Get port_id of device. */
  1156. fcport->d_id.b.domain = pd->port_id[0];
  1157. fcport->d_id.b.area = pd->port_id[3];
  1158. fcport->d_id.b.al_pa = pd->port_id[2];
  1159. fcport->d_id.b.rsvd_1 = 0;
  1160. /* If not target must be initiator or unknown type. */
  1161. if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
  1162. fcport->port_type = FCT_INITIATOR;
  1163. else
  1164. fcport->port_type = FCT_TARGET;
  1165. /* Passback COS information. */
  1166. fcport->supported_classes = (pd->options & BIT_4) ?
  1167. FC_COS_CLASS2: FC_COS_CLASS3;
  1168. }
  1169. gpd_error_out:
  1170. dma_pool_free(ha->s_dma_pool, pd, pd_dma);
  1171. if (rval != QLA_SUCCESS) {
  1172. ql_dbg(ql_dbg_mbx, vha, 0x1052,
  1173. "Failed=%x mb[0]=%x mb[1]=%x.\n", rval,
  1174. mcp->mb[0], mcp->mb[1]);
  1175. } else {
  1176. ql_dbg(ql_dbg_mbx, vha, 0x1053, "Done %s.\n", __func__);
  1177. }
  1178. return rval;
  1179. }
  1180. /*
  1181. * qla2x00_get_firmware_state
  1182. * Get adapter firmware state.
  1183. *
  1184. * Input:
  1185. * ha = adapter block pointer.
  1186. * dptr = pointer for firmware state.
  1187. * TARGET_QUEUE_LOCK must be released.
  1188. * ADAPTER_STATE_LOCK must be released.
  1189. *
  1190. * Returns:
  1191. * qla2x00 local function return status code.
  1192. *
  1193. * Context:
  1194. * Kernel context.
  1195. */
  1196. int
  1197. qla2x00_get_firmware_state(scsi_qla_host_t *vha, uint16_t *states)
  1198. {
  1199. int rval;
  1200. mbx_cmd_t mc;
  1201. mbx_cmd_t *mcp = &mc;
  1202. ql_dbg(ql_dbg_mbx, vha, 0x1054, "Entered %s.\n", __func__);
  1203. mcp->mb[0] = MBC_GET_FIRMWARE_STATE;
  1204. mcp->out_mb = MBX_0;
  1205. if (IS_FWI2_CAPABLE(vha->hw))
  1206. mcp->in_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  1207. else
  1208. mcp->in_mb = MBX_1|MBX_0;
  1209. mcp->tov = MBX_TOV_SECONDS;
  1210. mcp->flags = 0;
  1211. rval = qla2x00_mailbox_command(vha, mcp);
  1212. /* Return firmware states. */
  1213. states[0] = mcp->mb[1];
  1214. if (IS_FWI2_CAPABLE(vha->hw)) {
  1215. states[1] = mcp->mb[2];
  1216. states[2] = mcp->mb[3];
  1217. states[3] = mcp->mb[4];
  1218. states[4] = mcp->mb[5];
  1219. }
  1220. if (rval != QLA_SUCCESS) {
  1221. /*EMPTY*/
  1222. ql_dbg(ql_dbg_mbx, vha, 0x1055, "Failed=%x.\n", rval);
  1223. } else {
  1224. /*EMPTY*/
  1225. ql_dbg(ql_dbg_mbx, vha, 0x1056, "Done %s.\n", __func__);
  1226. }
  1227. return rval;
  1228. }
  1229. /*
  1230. * qla2x00_get_port_name
  1231. * Issue get port name mailbox command.
  1232. * Returned name is in big endian format.
  1233. *
  1234. * Input:
  1235. * ha = adapter block pointer.
  1236. * loop_id = loop ID of device.
  1237. * name = pointer for name.
  1238. * TARGET_QUEUE_LOCK must be released.
  1239. * ADAPTER_STATE_LOCK must be released.
  1240. *
  1241. * Returns:
  1242. * qla2x00 local function return status code.
  1243. *
  1244. * Context:
  1245. * Kernel context.
  1246. */
  1247. int
  1248. qla2x00_get_port_name(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t *name,
  1249. uint8_t opt)
  1250. {
  1251. int rval;
  1252. mbx_cmd_t mc;
  1253. mbx_cmd_t *mcp = &mc;
  1254. ql_dbg(ql_dbg_mbx, vha, 0x1057, "Entered %s.\n", __func__);
  1255. mcp->mb[0] = MBC_GET_PORT_NAME;
  1256. mcp->mb[9] = vha->vp_idx;
  1257. mcp->out_mb = MBX_9|MBX_1|MBX_0;
  1258. if (HAS_EXTENDED_IDS(vha->hw)) {
  1259. mcp->mb[1] = loop_id;
  1260. mcp->mb[10] = opt;
  1261. mcp->out_mb |= MBX_10;
  1262. } else {
  1263. mcp->mb[1] = loop_id << 8 | opt;
  1264. }
  1265. mcp->in_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  1266. mcp->tov = MBX_TOV_SECONDS;
  1267. mcp->flags = 0;
  1268. rval = qla2x00_mailbox_command(vha, mcp);
  1269. if (rval != QLA_SUCCESS) {
  1270. /*EMPTY*/
  1271. ql_dbg(ql_dbg_mbx, vha, 0x1058, "Failed=%x.\n", rval);
  1272. } else {
  1273. if (name != NULL) {
  1274. /* This function returns name in big endian. */
  1275. name[0] = MSB(mcp->mb[2]);
  1276. name[1] = LSB(mcp->mb[2]);
  1277. name[2] = MSB(mcp->mb[3]);
  1278. name[3] = LSB(mcp->mb[3]);
  1279. name[4] = MSB(mcp->mb[6]);
  1280. name[5] = LSB(mcp->mb[6]);
  1281. name[6] = MSB(mcp->mb[7]);
  1282. name[7] = LSB(mcp->mb[7]);
  1283. }
  1284. ql_dbg(ql_dbg_mbx, vha, 0x1059, "Done %s.\n", __func__);
  1285. }
  1286. return rval;
  1287. }
  1288. /*
  1289. * qla2x00_lip_reset
  1290. * Issue LIP reset mailbox command.
  1291. *
  1292. * Input:
  1293. * ha = adapter block pointer.
  1294. * TARGET_QUEUE_LOCK must be released.
  1295. * ADAPTER_STATE_LOCK must be released.
  1296. *
  1297. * Returns:
  1298. * qla2x00 local function return status code.
  1299. *
  1300. * Context:
  1301. * Kernel context.
  1302. */
  1303. int
  1304. qla2x00_lip_reset(scsi_qla_host_t *vha)
  1305. {
  1306. int rval;
  1307. mbx_cmd_t mc;
  1308. mbx_cmd_t *mcp = &mc;
  1309. ql_dbg(ql_dbg_mbx, vha, 0x105a, "Entered %s.\n", __func__);
  1310. if (IS_QLA8XXX_TYPE(vha->hw)) {
  1311. /* Logout across all FCFs. */
  1312. mcp->mb[0] = MBC_LIP_FULL_LOGIN;
  1313. mcp->mb[1] = BIT_1;
  1314. mcp->mb[2] = 0;
  1315. mcp->out_mb = MBX_2|MBX_1|MBX_0;
  1316. } else if (IS_FWI2_CAPABLE(vha->hw)) {
  1317. mcp->mb[0] = MBC_LIP_FULL_LOGIN;
  1318. mcp->mb[1] = BIT_6;
  1319. mcp->mb[2] = 0;
  1320. mcp->mb[3] = vha->hw->loop_reset_delay;
  1321. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1322. } else {
  1323. mcp->mb[0] = MBC_LIP_RESET;
  1324. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1325. if (HAS_EXTENDED_IDS(vha->hw)) {
  1326. mcp->mb[1] = 0x00ff;
  1327. mcp->mb[10] = 0;
  1328. mcp->out_mb |= MBX_10;
  1329. } else {
  1330. mcp->mb[1] = 0xff00;
  1331. }
  1332. mcp->mb[2] = vha->hw->loop_reset_delay;
  1333. mcp->mb[3] = 0;
  1334. }
  1335. mcp->in_mb = MBX_0;
  1336. mcp->tov = MBX_TOV_SECONDS;
  1337. mcp->flags = 0;
  1338. rval = qla2x00_mailbox_command(vha, mcp);
  1339. if (rval != QLA_SUCCESS) {
  1340. /*EMPTY*/
  1341. ql_dbg(ql_dbg_mbx, vha, 0x105b, "Failed=%x.\n", rval);
  1342. } else {
  1343. /*EMPTY*/
  1344. ql_dbg(ql_dbg_mbx, vha, 0x105c, "Done %s.\n", __func__);
  1345. }
  1346. return rval;
  1347. }
  1348. /*
  1349. * qla2x00_send_sns
  1350. * Send SNS command.
  1351. *
  1352. * Input:
  1353. * ha = adapter block pointer.
  1354. * sns = pointer for command.
  1355. * cmd_size = command size.
  1356. * buf_size = response/command size.
  1357. * TARGET_QUEUE_LOCK must be released.
  1358. * ADAPTER_STATE_LOCK must be released.
  1359. *
  1360. * Returns:
  1361. * qla2x00 local function return status code.
  1362. *
  1363. * Context:
  1364. * Kernel context.
  1365. */
  1366. int
  1367. qla2x00_send_sns(scsi_qla_host_t *vha, dma_addr_t sns_phys_address,
  1368. uint16_t cmd_size, size_t buf_size)
  1369. {
  1370. int rval;
  1371. mbx_cmd_t mc;
  1372. mbx_cmd_t *mcp = &mc;
  1373. ql_dbg(ql_dbg_mbx, vha, 0x105d, "Entered %s.\n", __func__);
  1374. ql_dbg(ql_dbg_mbx, vha, 0x105e,
  1375. "Retry cnt=%d ratov=%d total tov=%d.\n",
  1376. vha->hw->retry_count, vha->hw->login_timeout, mcp->tov);
  1377. mcp->mb[0] = MBC_SEND_SNS_COMMAND;
  1378. mcp->mb[1] = cmd_size;
  1379. mcp->mb[2] = MSW(sns_phys_address);
  1380. mcp->mb[3] = LSW(sns_phys_address);
  1381. mcp->mb[6] = MSW(MSD(sns_phys_address));
  1382. mcp->mb[7] = LSW(MSD(sns_phys_address));
  1383. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  1384. mcp->in_mb = MBX_0|MBX_1;
  1385. mcp->buf_size = buf_size;
  1386. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN;
  1387. mcp->tov = (vha->hw->login_timeout * 2) + (vha->hw->login_timeout / 2);
  1388. rval = qla2x00_mailbox_command(vha, mcp);
  1389. if (rval != QLA_SUCCESS) {
  1390. /*EMPTY*/
  1391. ql_dbg(ql_dbg_mbx, vha, 0x105f,
  1392. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  1393. rval, mcp->mb[0], mcp->mb[1]);
  1394. } else {
  1395. /*EMPTY*/
  1396. ql_dbg(ql_dbg_mbx, vha, 0x1060, "Done %s.\n", __func__);
  1397. }
  1398. return rval;
  1399. }
  1400. int
  1401. qla24xx_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
  1402. uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
  1403. {
  1404. int rval;
  1405. struct logio_entry_24xx *lg;
  1406. dma_addr_t lg_dma;
  1407. uint32_t iop[2];
  1408. struct qla_hw_data *ha = vha->hw;
  1409. struct req_que *req;
  1410. struct rsp_que *rsp;
  1411. ql_dbg(ql_dbg_mbx, vha, 0x1061, "Entered %s.\n", __func__);
  1412. if (ha->flags.cpu_affinity_enabled)
  1413. req = ha->req_q_map[0];
  1414. else
  1415. req = vha->req;
  1416. rsp = req->rsp;
  1417. lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
  1418. if (lg == NULL) {
  1419. ql_log(ql_log_warn, vha, 0x1062,
  1420. "Failed to allocate login IOCB.\n");
  1421. return QLA_MEMORY_ALLOC_FAILED;
  1422. }
  1423. memset(lg, 0, sizeof(struct logio_entry_24xx));
  1424. lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
  1425. lg->entry_count = 1;
  1426. lg->handle = MAKE_HANDLE(req->id, lg->handle);
  1427. lg->nport_handle = cpu_to_le16(loop_id);
  1428. lg->control_flags = __constant_cpu_to_le16(LCF_COMMAND_PLOGI);
  1429. if (opt & BIT_0)
  1430. lg->control_flags |= __constant_cpu_to_le16(LCF_COND_PLOGI);
  1431. if (opt & BIT_1)
  1432. lg->control_flags |= __constant_cpu_to_le16(LCF_SKIP_PRLI);
  1433. lg->port_id[0] = al_pa;
  1434. lg->port_id[1] = area;
  1435. lg->port_id[2] = domain;
  1436. lg->vp_index = vha->vp_idx;
  1437. rval = qla2x00_issue_iocb(vha, lg, lg_dma, 0);
  1438. if (rval != QLA_SUCCESS) {
  1439. ql_dbg(ql_dbg_mbx, vha, 0x1063,
  1440. "Failed to issue login IOCB (%x).\n", rval);
  1441. } else if (lg->entry_status != 0) {
  1442. ql_dbg(ql_dbg_mbx, vha, 0x1064,
  1443. "Failed to complete IOCB -- error status (%x).\n",
  1444. lg->entry_status);
  1445. rval = QLA_FUNCTION_FAILED;
  1446. } else if (lg->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
  1447. iop[0] = le32_to_cpu(lg->io_parameter[0]);
  1448. iop[1] = le32_to_cpu(lg->io_parameter[1]);
  1449. ql_dbg(ql_dbg_mbx, vha, 0x1065,
  1450. "Failed to complete IOCB -- completion status (%x) "
  1451. "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
  1452. iop[0], iop[1]);
  1453. switch (iop[0]) {
  1454. case LSC_SCODE_PORTID_USED:
  1455. mb[0] = MBS_PORT_ID_USED;
  1456. mb[1] = LSW(iop[1]);
  1457. break;
  1458. case LSC_SCODE_NPORT_USED:
  1459. mb[0] = MBS_LOOP_ID_USED;
  1460. break;
  1461. case LSC_SCODE_NOLINK:
  1462. case LSC_SCODE_NOIOCB:
  1463. case LSC_SCODE_NOXCB:
  1464. case LSC_SCODE_CMD_FAILED:
  1465. case LSC_SCODE_NOFABRIC:
  1466. case LSC_SCODE_FW_NOT_READY:
  1467. case LSC_SCODE_NOT_LOGGED_IN:
  1468. case LSC_SCODE_NOPCB:
  1469. case LSC_SCODE_ELS_REJECT:
  1470. case LSC_SCODE_CMD_PARAM_ERR:
  1471. case LSC_SCODE_NONPORT:
  1472. case LSC_SCODE_LOGGED_IN:
  1473. case LSC_SCODE_NOFLOGI_ACC:
  1474. default:
  1475. mb[0] = MBS_COMMAND_ERROR;
  1476. break;
  1477. }
  1478. } else {
  1479. ql_dbg(ql_dbg_mbx, vha, 0x1066, "Done %s.\n", __func__);
  1480. iop[0] = le32_to_cpu(lg->io_parameter[0]);
  1481. mb[0] = MBS_COMMAND_COMPLETE;
  1482. mb[1] = 0;
  1483. if (iop[0] & BIT_4) {
  1484. if (iop[0] & BIT_8)
  1485. mb[1] |= BIT_1;
  1486. } else
  1487. mb[1] = BIT_0;
  1488. /* Passback COS information. */
  1489. mb[10] = 0;
  1490. if (lg->io_parameter[7] || lg->io_parameter[8])
  1491. mb[10] |= BIT_0; /* Class 2. */
  1492. if (lg->io_parameter[9] || lg->io_parameter[10])
  1493. mb[10] |= BIT_1; /* Class 3. */
  1494. }
  1495. dma_pool_free(ha->s_dma_pool, lg, lg_dma);
  1496. return rval;
  1497. }
  1498. /*
  1499. * qla2x00_login_fabric
  1500. * Issue login fabric port mailbox command.
  1501. *
  1502. * Input:
  1503. * ha = adapter block pointer.
  1504. * loop_id = device loop ID.
  1505. * domain = device domain.
  1506. * area = device area.
  1507. * al_pa = device AL_PA.
  1508. * status = pointer for return status.
  1509. * opt = command options.
  1510. * TARGET_QUEUE_LOCK must be released.
  1511. * ADAPTER_STATE_LOCK must be released.
  1512. *
  1513. * Returns:
  1514. * qla2x00 local function return status code.
  1515. *
  1516. * Context:
  1517. * Kernel context.
  1518. */
  1519. int
  1520. qla2x00_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
  1521. uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
  1522. {
  1523. int rval;
  1524. mbx_cmd_t mc;
  1525. mbx_cmd_t *mcp = &mc;
  1526. struct qla_hw_data *ha = vha->hw;
  1527. ql_dbg(ql_dbg_mbx, vha, 0x1067, "Entered %s.\n", __func__);
  1528. mcp->mb[0] = MBC_LOGIN_FABRIC_PORT;
  1529. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1530. if (HAS_EXTENDED_IDS(ha)) {
  1531. mcp->mb[1] = loop_id;
  1532. mcp->mb[10] = opt;
  1533. mcp->out_mb |= MBX_10;
  1534. } else {
  1535. mcp->mb[1] = (loop_id << 8) | opt;
  1536. }
  1537. mcp->mb[2] = domain;
  1538. mcp->mb[3] = area << 8 | al_pa;
  1539. mcp->in_mb = MBX_7|MBX_6|MBX_2|MBX_1|MBX_0;
  1540. mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
  1541. mcp->flags = 0;
  1542. rval = qla2x00_mailbox_command(vha, mcp);
  1543. /* Return mailbox statuses. */
  1544. if (mb != NULL) {
  1545. mb[0] = mcp->mb[0];
  1546. mb[1] = mcp->mb[1];
  1547. mb[2] = mcp->mb[2];
  1548. mb[6] = mcp->mb[6];
  1549. mb[7] = mcp->mb[7];
  1550. /* COS retrieved from Get-Port-Database mailbox command. */
  1551. mb[10] = 0;
  1552. }
  1553. if (rval != QLA_SUCCESS) {
  1554. /* RLU tmp code: need to change main mailbox_command function to
  1555. * return ok even when the mailbox completion value is not
  1556. * SUCCESS. The caller needs to be responsible to interpret
  1557. * the return values of this mailbox command if we're not
  1558. * to change too much of the existing code.
  1559. */
  1560. if (mcp->mb[0] == 0x4001 || mcp->mb[0] == 0x4002 ||
  1561. mcp->mb[0] == 0x4003 || mcp->mb[0] == 0x4005 ||
  1562. mcp->mb[0] == 0x4006)
  1563. rval = QLA_SUCCESS;
  1564. /*EMPTY*/
  1565. ql_dbg(ql_dbg_mbx, vha, 0x1068,
  1566. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
  1567. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
  1568. } else {
  1569. /*EMPTY*/
  1570. ql_dbg(ql_dbg_mbx, vha, 0x1069, "Done %s.\n", __func__);
  1571. }
  1572. return rval;
  1573. }
  1574. /*
  1575. * qla2x00_login_local_device
  1576. * Issue login loop port mailbox command.
  1577. *
  1578. * Input:
  1579. * ha = adapter block pointer.
  1580. * loop_id = device loop ID.
  1581. * opt = command options.
  1582. *
  1583. * Returns:
  1584. * Return status code.
  1585. *
  1586. * Context:
  1587. * Kernel context.
  1588. *
  1589. */
  1590. int
  1591. qla2x00_login_local_device(scsi_qla_host_t *vha, fc_port_t *fcport,
  1592. uint16_t *mb_ret, uint8_t opt)
  1593. {
  1594. int rval;
  1595. mbx_cmd_t mc;
  1596. mbx_cmd_t *mcp = &mc;
  1597. struct qla_hw_data *ha = vha->hw;
  1598. ql_dbg(ql_dbg_mbx, vha, 0x106a, "Entered %s.\n", __func__);
  1599. if (IS_FWI2_CAPABLE(ha))
  1600. return qla24xx_login_fabric(vha, fcport->loop_id,
  1601. fcport->d_id.b.domain, fcport->d_id.b.area,
  1602. fcport->d_id.b.al_pa, mb_ret, opt);
  1603. mcp->mb[0] = MBC_LOGIN_LOOP_PORT;
  1604. if (HAS_EXTENDED_IDS(ha))
  1605. mcp->mb[1] = fcport->loop_id;
  1606. else
  1607. mcp->mb[1] = fcport->loop_id << 8;
  1608. mcp->mb[2] = opt;
  1609. mcp->out_mb = MBX_2|MBX_1|MBX_0;
  1610. mcp->in_mb = MBX_7|MBX_6|MBX_1|MBX_0;
  1611. mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
  1612. mcp->flags = 0;
  1613. rval = qla2x00_mailbox_command(vha, mcp);
  1614. /* Return mailbox statuses. */
  1615. if (mb_ret != NULL) {
  1616. mb_ret[0] = mcp->mb[0];
  1617. mb_ret[1] = mcp->mb[1];
  1618. mb_ret[6] = mcp->mb[6];
  1619. mb_ret[7] = mcp->mb[7];
  1620. }
  1621. if (rval != QLA_SUCCESS) {
  1622. /* AV tmp code: need to change main mailbox_command function to
  1623. * return ok even when the mailbox completion value is not
  1624. * SUCCESS. The caller needs to be responsible to interpret
  1625. * the return values of this mailbox command if we're not
  1626. * to change too much of the existing code.
  1627. */
  1628. if (mcp->mb[0] == 0x4005 || mcp->mb[0] == 0x4006)
  1629. rval = QLA_SUCCESS;
  1630. ql_dbg(ql_dbg_mbx, vha, 0x106b,
  1631. "Failed=%x mb[0]=%x mb[1]=%x mb[6]=%x mb[7]=%x.\n",
  1632. rval, mcp->mb[0], mcp->mb[1], mcp->mb[6], mcp->mb[7]);
  1633. } else {
  1634. /*EMPTY*/
  1635. ql_dbg(ql_dbg_mbx, vha, 0x106c, "Done %s.\n", __func__);
  1636. }
  1637. return (rval);
  1638. }
  1639. int
  1640. qla24xx_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
  1641. uint8_t area, uint8_t al_pa)
  1642. {
  1643. int rval;
  1644. struct logio_entry_24xx *lg;
  1645. dma_addr_t lg_dma;
  1646. struct qla_hw_data *ha = vha->hw;
  1647. struct req_que *req;
  1648. struct rsp_que *rsp;
  1649. ql_dbg(ql_dbg_mbx, vha, 0x106d, "Entered %s.\n", __func__);
  1650. lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
  1651. if (lg == NULL) {
  1652. ql_log(ql_log_warn, vha, 0x106e,
  1653. "Failed to allocate logout IOCB.\n");
  1654. return QLA_MEMORY_ALLOC_FAILED;
  1655. }
  1656. memset(lg, 0, sizeof(struct logio_entry_24xx));
  1657. if (ql2xmaxqueues > 1)
  1658. req = ha->req_q_map[0];
  1659. else
  1660. req = vha->req;
  1661. rsp = req->rsp;
  1662. lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
  1663. lg->entry_count = 1;
  1664. lg->handle = MAKE_HANDLE(req->id, lg->handle);
  1665. lg->nport_handle = cpu_to_le16(loop_id);
  1666. lg->control_flags =
  1667. __constant_cpu_to_le16(LCF_COMMAND_LOGO|LCF_IMPL_LOGO|
  1668. LCF_FREE_NPORT);
  1669. lg->port_id[0] = al_pa;
  1670. lg->port_id[1] = area;
  1671. lg->port_id[2] = domain;
  1672. lg->vp_index = vha->vp_idx;
  1673. rval = qla2x00_issue_iocb(vha, lg, lg_dma, 0);
  1674. if (rval != QLA_SUCCESS) {
  1675. ql_dbg(ql_dbg_mbx, vha, 0x106f,
  1676. "Failed to issue logout IOCB (%x).\n", rval);
  1677. } else if (lg->entry_status != 0) {
  1678. ql_dbg(ql_dbg_mbx, vha, 0x1070,
  1679. "Failed to complete IOCB -- error status (%x).\n",
  1680. lg->entry_status);
  1681. rval = QLA_FUNCTION_FAILED;
  1682. } else if (lg->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
  1683. ql_dbg(ql_dbg_mbx, vha, 0x1071,
  1684. "Failed to complete IOCB -- completion status (%x) "
  1685. "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
  1686. le32_to_cpu(lg->io_parameter[0]),
  1687. le32_to_cpu(lg->io_parameter[1]));
  1688. } else {
  1689. /*EMPTY*/
  1690. ql_dbg(ql_dbg_mbx, vha, 0x1072, "Done %s.\n", __func__);
  1691. }
  1692. dma_pool_free(ha->s_dma_pool, lg, lg_dma);
  1693. return rval;
  1694. }
  1695. /*
  1696. * qla2x00_fabric_logout
  1697. * Issue logout fabric port mailbox command.
  1698. *
  1699. * Input:
  1700. * ha = adapter block pointer.
  1701. * loop_id = device loop ID.
  1702. * TARGET_QUEUE_LOCK must be released.
  1703. * ADAPTER_STATE_LOCK must be released.
  1704. *
  1705. * Returns:
  1706. * qla2x00 local function return status code.
  1707. *
  1708. * Context:
  1709. * Kernel context.
  1710. */
  1711. int
  1712. qla2x00_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
  1713. uint8_t area, uint8_t al_pa)
  1714. {
  1715. int rval;
  1716. mbx_cmd_t mc;
  1717. mbx_cmd_t *mcp = &mc;
  1718. ql_dbg(ql_dbg_mbx, vha, 0x1073, "Entered %s.\n", __func__);
  1719. mcp->mb[0] = MBC_LOGOUT_FABRIC_PORT;
  1720. mcp->out_mb = MBX_1|MBX_0;
  1721. if (HAS_EXTENDED_IDS(vha->hw)) {
  1722. mcp->mb[1] = loop_id;
  1723. mcp->mb[10] = 0;
  1724. mcp->out_mb |= MBX_10;
  1725. } else {
  1726. mcp->mb[1] = loop_id << 8;
  1727. }
  1728. mcp->in_mb = MBX_1|MBX_0;
  1729. mcp->tov = MBX_TOV_SECONDS;
  1730. mcp->flags = 0;
  1731. rval = qla2x00_mailbox_command(vha, mcp);
  1732. if (rval != QLA_SUCCESS) {
  1733. /*EMPTY*/
  1734. ql_dbg(ql_dbg_mbx, vha, 0x1074,
  1735. "Failed=%x mb[1]=%x.\n", rval, mcp->mb[1]);
  1736. } else {
  1737. /*EMPTY*/
  1738. ql_dbg(ql_dbg_mbx, vha, 0x1075, "Done %s.\n", __func__);
  1739. }
  1740. return rval;
  1741. }
  1742. /*
  1743. * qla2x00_full_login_lip
  1744. * Issue full login LIP mailbox command.
  1745. *
  1746. * Input:
  1747. * ha = adapter block pointer.
  1748. * TARGET_QUEUE_LOCK must be released.
  1749. * ADAPTER_STATE_LOCK must be released.
  1750. *
  1751. * Returns:
  1752. * qla2x00 local function return status code.
  1753. *
  1754. * Context:
  1755. * Kernel context.
  1756. */
  1757. int
  1758. qla2x00_full_login_lip(scsi_qla_host_t *vha)
  1759. {
  1760. int rval;
  1761. mbx_cmd_t mc;
  1762. mbx_cmd_t *mcp = &mc;
  1763. ql_dbg(ql_dbg_mbx, vha, 0x1076, "Entered %s.\n", __func__);
  1764. mcp->mb[0] = MBC_LIP_FULL_LOGIN;
  1765. mcp->mb[1] = IS_FWI2_CAPABLE(vha->hw) ? BIT_3 : 0;
  1766. mcp->mb[2] = 0;
  1767. mcp->mb[3] = 0;
  1768. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1769. mcp->in_mb = MBX_0;
  1770. mcp->tov = MBX_TOV_SECONDS;
  1771. mcp->flags = 0;
  1772. rval = qla2x00_mailbox_command(vha, mcp);
  1773. if (rval != QLA_SUCCESS) {
  1774. /*EMPTY*/
  1775. ql_dbg(ql_dbg_mbx, vha, 0x1077, "Failed=%x.\n", rval);
  1776. } else {
  1777. /*EMPTY*/
  1778. ql_dbg(ql_dbg_mbx, vha, 0x1078, "Done %s.\n", __func__);
  1779. }
  1780. return rval;
  1781. }
  1782. /*
  1783. * qla2x00_get_id_list
  1784. *
  1785. * Input:
  1786. * ha = adapter block pointer.
  1787. *
  1788. * Returns:
  1789. * qla2x00 local function return status code.
  1790. *
  1791. * Context:
  1792. * Kernel context.
  1793. */
  1794. int
  1795. qla2x00_get_id_list(scsi_qla_host_t *vha, void *id_list, dma_addr_t id_list_dma,
  1796. uint16_t *entries)
  1797. {
  1798. int rval;
  1799. mbx_cmd_t mc;
  1800. mbx_cmd_t *mcp = &mc;
  1801. ql_dbg(ql_dbg_mbx, vha, 0x1079, "Entered %s.\n", __func__);
  1802. if (id_list == NULL)
  1803. return QLA_FUNCTION_FAILED;
  1804. mcp->mb[0] = MBC_GET_ID_LIST;
  1805. mcp->out_mb = MBX_0;
  1806. if (IS_FWI2_CAPABLE(vha->hw)) {
  1807. mcp->mb[2] = MSW(id_list_dma);
  1808. mcp->mb[3] = LSW(id_list_dma);
  1809. mcp->mb[6] = MSW(MSD(id_list_dma));
  1810. mcp->mb[7] = LSW(MSD(id_list_dma));
  1811. mcp->mb[8] = 0;
  1812. mcp->mb[9] = vha->vp_idx;
  1813. mcp->out_mb |= MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2;
  1814. } else {
  1815. mcp->mb[1] = MSW(id_list_dma);
  1816. mcp->mb[2] = LSW(id_list_dma);
  1817. mcp->mb[3] = MSW(MSD(id_list_dma));
  1818. mcp->mb[6] = LSW(MSD(id_list_dma));
  1819. mcp->out_mb |= MBX_6|MBX_3|MBX_2|MBX_1;
  1820. }
  1821. mcp->in_mb = MBX_1|MBX_0;
  1822. mcp->tov = MBX_TOV_SECONDS;
  1823. mcp->flags = 0;
  1824. rval = qla2x00_mailbox_command(vha, mcp);
  1825. if (rval != QLA_SUCCESS) {
  1826. /*EMPTY*/
  1827. ql_dbg(ql_dbg_mbx, vha, 0x107a, "Failed=%x.\n", rval);
  1828. } else {
  1829. *entries = mcp->mb[1];
  1830. ql_dbg(ql_dbg_mbx, vha, 0x107b, "Done %s.\n", __func__);
  1831. }
  1832. return rval;
  1833. }
  1834. /*
  1835. * qla2x00_get_resource_cnts
  1836. * Get current firmware resource counts.
  1837. *
  1838. * Input:
  1839. * ha = adapter block pointer.
  1840. *
  1841. * Returns:
  1842. * qla2x00 local function return status code.
  1843. *
  1844. * Context:
  1845. * Kernel context.
  1846. */
  1847. int
  1848. qla2x00_get_resource_cnts(scsi_qla_host_t *vha, uint16_t *cur_xchg_cnt,
  1849. uint16_t *orig_xchg_cnt, uint16_t *cur_iocb_cnt,
  1850. uint16_t *orig_iocb_cnt, uint16_t *max_npiv_vports, uint16_t *max_fcfs)
  1851. {
  1852. int rval;
  1853. mbx_cmd_t mc;
  1854. mbx_cmd_t *mcp = &mc;
  1855. ql_dbg(ql_dbg_mbx, vha, 0x107c, "Entered %s.\n", __func__);
  1856. mcp->mb[0] = MBC_GET_RESOURCE_COUNTS;
  1857. mcp->out_mb = MBX_0;
  1858. mcp->in_mb = MBX_11|MBX_10|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  1859. if (IS_QLA81XX(vha->hw))
  1860. mcp->in_mb |= MBX_12;
  1861. mcp->tov = MBX_TOV_SECONDS;
  1862. mcp->flags = 0;
  1863. rval = qla2x00_mailbox_command(vha, mcp);
  1864. if (rval != QLA_SUCCESS) {
  1865. /*EMPTY*/
  1866. ql_dbg(ql_dbg_mbx, vha, 0x107d,
  1867. "Failed mb[0]=%x.\n", mcp->mb[0]);
  1868. } else {
  1869. ql_dbg(ql_dbg_mbx, vha, 0x107e,
  1870. "Done %s mb1=%x mb2=%x mb3=%x mb6=%x mb7=%x mb10=%x "
  1871. "mb11=%x mb12=%x.\n", __func__, mcp->mb[1], mcp->mb[2],
  1872. mcp->mb[3], mcp->mb[6], mcp->mb[7], mcp->mb[10],
  1873. mcp->mb[11], mcp->mb[12]);
  1874. if (cur_xchg_cnt)
  1875. *cur_xchg_cnt = mcp->mb[3];
  1876. if (orig_xchg_cnt)
  1877. *orig_xchg_cnt = mcp->mb[6];
  1878. if (cur_iocb_cnt)
  1879. *cur_iocb_cnt = mcp->mb[7];
  1880. if (orig_iocb_cnt)
  1881. *orig_iocb_cnt = mcp->mb[10];
  1882. if (vha->hw->flags.npiv_supported && max_npiv_vports)
  1883. *max_npiv_vports = mcp->mb[11];
  1884. if (IS_QLA81XX(vha->hw) && max_fcfs)
  1885. *max_fcfs = mcp->mb[12];
  1886. }
  1887. return (rval);
  1888. }
  1889. /*
  1890. * qla2x00_get_fcal_position_map
  1891. * Get FCAL (LILP) position map using mailbox command
  1892. *
  1893. * Input:
  1894. * ha = adapter state pointer.
  1895. * pos_map = buffer pointer (can be NULL).
  1896. *
  1897. * Returns:
  1898. * qla2x00 local function return status code.
  1899. *
  1900. * Context:
  1901. * Kernel context.
  1902. */
  1903. int
  1904. qla2x00_get_fcal_position_map(scsi_qla_host_t *vha, char *pos_map)
  1905. {
  1906. int rval;
  1907. mbx_cmd_t mc;
  1908. mbx_cmd_t *mcp = &mc;
  1909. char *pmap;
  1910. dma_addr_t pmap_dma;
  1911. struct qla_hw_data *ha = vha->hw;
  1912. ql_dbg(ql_dbg_mbx, vha, 0x107f, "Entered %s.\n", __func__);
  1913. pmap = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pmap_dma);
  1914. if (pmap == NULL) {
  1915. ql_log(ql_log_warn, vha, 0x1080,
  1916. "Memory alloc failed.\n");
  1917. return QLA_MEMORY_ALLOC_FAILED;
  1918. }
  1919. memset(pmap, 0, FCAL_MAP_SIZE);
  1920. mcp->mb[0] = MBC_GET_FC_AL_POSITION_MAP;
  1921. mcp->mb[2] = MSW(pmap_dma);
  1922. mcp->mb[3] = LSW(pmap_dma);
  1923. mcp->mb[6] = MSW(MSD(pmap_dma));
  1924. mcp->mb[7] = LSW(MSD(pmap_dma));
  1925. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  1926. mcp->in_mb = MBX_1|MBX_0;
  1927. mcp->buf_size = FCAL_MAP_SIZE;
  1928. mcp->flags = MBX_DMA_IN;
  1929. mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
  1930. rval = qla2x00_mailbox_command(vha, mcp);
  1931. if (rval == QLA_SUCCESS) {
  1932. ql_dbg(ql_dbg_mbx, vha, 0x1081,
  1933. "mb0/mb1=%x/%X FC/AL position map size (%x).\n",
  1934. mcp->mb[0], mcp->mb[1], (unsigned)pmap[0]);
  1935. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111d,
  1936. pmap, pmap[0] + 1);
  1937. if (pos_map)
  1938. memcpy(pos_map, pmap, FCAL_MAP_SIZE);
  1939. }
  1940. dma_pool_free(ha->s_dma_pool, pmap, pmap_dma);
  1941. if (rval != QLA_SUCCESS) {
  1942. ql_dbg(ql_dbg_mbx, vha, 0x1082, "Failed=%x.\n", rval);
  1943. } else {
  1944. ql_dbg(ql_dbg_mbx, vha, 0x1083, "Done %s.\n", __func__);
  1945. }
  1946. return rval;
  1947. }
  1948. /*
  1949. * qla2x00_get_link_status
  1950. *
  1951. * Input:
  1952. * ha = adapter block pointer.
  1953. * loop_id = device loop ID.
  1954. * ret_buf = pointer to link status return buffer.
  1955. *
  1956. * Returns:
  1957. * 0 = success.
  1958. * BIT_0 = mem alloc error.
  1959. * BIT_1 = mailbox error.
  1960. */
  1961. int
  1962. qla2x00_get_link_status(scsi_qla_host_t *vha, uint16_t loop_id,
  1963. struct link_statistics *stats, dma_addr_t stats_dma)
  1964. {
  1965. int rval;
  1966. mbx_cmd_t mc;
  1967. mbx_cmd_t *mcp = &mc;
  1968. uint32_t *siter, *diter, dwords;
  1969. struct qla_hw_data *ha = vha->hw;
  1970. ql_dbg(ql_dbg_mbx, vha, 0x1084, "Entered %s.\n", __func__);
  1971. mcp->mb[0] = MBC_GET_LINK_STATUS;
  1972. mcp->mb[2] = MSW(stats_dma);
  1973. mcp->mb[3] = LSW(stats_dma);
  1974. mcp->mb[6] = MSW(MSD(stats_dma));
  1975. mcp->mb[7] = LSW(MSD(stats_dma));
  1976. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  1977. mcp->in_mb = MBX_0;
  1978. if (IS_FWI2_CAPABLE(ha)) {
  1979. mcp->mb[1] = loop_id;
  1980. mcp->mb[4] = 0;
  1981. mcp->mb[10] = 0;
  1982. mcp->out_mb |= MBX_10|MBX_4|MBX_1;
  1983. mcp->in_mb |= MBX_1;
  1984. } else if (HAS_EXTENDED_IDS(ha)) {
  1985. mcp->mb[1] = loop_id;
  1986. mcp->mb[10] = 0;
  1987. mcp->out_mb |= MBX_10|MBX_1;
  1988. } else {
  1989. mcp->mb[1] = loop_id << 8;
  1990. mcp->out_mb |= MBX_1;
  1991. }
  1992. mcp->tov = MBX_TOV_SECONDS;
  1993. mcp->flags = IOCTL_CMD;
  1994. rval = qla2x00_mailbox_command(vha, mcp);
  1995. if (rval == QLA_SUCCESS) {
  1996. if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
  1997. ql_dbg(ql_dbg_mbx, vha, 0x1085,
  1998. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  1999. rval = QLA_FUNCTION_FAILED;
  2000. } else {
  2001. /* Copy over data -- firmware data is LE. */
  2002. ql_dbg(ql_dbg_mbx, vha, 0x1086, "Done %s.\n", __func__);
  2003. dwords = offsetof(struct link_statistics, unused1) / 4;
  2004. siter = diter = &stats->link_fail_cnt;
  2005. while (dwords--)
  2006. *diter++ = le32_to_cpu(*siter++);
  2007. }
  2008. } else {
  2009. /* Failed. */
  2010. ql_dbg(ql_dbg_mbx, vha, 0x1087, "Failed=%x.\n", rval);
  2011. }
  2012. return rval;
  2013. }
  2014. int
  2015. qla24xx_get_isp_stats(scsi_qla_host_t *vha, struct link_statistics *stats,
  2016. dma_addr_t stats_dma)
  2017. {
  2018. int rval;
  2019. mbx_cmd_t mc;
  2020. mbx_cmd_t *mcp = &mc;
  2021. uint32_t *siter, *diter, dwords;
  2022. ql_dbg(ql_dbg_mbx, vha, 0x1088, "Entered %s.\n", __func__);
  2023. mcp->mb[0] = MBC_GET_LINK_PRIV_STATS;
  2024. mcp->mb[2] = MSW(stats_dma);
  2025. mcp->mb[3] = LSW(stats_dma);
  2026. mcp->mb[6] = MSW(MSD(stats_dma));
  2027. mcp->mb[7] = LSW(MSD(stats_dma));
  2028. mcp->mb[8] = sizeof(struct link_statistics) / 4;
  2029. mcp->mb[9] = vha->vp_idx;
  2030. mcp->mb[10] = 0;
  2031. mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  2032. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  2033. mcp->tov = MBX_TOV_SECONDS;
  2034. mcp->flags = IOCTL_CMD;
  2035. rval = qla2x00_mailbox_command(vha, mcp);
  2036. if (rval == QLA_SUCCESS) {
  2037. if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
  2038. ql_dbg(ql_dbg_mbx, vha, 0x1089,
  2039. "Failed mb[0]=%x.\n", mcp->mb[0]);
  2040. rval = QLA_FUNCTION_FAILED;
  2041. } else {
  2042. ql_dbg(ql_dbg_mbx, vha, 0x108a, "Done %s.\n", __func__);
  2043. /* Copy over data -- firmware data is LE. */
  2044. dwords = sizeof(struct link_statistics) / 4;
  2045. siter = diter = &stats->link_fail_cnt;
  2046. while (dwords--)
  2047. *diter++ = le32_to_cpu(*siter++);
  2048. }
  2049. } else {
  2050. /* Failed. */
  2051. ql_dbg(ql_dbg_mbx, vha, 0x108b, "Failed=%x.\n", rval);
  2052. }
  2053. return rval;
  2054. }
  2055. int
  2056. qla24xx_abort_command(srb_t *sp)
  2057. {
  2058. int rval;
  2059. unsigned long flags = 0;
  2060. struct abort_entry_24xx *abt;
  2061. dma_addr_t abt_dma;
  2062. uint32_t handle;
  2063. fc_port_t *fcport = sp->fcport;
  2064. struct scsi_qla_host *vha = fcport->vha;
  2065. struct qla_hw_data *ha = vha->hw;
  2066. struct req_que *req = vha->req;
  2067. ql_dbg(ql_dbg_mbx, vha, 0x108c, "Entered %s.\n", __func__);
  2068. spin_lock_irqsave(&ha->hardware_lock, flags);
  2069. for (handle = 1; handle < MAX_OUTSTANDING_COMMANDS; handle++) {
  2070. if (req->outstanding_cmds[handle] == sp)
  2071. break;
  2072. }
  2073. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2074. if (handle == MAX_OUTSTANDING_COMMANDS) {
  2075. /* Command not found. */
  2076. return QLA_FUNCTION_FAILED;
  2077. }
  2078. abt = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &abt_dma);
  2079. if (abt == NULL) {
  2080. ql_log(ql_log_warn, vha, 0x108d,
  2081. "Failed to allocate abort IOCB.\n");
  2082. return QLA_MEMORY_ALLOC_FAILED;
  2083. }
  2084. memset(abt, 0, sizeof(struct abort_entry_24xx));
  2085. abt->entry_type = ABORT_IOCB_TYPE;
  2086. abt->entry_count = 1;
  2087. abt->handle = MAKE_HANDLE(req->id, abt->handle);
  2088. abt->nport_handle = cpu_to_le16(fcport->loop_id);
  2089. abt->handle_to_abort = MAKE_HANDLE(req->id, handle);
  2090. abt->port_id[0] = fcport->d_id.b.al_pa;
  2091. abt->port_id[1] = fcport->d_id.b.area;
  2092. abt->port_id[2] = fcport->d_id.b.domain;
  2093. abt->vp_index = fcport->vp_idx;
  2094. abt->req_que_no = cpu_to_le16(req->id);
  2095. rval = qla2x00_issue_iocb(vha, abt, abt_dma, 0);
  2096. if (rval != QLA_SUCCESS) {
  2097. ql_dbg(ql_dbg_mbx, vha, 0x108e,
  2098. "Failed to issue IOCB (%x).\n", rval);
  2099. } else if (abt->entry_status != 0) {
  2100. ql_dbg(ql_dbg_mbx, vha, 0x108f,
  2101. "Failed to complete IOCB -- error status (%x).\n",
  2102. abt->entry_status);
  2103. rval = QLA_FUNCTION_FAILED;
  2104. } else if (abt->nport_handle != __constant_cpu_to_le16(0)) {
  2105. ql_dbg(ql_dbg_mbx, vha, 0x1090,
  2106. "Failed to complete IOCB -- completion status (%x).\n",
  2107. le16_to_cpu(abt->nport_handle));
  2108. rval = QLA_FUNCTION_FAILED;
  2109. } else {
  2110. ql_dbg(ql_dbg_mbx, vha, 0x1091, "Done %s.\n", __func__);
  2111. }
  2112. dma_pool_free(ha->s_dma_pool, abt, abt_dma);
  2113. return rval;
  2114. }
  2115. struct tsk_mgmt_cmd {
  2116. union {
  2117. struct tsk_mgmt_entry tsk;
  2118. struct sts_entry_24xx sts;
  2119. } p;
  2120. };
  2121. static int
  2122. __qla24xx_issue_tmf(char *name, uint32_t type, struct fc_port *fcport,
  2123. unsigned int l, int tag)
  2124. {
  2125. int rval, rval2;
  2126. struct tsk_mgmt_cmd *tsk;
  2127. struct sts_entry_24xx *sts;
  2128. dma_addr_t tsk_dma;
  2129. scsi_qla_host_t *vha;
  2130. struct qla_hw_data *ha;
  2131. struct req_que *req;
  2132. struct rsp_que *rsp;
  2133. vha = fcport->vha;
  2134. ha = vha->hw;
  2135. req = vha->req;
  2136. ql_dbg(ql_dbg_mbx, vha, 0x1092, "Entered %s.\n", __func__);
  2137. if (ha->flags.cpu_affinity_enabled)
  2138. rsp = ha->rsp_q_map[tag + 1];
  2139. else
  2140. rsp = req->rsp;
  2141. tsk = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &tsk_dma);
  2142. if (tsk == NULL) {
  2143. ql_log(ql_log_warn, vha, 0x1093,
  2144. "Failed to allocate task management IOCB.\n");
  2145. return QLA_MEMORY_ALLOC_FAILED;
  2146. }
  2147. memset(tsk, 0, sizeof(struct tsk_mgmt_cmd));
  2148. tsk->p.tsk.entry_type = TSK_MGMT_IOCB_TYPE;
  2149. tsk->p.tsk.entry_count = 1;
  2150. tsk->p.tsk.handle = MAKE_HANDLE(req->id, tsk->p.tsk.handle);
  2151. tsk->p.tsk.nport_handle = cpu_to_le16(fcport->loop_id);
  2152. tsk->p.tsk.timeout = cpu_to_le16(ha->r_a_tov / 10 * 2);
  2153. tsk->p.tsk.control_flags = cpu_to_le32(type);
  2154. tsk->p.tsk.port_id[0] = fcport->d_id.b.al_pa;
  2155. tsk->p.tsk.port_id[1] = fcport->d_id.b.area;
  2156. tsk->p.tsk.port_id[2] = fcport->d_id.b.domain;
  2157. tsk->p.tsk.vp_index = fcport->vp_idx;
  2158. if (type == TCF_LUN_RESET) {
  2159. int_to_scsilun(l, &tsk->p.tsk.lun);
  2160. host_to_fcp_swap((uint8_t *)&tsk->p.tsk.lun,
  2161. sizeof(tsk->p.tsk.lun));
  2162. }
  2163. sts = &tsk->p.sts;
  2164. rval = qla2x00_issue_iocb(vha, tsk, tsk_dma, 0);
  2165. if (rval != QLA_SUCCESS) {
  2166. ql_dbg(ql_dbg_mbx, vha, 0x1094,
  2167. "Failed to issue %s reset IOCB (%x).\n", name, rval);
  2168. } else if (sts->entry_status != 0) {
  2169. ql_dbg(ql_dbg_mbx, vha, 0x1095,
  2170. "Failed to complete IOCB -- error status (%x).\n",
  2171. sts->entry_status);
  2172. rval = QLA_FUNCTION_FAILED;
  2173. } else if (sts->comp_status !=
  2174. __constant_cpu_to_le16(CS_COMPLETE)) {
  2175. ql_dbg(ql_dbg_mbx, vha, 0x1096,
  2176. "Failed to complete IOCB -- completion status (%x).\n",
  2177. le16_to_cpu(sts->comp_status));
  2178. rval = QLA_FUNCTION_FAILED;
  2179. } else if (le16_to_cpu(sts->scsi_status) &
  2180. SS_RESPONSE_INFO_LEN_VALID) {
  2181. if (le32_to_cpu(sts->rsp_data_len) < 4) {
  2182. ql_dbg(ql_dbg_mbx, vha, 0x1097,
  2183. "Ignoring inconsistent data length -- not enough "
  2184. "response info (%d).\n",
  2185. le32_to_cpu(sts->rsp_data_len));
  2186. } else if (sts->data[3]) {
  2187. ql_dbg(ql_dbg_mbx, vha, 0x1098,
  2188. "Failed to complete IOCB -- response (%x).\n",
  2189. sts->data[3]);
  2190. rval = QLA_FUNCTION_FAILED;
  2191. }
  2192. }
  2193. /* Issue marker IOCB. */
  2194. rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
  2195. type == TCF_LUN_RESET ? MK_SYNC_ID_LUN: MK_SYNC_ID);
  2196. if (rval2 != QLA_SUCCESS) {
  2197. ql_dbg(ql_dbg_mbx, vha, 0x1099,
  2198. "Failed to issue marker IOCB (%x).\n", rval2);
  2199. } else {
  2200. ql_dbg(ql_dbg_mbx, vha, 0x109a, "Done %s.\n", __func__);
  2201. }
  2202. dma_pool_free(ha->s_dma_pool, tsk, tsk_dma);
  2203. return rval;
  2204. }
  2205. int
  2206. qla24xx_abort_target(struct fc_port *fcport, unsigned int l, int tag)
  2207. {
  2208. struct qla_hw_data *ha = fcport->vha->hw;
  2209. if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
  2210. return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag);
  2211. return __qla24xx_issue_tmf("Target", TCF_TARGET_RESET, fcport, l, tag);
  2212. }
  2213. int
  2214. qla24xx_lun_reset(struct fc_port *fcport, unsigned int l, int tag)
  2215. {
  2216. struct qla_hw_data *ha = fcport->vha->hw;
  2217. if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
  2218. return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag);
  2219. return __qla24xx_issue_tmf("Lun", TCF_LUN_RESET, fcport, l, tag);
  2220. }
  2221. int
  2222. qla2x00_system_error(scsi_qla_host_t *vha)
  2223. {
  2224. int rval;
  2225. mbx_cmd_t mc;
  2226. mbx_cmd_t *mcp = &mc;
  2227. struct qla_hw_data *ha = vha->hw;
  2228. if (!IS_QLA23XX(ha) && !IS_FWI2_CAPABLE(ha))
  2229. return QLA_FUNCTION_FAILED;
  2230. ql_dbg(ql_dbg_mbx, vha, 0x109b, "Entered %s.\n", __func__);
  2231. mcp->mb[0] = MBC_GEN_SYSTEM_ERROR;
  2232. mcp->out_mb = MBX_0;
  2233. mcp->in_mb = MBX_0;
  2234. mcp->tov = 5;
  2235. mcp->flags = 0;
  2236. rval = qla2x00_mailbox_command(vha, mcp);
  2237. if (rval != QLA_SUCCESS) {
  2238. ql_dbg(ql_dbg_mbx, vha, 0x109c, "Failed=%x.\n", rval);
  2239. } else {
  2240. ql_dbg(ql_dbg_mbx, vha, 0x109d, "Done %s.\n", __func__);
  2241. }
  2242. return rval;
  2243. }
  2244. /**
  2245. * qla2x00_set_serdes_params() -
  2246. * @ha: HA context
  2247. *
  2248. * Returns
  2249. */
  2250. int
  2251. qla2x00_set_serdes_params(scsi_qla_host_t *vha, uint16_t sw_em_1g,
  2252. uint16_t sw_em_2g, uint16_t sw_em_4g)
  2253. {
  2254. int rval;
  2255. mbx_cmd_t mc;
  2256. mbx_cmd_t *mcp = &mc;
  2257. ql_dbg(ql_dbg_mbx, vha, 0x109e, "Entered %s.\n", __func__);
  2258. mcp->mb[0] = MBC_SERDES_PARAMS;
  2259. mcp->mb[1] = BIT_0;
  2260. mcp->mb[2] = sw_em_1g | BIT_15;
  2261. mcp->mb[3] = sw_em_2g | BIT_15;
  2262. mcp->mb[4] = sw_em_4g | BIT_15;
  2263. mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  2264. mcp->in_mb = MBX_0;
  2265. mcp->tov = MBX_TOV_SECONDS;
  2266. mcp->flags = 0;
  2267. rval = qla2x00_mailbox_command(vha, mcp);
  2268. if (rval != QLA_SUCCESS) {
  2269. /*EMPTY*/
  2270. ql_dbg(ql_dbg_mbx, vha, 0x109f,
  2271. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  2272. } else {
  2273. /*EMPTY*/
  2274. ql_dbg(ql_dbg_mbx, vha, 0x10a0, "Done %s.\n", __func__);
  2275. }
  2276. return rval;
  2277. }
  2278. int
  2279. qla2x00_stop_firmware(scsi_qla_host_t *vha)
  2280. {
  2281. int rval;
  2282. mbx_cmd_t mc;
  2283. mbx_cmd_t *mcp = &mc;
  2284. if (!IS_FWI2_CAPABLE(vha->hw))
  2285. return QLA_FUNCTION_FAILED;
  2286. ql_dbg(ql_dbg_mbx, vha, 0x10a1, "Entered %s.\n", __func__);
  2287. mcp->mb[0] = MBC_STOP_FIRMWARE;
  2288. mcp->mb[1] = 0;
  2289. mcp->out_mb = MBX_1|MBX_0;
  2290. mcp->in_mb = MBX_0;
  2291. mcp->tov = 5;
  2292. mcp->flags = 0;
  2293. rval = qla2x00_mailbox_command(vha, mcp);
  2294. if (rval != QLA_SUCCESS) {
  2295. ql_dbg(ql_dbg_mbx, vha, 0x10a2, "Failed=%x.\n", rval);
  2296. if (mcp->mb[0] == MBS_INVALID_COMMAND)
  2297. rval = QLA_INVALID_COMMAND;
  2298. } else {
  2299. ql_dbg(ql_dbg_mbx, vha, 0x10a3, "Done %s.\n", __func__);
  2300. }
  2301. return rval;
  2302. }
  2303. int
  2304. qla2x00_enable_eft_trace(scsi_qla_host_t *vha, dma_addr_t eft_dma,
  2305. uint16_t buffers)
  2306. {
  2307. int rval;
  2308. mbx_cmd_t mc;
  2309. mbx_cmd_t *mcp = &mc;
  2310. ql_dbg(ql_dbg_mbx, vha, 0x10a4, "Entered %s.\n", __func__);
  2311. if (!IS_FWI2_CAPABLE(vha->hw))
  2312. return QLA_FUNCTION_FAILED;
  2313. if (unlikely(pci_channel_offline(vha->hw->pdev)))
  2314. return QLA_FUNCTION_FAILED;
  2315. mcp->mb[0] = MBC_TRACE_CONTROL;
  2316. mcp->mb[1] = TC_EFT_ENABLE;
  2317. mcp->mb[2] = LSW(eft_dma);
  2318. mcp->mb[3] = MSW(eft_dma);
  2319. mcp->mb[4] = LSW(MSD(eft_dma));
  2320. mcp->mb[5] = MSW(MSD(eft_dma));
  2321. mcp->mb[6] = buffers;
  2322. mcp->mb[7] = TC_AEN_DISABLE;
  2323. mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  2324. mcp->in_mb = MBX_1|MBX_0;
  2325. mcp->tov = MBX_TOV_SECONDS;
  2326. mcp->flags = 0;
  2327. rval = qla2x00_mailbox_command(vha, mcp);
  2328. if (rval != QLA_SUCCESS) {
  2329. ql_dbg(ql_dbg_mbx, vha, 0x10a5,
  2330. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  2331. rval, mcp->mb[0], mcp->mb[1]);
  2332. } else {
  2333. ql_dbg(ql_dbg_mbx, vha, 0x10a6, "Done %s.\n", __func__);
  2334. }
  2335. return rval;
  2336. }
  2337. int
  2338. qla2x00_disable_eft_trace(scsi_qla_host_t *vha)
  2339. {
  2340. int rval;
  2341. mbx_cmd_t mc;
  2342. mbx_cmd_t *mcp = &mc;
  2343. ql_dbg(ql_dbg_mbx, vha, 0x10a7, "Entered %s.\n", __func__);
  2344. if (!IS_FWI2_CAPABLE(vha->hw))
  2345. return QLA_FUNCTION_FAILED;
  2346. if (unlikely(pci_channel_offline(vha->hw->pdev)))
  2347. return QLA_FUNCTION_FAILED;
  2348. mcp->mb[0] = MBC_TRACE_CONTROL;
  2349. mcp->mb[1] = TC_EFT_DISABLE;
  2350. mcp->out_mb = MBX_1|MBX_0;
  2351. mcp->in_mb = MBX_1|MBX_0;
  2352. mcp->tov = MBX_TOV_SECONDS;
  2353. mcp->flags = 0;
  2354. rval = qla2x00_mailbox_command(vha, mcp);
  2355. if (rval != QLA_SUCCESS) {
  2356. ql_dbg(ql_dbg_mbx, vha, 0x10a8,
  2357. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  2358. rval, mcp->mb[0], mcp->mb[1]);
  2359. } else {
  2360. ql_dbg(ql_dbg_mbx, vha, 0x10a9, "Done %s.\n", __func__);
  2361. }
  2362. return rval;
  2363. }
  2364. int
  2365. qla2x00_enable_fce_trace(scsi_qla_host_t *vha, dma_addr_t fce_dma,
  2366. uint16_t buffers, uint16_t *mb, uint32_t *dwords)
  2367. {
  2368. int rval;
  2369. mbx_cmd_t mc;
  2370. mbx_cmd_t *mcp = &mc;
  2371. ql_dbg(ql_dbg_mbx, vha, 0x10aa, "Entered %s.\n", __func__);
  2372. if (!IS_QLA25XX(vha->hw) && !IS_QLA81XX(vha->hw))
  2373. return QLA_FUNCTION_FAILED;
  2374. if (unlikely(pci_channel_offline(vha->hw->pdev)))
  2375. return QLA_FUNCTION_FAILED;
  2376. mcp->mb[0] = MBC_TRACE_CONTROL;
  2377. mcp->mb[1] = TC_FCE_ENABLE;
  2378. mcp->mb[2] = LSW(fce_dma);
  2379. mcp->mb[3] = MSW(fce_dma);
  2380. mcp->mb[4] = LSW(MSD(fce_dma));
  2381. mcp->mb[5] = MSW(MSD(fce_dma));
  2382. mcp->mb[6] = buffers;
  2383. mcp->mb[7] = TC_AEN_DISABLE;
  2384. mcp->mb[8] = 0;
  2385. mcp->mb[9] = TC_FCE_DEFAULT_RX_SIZE;
  2386. mcp->mb[10] = TC_FCE_DEFAULT_TX_SIZE;
  2387. mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
  2388. MBX_1|MBX_0;
  2389. mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  2390. mcp->tov = MBX_TOV_SECONDS;
  2391. mcp->flags = 0;
  2392. rval = qla2x00_mailbox_command(vha, mcp);
  2393. if (rval != QLA_SUCCESS) {
  2394. ql_dbg(ql_dbg_mbx, vha, 0x10ab,
  2395. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  2396. rval, mcp->mb[0], mcp->mb[1]);
  2397. } else {
  2398. ql_dbg(ql_dbg_mbx, vha, 0x10ac, "Done %s.\n", __func__);
  2399. if (mb)
  2400. memcpy(mb, mcp->mb, 8 * sizeof(*mb));
  2401. if (dwords)
  2402. *dwords = buffers;
  2403. }
  2404. return rval;
  2405. }
  2406. int
  2407. qla2x00_disable_fce_trace(scsi_qla_host_t *vha, uint64_t *wr, uint64_t *rd)
  2408. {
  2409. int rval;
  2410. mbx_cmd_t mc;
  2411. mbx_cmd_t *mcp = &mc;
  2412. ql_dbg(ql_dbg_mbx, vha, 0x10ad, "Entered %s.\n", __func__);
  2413. if (!IS_FWI2_CAPABLE(vha->hw))
  2414. return QLA_FUNCTION_FAILED;
  2415. if (unlikely(pci_channel_offline(vha->hw->pdev)))
  2416. return QLA_FUNCTION_FAILED;
  2417. mcp->mb[0] = MBC_TRACE_CONTROL;
  2418. mcp->mb[1] = TC_FCE_DISABLE;
  2419. mcp->mb[2] = TC_FCE_DISABLE_TRACE;
  2420. mcp->out_mb = MBX_2|MBX_1|MBX_0;
  2421. mcp->in_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
  2422. MBX_1|MBX_0;
  2423. mcp->tov = MBX_TOV_SECONDS;
  2424. mcp->flags = 0;
  2425. rval = qla2x00_mailbox_command(vha, mcp);
  2426. if (rval != QLA_SUCCESS) {
  2427. ql_dbg(ql_dbg_mbx, vha, 0x10ae,
  2428. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  2429. rval, mcp->mb[0], mcp->mb[1]);
  2430. } else {
  2431. ql_dbg(ql_dbg_mbx, vha, 0x10af, "Done %s.\n", __func__);
  2432. if (wr)
  2433. *wr = (uint64_t) mcp->mb[5] << 48 |
  2434. (uint64_t) mcp->mb[4] << 32 |
  2435. (uint64_t) mcp->mb[3] << 16 |
  2436. (uint64_t) mcp->mb[2];
  2437. if (rd)
  2438. *rd = (uint64_t) mcp->mb[9] << 48 |
  2439. (uint64_t) mcp->mb[8] << 32 |
  2440. (uint64_t) mcp->mb[7] << 16 |
  2441. (uint64_t) mcp->mb[6];
  2442. }
  2443. return rval;
  2444. }
  2445. int
  2446. qla2x00_get_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
  2447. uint16_t *port_speed, uint16_t *mb)
  2448. {
  2449. int rval;
  2450. mbx_cmd_t mc;
  2451. mbx_cmd_t *mcp = &mc;
  2452. ql_dbg(ql_dbg_mbx, vha, 0x10b0, "Entered %s.\n", __func__);
  2453. if (!IS_IIDMA_CAPABLE(vha->hw))
  2454. return QLA_FUNCTION_FAILED;
  2455. mcp->mb[0] = MBC_PORT_PARAMS;
  2456. mcp->mb[1] = loop_id;
  2457. mcp->mb[2] = mcp->mb[3] = 0;
  2458. mcp->mb[9] = vha->vp_idx;
  2459. mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
  2460. mcp->in_mb = MBX_3|MBX_1|MBX_0;
  2461. mcp->tov = MBX_TOV_SECONDS;
  2462. mcp->flags = 0;
  2463. rval = qla2x00_mailbox_command(vha, mcp);
  2464. /* Return mailbox statuses. */
  2465. if (mb != NULL) {
  2466. mb[0] = mcp->mb[0];
  2467. mb[1] = mcp->mb[1];
  2468. mb[3] = mcp->mb[3];
  2469. }
  2470. if (rval != QLA_SUCCESS) {
  2471. ql_dbg(ql_dbg_mbx, vha, 0x10b1, "Failed=%x.\n", rval);
  2472. } else {
  2473. ql_dbg(ql_dbg_mbx, vha, 0x10b2, "Done %s.\n", __func__);
  2474. if (port_speed)
  2475. *port_speed = mcp->mb[3];
  2476. }
  2477. return rval;
  2478. }
  2479. int
  2480. qla2x00_set_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
  2481. uint16_t port_speed, uint16_t *mb)
  2482. {
  2483. int rval;
  2484. mbx_cmd_t mc;
  2485. mbx_cmd_t *mcp = &mc;
  2486. ql_dbg(ql_dbg_mbx, vha, 0x10b3, "Entered %s.\n", __func__);
  2487. if (!IS_IIDMA_CAPABLE(vha->hw))
  2488. return QLA_FUNCTION_FAILED;
  2489. mcp->mb[0] = MBC_PORT_PARAMS;
  2490. mcp->mb[1] = loop_id;
  2491. mcp->mb[2] = BIT_0;
  2492. if (IS_QLA8XXX_TYPE(vha->hw))
  2493. mcp->mb[3] = port_speed & (BIT_5|BIT_4|BIT_3|BIT_2|BIT_1|BIT_0);
  2494. else
  2495. mcp->mb[3] = port_speed & (BIT_2|BIT_1|BIT_0);
  2496. mcp->mb[9] = vha->vp_idx;
  2497. mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
  2498. mcp->in_mb = MBX_3|MBX_1|MBX_0;
  2499. mcp->tov = MBX_TOV_SECONDS;
  2500. mcp->flags = 0;
  2501. rval = qla2x00_mailbox_command(vha, mcp);
  2502. /* Return mailbox statuses. */
  2503. if (mb != NULL) {
  2504. mb[0] = mcp->mb[0];
  2505. mb[1] = mcp->mb[1];
  2506. mb[3] = mcp->mb[3];
  2507. }
  2508. if (rval != QLA_SUCCESS) {
  2509. ql_dbg(ql_dbg_mbx, vha, 0x10b4, "Failed=%x.\n", rval);
  2510. } else {
  2511. ql_dbg(ql_dbg_mbx, vha, 0x10b5, "Done %s.\n", __func__);
  2512. }
  2513. return rval;
  2514. }
  2515. void
  2516. qla24xx_report_id_acquisition(scsi_qla_host_t *vha,
  2517. struct vp_rpt_id_entry_24xx *rptid_entry)
  2518. {
  2519. uint8_t vp_idx;
  2520. uint16_t stat = le16_to_cpu(rptid_entry->vp_idx);
  2521. struct qla_hw_data *ha = vha->hw;
  2522. scsi_qla_host_t *vp;
  2523. unsigned long flags;
  2524. ql_dbg(ql_dbg_mbx, vha, 0x10b6, "Entered %s.\n", __func__);
  2525. if (rptid_entry->entry_status != 0)
  2526. return;
  2527. if (rptid_entry->format == 0) {
  2528. ql_dbg(ql_dbg_mbx, vha, 0x10b7,
  2529. "Format 0 : Number of VPs setup %d, number of "
  2530. "VPs acquired %d.\n",
  2531. MSB(le16_to_cpu(rptid_entry->vp_count)),
  2532. LSB(le16_to_cpu(rptid_entry->vp_count)));
  2533. ql_dbg(ql_dbg_mbx, vha, 0x10b8,
  2534. "Primary port id %02x%02x%02x.\n",
  2535. rptid_entry->port_id[2], rptid_entry->port_id[1],
  2536. rptid_entry->port_id[0]);
  2537. } else if (rptid_entry->format == 1) {
  2538. vp_idx = LSB(stat);
  2539. ql_dbg(ql_dbg_mbx, vha, 0x10b9,
  2540. "Format 1: VP[%d] enabled - status %d - with "
  2541. "port id %02x%02x%02x.\n", vp_idx, MSB(stat),
  2542. rptid_entry->port_id[2], rptid_entry->port_id[1],
  2543. rptid_entry->port_id[0]);
  2544. vp = vha;
  2545. if (vp_idx == 0 && (MSB(stat) != 1))
  2546. goto reg_needed;
  2547. if (MSB(stat) != 0) {
  2548. ql_dbg(ql_dbg_mbx, vha, 0x10ba,
  2549. "Could not acquire ID for VP[%d].\n", vp_idx);
  2550. return;
  2551. }
  2552. spin_lock_irqsave(&ha->vport_slock, flags);
  2553. list_for_each_entry(vp, &ha->vp_list, list)
  2554. if (vp_idx == vp->vp_idx)
  2555. break;
  2556. spin_unlock_irqrestore(&ha->vport_slock, flags);
  2557. if (!vp)
  2558. return;
  2559. vp->d_id.b.domain = rptid_entry->port_id[2];
  2560. vp->d_id.b.area = rptid_entry->port_id[1];
  2561. vp->d_id.b.al_pa = rptid_entry->port_id[0];
  2562. /*
  2563. * Cannot configure here as we are still sitting on the
  2564. * response queue. Handle it in dpc context.
  2565. */
  2566. set_bit(VP_IDX_ACQUIRED, &vp->vp_flags);
  2567. reg_needed:
  2568. set_bit(REGISTER_FC4_NEEDED, &vp->dpc_flags);
  2569. set_bit(REGISTER_FDMI_NEEDED, &vp->dpc_flags);
  2570. set_bit(VP_DPC_NEEDED, &vha->dpc_flags);
  2571. qla2xxx_wake_dpc(vha);
  2572. }
  2573. }
  2574. /*
  2575. * qla24xx_modify_vp_config
  2576. * Change VP configuration for vha
  2577. *
  2578. * Input:
  2579. * vha = adapter block pointer.
  2580. *
  2581. * Returns:
  2582. * qla2xxx local function return status code.
  2583. *
  2584. * Context:
  2585. * Kernel context.
  2586. */
  2587. int
  2588. qla24xx_modify_vp_config(scsi_qla_host_t *vha)
  2589. {
  2590. int rval;
  2591. struct vp_config_entry_24xx *vpmod;
  2592. dma_addr_t vpmod_dma;
  2593. struct qla_hw_data *ha = vha->hw;
  2594. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  2595. /* This can be called by the parent */
  2596. ql_dbg(ql_dbg_mbx, vha, 0x10bb, "Entered %s.\n", __func__);
  2597. vpmod = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vpmod_dma);
  2598. if (!vpmod) {
  2599. ql_log(ql_log_warn, vha, 0x10bc,
  2600. "Failed to allocate modify VP IOCB.\n");
  2601. return QLA_MEMORY_ALLOC_FAILED;
  2602. }
  2603. memset(vpmod, 0, sizeof(struct vp_config_entry_24xx));
  2604. vpmod->entry_type = VP_CONFIG_IOCB_TYPE;
  2605. vpmod->entry_count = 1;
  2606. vpmod->command = VCT_COMMAND_MOD_ENABLE_VPS;
  2607. vpmod->vp_count = 1;
  2608. vpmod->vp_index1 = vha->vp_idx;
  2609. vpmod->options_idx1 = BIT_3|BIT_4|BIT_5;
  2610. memcpy(vpmod->node_name_idx1, vha->node_name, WWN_SIZE);
  2611. memcpy(vpmod->port_name_idx1, vha->port_name, WWN_SIZE);
  2612. vpmod->entry_count = 1;
  2613. rval = qla2x00_issue_iocb(base_vha, vpmod, vpmod_dma, 0);
  2614. if (rval != QLA_SUCCESS) {
  2615. ql_dbg(ql_dbg_mbx, vha, 0x10bd,
  2616. "Failed to issue VP config IOCB (%x).\n", rval);
  2617. } else if (vpmod->comp_status != 0) {
  2618. ql_dbg(ql_dbg_mbx, vha, 0x10be,
  2619. "Failed to complete IOCB -- error status (%x).\n",
  2620. vpmod->comp_status);
  2621. rval = QLA_FUNCTION_FAILED;
  2622. } else if (vpmod->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
  2623. ql_dbg(ql_dbg_mbx, vha, 0x10bf,
  2624. "Failed to complete IOCB -- completion status (%x).\n",
  2625. le16_to_cpu(vpmod->comp_status));
  2626. rval = QLA_FUNCTION_FAILED;
  2627. } else {
  2628. /* EMPTY */
  2629. ql_dbg(ql_dbg_mbx, vha, 0x10c0, "Done %s.\n", __func__);
  2630. fc_vport_set_state(vha->fc_vport, FC_VPORT_INITIALIZING);
  2631. }
  2632. dma_pool_free(ha->s_dma_pool, vpmod, vpmod_dma);
  2633. return rval;
  2634. }
  2635. /*
  2636. * qla24xx_control_vp
  2637. * Enable a virtual port for given host
  2638. *
  2639. * Input:
  2640. * ha = adapter block pointer.
  2641. * vhba = virtual adapter (unused)
  2642. * index = index number for enabled VP
  2643. *
  2644. * Returns:
  2645. * qla2xxx local function return status code.
  2646. *
  2647. * Context:
  2648. * Kernel context.
  2649. */
  2650. int
  2651. qla24xx_control_vp(scsi_qla_host_t *vha, int cmd)
  2652. {
  2653. int rval;
  2654. int map, pos;
  2655. struct vp_ctrl_entry_24xx *vce;
  2656. dma_addr_t vce_dma;
  2657. struct qla_hw_data *ha = vha->hw;
  2658. int vp_index = vha->vp_idx;
  2659. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  2660. ql_dbg(ql_dbg_mbx, vha, 0x10c1,
  2661. "Entered %s enabling index %d.\n", __func__, vp_index);
  2662. if (vp_index == 0 || vp_index >= ha->max_npiv_vports)
  2663. return QLA_PARAMETER_ERROR;
  2664. vce = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vce_dma);
  2665. if (!vce) {
  2666. ql_log(ql_log_warn, vha, 0x10c2,
  2667. "Failed to allocate VP control IOCB.\n");
  2668. return QLA_MEMORY_ALLOC_FAILED;
  2669. }
  2670. memset(vce, 0, sizeof(struct vp_ctrl_entry_24xx));
  2671. vce->entry_type = VP_CTRL_IOCB_TYPE;
  2672. vce->entry_count = 1;
  2673. vce->command = cpu_to_le16(cmd);
  2674. vce->vp_count = __constant_cpu_to_le16(1);
  2675. /* index map in firmware starts with 1; decrement index
  2676. * this is ok as we never use index 0
  2677. */
  2678. map = (vp_index - 1) / 8;
  2679. pos = (vp_index - 1) & 7;
  2680. mutex_lock(&ha->vport_lock);
  2681. vce->vp_idx_map[map] |= 1 << pos;
  2682. mutex_unlock(&ha->vport_lock);
  2683. rval = qla2x00_issue_iocb(base_vha, vce, vce_dma, 0);
  2684. if (rval != QLA_SUCCESS) {
  2685. ql_dbg(ql_dbg_mbx, vha, 0x10c3,
  2686. "Failed to issue VP control IOCB (%x).\n", rval);
  2687. } else if (vce->entry_status != 0) {
  2688. ql_dbg(ql_dbg_mbx, vha, 0x10c4,
  2689. "Failed to complete IOCB -- error status (%x).\n",
  2690. vce->entry_status);
  2691. rval = QLA_FUNCTION_FAILED;
  2692. } else if (vce->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
  2693. ql_dbg(ql_dbg_mbx, vha, 0x10c5,
  2694. "Failed to complet IOCB -- completion status (%x).\n",
  2695. le16_to_cpu(vce->comp_status));
  2696. rval = QLA_FUNCTION_FAILED;
  2697. } else {
  2698. ql_dbg(ql_dbg_mbx, vha, 0x10c6, "Done %s.\n", __func__);
  2699. }
  2700. dma_pool_free(ha->s_dma_pool, vce, vce_dma);
  2701. return rval;
  2702. }
  2703. /*
  2704. * qla2x00_send_change_request
  2705. * Receive or disable RSCN request from fabric controller
  2706. *
  2707. * Input:
  2708. * ha = adapter block pointer
  2709. * format = registration format:
  2710. * 0 - Reserved
  2711. * 1 - Fabric detected registration
  2712. * 2 - N_port detected registration
  2713. * 3 - Full registration
  2714. * FF - clear registration
  2715. * vp_idx = Virtual port index
  2716. *
  2717. * Returns:
  2718. * qla2x00 local function return status code.
  2719. *
  2720. * Context:
  2721. * Kernel Context
  2722. */
  2723. int
  2724. qla2x00_send_change_request(scsi_qla_host_t *vha, uint16_t format,
  2725. uint16_t vp_idx)
  2726. {
  2727. int rval;
  2728. mbx_cmd_t mc;
  2729. mbx_cmd_t *mcp = &mc;
  2730. ql_dbg(ql_dbg_mbx, vha, 0x10c7, "Entered %s.\n", __func__);
  2731. /*
  2732. * This command is implicitly executed by firmware during login for the
  2733. * physical hosts
  2734. */
  2735. if (vp_idx == 0)
  2736. return QLA_FUNCTION_FAILED;
  2737. mcp->mb[0] = MBC_SEND_CHANGE_REQUEST;
  2738. mcp->mb[1] = format;
  2739. mcp->mb[9] = vp_idx;
  2740. mcp->out_mb = MBX_9|MBX_1|MBX_0;
  2741. mcp->in_mb = MBX_0|MBX_1;
  2742. mcp->tov = MBX_TOV_SECONDS;
  2743. mcp->flags = 0;
  2744. rval = qla2x00_mailbox_command(vha, mcp);
  2745. if (rval == QLA_SUCCESS) {
  2746. if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
  2747. rval = BIT_1;
  2748. }
  2749. } else
  2750. rval = BIT_1;
  2751. return rval;
  2752. }
  2753. int
  2754. qla2x00_dump_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
  2755. uint32_t size)
  2756. {
  2757. int rval;
  2758. mbx_cmd_t mc;
  2759. mbx_cmd_t *mcp = &mc;
  2760. ql_dbg(ql_dbg_mbx, vha, 0x1009, "Entered %s.\n", __func__);
  2761. if (MSW(addr) || IS_FWI2_CAPABLE(vha->hw)) {
  2762. mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
  2763. mcp->mb[8] = MSW(addr);
  2764. mcp->out_mb = MBX_8|MBX_0;
  2765. } else {
  2766. mcp->mb[0] = MBC_DUMP_RISC_RAM;
  2767. mcp->out_mb = MBX_0;
  2768. }
  2769. mcp->mb[1] = LSW(addr);
  2770. mcp->mb[2] = MSW(req_dma);
  2771. mcp->mb[3] = LSW(req_dma);
  2772. mcp->mb[6] = MSW(MSD(req_dma));
  2773. mcp->mb[7] = LSW(MSD(req_dma));
  2774. mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
  2775. if (IS_FWI2_CAPABLE(vha->hw)) {
  2776. mcp->mb[4] = MSW(size);
  2777. mcp->mb[5] = LSW(size);
  2778. mcp->out_mb |= MBX_5|MBX_4;
  2779. } else {
  2780. mcp->mb[4] = LSW(size);
  2781. mcp->out_mb |= MBX_4;
  2782. }
  2783. mcp->in_mb = MBX_0;
  2784. mcp->tov = MBX_TOV_SECONDS;
  2785. mcp->flags = 0;
  2786. rval = qla2x00_mailbox_command(vha, mcp);
  2787. if (rval != QLA_SUCCESS) {
  2788. ql_dbg(ql_dbg_mbx, vha, 0x1008,
  2789. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  2790. } else {
  2791. ql_dbg(ql_dbg_mbx, vha, 0x1007, "Done %s.\n", __func__);
  2792. }
  2793. return rval;
  2794. }
  2795. /* 84XX Support **************************************************************/
  2796. struct cs84xx_mgmt_cmd {
  2797. union {
  2798. struct verify_chip_entry_84xx req;
  2799. struct verify_chip_rsp_84xx rsp;
  2800. } p;
  2801. };
  2802. int
  2803. qla84xx_verify_chip(struct scsi_qla_host *vha, uint16_t *status)
  2804. {
  2805. int rval, retry;
  2806. struct cs84xx_mgmt_cmd *mn;
  2807. dma_addr_t mn_dma;
  2808. uint16_t options;
  2809. unsigned long flags;
  2810. struct qla_hw_data *ha = vha->hw;
  2811. ql_dbg(ql_dbg_mbx, vha, 0x10c8, "Entered %s.\n", __func__);
  2812. mn = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &mn_dma);
  2813. if (mn == NULL) {
  2814. return QLA_MEMORY_ALLOC_FAILED;
  2815. }
  2816. /* Force Update? */
  2817. options = ha->cs84xx->fw_update ? VCO_FORCE_UPDATE : 0;
  2818. /* Diagnostic firmware? */
  2819. /* options |= MENLO_DIAG_FW; */
  2820. /* We update the firmware with only one data sequence. */
  2821. options |= VCO_END_OF_DATA;
  2822. do {
  2823. retry = 0;
  2824. memset(mn, 0, sizeof(*mn));
  2825. mn->p.req.entry_type = VERIFY_CHIP_IOCB_TYPE;
  2826. mn->p.req.entry_count = 1;
  2827. mn->p.req.options = cpu_to_le16(options);
  2828. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111c,
  2829. "Dump of Verify Request.\n");
  2830. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111e,
  2831. (uint8_t *)mn, sizeof(*mn));
  2832. rval = qla2x00_issue_iocb_timeout(vha, mn, mn_dma, 0, 120);
  2833. if (rval != QLA_SUCCESS) {
  2834. ql_dbg(ql_dbg_mbx, vha, 0x10cb,
  2835. "Failed to issue verify IOCB (%x).\n", rval);
  2836. goto verify_done;
  2837. }
  2838. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1110,
  2839. "Dump of Verify Response.\n");
  2840. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1118,
  2841. (uint8_t *)mn, sizeof(*mn));
  2842. status[0] = le16_to_cpu(mn->p.rsp.comp_status);
  2843. status[1] = status[0] == CS_VCS_CHIP_FAILURE ?
  2844. le16_to_cpu(mn->p.rsp.failure_code) : 0;
  2845. ql_dbg(ql_dbg_mbx, vha, 0x10ce,
  2846. "cs=%x fc=%x.\n", status[0], status[1]);
  2847. if (status[0] != CS_COMPLETE) {
  2848. rval = QLA_FUNCTION_FAILED;
  2849. if (!(options & VCO_DONT_UPDATE_FW)) {
  2850. ql_dbg(ql_dbg_mbx, vha, 0x10cf,
  2851. "Firmware update failed. Retrying "
  2852. "without update firmware.\n");
  2853. options |= VCO_DONT_UPDATE_FW;
  2854. options &= ~VCO_FORCE_UPDATE;
  2855. retry = 1;
  2856. }
  2857. } else {
  2858. ql_dbg(ql_dbg_mbx, vha, 0x10d0,
  2859. "Firmware updated to %x.\n",
  2860. le32_to_cpu(mn->p.rsp.fw_ver));
  2861. /* NOTE: we only update OP firmware. */
  2862. spin_lock_irqsave(&ha->cs84xx->access_lock, flags);
  2863. ha->cs84xx->op_fw_version =
  2864. le32_to_cpu(mn->p.rsp.fw_ver);
  2865. spin_unlock_irqrestore(&ha->cs84xx->access_lock,
  2866. flags);
  2867. }
  2868. } while (retry);
  2869. verify_done:
  2870. dma_pool_free(ha->s_dma_pool, mn, mn_dma);
  2871. if (rval != QLA_SUCCESS) {
  2872. ql_dbg(ql_dbg_mbx, vha, 0x10d1, "Failed=%x.\n", rval);
  2873. } else {
  2874. ql_dbg(ql_dbg_mbx, vha, 0x10d2, "Done %s.\n", __func__);
  2875. }
  2876. return rval;
  2877. }
  2878. int
  2879. qla25xx_init_req_que(struct scsi_qla_host *vha, struct req_que *req)
  2880. {
  2881. int rval;
  2882. unsigned long flags;
  2883. mbx_cmd_t mc;
  2884. mbx_cmd_t *mcp = &mc;
  2885. struct device_reg_25xxmq __iomem *reg;
  2886. struct qla_hw_data *ha = vha->hw;
  2887. ql_dbg(ql_dbg_mbx, vha, 0x10d3, "Entered %s.\n", __func__);
  2888. mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
  2889. mcp->mb[1] = req->options;
  2890. mcp->mb[2] = MSW(LSD(req->dma));
  2891. mcp->mb[3] = LSW(LSD(req->dma));
  2892. mcp->mb[6] = MSW(MSD(req->dma));
  2893. mcp->mb[7] = LSW(MSD(req->dma));
  2894. mcp->mb[5] = req->length;
  2895. if (req->rsp)
  2896. mcp->mb[10] = req->rsp->id;
  2897. mcp->mb[12] = req->qos;
  2898. mcp->mb[11] = req->vp_idx;
  2899. mcp->mb[13] = req->rid;
  2900. reg = (struct device_reg_25xxmq *)((void *)(ha->mqiobase) +
  2901. QLA_QUE_PAGE * req->id);
  2902. mcp->mb[4] = req->id;
  2903. /* que in ptr index */
  2904. mcp->mb[8] = 0;
  2905. /* que out ptr index */
  2906. mcp->mb[9] = 0;
  2907. mcp->out_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|MBX_7|
  2908. MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  2909. mcp->in_mb = MBX_0;
  2910. mcp->flags = MBX_DMA_OUT;
  2911. mcp->tov = 60;
  2912. spin_lock_irqsave(&ha->hardware_lock, flags);
  2913. if (!(req->options & BIT_0)) {
  2914. WRT_REG_DWORD(&reg->req_q_in, 0);
  2915. WRT_REG_DWORD(&reg->req_q_out, 0);
  2916. }
  2917. req->req_q_in = &reg->req_q_in;
  2918. req->req_q_out = &reg->req_q_out;
  2919. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2920. rval = qla2x00_mailbox_command(vha, mcp);
  2921. if (rval != QLA_SUCCESS) {
  2922. ql_dbg(ql_dbg_mbx, vha, 0x10d4,
  2923. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  2924. } else {
  2925. ql_dbg(ql_dbg_mbx, vha, 0x10d5, "Done %s.\n", __func__);
  2926. }
  2927. return rval;
  2928. }
  2929. int
  2930. qla25xx_init_rsp_que(struct scsi_qla_host *vha, struct rsp_que *rsp)
  2931. {
  2932. int rval;
  2933. unsigned long flags;
  2934. mbx_cmd_t mc;
  2935. mbx_cmd_t *mcp = &mc;
  2936. struct device_reg_25xxmq __iomem *reg;
  2937. struct qla_hw_data *ha = vha->hw;
  2938. ql_dbg(ql_dbg_mbx, vha, 0x10d6, "Entered %s.\n", __func__);
  2939. mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
  2940. mcp->mb[1] = rsp->options;
  2941. mcp->mb[2] = MSW(LSD(rsp->dma));
  2942. mcp->mb[3] = LSW(LSD(rsp->dma));
  2943. mcp->mb[6] = MSW(MSD(rsp->dma));
  2944. mcp->mb[7] = LSW(MSD(rsp->dma));
  2945. mcp->mb[5] = rsp->length;
  2946. mcp->mb[14] = rsp->msix->entry;
  2947. mcp->mb[13] = rsp->rid;
  2948. reg = (struct device_reg_25xxmq *)((void *)(ha->mqiobase) +
  2949. QLA_QUE_PAGE * rsp->id);
  2950. mcp->mb[4] = rsp->id;
  2951. /* que in ptr index */
  2952. mcp->mb[8] = 0;
  2953. /* que out ptr index */
  2954. mcp->mb[9] = 0;
  2955. mcp->out_mb = MBX_14|MBX_13|MBX_9|MBX_8|MBX_7
  2956. |MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  2957. mcp->in_mb = MBX_0;
  2958. mcp->flags = MBX_DMA_OUT;
  2959. mcp->tov = 60;
  2960. spin_lock_irqsave(&ha->hardware_lock, flags);
  2961. if (!(rsp->options & BIT_0)) {
  2962. WRT_REG_DWORD(&reg->rsp_q_out, 0);
  2963. WRT_REG_DWORD(&reg->rsp_q_in, 0);
  2964. }
  2965. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2966. rval = qla2x00_mailbox_command(vha, mcp);
  2967. if (rval != QLA_SUCCESS) {
  2968. ql_dbg(ql_dbg_mbx, vha, 0x10d7,
  2969. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  2970. } else {
  2971. ql_dbg(ql_dbg_mbx, vha, 0x10d8, "Done %s.\n", __func__);
  2972. }
  2973. return rval;
  2974. }
  2975. int
  2976. qla81xx_idc_ack(scsi_qla_host_t *vha, uint16_t *mb)
  2977. {
  2978. int rval;
  2979. mbx_cmd_t mc;
  2980. mbx_cmd_t *mcp = &mc;
  2981. ql_dbg(ql_dbg_mbx, vha, 0x10d9, "Entered %s.\n", __func__);
  2982. mcp->mb[0] = MBC_IDC_ACK;
  2983. memcpy(&mcp->mb[1], mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
  2984. mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  2985. mcp->in_mb = MBX_0;
  2986. mcp->tov = MBX_TOV_SECONDS;
  2987. mcp->flags = 0;
  2988. rval = qla2x00_mailbox_command(vha, mcp);
  2989. if (rval != QLA_SUCCESS) {
  2990. ql_dbg(ql_dbg_mbx, vha, 0x10da,
  2991. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  2992. } else {
  2993. ql_dbg(ql_dbg_mbx, vha, 0x10db, "Done %s.\n", __func__);
  2994. }
  2995. return rval;
  2996. }
  2997. int
  2998. qla81xx_fac_get_sector_size(scsi_qla_host_t *vha, uint32_t *sector_size)
  2999. {
  3000. int rval;
  3001. mbx_cmd_t mc;
  3002. mbx_cmd_t *mcp = &mc;
  3003. ql_dbg(ql_dbg_mbx, vha, 0x10dc, "Entered %s.\n", __func__);
  3004. if (!IS_QLA81XX(vha->hw))
  3005. return QLA_FUNCTION_FAILED;
  3006. mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
  3007. mcp->mb[1] = FAC_OPT_CMD_GET_SECTOR_SIZE;
  3008. mcp->out_mb = MBX_1|MBX_0;
  3009. mcp->in_mb = MBX_1|MBX_0;
  3010. mcp->tov = MBX_TOV_SECONDS;
  3011. mcp->flags = 0;
  3012. rval = qla2x00_mailbox_command(vha, mcp);
  3013. if (rval != QLA_SUCCESS) {
  3014. ql_dbg(ql_dbg_mbx, vha, 0x10dd,
  3015. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  3016. rval, mcp->mb[0], mcp->mb[1]);
  3017. } else {
  3018. ql_dbg(ql_dbg_mbx, vha, 0x10de, "Done %s.\n", __func__);
  3019. *sector_size = mcp->mb[1];
  3020. }
  3021. return rval;
  3022. }
  3023. int
  3024. qla81xx_fac_do_write_enable(scsi_qla_host_t *vha, int enable)
  3025. {
  3026. int rval;
  3027. mbx_cmd_t mc;
  3028. mbx_cmd_t *mcp = &mc;
  3029. if (!IS_QLA81XX(vha->hw))
  3030. return QLA_FUNCTION_FAILED;
  3031. ql_dbg(ql_dbg_mbx, vha, 0x10df, "Entered %s.\n", __func__);
  3032. mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
  3033. mcp->mb[1] = enable ? FAC_OPT_CMD_WRITE_ENABLE :
  3034. FAC_OPT_CMD_WRITE_PROTECT;
  3035. mcp->out_mb = MBX_1|MBX_0;
  3036. mcp->in_mb = MBX_1|MBX_0;
  3037. mcp->tov = MBX_TOV_SECONDS;
  3038. mcp->flags = 0;
  3039. rval = qla2x00_mailbox_command(vha, mcp);
  3040. if (rval != QLA_SUCCESS) {
  3041. ql_dbg(ql_dbg_mbx, vha, 0x10e0,
  3042. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  3043. rval, mcp->mb[0], mcp->mb[1]);
  3044. } else {
  3045. ql_dbg(ql_dbg_mbx, vha, 0x10e1, "Done %s.\n", __func__);
  3046. }
  3047. return rval;
  3048. }
  3049. int
  3050. qla81xx_fac_erase_sector(scsi_qla_host_t *vha, uint32_t start, uint32_t finish)
  3051. {
  3052. int rval;
  3053. mbx_cmd_t mc;
  3054. mbx_cmd_t *mcp = &mc;
  3055. if (!IS_QLA81XX(vha->hw))
  3056. return QLA_FUNCTION_FAILED;
  3057. ql_dbg(ql_dbg_mbx, vha, 0x10e2, "Entered %s.\n", __func__);
  3058. mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
  3059. mcp->mb[1] = FAC_OPT_CMD_ERASE_SECTOR;
  3060. mcp->mb[2] = LSW(start);
  3061. mcp->mb[3] = MSW(start);
  3062. mcp->mb[4] = LSW(finish);
  3063. mcp->mb[5] = MSW(finish);
  3064. mcp->out_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3065. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  3066. mcp->tov = MBX_TOV_SECONDS;
  3067. mcp->flags = 0;
  3068. rval = qla2x00_mailbox_command(vha, mcp);
  3069. if (rval != QLA_SUCCESS) {
  3070. ql_dbg(ql_dbg_mbx, vha, 0x10e3,
  3071. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
  3072. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
  3073. } else {
  3074. ql_dbg(ql_dbg_mbx, vha, 0x10e4, "Done %s.\n", __func__);
  3075. }
  3076. return rval;
  3077. }
  3078. int
  3079. qla81xx_restart_mpi_firmware(scsi_qla_host_t *vha)
  3080. {
  3081. int rval = 0;
  3082. mbx_cmd_t mc;
  3083. mbx_cmd_t *mcp = &mc;
  3084. ql_dbg(ql_dbg_mbx, vha, 0x10e5, "Entered %s.\n", __func__);
  3085. mcp->mb[0] = MBC_RESTART_MPI_FW;
  3086. mcp->out_mb = MBX_0;
  3087. mcp->in_mb = MBX_0|MBX_1;
  3088. mcp->tov = MBX_TOV_SECONDS;
  3089. mcp->flags = 0;
  3090. rval = qla2x00_mailbox_command(vha, mcp);
  3091. if (rval != QLA_SUCCESS) {
  3092. ql_dbg(ql_dbg_mbx, vha, 0x10e6,
  3093. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  3094. rval, mcp->mb[0], mcp->mb[1]);
  3095. } else {
  3096. ql_dbg(ql_dbg_mbx, vha, 0x10e7, "Done %s.\n", __func__);
  3097. }
  3098. return rval;
  3099. }
  3100. int
  3101. qla2x00_read_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
  3102. uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
  3103. {
  3104. int rval;
  3105. mbx_cmd_t mc;
  3106. mbx_cmd_t *mcp = &mc;
  3107. struct qla_hw_data *ha = vha->hw;
  3108. ql_dbg(ql_dbg_mbx, vha, 0x10e8, "Entered %s.\n", __func__);
  3109. if (!IS_FWI2_CAPABLE(ha))
  3110. return QLA_FUNCTION_FAILED;
  3111. if (len == 1)
  3112. opt |= BIT_0;
  3113. mcp->mb[0] = MBC_READ_SFP;
  3114. mcp->mb[1] = dev;
  3115. mcp->mb[2] = MSW(sfp_dma);
  3116. mcp->mb[3] = LSW(sfp_dma);
  3117. mcp->mb[6] = MSW(MSD(sfp_dma));
  3118. mcp->mb[7] = LSW(MSD(sfp_dma));
  3119. mcp->mb[8] = len;
  3120. mcp->mb[9] = off;
  3121. mcp->mb[10] = opt;
  3122. mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  3123. mcp->in_mb = MBX_1|MBX_0;
  3124. mcp->tov = MBX_TOV_SECONDS;
  3125. mcp->flags = 0;
  3126. rval = qla2x00_mailbox_command(vha, mcp);
  3127. if (opt & BIT_0)
  3128. *sfp = mcp->mb[1];
  3129. if (rval != QLA_SUCCESS) {
  3130. ql_dbg(ql_dbg_mbx, vha, 0x10e9,
  3131. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3132. } else {
  3133. ql_dbg(ql_dbg_mbx, vha, 0x10ea, "Done %s.\n", __func__);
  3134. }
  3135. return rval;
  3136. }
  3137. int
  3138. qla2x00_write_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
  3139. uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
  3140. {
  3141. int rval;
  3142. mbx_cmd_t mc;
  3143. mbx_cmd_t *mcp = &mc;
  3144. struct qla_hw_data *ha = vha->hw;
  3145. ql_dbg(ql_dbg_mbx, vha, 0x10eb, "Entered %s.\n", __func__);
  3146. if (!IS_FWI2_CAPABLE(ha))
  3147. return QLA_FUNCTION_FAILED;
  3148. if (len == 1)
  3149. opt |= BIT_0;
  3150. if (opt & BIT_0)
  3151. len = *sfp;
  3152. mcp->mb[0] = MBC_WRITE_SFP;
  3153. mcp->mb[1] = dev;
  3154. mcp->mb[2] = MSW(sfp_dma);
  3155. mcp->mb[3] = LSW(sfp_dma);
  3156. mcp->mb[6] = MSW(MSD(sfp_dma));
  3157. mcp->mb[7] = LSW(MSD(sfp_dma));
  3158. mcp->mb[8] = len;
  3159. mcp->mb[9] = off;
  3160. mcp->mb[10] = opt;
  3161. mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  3162. mcp->in_mb = MBX_1|MBX_0;
  3163. mcp->tov = MBX_TOV_SECONDS;
  3164. mcp->flags = 0;
  3165. rval = qla2x00_mailbox_command(vha, mcp);
  3166. if (rval != QLA_SUCCESS) {
  3167. ql_dbg(ql_dbg_mbx, vha, 0x10ec,
  3168. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3169. } else {
  3170. ql_dbg(ql_dbg_mbx, vha, 0x10ed, "Done %s.\n", __func__);
  3171. }
  3172. return rval;
  3173. }
  3174. int
  3175. qla2x00_get_xgmac_stats(scsi_qla_host_t *vha, dma_addr_t stats_dma,
  3176. uint16_t size_in_bytes, uint16_t *actual_size)
  3177. {
  3178. int rval;
  3179. mbx_cmd_t mc;
  3180. mbx_cmd_t *mcp = &mc;
  3181. ql_dbg(ql_dbg_mbx, vha, 0x10ee, "Entered %s.\n", __func__);
  3182. if (!IS_QLA8XXX_TYPE(vha->hw))
  3183. return QLA_FUNCTION_FAILED;
  3184. mcp->mb[0] = MBC_GET_XGMAC_STATS;
  3185. mcp->mb[2] = MSW(stats_dma);
  3186. mcp->mb[3] = LSW(stats_dma);
  3187. mcp->mb[6] = MSW(MSD(stats_dma));
  3188. mcp->mb[7] = LSW(MSD(stats_dma));
  3189. mcp->mb[8] = size_in_bytes >> 2;
  3190. mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  3191. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  3192. mcp->tov = MBX_TOV_SECONDS;
  3193. mcp->flags = 0;
  3194. rval = qla2x00_mailbox_command(vha, mcp);
  3195. if (rval != QLA_SUCCESS) {
  3196. ql_dbg(ql_dbg_mbx, vha, 0x10ef,
  3197. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
  3198. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
  3199. } else {
  3200. ql_dbg(ql_dbg_mbx, vha, 0x10f0, "Done %s.\n", __func__);
  3201. *actual_size = mcp->mb[2] << 2;
  3202. }
  3203. return rval;
  3204. }
  3205. int
  3206. qla2x00_get_dcbx_params(scsi_qla_host_t *vha, dma_addr_t tlv_dma,
  3207. uint16_t size)
  3208. {
  3209. int rval;
  3210. mbx_cmd_t mc;
  3211. mbx_cmd_t *mcp = &mc;
  3212. ql_dbg(ql_dbg_mbx, vha, 0x10f1, "Entered %s.\n", __func__);
  3213. if (!IS_QLA8XXX_TYPE(vha->hw))
  3214. return QLA_FUNCTION_FAILED;
  3215. mcp->mb[0] = MBC_GET_DCBX_PARAMS;
  3216. mcp->mb[1] = 0;
  3217. mcp->mb[2] = MSW(tlv_dma);
  3218. mcp->mb[3] = LSW(tlv_dma);
  3219. mcp->mb[6] = MSW(MSD(tlv_dma));
  3220. mcp->mb[7] = LSW(MSD(tlv_dma));
  3221. mcp->mb[8] = size;
  3222. mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  3223. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  3224. mcp->tov = MBX_TOV_SECONDS;
  3225. mcp->flags = 0;
  3226. rval = qla2x00_mailbox_command(vha, mcp);
  3227. if (rval != QLA_SUCCESS) {
  3228. ql_dbg(ql_dbg_mbx, vha, 0x10f2,
  3229. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
  3230. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
  3231. } else {
  3232. ql_dbg(ql_dbg_mbx, vha, 0x10f3, "Done %s.\n", __func__);
  3233. }
  3234. return rval;
  3235. }
  3236. int
  3237. qla2x00_read_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t *data)
  3238. {
  3239. int rval;
  3240. mbx_cmd_t mc;
  3241. mbx_cmd_t *mcp = &mc;
  3242. ql_dbg(ql_dbg_mbx, vha, 0x10f4, "Entered %s.\n", __func__);
  3243. if (!IS_FWI2_CAPABLE(vha->hw))
  3244. return QLA_FUNCTION_FAILED;
  3245. mcp->mb[0] = MBC_READ_RAM_EXTENDED;
  3246. mcp->mb[1] = LSW(risc_addr);
  3247. mcp->mb[8] = MSW(risc_addr);
  3248. mcp->out_mb = MBX_8|MBX_1|MBX_0;
  3249. mcp->in_mb = MBX_3|MBX_2|MBX_0;
  3250. mcp->tov = 30;
  3251. mcp->flags = 0;
  3252. rval = qla2x00_mailbox_command(vha, mcp);
  3253. if (rval != QLA_SUCCESS) {
  3254. ql_dbg(ql_dbg_mbx, vha, 0x10f5,
  3255. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3256. } else {
  3257. ql_dbg(ql_dbg_mbx, vha, 0x10f6, "Done %s.\n", __func__);
  3258. *data = mcp->mb[3] << 16 | mcp->mb[2];
  3259. }
  3260. return rval;
  3261. }
  3262. int
  3263. qla2x00_loopback_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
  3264. uint16_t *mresp)
  3265. {
  3266. int rval;
  3267. mbx_cmd_t mc;
  3268. mbx_cmd_t *mcp = &mc;
  3269. uint32_t iter_cnt = 0x1;
  3270. ql_dbg(ql_dbg_mbx, vha, 0x10f7, "Entered %s.\n", __func__);
  3271. memset(mcp->mb, 0 , sizeof(mcp->mb));
  3272. mcp->mb[0] = MBC_DIAGNOSTIC_LOOP_BACK;
  3273. mcp->mb[1] = mreq->options | BIT_6; // BIT_6 specifies 64 bit addressing
  3274. /* transfer count */
  3275. mcp->mb[10] = LSW(mreq->transfer_size);
  3276. mcp->mb[11] = MSW(mreq->transfer_size);
  3277. /* send data address */
  3278. mcp->mb[14] = LSW(mreq->send_dma);
  3279. mcp->mb[15] = MSW(mreq->send_dma);
  3280. mcp->mb[20] = LSW(MSD(mreq->send_dma));
  3281. mcp->mb[21] = MSW(MSD(mreq->send_dma));
  3282. /* receive data address */
  3283. mcp->mb[16] = LSW(mreq->rcv_dma);
  3284. mcp->mb[17] = MSW(mreq->rcv_dma);
  3285. mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
  3286. mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
  3287. /* Iteration count */
  3288. mcp->mb[18] = LSW(iter_cnt);
  3289. mcp->mb[19] = MSW(iter_cnt);
  3290. mcp->out_mb = MBX_21|MBX_20|MBX_19|MBX_18|MBX_17|MBX_16|MBX_15|
  3291. MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
  3292. if (IS_QLA8XXX_TYPE(vha->hw))
  3293. mcp->out_mb |= MBX_2;
  3294. mcp->in_mb = MBX_19|MBX_18|MBX_3|MBX_2|MBX_1|MBX_0;
  3295. mcp->buf_size = mreq->transfer_size;
  3296. mcp->tov = MBX_TOV_SECONDS;
  3297. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  3298. rval = qla2x00_mailbox_command(vha, mcp);
  3299. if (rval != QLA_SUCCESS) {
  3300. ql_dbg(ql_dbg_mbx, vha, 0x10f8,
  3301. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[18]=%x "
  3302. "mb[19]=%x.\n", rval, mcp->mb[0], mcp->mb[1], mcp->mb[2],
  3303. mcp->mb[3], mcp->mb[18], mcp->mb[19]);
  3304. } else {
  3305. ql_dbg(ql_dbg_mbx, vha, 0x10f9, "Done %s.\n", __func__);
  3306. }
  3307. /* Copy mailbox information */
  3308. memcpy( mresp, mcp->mb, 64);
  3309. return rval;
  3310. }
  3311. int
  3312. qla2x00_echo_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
  3313. uint16_t *mresp)
  3314. {
  3315. int rval;
  3316. mbx_cmd_t mc;
  3317. mbx_cmd_t *mcp = &mc;
  3318. struct qla_hw_data *ha = vha->hw;
  3319. ql_dbg(ql_dbg_mbx, vha, 0x10fa, "Entered %s.\n", __func__);
  3320. memset(mcp->mb, 0 , sizeof(mcp->mb));
  3321. mcp->mb[0] = MBC_DIAGNOSTIC_ECHO;
  3322. mcp->mb[1] = mreq->options | BIT_6; /* BIT_6 specifies 64bit address */
  3323. if (IS_QLA8XXX_TYPE(ha)) {
  3324. mcp->mb[1] |= BIT_15;
  3325. mcp->mb[2] = vha->fcoe_fcf_idx;
  3326. }
  3327. mcp->mb[16] = LSW(mreq->rcv_dma);
  3328. mcp->mb[17] = MSW(mreq->rcv_dma);
  3329. mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
  3330. mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
  3331. mcp->mb[10] = LSW(mreq->transfer_size);
  3332. mcp->mb[14] = LSW(mreq->send_dma);
  3333. mcp->mb[15] = MSW(mreq->send_dma);
  3334. mcp->mb[20] = LSW(MSD(mreq->send_dma));
  3335. mcp->mb[21] = MSW(MSD(mreq->send_dma));
  3336. mcp->out_mb = MBX_21|MBX_20|MBX_17|MBX_16|MBX_15|
  3337. MBX_14|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
  3338. if (IS_QLA8XXX_TYPE(ha))
  3339. mcp->out_mb |= MBX_2;
  3340. mcp->in_mb = MBX_0;
  3341. if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha) || IS_QLA8XXX_TYPE(ha))
  3342. mcp->in_mb |= MBX_1;
  3343. if (IS_QLA8XXX_TYPE(ha))
  3344. mcp->in_mb |= MBX_3;
  3345. mcp->tov = MBX_TOV_SECONDS;
  3346. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  3347. mcp->buf_size = mreq->transfer_size;
  3348. rval = qla2x00_mailbox_command(vha, mcp);
  3349. if (rval != QLA_SUCCESS) {
  3350. ql_dbg(ql_dbg_mbx, vha, 0x10fb,
  3351. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  3352. rval, mcp->mb[0], mcp->mb[1]);
  3353. } else {
  3354. ql_dbg(ql_dbg_mbx, vha, 0x10fc, "Done %s.\n", __func__);
  3355. }
  3356. /* Copy mailbox information */
  3357. memcpy(mresp, mcp->mb, 64);
  3358. return rval;
  3359. }
  3360. int
  3361. qla84xx_reset_chip(scsi_qla_host_t *vha, uint16_t enable_diagnostic)
  3362. {
  3363. int rval;
  3364. mbx_cmd_t mc;
  3365. mbx_cmd_t *mcp = &mc;
  3366. ql_dbg(ql_dbg_mbx, vha, 0x10fd,
  3367. "Entered %s enable_diag=%d.\n", __func__, enable_diagnostic);
  3368. mcp->mb[0] = MBC_ISP84XX_RESET;
  3369. mcp->mb[1] = enable_diagnostic;
  3370. mcp->out_mb = MBX_1|MBX_0;
  3371. mcp->in_mb = MBX_1|MBX_0;
  3372. mcp->tov = MBX_TOV_SECONDS;
  3373. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  3374. rval = qla2x00_mailbox_command(vha, mcp);
  3375. if (rval != QLA_SUCCESS)
  3376. ql_dbg(ql_dbg_mbx, vha, 0x10fe, "Failed=%x.\n", rval);
  3377. else
  3378. ql_dbg(ql_dbg_mbx, vha, 0x10ff, "Done %s.\n", __func__);
  3379. return rval;
  3380. }
  3381. int
  3382. qla2x00_write_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t data)
  3383. {
  3384. int rval;
  3385. mbx_cmd_t mc;
  3386. mbx_cmd_t *mcp = &mc;
  3387. ql_dbg(ql_dbg_mbx, vha, 0x1100, "Entered %s.\n", __func__);
  3388. if (!IS_FWI2_CAPABLE(vha->hw))
  3389. return QLA_FUNCTION_FAILED;
  3390. mcp->mb[0] = MBC_WRITE_RAM_WORD_EXTENDED;
  3391. mcp->mb[1] = LSW(risc_addr);
  3392. mcp->mb[2] = LSW(data);
  3393. mcp->mb[3] = MSW(data);
  3394. mcp->mb[8] = MSW(risc_addr);
  3395. mcp->out_mb = MBX_8|MBX_3|MBX_2|MBX_1|MBX_0;
  3396. mcp->in_mb = MBX_0;
  3397. mcp->tov = 30;
  3398. mcp->flags = 0;
  3399. rval = qla2x00_mailbox_command(vha, mcp);
  3400. if (rval != QLA_SUCCESS) {
  3401. ql_dbg(ql_dbg_mbx, vha, 0x1101,
  3402. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3403. } else {
  3404. ql_dbg(ql_dbg_mbx, vha, 0x1102, "Done %s.\n", __func__);
  3405. }
  3406. return rval;
  3407. }
  3408. int
  3409. qla81xx_write_mpi_register(scsi_qla_host_t *vha, uint16_t *mb)
  3410. {
  3411. int rval;
  3412. uint32_t stat, timer;
  3413. uint16_t mb0 = 0;
  3414. struct qla_hw_data *ha = vha->hw;
  3415. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  3416. rval = QLA_SUCCESS;
  3417. ql_dbg(ql_dbg_mbx, vha, 0x1103, "Entered %s.\n", __func__);
  3418. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  3419. /* Write the MBC data to the registers */
  3420. WRT_REG_WORD(&reg->mailbox0, MBC_WRITE_MPI_REGISTER);
  3421. WRT_REG_WORD(&reg->mailbox1, mb[0]);
  3422. WRT_REG_WORD(&reg->mailbox2, mb[1]);
  3423. WRT_REG_WORD(&reg->mailbox3, mb[2]);
  3424. WRT_REG_WORD(&reg->mailbox4, mb[3]);
  3425. WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
  3426. /* Poll for MBC interrupt */
  3427. for (timer = 6000000; timer; timer--) {
  3428. /* Check for pending interrupts. */
  3429. stat = RD_REG_DWORD(&reg->host_status);
  3430. if (stat & HSRX_RISC_INT) {
  3431. stat &= 0xff;
  3432. if (stat == 0x1 || stat == 0x2 ||
  3433. stat == 0x10 || stat == 0x11) {
  3434. set_bit(MBX_INTERRUPT,
  3435. &ha->mbx_cmd_flags);
  3436. mb0 = RD_REG_WORD(&reg->mailbox0);
  3437. WRT_REG_DWORD(&reg->hccr,
  3438. HCCRX_CLR_RISC_INT);
  3439. RD_REG_DWORD(&reg->hccr);
  3440. break;
  3441. }
  3442. }
  3443. udelay(5);
  3444. }
  3445. if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags))
  3446. rval = mb0 & MBS_MASK;
  3447. else
  3448. rval = QLA_FUNCTION_FAILED;
  3449. if (rval != QLA_SUCCESS) {
  3450. ql_dbg(ql_dbg_mbx, vha, 0x1104,
  3451. "Failed=%x mb[0]=%x.\n", rval, mb[0]);
  3452. } else {
  3453. ql_dbg(ql_dbg_mbx, vha, 0x1105, "Done %s.\n", __func__);
  3454. }
  3455. return rval;
  3456. }
  3457. int
  3458. qla2x00_get_data_rate(scsi_qla_host_t *vha)
  3459. {
  3460. int rval;
  3461. mbx_cmd_t mc;
  3462. mbx_cmd_t *mcp = &mc;
  3463. struct qla_hw_data *ha = vha->hw;
  3464. ql_dbg(ql_dbg_mbx, vha, 0x1106, "Entered %s.\n", __func__);
  3465. if (!IS_FWI2_CAPABLE(ha))
  3466. return QLA_FUNCTION_FAILED;
  3467. mcp->mb[0] = MBC_DATA_RATE;
  3468. mcp->mb[1] = 0;
  3469. mcp->out_mb = MBX_1|MBX_0;
  3470. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  3471. mcp->tov = MBX_TOV_SECONDS;
  3472. mcp->flags = 0;
  3473. rval = qla2x00_mailbox_command(vha, mcp);
  3474. if (rval != QLA_SUCCESS) {
  3475. ql_dbg(ql_dbg_mbx, vha, 0x1107,
  3476. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3477. } else {
  3478. ql_dbg(ql_dbg_mbx, vha, 0x1108, "Done %s.\n", __func__);
  3479. if (mcp->mb[1] != 0x7)
  3480. ha->link_data_rate = mcp->mb[1];
  3481. }
  3482. return rval;
  3483. }
  3484. int
  3485. qla81xx_get_port_config(scsi_qla_host_t *vha, uint16_t *mb)
  3486. {
  3487. int rval;
  3488. mbx_cmd_t mc;
  3489. mbx_cmd_t *mcp = &mc;
  3490. struct qla_hw_data *ha = vha->hw;
  3491. ql_dbg(ql_dbg_mbx, vha, 0x1109, "Entered %s.\n", __func__);
  3492. if (!IS_QLA81XX(ha))
  3493. return QLA_FUNCTION_FAILED;
  3494. mcp->mb[0] = MBC_GET_PORT_CONFIG;
  3495. mcp->out_mb = MBX_0;
  3496. mcp->in_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3497. mcp->tov = MBX_TOV_SECONDS;
  3498. mcp->flags = 0;
  3499. rval = qla2x00_mailbox_command(vha, mcp);
  3500. if (rval != QLA_SUCCESS) {
  3501. ql_dbg(ql_dbg_mbx, vha, 0x110a,
  3502. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3503. } else {
  3504. /* Copy all bits to preserve original value */
  3505. memcpy(mb, &mcp->mb[1], sizeof(uint16_t) * 4);
  3506. ql_dbg(ql_dbg_mbx, vha, 0x110b, "Done %s.\n", __func__);
  3507. }
  3508. return rval;
  3509. }
  3510. int
  3511. qla81xx_set_port_config(scsi_qla_host_t *vha, uint16_t *mb)
  3512. {
  3513. int rval;
  3514. mbx_cmd_t mc;
  3515. mbx_cmd_t *mcp = &mc;
  3516. ql_dbg(ql_dbg_mbx, vha, 0x110c, "Entered %s.\n", __func__);
  3517. mcp->mb[0] = MBC_SET_PORT_CONFIG;
  3518. /* Copy all bits to preserve original setting */
  3519. memcpy(&mcp->mb[1], mb, sizeof(uint16_t) * 4);
  3520. mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3521. mcp->in_mb = MBX_0;
  3522. mcp->tov = MBX_TOV_SECONDS;
  3523. mcp->flags = 0;
  3524. rval = qla2x00_mailbox_command(vha, mcp);
  3525. if (rval != QLA_SUCCESS) {
  3526. ql_dbg(ql_dbg_mbx, vha, 0x110d,
  3527. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3528. } else
  3529. ql_dbg(ql_dbg_mbx, vha, 0x110e, "Done %s.\n", __func__);
  3530. return rval;
  3531. }
  3532. int
  3533. qla24xx_set_fcp_prio(scsi_qla_host_t *vha, uint16_t loop_id, uint16_t priority,
  3534. uint16_t *mb)
  3535. {
  3536. int rval;
  3537. mbx_cmd_t mc;
  3538. mbx_cmd_t *mcp = &mc;
  3539. struct qla_hw_data *ha = vha->hw;
  3540. ql_dbg(ql_dbg_mbx, vha, 0x110f, "Entered %s.\n", __func__);
  3541. if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha))
  3542. return QLA_FUNCTION_FAILED;
  3543. mcp->mb[0] = MBC_PORT_PARAMS;
  3544. mcp->mb[1] = loop_id;
  3545. if (ha->flags.fcp_prio_enabled)
  3546. mcp->mb[2] = BIT_1;
  3547. else
  3548. mcp->mb[2] = BIT_2;
  3549. mcp->mb[4] = priority & 0xf;
  3550. mcp->mb[9] = vha->vp_idx;
  3551. mcp->out_mb = MBX_9|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3552. mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
  3553. mcp->tov = 30;
  3554. mcp->flags = 0;
  3555. rval = qla2x00_mailbox_command(vha, mcp);
  3556. if (mb != NULL) {
  3557. mb[0] = mcp->mb[0];
  3558. mb[1] = mcp->mb[1];
  3559. mb[3] = mcp->mb[3];
  3560. mb[4] = mcp->mb[4];
  3561. }
  3562. if (rval != QLA_SUCCESS) {
  3563. ql_dbg(ql_dbg_mbx, vha, 0x10cd, "Failed=%x.\n", rval);
  3564. } else {
  3565. ql_dbg(ql_dbg_mbx, vha, 0x10cc, "Done %s.\n", __func__);
  3566. }
  3567. return rval;
  3568. }
  3569. int
  3570. qla2x00_get_thermal_temp(scsi_qla_host_t *vha, uint16_t *temp, uint16_t *frac)
  3571. {
  3572. int rval;
  3573. uint8_t byte;
  3574. struct qla_hw_data *ha = vha->hw;
  3575. ql_dbg(ql_dbg_mbx, vha, 0x10ca, "Entered %s.\n", __func__);
  3576. /* Integer part */
  3577. rval = qla2x00_read_sfp(vha, 0, &byte, 0x98, 0x01, 1, BIT_13|BIT_0);
  3578. if (rval != QLA_SUCCESS) {
  3579. ql_dbg(ql_dbg_mbx, vha, 0x10c9, "Failed=%x.\n", rval);
  3580. ha->flags.thermal_supported = 0;
  3581. goto fail;
  3582. }
  3583. *temp = byte;
  3584. /* Fraction part */
  3585. rval = qla2x00_read_sfp(vha, 0, &byte, 0x98, 0x10, 1, BIT_13|BIT_0);
  3586. if (rval != QLA_SUCCESS) {
  3587. ql_dbg(ql_dbg_mbx, vha, 0x1019, "Failed=%x.\n", rval);
  3588. ha->flags.thermal_supported = 0;
  3589. goto fail;
  3590. }
  3591. *frac = (byte >> 6) * 25;
  3592. ql_dbg(ql_dbg_mbx, vha, 0x1018, "Done %s.\n", __func__);
  3593. fail:
  3594. return rval;
  3595. }
  3596. int
  3597. qla82xx_mbx_intr_enable(scsi_qla_host_t *vha)
  3598. {
  3599. int rval;
  3600. struct qla_hw_data *ha = vha->hw;
  3601. mbx_cmd_t mc;
  3602. mbx_cmd_t *mcp = &mc;
  3603. ql_dbg(ql_dbg_mbx, vha, 0x1017, "Entered %s.\n", __func__);
  3604. if (!IS_FWI2_CAPABLE(ha))
  3605. return QLA_FUNCTION_FAILED;
  3606. memset(mcp, 0, sizeof(mbx_cmd_t));
  3607. mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
  3608. mcp->mb[1] = 1;
  3609. mcp->out_mb = MBX_1|MBX_0;
  3610. mcp->in_mb = MBX_0;
  3611. mcp->tov = 30;
  3612. mcp->flags = 0;
  3613. rval = qla2x00_mailbox_command(vha, mcp);
  3614. if (rval != QLA_SUCCESS) {
  3615. ql_dbg(ql_dbg_mbx, vha, 0x1016,
  3616. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3617. } else {
  3618. ql_dbg(ql_dbg_mbx, vha, 0x100e, "Done %s.\n", __func__);
  3619. }
  3620. return rval;
  3621. }
  3622. int
  3623. qla82xx_mbx_intr_disable(scsi_qla_host_t *vha)
  3624. {
  3625. int rval;
  3626. struct qla_hw_data *ha = vha->hw;
  3627. mbx_cmd_t mc;
  3628. mbx_cmd_t *mcp = &mc;
  3629. ql_dbg(ql_dbg_mbx, vha, 0x100d, "Entered %s.\n", __func__);
  3630. if (!IS_QLA82XX(ha))
  3631. return QLA_FUNCTION_FAILED;
  3632. memset(mcp, 0, sizeof(mbx_cmd_t));
  3633. mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
  3634. mcp->mb[1] = 0;
  3635. mcp->out_mb = MBX_1|MBX_0;
  3636. mcp->in_mb = MBX_0;
  3637. mcp->tov = 30;
  3638. mcp->flags = 0;
  3639. rval = qla2x00_mailbox_command(vha, mcp);
  3640. if (rval != QLA_SUCCESS) {
  3641. ql_dbg(ql_dbg_mbx, vha, 0x100c,
  3642. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3643. } else {
  3644. ql_dbg(ql_dbg_mbx, vha, 0x100b, "Done %s.\n", __func__);
  3645. }
  3646. return rval;
  3647. }
  3648. int
  3649. qla82xx_md_get_template_size(scsi_qla_host_t *vha)
  3650. {
  3651. struct qla_hw_data *ha = vha->hw;
  3652. mbx_cmd_t mc;
  3653. mbx_cmd_t *mcp = &mc;
  3654. int rval = QLA_FUNCTION_FAILED;
  3655. ql_dbg(ql_dbg_mbx, vha, 0x111f, "Entered %s.\n", __func__);
  3656. memset(mcp->mb, 0 , sizeof(mcp->mb));
  3657. mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
  3658. mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
  3659. mcp->mb[2] = LSW(RQST_TMPLT_SIZE);
  3660. mcp->mb[3] = MSW(RQST_TMPLT_SIZE);
  3661. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  3662. mcp->in_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
  3663. MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3664. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  3665. mcp->tov = MBX_TOV_SECONDS;
  3666. rval = qla2x00_mailbox_command(vha, mcp);
  3667. /* Always copy back return mailbox values. */
  3668. if (rval != QLA_SUCCESS) {
  3669. ql_dbg(ql_dbg_mbx, vha, 0x1120,
  3670. "mailbox command FAILED=0x%x, subcode=%x.\n",
  3671. (mcp->mb[1] << 16) | mcp->mb[0],
  3672. (mcp->mb[3] << 16) | mcp->mb[2]);
  3673. } else {
  3674. ql_dbg(ql_dbg_mbx, vha, 0x1121, "Done %s.\n", __func__);
  3675. ha->md_template_size = ((mcp->mb[3] << 16) | mcp->mb[2]);
  3676. if (!ha->md_template_size) {
  3677. ql_dbg(ql_dbg_mbx, vha, 0x1122,
  3678. "Null template size obtained.\n");
  3679. rval = QLA_FUNCTION_FAILED;
  3680. }
  3681. }
  3682. return rval;
  3683. }
  3684. int
  3685. qla82xx_md_get_template(scsi_qla_host_t *vha)
  3686. {
  3687. struct qla_hw_data *ha = vha->hw;
  3688. mbx_cmd_t mc;
  3689. mbx_cmd_t *mcp = &mc;
  3690. int rval = QLA_FUNCTION_FAILED;
  3691. ql_dbg(ql_dbg_mbx, vha, 0x1123, "Entered %s.\n", __func__);
  3692. ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
  3693. ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
  3694. if (!ha->md_tmplt_hdr) {
  3695. ql_log(ql_log_warn, vha, 0x1124,
  3696. "Unable to allocate memory for Minidump template.\n");
  3697. return rval;
  3698. }
  3699. memset(mcp->mb, 0 , sizeof(mcp->mb));
  3700. mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
  3701. mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
  3702. mcp->mb[2] = LSW(RQST_TMPLT);
  3703. mcp->mb[3] = MSW(RQST_TMPLT);
  3704. mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma));
  3705. mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma));
  3706. mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma));
  3707. mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma));
  3708. mcp->mb[8] = LSW(ha->md_template_size);
  3709. mcp->mb[9] = MSW(ha->md_template_size);
  3710. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  3711. mcp->tov = MBX_TOV_SECONDS;
  3712. mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
  3713. MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3714. mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  3715. rval = qla2x00_mailbox_command(vha, mcp);
  3716. if (rval != QLA_SUCCESS) {
  3717. ql_dbg(ql_dbg_mbx, vha, 0x1125,
  3718. "mailbox command FAILED=0x%x, subcode=%x.\n",
  3719. ((mcp->mb[1] << 16) | mcp->mb[0]),
  3720. ((mcp->mb[3] << 16) | mcp->mb[2]));
  3721. } else
  3722. ql_dbg(ql_dbg_mbx, vha, 0x1126, "Done %s.\n", __func__);
  3723. return rval;
  3724. }
  3725. int
  3726. qla82xx_mbx_beacon_ctl(scsi_qla_host_t *vha, int enable)
  3727. {
  3728. int rval;
  3729. struct qla_hw_data *ha = vha->hw;
  3730. mbx_cmd_t mc;
  3731. mbx_cmd_t *mcp = &mc;
  3732. if (!IS_QLA82XX(ha))
  3733. return QLA_FUNCTION_FAILED;
  3734. ql_dbg(ql_dbg_mbx, vha, 0x1127,
  3735. "Entered %s.\n", __func__);
  3736. memset(mcp, 0, sizeof(mbx_cmd_t));
  3737. mcp->mb[0] = MBC_SET_LED_CONFIG;
  3738. if (enable)
  3739. mcp->mb[7] = 0xE;
  3740. else
  3741. mcp->mb[7] = 0xD;
  3742. mcp->out_mb = MBX_7|MBX_0;
  3743. mcp->in_mb = MBX_0;
  3744. mcp->tov = 30;
  3745. mcp->flags = 0;
  3746. rval = qla2x00_mailbox_command(vha, mcp);
  3747. if (rval != QLA_SUCCESS) {
  3748. ql_dbg(ql_dbg_mbx, vha, 0x1128,
  3749. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3750. } else {
  3751. ql_dbg(ql_dbg_mbx, vha, 0x1129,
  3752. "Done %s.\n", __func__);
  3753. }
  3754. return rval;
  3755. }