mv_sas.c 56 KB

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  1. /*
  2. * Marvell 88SE64xx/88SE94xx main function
  3. *
  4. * Copyright 2007 Red Hat, Inc.
  5. * Copyright 2008 Marvell. <kewei@marvell.com>
  6. * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
  7. *
  8. * This file is licensed under GPLv2.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; version 2 of the
  13. * License.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  18. * General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
  23. * USA
  24. */
  25. #include "mv_sas.h"
  26. static int mvs_find_tag(struct mvs_info *mvi, struct sas_task *task, u32 *tag)
  27. {
  28. if (task->lldd_task) {
  29. struct mvs_slot_info *slot;
  30. slot = task->lldd_task;
  31. *tag = slot->slot_tag;
  32. return 1;
  33. }
  34. return 0;
  35. }
  36. void mvs_tag_clear(struct mvs_info *mvi, u32 tag)
  37. {
  38. void *bitmap = mvi->tags;
  39. clear_bit(tag, bitmap);
  40. }
  41. void mvs_tag_free(struct mvs_info *mvi, u32 tag)
  42. {
  43. mvs_tag_clear(mvi, tag);
  44. }
  45. void mvs_tag_set(struct mvs_info *mvi, unsigned int tag)
  46. {
  47. void *bitmap = mvi->tags;
  48. set_bit(tag, bitmap);
  49. }
  50. inline int mvs_tag_alloc(struct mvs_info *mvi, u32 *tag_out)
  51. {
  52. unsigned int index, tag;
  53. void *bitmap = mvi->tags;
  54. index = find_first_zero_bit(bitmap, mvi->tags_num);
  55. tag = index;
  56. if (tag >= mvi->tags_num)
  57. return -SAS_QUEUE_FULL;
  58. mvs_tag_set(mvi, tag);
  59. *tag_out = tag;
  60. return 0;
  61. }
  62. void mvs_tag_init(struct mvs_info *mvi)
  63. {
  64. int i;
  65. for (i = 0; i < mvi->tags_num; ++i)
  66. mvs_tag_clear(mvi, i);
  67. }
  68. struct mvs_info *mvs_find_dev_mvi(struct domain_device *dev)
  69. {
  70. unsigned long i = 0, j = 0, hi = 0;
  71. struct sas_ha_struct *sha = dev->port->ha;
  72. struct mvs_info *mvi = NULL;
  73. struct asd_sas_phy *phy;
  74. while (sha->sas_port[i]) {
  75. if (sha->sas_port[i] == dev->port) {
  76. phy = container_of(sha->sas_port[i]->phy_list.next,
  77. struct asd_sas_phy, port_phy_el);
  78. j = 0;
  79. while (sha->sas_phy[j]) {
  80. if (sha->sas_phy[j] == phy)
  81. break;
  82. j++;
  83. }
  84. break;
  85. }
  86. i++;
  87. }
  88. hi = j/((struct mvs_prv_info *)sha->lldd_ha)->n_phy;
  89. mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[hi];
  90. return mvi;
  91. }
  92. int mvs_find_dev_phyno(struct domain_device *dev, int *phyno)
  93. {
  94. unsigned long i = 0, j = 0, n = 0, num = 0;
  95. struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
  96. struct mvs_info *mvi = mvi_dev->mvi_info;
  97. struct sas_ha_struct *sha = dev->port->ha;
  98. while (sha->sas_port[i]) {
  99. if (sha->sas_port[i] == dev->port) {
  100. struct asd_sas_phy *phy;
  101. list_for_each_entry(phy,
  102. &sha->sas_port[i]->phy_list, port_phy_el) {
  103. j = 0;
  104. while (sha->sas_phy[j]) {
  105. if (sha->sas_phy[j] == phy)
  106. break;
  107. j++;
  108. }
  109. phyno[n] = (j >= mvi->chip->n_phy) ?
  110. (j - mvi->chip->n_phy) : j;
  111. num++;
  112. n++;
  113. }
  114. break;
  115. }
  116. i++;
  117. }
  118. return num;
  119. }
  120. struct mvs_device *mvs_find_dev_by_reg_set(struct mvs_info *mvi,
  121. u8 reg_set)
  122. {
  123. u32 dev_no;
  124. for (dev_no = 0; dev_no < MVS_MAX_DEVICES; dev_no++) {
  125. if (mvi->devices[dev_no].taskfileset == MVS_ID_NOT_MAPPED)
  126. continue;
  127. if (mvi->devices[dev_no].taskfileset == reg_set)
  128. return &mvi->devices[dev_no];
  129. }
  130. return NULL;
  131. }
  132. static inline void mvs_free_reg_set(struct mvs_info *mvi,
  133. struct mvs_device *dev)
  134. {
  135. if (!dev) {
  136. mv_printk("device has been free.\n");
  137. return;
  138. }
  139. if (dev->taskfileset == MVS_ID_NOT_MAPPED)
  140. return;
  141. MVS_CHIP_DISP->free_reg_set(mvi, &dev->taskfileset);
  142. }
  143. static inline u8 mvs_assign_reg_set(struct mvs_info *mvi,
  144. struct mvs_device *dev)
  145. {
  146. if (dev->taskfileset != MVS_ID_NOT_MAPPED)
  147. return 0;
  148. return MVS_CHIP_DISP->assign_reg_set(mvi, &dev->taskfileset);
  149. }
  150. void mvs_phys_reset(struct mvs_info *mvi, u32 phy_mask, int hard)
  151. {
  152. u32 no;
  153. for_each_phy(phy_mask, phy_mask, no) {
  154. if (!(phy_mask & 1))
  155. continue;
  156. MVS_CHIP_DISP->phy_reset(mvi, no, hard);
  157. }
  158. }
  159. int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
  160. void *funcdata)
  161. {
  162. int rc = 0, phy_id = sas_phy->id;
  163. u32 tmp, i = 0, hi;
  164. struct sas_ha_struct *sha = sas_phy->ha;
  165. struct mvs_info *mvi = NULL;
  166. while (sha->sas_phy[i]) {
  167. if (sha->sas_phy[i] == sas_phy)
  168. break;
  169. i++;
  170. }
  171. hi = i/((struct mvs_prv_info *)sha->lldd_ha)->n_phy;
  172. mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[hi];
  173. switch (func) {
  174. case PHY_FUNC_SET_LINK_RATE:
  175. MVS_CHIP_DISP->phy_set_link_rate(mvi, phy_id, funcdata);
  176. break;
  177. case PHY_FUNC_HARD_RESET:
  178. tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_id);
  179. if (tmp & PHY_RST_HARD)
  180. break;
  181. MVS_CHIP_DISP->phy_reset(mvi, phy_id, MVS_HARD_RESET);
  182. break;
  183. case PHY_FUNC_LINK_RESET:
  184. MVS_CHIP_DISP->phy_enable(mvi, phy_id);
  185. MVS_CHIP_DISP->phy_reset(mvi, phy_id, MVS_SOFT_RESET);
  186. break;
  187. case PHY_FUNC_DISABLE:
  188. MVS_CHIP_DISP->phy_disable(mvi, phy_id);
  189. break;
  190. case PHY_FUNC_RELEASE_SPINUP_HOLD:
  191. default:
  192. rc = -ENOSYS;
  193. }
  194. msleep(200);
  195. return rc;
  196. }
  197. void __devinit mvs_set_sas_addr(struct mvs_info *mvi, int port_id,
  198. u32 off_lo, u32 off_hi, u64 sas_addr)
  199. {
  200. u32 lo = (u32)sas_addr;
  201. u32 hi = (u32)(sas_addr>>32);
  202. MVS_CHIP_DISP->write_port_cfg_addr(mvi, port_id, off_lo);
  203. MVS_CHIP_DISP->write_port_cfg_data(mvi, port_id, lo);
  204. MVS_CHIP_DISP->write_port_cfg_addr(mvi, port_id, off_hi);
  205. MVS_CHIP_DISP->write_port_cfg_data(mvi, port_id, hi);
  206. }
  207. static void mvs_bytes_dmaed(struct mvs_info *mvi, int i)
  208. {
  209. struct mvs_phy *phy = &mvi->phy[i];
  210. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  211. struct sas_ha_struct *sas_ha;
  212. if (!phy->phy_attached)
  213. return;
  214. if (!(phy->att_dev_info & PORT_DEV_TRGT_MASK)
  215. && phy->phy_type & PORT_TYPE_SAS) {
  216. return;
  217. }
  218. sas_ha = mvi->sas;
  219. sas_ha->notify_phy_event(sas_phy, PHYE_OOB_DONE);
  220. if (sas_phy->phy) {
  221. struct sas_phy *sphy = sas_phy->phy;
  222. sphy->negotiated_linkrate = sas_phy->linkrate;
  223. sphy->minimum_linkrate = phy->minimum_linkrate;
  224. sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
  225. sphy->maximum_linkrate = phy->maximum_linkrate;
  226. sphy->maximum_linkrate_hw = MVS_CHIP_DISP->phy_max_link_rate();
  227. }
  228. if (phy->phy_type & PORT_TYPE_SAS) {
  229. struct sas_identify_frame *id;
  230. id = (struct sas_identify_frame *)phy->frame_rcvd;
  231. id->dev_type = phy->identify.device_type;
  232. id->initiator_bits = SAS_PROTOCOL_ALL;
  233. id->target_bits = phy->identify.target_port_protocols;
  234. /* direct attached SAS device */
  235. if (phy->att_dev_info & PORT_SSP_TRGT_MASK) {
  236. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_PHY_STAT);
  237. MVS_CHIP_DISP->write_port_cfg_data(mvi, i, 0x00);
  238. }
  239. } else if (phy->phy_type & PORT_TYPE_SATA) {
  240. /*Nothing*/
  241. }
  242. mv_dprintk("phy %d byte dmaded.\n", i + mvi->id * mvi->chip->n_phy);
  243. sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
  244. mvi->sas->notify_port_event(sas_phy,
  245. PORTE_BYTES_DMAED);
  246. }
  247. void mvs_scan_start(struct Scsi_Host *shost)
  248. {
  249. int i, j;
  250. unsigned short core_nr;
  251. struct mvs_info *mvi;
  252. struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
  253. struct mvs_prv_info *mvs_prv = sha->lldd_ha;
  254. core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
  255. for (j = 0; j < core_nr; j++) {
  256. mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j];
  257. for (i = 0; i < mvi->chip->n_phy; ++i)
  258. mvs_bytes_dmaed(mvi, i);
  259. }
  260. mvs_prv->scan_finished = 1;
  261. }
  262. int mvs_scan_finished(struct Scsi_Host *shost, unsigned long time)
  263. {
  264. struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
  265. struct mvs_prv_info *mvs_prv = sha->lldd_ha;
  266. if (mvs_prv->scan_finished == 0)
  267. return 0;
  268. scsi_flush_work(shost);
  269. return 1;
  270. }
  271. static int mvs_task_prep_smp(struct mvs_info *mvi,
  272. struct mvs_task_exec_info *tei)
  273. {
  274. int elem, rc, i;
  275. struct sas_task *task = tei->task;
  276. struct mvs_cmd_hdr *hdr = tei->hdr;
  277. struct domain_device *dev = task->dev;
  278. struct asd_sas_port *sas_port = dev->port;
  279. struct scatterlist *sg_req, *sg_resp;
  280. u32 req_len, resp_len, tag = tei->tag;
  281. void *buf_tmp;
  282. u8 *buf_oaf;
  283. dma_addr_t buf_tmp_dma;
  284. void *buf_prd;
  285. struct mvs_slot_info *slot = &mvi->slot_info[tag];
  286. u32 flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
  287. /*
  288. * DMA-map SMP request, response buffers
  289. */
  290. sg_req = &task->smp_task.smp_req;
  291. elem = dma_map_sg(mvi->dev, sg_req, 1, PCI_DMA_TODEVICE);
  292. if (!elem)
  293. return -ENOMEM;
  294. req_len = sg_dma_len(sg_req);
  295. sg_resp = &task->smp_task.smp_resp;
  296. elem = dma_map_sg(mvi->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
  297. if (!elem) {
  298. rc = -ENOMEM;
  299. goto err_out;
  300. }
  301. resp_len = SB_RFB_MAX;
  302. /* must be in dwords */
  303. if ((req_len & 0x3) || (resp_len & 0x3)) {
  304. rc = -EINVAL;
  305. goto err_out_2;
  306. }
  307. /*
  308. * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
  309. */
  310. /* region 1: command table area (MVS_SSP_CMD_SZ bytes) ***** */
  311. buf_tmp = slot->buf;
  312. buf_tmp_dma = slot->buf_dma;
  313. hdr->cmd_tbl = cpu_to_le64(sg_dma_address(sg_req));
  314. /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
  315. buf_oaf = buf_tmp;
  316. hdr->open_frame = cpu_to_le64(buf_tmp_dma);
  317. buf_tmp += MVS_OAF_SZ;
  318. buf_tmp_dma += MVS_OAF_SZ;
  319. /* region 3: PRD table *********************************** */
  320. buf_prd = buf_tmp;
  321. if (tei->n_elem)
  322. hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
  323. else
  324. hdr->prd_tbl = 0;
  325. i = MVS_CHIP_DISP->prd_size() * tei->n_elem;
  326. buf_tmp += i;
  327. buf_tmp_dma += i;
  328. /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
  329. slot->response = buf_tmp;
  330. hdr->status_buf = cpu_to_le64(buf_tmp_dma);
  331. if (mvi->flags & MVF_FLAG_SOC)
  332. hdr->reserved[0] = 0;
  333. /*
  334. * Fill in TX ring and command slot header
  335. */
  336. slot->tx = mvi->tx_prod;
  337. mvi->tx[mvi->tx_prod] = cpu_to_le32((TXQ_CMD_SMP << TXQ_CMD_SHIFT) |
  338. TXQ_MODE_I | tag |
  339. (sas_port->phy_mask << TXQ_PHY_SHIFT));
  340. hdr->flags |= flags;
  341. hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | ((req_len - 4) / 4));
  342. hdr->tags = cpu_to_le32(tag);
  343. hdr->data_len = 0;
  344. /* generate open address frame hdr (first 12 bytes) */
  345. /* initiator, SMP, ftype 1h */
  346. buf_oaf[0] = (1 << 7) | (PROTOCOL_SMP << 4) | 0x01;
  347. buf_oaf[1] = min(sas_port->linkrate, dev->linkrate) & 0xf;
  348. *(u16 *)(buf_oaf + 2) = 0xFFFF; /* SAS SPEC */
  349. memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
  350. /* fill in PRD (scatter/gather) table, if any */
  351. MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
  352. return 0;
  353. err_out_2:
  354. dma_unmap_sg(mvi->dev, &tei->task->smp_task.smp_resp, 1,
  355. PCI_DMA_FROMDEVICE);
  356. err_out:
  357. dma_unmap_sg(mvi->dev, &tei->task->smp_task.smp_req, 1,
  358. PCI_DMA_TODEVICE);
  359. return rc;
  360. }
  361. static u32 mvs_get_ncq_tag(struct sas_task *task, u32 *tag)
  362. {
  363. struct ata_queued_cmd *qc = task->uldd_task;
  364. if (qc) {
  365. if (qc->tf.command == ATA_CMD_FPDMA_WRITE ||
  366. qc->tf.command == ATA_CMD_FPDMA_READ) {
  367. *tag = qc->tag;
  368. return 1;
  369. }
  370. }
  371. return 0;
  372. }
  373. static int mvs_task_prep_ata(struct mvs_info *mvi,
  374. struct mvs_task_exec_info *tei)
  375. {
  376. struct sas_task *task = tei->task;
  377. struct domain_device *dev = task->dev;
  378. struct mvs_device *mvi_dev = dev->lldd_dev;
  379. struct mvs_cmd_hdr *hdr = tei->hdr;
  380. struct asd_sas_port *sas_port = dev->port;
  381. struct mvs_slot_info *slot;
  382. void *buf_prd;
  383. u32 tag = tei->tag, hdr_tag;
  384. u32 flags, del_q;
  385. void *buf_tmp;
  386. u8 *buf_cmd, *buf_oaf;
  387. dma_addr_t buf_tmp_dma;
  388. u32 i, req_len, resp_len;
  389. const u32 max_resp_len = SB_RFB_MAX;
  390. if (mvs_assign_reg_set(mvi, mvi_dev) == MVS_ID_NOT_MAPPED) {
  391. mv_dprintk("Have not enough regiset for dev %d.\n",
  392. mvi_dev->device_id);
  393. return -EBUSY;
  394. }
  395. slot = &mvi->slot_info[tag];
  396. slot->tx = mvi->tx_prod;
  397. del_q = TXQ_MODE_I | tag |
  398. (TXQ_CMD_STP << TXQ_CMD_SHIFT) |
  399. (sas_port->phy_mask << TXQ_PHY_SHIFT) |
  400. (mvi_dev->taskfileset << TXQ_SRS_SHIFT);
  401. mvi->tx[mvi->tx_prod] = cpu_to_le32(del_q);
  402. if (task->data_dir == DMA_FROM_DEVICE)
  403. flags = (MVS_CHIP_DISP->prd_count() << MCH_PRD_LEN_SHIFT);
  404. else
  405. flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
  406. if (task->ata_task.use_ncq)
  407. flags |= MCH_FPDMA;
  408. if (dev->sata_dev.command_set == ATAPI_COMMAND_SET) {
  409. if (task->ata_task.fis.command != ATA_CMD_ID_ATAPI)
  410. flags |= MCH_ATAPI;
  411. }
  412. hdr->flags = cpu_to_le32(flags);
  413. if (task->ata_task.use_ncq && mvs_get_ncq_tag(task, &hdr_tag))
  414. task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
  415. else
  416. hdr_tag = tag;
  417. hdr->tags = cpu_to_le32(hdr_tag);
  418. hdr->data_len = cpu_to_le32(task->total_xfer_len);
  419. /*
  420. * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
  421. */
  422. /* region 1: command table area (MVS_ATA_CMD_SZ bytes) ************** */
  423. buf_cmd = buf_tmp = slot->buf;
  424. buf_tmp_dma = slot->buf_dma;
  425. hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
  426. buf_tmp += MVS_ATA_CMD_SZ;
  427. buf_tmp_dma += MVS_ATA_CMD_SZ;
  428. /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
  429. /* used for STP. unused for SATA? */
  430. buf_oaf = buf_tmp;
  431. hdr->open_frame = cpu_to_le64(buf_tmp_dma);
  432. buf_tmp += MVS_OAF_SZ;
  433. buf_tmp_dma += MVS_OAF_SZ;
  434. /* region 3: PRD table ********************************************* */
  435. buf_prd = buf_tmp;
  436. if (tei->n_elem)
  437. hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
  438. else
  439. hdr->prd_tbl = 0;
  440. i = MVS_CHIP_DISP->prd_size() * MVS_CHIP_DISP->prd_count();
  441. buf_tmp += i;
  442. buf_tmp_dma += i;
  443. /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
  444. slot->response = buf_tmp;
  445. hdr->status_buf = cpu_to_le64(buf_tmp_dma);
  446. if (mvi->flags & MVF_FLAG_SOC)
  447. hdr->reserved[0] = 0;
  448. req_len = sizeof(struct host_to_dev_fis);
  449. resp_len = MVS_SLOT_BUF_SZ - MVS_ATA_CMD_SZ -
  450. sizeof(struct mvs_err_info) - i;
  451. /* request, response lengths */
  452. resp_len = min(resp_len, max_resp_len);
  453. hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | (req_len / 4));
  454. if (likely(!task->ata_task.device_control_reg_update))
  455. task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
  456. /* fill in command FIS and ATAPI CDB */
  457. memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
  458. if (dev->sata_dev.command_set == ATAPI_COMMAND_SET)
  459. memcpy(buf_cmd + STP_ATAPI_CMD,
  460. task->ata_task.atapi_packet, 16);
  461. /* generate open address frame hdr (first 12 bytes) */
  462. /* initiator, STP, ftype 1h */
  463. buf_oaf[0] = (1 << 7) | (PROTOCOL_STP << 4) | 0x1;
  464. buf_oaf[1] = min(sas_port->linkrate, dev->linkrate) & 0xf;
  465. *(u16 *)(buf_oaf + 2) = cpu_to_be16(mvi_dev->device_id + 1);
  466. memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
  467. /* fill in PRD (scatter/gather) table, if any */
  468. MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
  469. if (task->data_dir == DMA_FROM_DEVICE)
  470. MVS_CHIP_DISP->dma_fix(mvi, sas_port->phy_mask,
  471. TRASH_BUCKET_SIZE, tei->n_elem, buf_prd);
  472. return 0;
  473. }
  474. static int mvs_task_prep_ssp(struct mvs_info *mvi,
  475. struct mvs_task_exec_info *tei, int is_tmf,
  476. struct mvs_tmf_task *tmf)
  477. {
  478. struct sas_task *task = tei->task;
  479. struct mvs_cmd_hdr *hdr = tei->hdr;
  480. struct mvs_port *port = tei->port;
  481. struct domain_device *dev = task->dev;
  482. struct mvs_device *mvi_dev = dev->lldd_dev;
  483. struct asd_sas_port *sas_port = dev->port;
  484. struct mvs_slot_info *slot;
  485. void *buf_prd;
  486. struct ssp_frame_hdr *ssp_hdr;
  487. void *buf_tmp;
  488. u8 *buf_cmd, *buf_oaf, fburst = 0;
  489. dma_addr_t buf_tmp_dma;
  490. u32 flags;
  491. u32 resp_len, req_len, i, tag = tei->tag;
  492. const u32 max_resp_len = SB_RFB_MAX;
  493. u32 phy_mask;
  494. slot = &mvi->slot_info[tag];
  495. phy_mask = ((port->wide_port_phymap) ? port->wide_port_phymap :
  496. sas_port->phy_mask) & TXQ_PHY_MASK;
  497. slot->tx = mvi->tx_prod;
  498. mvi->tx[mvi->tx_prod] = cpu_to_le32(TXQ_MODE_I | tag |
  499. (TXQ_CMD_SSP << TXQ_CMD_SHIFT) |
  500. (phy_mask << TXQ_PHY_SHIFT));
  501. flags = MCH_RETRY;
  502. if (task->ssp_task.enable_first_burst) {
  503. flags |= MCH_FBURST;
  504. fburst = (1 << 7);
  505. }
  506. if (is_tmf)
  507. flags |= (MCH_SSP_FR_TASK << MCH_SSP_FR_TYPE_SHIFT);
  508. else
  509. flags |= (MCH_SSP_FR_CMD << MCH_SSP_FR_TYPE_SHIFT);
  510. hdr->flags = cpu_to_le32(flags | (tei->n_elem << MCH_PRD_LEN_SHIFT));
  511. hdr->tags = cpu_to_le32(tag);
  512. hdr->data_len = cpu_to_le32(task->total_xfer_len);
  513. /*
  514. * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
  515. */
  516. /* region 1: command table area (MVS_SSP_CMD_SZ bytes) ************** */
  517. buf_cmd = buf_tmp = slot->buf;
  518. buf_tmp_dma = slot->buf_dma;
  519. hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
  520. buf_tmp += MVS_SSP_CMD_SZ;
  521. buf_tmp_dma += MVS_SSP_CMD_SZ;
  522. /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
  523. buf_oaf = buf_tmp;
  524. hdr->open_frame = cpu_to_le64(buf_tmp_dma);
  525. buf_tmp += MVS_OAF_SZ;
  526. buf_tmp_dma += MVS_OAF_SZ;
  527. /* region 3: PRD table ********************************************* */
  528. buf_prd = buf_tmp;
  529. if (tei->n_elem)
  530. hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
  531. else
  532. hdr->prd_tbl = 0;
  533. i = MVS_CHIP_DISP->prd_size() * tei->n_elem;
  534. buf_tmp += i;
  535. buf_tmp_dma += i;
  536. /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
  537. slot->response = buf_tmp;
  538. hdr->status_buf = cpu_to_le64(buf_tmp_dma);
  539. if (mvi->flags & MVF_FLAG_SOC)
  540. hdr->reserved[0] = 0;
  541. resp_len = MVS_SLOT_BUF_SZ - MVS_SSP_CMD_SZ - MVS_OAF_SZ -
  542. sizeof(struct mvs_err_info) - i;
  543. resp_len = min(resp_len, max_resp_len);
  544. req_len = sizeof(struct ssp_frame_hdr) + 28;
  545. /* request, response lengths */
  546. hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | (req_len / 4));
  547. /* generate open address frame hdr (first 12 bytes) */
  548. /* initiator, SSP, ftype 1h */
  549. buf_oaf[0] = (1 << 7) | (PROTOCOL_SSP << 4) | 0x1;
  550. buf_oaf[1] = min(sas_port->linkrate, dev->linkrate) & 0xf;
  551. *(u16 *)(buf_oaf + 2) = cpu_to_be16(mvi_dev->device_id + 1);
  552. memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
  553. /* fill in SSP frame header (Command Table.SSP frame header) */
  554. ssp_hdr = (struct ssp_frame_hdr *)buf_cmd;
  555. if (is_tmf)
  556. ssp_hdr->frame_type = SSP_TASK;
  557. else
  558. ssp_hdr->frame_type = SSP_COMMAND;
  559. memcpy(ssp_hdr->hashed_dest_addr, dev->hashed_sas_addr,
  560. HASHED_SAS_ADDR_SIZE);
  561. memcpy(ssp_hdr->hashed_src_addr,
  562. dev->hashed_sas_addr, HASHED_SAS_ADDR_SIZE);
  563. ssp_hdr->tag = cpu_to_be16(tag);
  564. /* fill in IU for TASK and Command Frame */
  565. buf_cmd += sizeof(*ssp_hdr);
  566. memcpy(buf_cmd, &task->ssp_task.LUN, 8);
  567. if (ssp_hdr->frame_type != SSP_TASK) {
  568. buf_cmd[9] = fburst | task->ssp_task.task_attr |
  569. (task->ssp_task.task_prio << 3);
  570. memcpy(buf_cmd + 12, &task->ssp_task.cdb, 16);
  571. } else{
  572. buf_cmd[10] = tmf->tmf;
  573. switch (tmf->tmf) {
  574. case TMF_ABORT_TASK:
  575. case TMF_QUERY_TASK:
  576. buf_cmd[12] =
  577. (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
  578. buf_cmd[13] =
  579. tmf->tag_of_task_to_be_managed & 0xff;
  580. break;
  581. default:
  582. break;
  583. }
  584. }
  585. /* fill in PRD (scatter/gather) table, if any */
  586. MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
  587. return 0;
  588. }
  589. #define DEV_IS_GONE(mvi_dev) ((!mvi_dev || (mvi_dev->dev_type == NO_DEVICE)))
  590. static int mvs_task_prep(struct sas_task *task, struct mvs_info *mvi, int is_tmf,
  591. struct mvs_tmf_task *tmf, int *pass)
  592. {
  593. struct domain_device *dev = task->dev;
  594. struct mvs_device *mvi_dev = dev->lldd_dev;
  595. struct mvs_task_exec_info tei;
  596. struct mvs_slot_info *slot;
  597. u32 tag = 0xdeadbeef, n_elem = 0;
  598. int rc = 0;
  599. if (!dev->port) {
  600. struct task_status_struct *tsm = &task->task_status;
  601. tsm->resp = SAS_TASK_UNDELIVERED;
  602. tsm->stat = SAS_PHY_DOWN;
  603. /*
  604. * libsas will use dev->port, should
  605. * not call task_done for sata
  606. */
  607. if (dev->dev_type != SATA_DEV)
  608. task->task_done(task);
  609. return rc;
  610. }
  611. if (DEV_IS_GONE(mvi_dev)) {
  612. if (mvi_dev)
  613. mv_dprintk("device %d not ready.\n",
  614. mvi_dev->device_id);
  615. else
  616. mv_dprintk("device %016llx not ready.\n",
  617. SAS_ADDR(dev->sas_addr));
  618. rc = SAS_PHY_DOWN;
  619. return rc;
  620. }
  621. tei.port = dev->port->lldd_port;
  622. if (tei.port && !tei.port->port_attached && !tmf) {
  623. if (sas_protocol_ata(task->task_proto)) {
  624. struct task_status_struct *ts = &task->task_status;
  625. mv_dprintk("SATA/STP port %d does not attach"
  626. "device.\n", dev->port->id);
  627. ts->resp = SAS_TASK_COMPLETE;
  628. ts->stat = SAS_PHY_DOWN;
  629. task->task_done(task);
  630. } else {
  631. struct task_status_struct *ts = &task->task_status;
  632. mv_dprintk("SAS port %d does not attach"
  633. "device.\n", dev->port->id);
  634. ts->resp = SAS_TASK_UNDELIVERED;
  635. ts->stat = SAS_PHY_DOWN;
  636. task->task_done(task);
  637. }
  638. return rc;
  639. }
  640. if (!sas_protocol_ata(task->task_proto)) {
  641. if (task->num_scatter) {
  642. n_elem = dma_map_sg(mvi->dev,
  643. task->scatter,
  644. task->num_scatter,
  645. task->data_dir);
  646. if (!n_elem) {
  647. rc = -ENOMEM;
  648. goto prep_out;
  649. }
  650. }
  651. } else {
  652. n_elem = task->num_scatter;
  653. }
  654. rc = mvs_tag_alloc(mvi, &tag);
  655. if (rc)
  656. goto err_out;
  657. slot = &mvi->slot_info[tag];
  658. task->lldd_task = NULL;
  659. slot->n_elem = n_elem;
  660. slot->slot_tag = tag;
  661. slot->buf = pci_pool_alloc(mvi->dma_pool, GFP_ATOMIC, &slot->buf_dma);
  662. if (!slot->buf)
  663. goto err_out_tag;
  664. memset(slot->buf, 0, MVS_SLOT_BUF_SZ);
  665. tei.task = task;
  666. tei.hdr = &mvi->slot[tag];
  667. tei.tag = tag;
  668. tei.n_elem = n_elem;
  669. switch (task->task_proto) {
  670. case SAS_PROTOCOL_SMP:
  671. rc = mvs_task_prep_smp(mvi, &tei);
  672. break;
  673. case SAS_PROTOCOL_SSP:
  674. rc = mvs_task_prep_ssp(mvi, &tei, is_tmf, tmf);
  675. break;
  676. case SAS_PROTOCOL_SATA:
  677. case SAS_PROTOCOL_STP:
  678. case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
  679. rc = mvs_task_prep_ata(mvi, &tei);
  680. break;
  681. default:
  682. dev_printk(KERN_ERR, mvi->dev,
  683. "unknown sas_task proto: 0x%x\n",
  684. task->task_proto);
  685. rc = -EINVAL;
  686. break;
  687. }
  688. if (rc) {
  689. mv_dprintk("rc is %x\n", rc);
  690. goto err_out_slot_buf;
  691. }
  692. slot->task = task;
  693. slot->port = tei.port;
  694. task->lldd_task = slot;
  695. list_add_tail(&slot->entry, &tei.port->list);
  696. spin_lock(&task->task_state_lock);
  697. task->task_state_flags |= SAS_TASK_AT_INITIATOR;
  698. spin_unlock(&task->task_state_lock);
  699. mvi_dev->running_req++;
  700. ++(*pass);
  701. mvi->tx_prod = (mvi->tx_prod + 1) & (MVS_CHIP_SLOT_SZ - 1);
  702. return rc;
  703. err_out_slot_buf:
  704. pci_pool_free(mvi->dma_pool, slot->buf, slot->buf_dma);
  705. err_out_tag:
  706. mvs_tag_free(mvi, tag);
  707. err_out:
  708. dev_printk(KERN_ERR, mvi->dev, "mvsas prep failed[%d]!\n", rc);
  709. if (!sas_protocol_ata(task->task_proto))
  710. if (n_elem)
  711. dma_unmap_sg(mvi->dev, task->scatter, n_elem,
  712. task->data_dir);
  713. prep_out:
  714. return rc;
  715. }
  716. static struct mvs_task_list *mvs_task_alloc_list(int *num, gfp_t gfp_flags)
  717. {
  718. struct mvs_task_list *first = NULL;
  719. for (; *num > 0; --*num) {
  720. struct mvs_task_list *mvs_list = kmem_cache_zalloc(mvs_task_list_cache, gfp_flags);
  721. if (!mvs_list)
  722. break;
  723. INIT_LIST_HEAD(&mvs_list->list);
  724. if (!first)
  725. first = mvs_list;
  726. else
  727. list_add_tail(&mvs_list->list, &first->list);
  728. }
  729. return first;
  730. }
  731. static inline void mvs_task_free_list(struct mvs_task_list *mvs_list)
  732. {
  733. LIST_HEAD(list);
  734. struct list_head *pos, *a;
  735. struct mvs_task_list *mlist = NULL;
  736. __list_add(&list, mvs_list->list.prev, &mvs_list->list);
  737. list_for_each_safe(pos, a, &list) {
  738. list_del_init(pos);
  739. mlist = list_entry(pos, struct mvs_task_list, list);
  740. kmem_cache_free(mvs_task_list_cache, mlist);
  741. }
  742. }
  743. static int mvs_task_exec(struct sas_task *task, const int num, gfp_t gfp_flags,
  744. struct completion *completion, int is_tmf,
  745. struct mvs_tmf_task *tmf)
  746. {
  747. struct domain_device *dev = task->dev;
  748. struct mvs_info *mvi = NULL;
  749. u32 rc = 0;
  750. u32 pass = 0;
  751. unsigned long flags = 0;
  752. mvi = ((struct mvs_device *)task->dev->lldd_dev)->mvi_info;
  753. if ((dev->dev_type == SATA_DEV) && (dev->sata_dev.ap != NULL))
  754. spin_unlock_irq(dev->sata_dev.ap->lock);
  755. spin_lock_irqsave(&mvi->lock, flags);
  756. rc = mvs_task_prep(task, mvi, is_tmf, tmf, &pass);
  757. if (rc)
  758. dev_printk(KERN_ERR, mvi->dev, "mvsas exec failed[%d]!\n", rc);
  759. if (likely(pass))
  760. MVS_CHIP_DISP->start_delivery(mvi, (mvi->tx_prod - 1) &
  761. (MVS_CHIP_SLOT_SZ - 1));
  762. spin_unlock_irqrestore(&mvi->lock, flags);
  763. if ((dev->dev_type == SATA_DEV) && (dev->sata_dev.ap != NULL))
  764. spin_lock_irq(dev->sata_dev.ap->lock);
  765. return rc;
  766. }
  767. static int mvs_collector_task_exec(struct sas_task *task, const int num, gfp_t gfp_flags,
  768. struct completion *completion, int is_tmf,
  769. struct mvs_tmf_task *tmf)
  770. {
  771. struct domain_device *dev = task->dev;
  772. struct mvs_prv_info *mpi = dev->port->ha->lldd_ha;
  773. struct mvs_info *mvi = NULL;
  774. struct sas_task *t = task;
  775. struct mvs_task_list *mvs_list = NULL, *a;
  776. LIST_HEAD(q);
  777. int pass[2] = {0};
  778. u32 rc = 0;
  779. u32 n = num;
  780. unsigned long flags = 0;
  781. mvs_list = mvs_task_alloc_list(&n, gfp_flags);
  782. if (n) {
  783. printk(KERN_ERR "%s: mvs alloc list failed.\n", __func__);
  784. rc = -ENOMEM;
  785. goto free_list;
  786. }
  787. __list_add(&q, mvs_list->list.prev, &mvs_list->list);
  788. list_for_each_entry(a, &q, list) {
  789. a->task = t;
  790. t = list_entry(t->list.next, struct sas_task, list);
  791. }
  792. list_for_each_entry(a, &q , list) {
  793. t = a->task;
  794. mvi = ((struct mvs_device *)t->dev->lldd_dev)->mvi_info;
  795. spin_lock_irqsave(&mvi->lock, flags);
  796. rc = mvs_task_prep(t, mvi, is_tmf, tmf, &pass[mvi->id]);
  797. if (rc)
  798. dev_printk(KERN_ERR, mvi->dev, "mvsas exec failed[%d]!\n", rc);
  799. spin_unlock_irqrestore(&mvi->lock, flags);
  800. }
  801. if (likely(pass[0]))
  802. MVS_CHIP_DISP->start_delivery(mpi->mvi[0],
  803. (mpi->mvi[0]->tx_prod - 1) & (MVS_CHIP_SLOT_SZ - 1));
  804. if (likely(pass[1]))
  805. MVS_CHIP_DISP->start_delivery(mpi->mvi[1],
  806. (mpi->mvi[1]->tx_prod - 1) & (MVS_CHIP_SLOT_SZ - 1));
  807. list_del_init(&q);
  808. free_list:
  809. if (mvs_list)
  810. mvs_task_free_list(mvs_list);
  811. return rc;
  812. }
  813. int mvs_queue_command(struct sas_task *task, const int num,
  814. gfp_t gfp_flags)
  815. {
  816. struct mvs_device *mvi_dev = task->dev->lldd_dev;
  817. struct sas_ha_struct *sas = mvi_dev->mvi_info->sas;
  818. if (sas->lldd_max_execute_num < 2)
  819. return mvs_task_exec(task, num, gfp_flags, NULL, 0, NULL);
  820. else
  821. return mvs_collector_task_exec(task, num, gfp_flags, NULL, 0, NULL);
  822. }
  823. static void mvs_slot_free(struct mvs_info *mvi, u32 rx_desc)
  824. {
  825. u32 slot_idx = rx_desc & RXQ_SLOT_MASK;
  826. mvs_tag_clear(mvi, slot_idx);
  827. }
  828. static void mvs_slot_task_free(struct mvs_info *mvi, struct sas_task *task,
  829. struct mvs_slot_info *slot, u32 slot_idx)
  830. {
  831. if (!slot->task)
  832. return;
  833. if (!sas_protocol_ata(task->task_proto))
  834. if (slot->n_elem)
  835. dma_unmap_sg(mvi->dev, task->scatter,
  836. slot->n_elem, task->data_dir);
  837. switch (task->task_proto) {
  838. case SAS_PROTOCOL_SMP:
  839. dma_unmap_sg(mvi->dev, &task->smp_task.smp_resp, 1,
  840. PCI_DMA_FROMDEVICE);
  841. dma_unmap_sg(mvi->dev, &task->smp_task.smp_req, 1,
  842. PCI_DMA_TODEVICE);
  843. break;
  844. case SAS_PROTOCOL_SATA:
  845. case SAS_PROTOCOL_STP:
  846. case SAS_PROTOCOL_SSP:
  847. default:
  848. /* do nothing */
  849. break;
  850. }
  851. if (slot->buf) {
  852. pci_pool_free(mvi->dma_pool, slot->buf, slot->buf_dma);
  853. slot->buf = NULL;
  854. }
  855. list_del_init(&slot->entry);
  856. task->lldd_task = NULL;
  857. slot->task = NULL;
  858. slot->port = NULL;
  859. slot->slot_tag = 0xFFFFFFFF;
  860. mvs_slot_free(mvi, slot_idx);
  861. }
  862. static void mvs_update_wideport(struct mvs_info *mvi, int phy_no)
  863. {
  864. struct mvs_phy *phy = &mvi->phy[phy_no];
  865. struct mvs_port *port = phy->port;
  866. int j, no;
  867. for_each_phy(port->wide_port_phymap, j, no) {
  868. if (j & 1) {
  869. MVS_CHIP_DISP->write_port_cfg_addr(mvi, no,
  870. PHYR_WIDE_PORT);
  871. MVS_CHIP_DISP->write_port_cfg_data(mvi, no,
  872. port->wide_port_phymap);
  873. } else {
  874. MVS_CHIP_DISP->write_port_cfg_addr(mvi, no,
  875. PHYR_WIDE_PORT);
  876. MVS_CHIP_DISP->write_port_cfg_data(mvi, no,
  877. 0);
  878. }
  879. }
  880. }
  881. static u32 mvs_is_phy_ready(struct mvs_info *mvi, int i)
  882. {
  883. u32 tmp;
  884. struct mvs_phy *phy = &mvi->phy[i];
  885. struct mvs_port *port = phy->port;
  886. tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, i);
  887. if ((tmp & PHY_READY_MASK) && !(phy->irq_status & PHYEV_POOF)) {
  888. if (!port)
  889. phy->phy_attached = 1;
  890. return tmp;
  891. }
  892. if (port) {
  893. if (phy->phy_type & PORT_TYPE_SAS) {
  894. port->wide_port_phymap &= ~(1U << i);
  895. if (!port->wide_port_phymap)
  896. port->port_attached = 0;
  897. mvs_update_wideport(mvi, i);
  898. } else if (phy->phy_type & PORT_TYPE_SATA)
  899. port->port_attached = 0;
  900. phy->port = NULL;
  901. phy->phy_attached = 0;
  902. phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
  903. }
  904. return 0;
  905. }
  906. static void *mvs_get_d2h_reg(struct mvs_info *mvi, int i, void *buf)
  907. {
  908. u32 *s = (u32 *) buf;
  909. if (!s)
  910. return NULL;
  911. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG3);
  912. s[3] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));
  913. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG2);
  914. s[2] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));
  915. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG1);
  916. s[1] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));
  917. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG0);
  918. s[0] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));
  919. if (((s[1] & 0x00FFFFFF) == 0x00EB1401) && (*(u8 *)&s[3] == 0x01))
  920. s[1] = 0x00EB1401 | (*((u8 *)&s[1] + 3) & 0x10);
  921. return s;
  922. }
  923. static u32 mvs_is_sig_fis_received(u32 irq_status)
  924. {
  925. return irq_status & PHYEV_SIG_FIS;
  926. }
  927. static void mvs_sig_remove_timer(struct mvs_phy *phy)
  928. {
  929. if (phy->timer.function)
  930. del_timer(&phy->timer);
  931. phy->timer.function = NULL;
  932. }
  933. void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st)
  934. {
  935. struct mvs_phy *phy = &mvi->phy[i];
  936. struct sas_identify_frame *id;
  937. id = (struct sas_identify_frame *)phy->frame_rcvd;
  938. if (get_st) {
  939. phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, i);
  940. phy->phy_status = mvs_is_phy_ready(mvi, i);
  941. }
  942. if (phy->phy_status) {
  943. int oob_done = 0;
  944. struct asd_sas_phy *sas_phy = &mvi->phy[i].sas_phy;
  945. oob_done = MVS_CHIP_DISP->oob_done(mvi, i);
  946. MVS_CHIP_DISP->fix_phy_info(mvi, i, id);
  947. if (phy->phy_type & PORT_TYPE_SATA) {
  948. phy->identify.target_port_protocols = SAS_PROTOCOL_STP;
  949. if (mvs_is_sig_fis_received(phy->irq_status)) {
  950. mvs_sig_remove_timer(phy);
  951. phy->phy_attached = 1;
  952. phy->att_dev_sas_addr =
  953. i + mvi->id * mvi->chip->n_phy;
  954. if (oob_done)
  955. sas_phy->oob_mode = SATA_OOB_MODE;
  956. phy->frame_rcvd_size =
  957. sizeof(struct dev_to_host_fis);
  958. mvs_get_d2h_reg(mvi, i, id);
  959. } else {
  960. u32 tmp;
  961. dev_printk(KERN_DEBUG, mvi->dev,
  962. "Phy%d : No sig fis\n", i);
  963. tmp = MVS_CHIP_DISP->read_port_irq_mask(mvi, i);
  964. MVS_CHIP_DISP->write_port_irq_mask(mvi, i,
  965. tmp | PHYEV_SIG_FIS);
  966. phy->phy_attached = 0;
  967. phy->phy_type &= ~PORT_TYPE_SATA;
  968. goto out_done;
  969. }
  970. } else if (phy->phy_type & PORT_TYPE_SAS
  971. || phy->att_dev_info & PORT_SSP_INIT_MASK) {
  972. phy->phy_attached = 1;
  973. phy->identify.device_type =
  974. phy->att_dev_info & PORT_DEV_TYPE_MASK;
  975. if (phy->identify.device_type == SAS_END_DEV)
  976. phy->identify.target_port_protocols =
  977. SAS_PROTOCOL_SSP;
  978. else if (phy->identify.device_type != NO_DEVICE)
  979. phy->identify.target_port_protocols =
  980. SAS_PROTOCOL_SMP;
  981. if (oob_done)
  982. sas_phy->oob_mode = SAS_OOB_MODE;
  983. phy->frame_rcvd_size =
  984. sizeof(struct sas_identify_frame);
  985. }
  986. memcpy(sas_phy->attached_sas_addr,
  987. &phy->att_dev_sas_addr, SAS_ADDR_SIZE);
  988. if (MVS_CHIP_DISP->phy_work_around)
  989. MVS_CHIP_DISP->phy_work_around(mvi, i);
  990. }
  991. mv_dprintk("phy %d attach dev info is %x\n",
  992. i + mvi->id * mvi->chip->n_phy, phy->att_dev_info);
  993. mv_dprintk("phy %d attach sas addr is %llx\n",
  994. i + mvi->id * mvi->chip->n_phy, phy->att_dev_sas_addr);
  995. out_done:
  996. if (get_st)
  997. MVS_CHIP_DISP->write_port_irq_stat(mvi, i, phy->irq_status);
  998. }
  999. static void mvs_port_notify_formed(struct asd_sas_phy *sas_phy, int lock)
  1000. {
  1001. struct sas_ha_struct *sas_ha = sas_phy->ha;
  1002. struct mvs_info *mvi = NULL; int i = 0, hi;
  1003. struct mvs_phy *phy = sas_phy->lldd_phy;
  1004. struct asd_sas_port *sas_port = sas_phy->port;
  1005. struct mvs_port *port;
  1006. unsigned long flags = 0;
  1007. if (!sas_port)
  1008. return;
  1009. while (sas_ha->sas_phy[i]) {
  1010. if (sas_ha->sas_phy[i] == sas_phy)
  1011. break;
  1012. i++;
  1013. }
  1014. hi = i/((struct mvs_prv_info *)sas_ha->lldd_ha)->n_phy;
  1015. mvi = ((struct mvs_prv_info *)sas_ha->lldd_ha)->mvi[hi];
  1016. if (i >= mvi->chip->n_phy)
  1017. port = &mvi->port[i - mvi->chip->n_phy];
  1018. else
  1019. port = &mvi->port[i];
  1020. if (lock)
  1021. spin_lock_irqsave(&mvi->lock, flags);
  1022. port->port_attached = 1;
  1023. phy->port = port;
  1024. sas_port->lldd_port = port;
  1025. if (phy->phy_type & PORT_TYPE_SAS) {
  1026. port->wide_port_phymap = sas_port->phy_mask;
  1027. mv_printk("set wide port phy map %x\n", sas_port->phy_mask);
  1028. mvs_update_wideport(mvi, sas_phy->id);
  1029. /* direct attached SAS device */
  1030. if (phy->att_dev_info & PORT_SSP_TRGT_MASK) {
  1031. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_PHY_STAT);
  1032. MVS_CHIP_DISP->write_port_cfg_data(mvi, i, 0x04);
  1033. }
  1034. }
  1035. if (lock)
  1036. spin_unlock_irqrestore(&mvi->lock, flags);
  1037. }
  1038. static void mvs_port_notify_deformed(struct asd_sas_phy *sas_phy, int lock)
  1039. {
  1040. struct domain_device *dev;
  1041. struct mvs_phy *phy = sas_phy->lldd_phy;
  1042. struct mvs_info *mvi = phy->mvi;
  1043. struct asd_sas_port *port = sas_phy->port;
  1044. int phy_no = 0;
  1045. while (phy != &mvi->phy[phy_no]) {
  1046. phy_no++;
  1047. if (phy_no >= MVS_MAX_PHYS)
  1048. return;
  1049. }
  1050. list_for_each_entry(dev, &port->dev_list, dev_list_node)
  1051. mvs_do_release_task(phy->mvi, phy_no, dev);
  1052. }
  1053. void mvs_port_formed(struct asd_sas_phy *sas_phy)
  1054. {
  1055. mvs_port_notify_formed(sas_phy, 1);
  1056. }
  1057. void mvs_port_deformed(struct asd_sas_phy *sas_phy)
  1058. {
  1059. mvs_port_notify_deformed(sas_phy, 1);
  1060. }
  1061. struct mvs_device *mvs_alloc_dev(struct mvs_info *mvi)
  1062. {
  1063. u32 dev;
  1064. for (dev = 0; dev < MVS_MAX_DEVICES; dev++) {
  1065. if (mvi->devices[dev].dev_type == NO_DEVICE) {
  1066. mvi->devices[dev].device_id = dev;
  1067. return &mvi->devices[dev];
  1068. }
  1069. }
  1070. if (dev == MVS_MAX_DEVICES)
  1071. mv_printk("max support %d devices, ignore ..\n",
  1072. MVS_MAX_DEVICES);
  1073. return NULL;
  1074. }
  1075. void mvs_free_dev(struct mvs_device *mvi_dev)
  1076. {
  1077. u32 id = mvi_dev->device_id;
  1078. memset(mvi_dev, 0, sizeof(*mvi_dev));
  1079. mvi_dev->device_id = id;
  1080. mvi_dev->dev_type = NO_DEVICE;
  1081. mvi_dev->dev_status = MVS_DEV_NORMAL;
  1082. mvi_dev->taskfileset = MVS_ID_NOT_MAPPED;
  1083. }
  1084. int mvs_dev_found_notify(struct domain_device *dev, int lock)
  1085. {
  1086. unsigned long flags = 0;
  1087. int res = 0;
  1088. struct mvs_info *mvi = NULL;
  1089. struct domain_device *parent_dev = dev->parent;
  1090. struct mvs_device *mvi_device;
  1091. mvi = mvs_find_dev_mvi(dev);
  1092. if (lock)
  1093. spin_lock_irqsave(&mvi->lock, flags);
  1094. mvi_device = mvs_alloc_dev(mvi);
  1095. if (!mvi_device) {
  1096. res = -1;
  1097. goto found_out;
  1098. }
  1099. dev->lldd_dev = mvi_device;
  1100. mvi_device->dev_status = MVS_DEV_NORMAL;
  1101. mvi_device->dev_type = dev->dev_type;
  1102. mvi_device->mvi_info = mvi;
  1103. mvi_device->sas_device = dev;
  1104. if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) {
  1105. int phy_id;
  1106. u8 phy_num = parent_dev->ex_dev.num_phys;
  1107. struct ex_phy *phy;
  1108. for (phy_id = 0; phy_id < phy_num; phy_id++) {
  1109. phy = &parent_dev->ex_dev.ex_phy[phy_id];
  1110. if (SAS_ADDR(phy->attached_sas_addr) ==
  1111. SAS_ADDR(dev->sas_addr)) {
  1112. mvi_device->attached_phy = phy_id;
  1113. break;
  1114. }
  1115. }
  1116. if (phy_id == phy_num) {
  1117. mv_printk("Error: no attached dev:%016llx"
  1118. "at ex:%016llx.\n",
  1119. SAS_ADDR(dev->sas_addr),
  1120. SAS_ADDR(parent_dev->sas_addr));
  1121. res = -1;
  1122. }
  1123. }
  1124. found_out:
  1125. if (lock)
  1126. spin_unlock_irqrestore(&mvi->lock, flags);
  1127. return res;
  1128. }
  1129. int mvs_dev_found(struct domain_device *dev)
  1130. {
  1131. return mvs_dev_found_notify(dev, 1);
  1132. }
  1133. void mvs_dev_gone_notify(struct domain_device *dev)
  1134. {
  1135. unsigned long flags = 0;
  1136. struct mvs_device *mvi_dev = dev->lldd_dev;
  1137. struct mvs_info *mvi = mvi_dev->mvi_info;
  1138. spin_lock_irqsave(&mvi->lock, flags);
  1139. if (mvi_dev) {
  1140. mv_dprintk("found dev[%d:%x] is gone.\n",
  1141. mvi_dev->device_id, mvi_dev->dev_type);
  1142. mvs_release_task(mvi, dev);
  1143. mvs_free_reg_set(mvi, mvi_dev);
  1144. mvs_free_dev(mvi_dev);
  1145. } else {
  1146. mv_dprintk("found dev has gone.\n");
  1147. }
  1148. dev->lldd_dev = NULL;
  1149. mvi_dev->sas_device = NULL;
  1150. spin_unlock_irqrestore(&mvi->lock, flags);
  1151. }
  1152. void mvs_dev_gone(struct domain_device *dev)
  1153. {
  1154. mvs_dev_gone_notify(dev);
  1155. }
  1156. static void mvs_task_done(struct sas_task *task)
  1157. {
  1158. if (!del_timer(&task->timer))
  1159. return;
  1160. complete(&task->completion);
  1161. }
  1162. static void mvs_tmf_timedout(unsigned long data)
  1163. {
  1164. struct sas_task *task = (struct sas_task *)data;
  1165. task->task_state_flags |= SAS_TASK_STATE_ABORTED;
  1166. complete(&task->completion);
  1167. }
  1168. #define MVS_TASK_TIMEOUT 20
  1169. static int mvs_exec_internal_tmf_task(struct domain_device *dev,
  1170. void *parameter, u32 para_len, struct mvs_tmf_task *tmf)
  1171. {
  1172. int res, retry;
  1173. struct sas_task *task = NULL;
  1174. for (retry = 0; retry < 3; retry++) {
  1175. task = sas_alloc_task(GFP_KERNEL);
  1176. if (!task)
  1177. return -ENOMEM;
  1178. task->dev = dev;
  1179. task->task_proto = dev->tproto;
  1180. memcpy(&task->ssp_task, parameter, para_len);
  1181. task->task_done = mvs_task_done;
  1182. task->timer.data = (unsigned long) task;
  1183. task->timer.function = mvs_tmf_timedout;
  1184. task->timer.expires = jiffies + MVS_TASK_TIMEOUT*HZ;
  1185. add_timer(&task->timer);
  1186. res = mvs_task_exec(task, 1, GFP_KERNEL, NULL, 1, tmf);
  1187. if (res) {
  1188. del_timer(&task->timer);
  1189. mv_printk("executing internel task failed:%d\n", res);
  1190. goto ex_err;
  1191. }
  1192. wait_for_completion(&task->completion);
  1193. res = TMF_RESP_FUNC_FAILED;
  1194. /* Even TMF timed out, return direct. */
  1195. if ((task->task_state_flags & SAS_TASK_STATE_ABORTED)) {
  1196. if (!(task->task_state_flags & SAS_TASK_STATE_DONE)) {
  1197. mv_printk("TMF task[%x] timeout.\n", tmf->tmf);
  1198. goto ex_err;
  1199. }
  1200. }
  1201. if (task->task_status.resp == SAS_TASK_COMPLETE &&
  1202. task->task_status.stat == SAM_STAT_GOOD) {
  1203. res = TMF_RESP_FUNC_COMPLETE;
  1204. break;
  1205. }
  1206. if (task->task_status.resp == SAS_TASK_COMPLETE &&
  1207. task->task_status.stat == SAS_DATA_UNDERRUN) {
  1208. /* no error, but return the number of bytes of
  1209. * underrun */
  1210. res = task->task_status.residual;
  1211. break;
  1212. }
  1213. if (task->task_status.resp == SAS_TASK_COMPLETE &&
  1214. task->task_status.stat == SAS_DATA_OVERRUN) {
  1215. mv_dprintk("blocked task error.\n");
  1216. res = -EMSGSIZE;
  1217. break;
  1218. } else {
  1219. mv_dprintk(" task to dev %016llx response: 0x%x "
  1220. "status 0x%x\n",
  1221. SAS_ADDR(dev->sas_addr),
  1222. task->task_status.resp,
  1223. task->task_status.stat);
  1224. sas_free_task(task);
  1225. task = NULL;
  1226. }
  1227. }
  1228. ex_err:
  1229. BUG_ON(retry == 3 && task != NULL);
  1230. sas_free_task(task);
  1231. return res;
  1232. }
  1233. static int mvs_debug_issue_ssp_tmf(struct domain_device *dev,
  1234. u8 *lun, struct mvs_tmf_task *tmf)
  1235. {
  1236. struct sas_ssp_task ssp_task;
  1237. if (!(dev->tproto & SAS_PROTOCOL_SSP))
  1238. return TMF_RESP_FUNC_ESUPP;
  1239. memcpy(ssp_task.LUN, lun, 8);
  1240. return mvs_exec_internal_tmf_task(dev, &ssp_task,
  1241. sizeof(ssp_task), tmf);
  1242. }
  1243. /* Standard mandates link reset for ATA (type 0)
  1244. and hard reset for SSP (type 1) , only for RECOVERY */
  1245. static int mvs_debug_I_T_nexus_reset(struct domain_device *dev)
  1246. {
  1247. int rc;
  1248. struct sas_phy *phy = sas_find_local_phy(dev);
  1249. int reset_type = (dev->dev_type == SATA_DEV ||
  1250. (dev->tproto & SAS_PROTOCOL_STP)) ? 0 : 1;
  1251. rc = sas_phy_reset(phy, reset_type);
  1252. msleep(2000);
  1253. return rc;
  1254. }
  1255. /* mandatory SAM-3 */
  1256. int mvs_lu_reset(struct domain_device *dev, u8 *lun)
  1257. {
  1258. unsigned long flags;
  1259. int rc = TMF_RESP_FUNC_FAILED;
  1260. struct mvs_tmf_task tmf_task;
  1261. struct mvs_device * mvi_dev = dev->lldd_dev;
  1262. struct mvs_info *mvi = mvi_dev->mvi_info;
  1263. tmf_task.tmf = TMF_LU_RESET;
  1264. mvi_dev->dev_status = MVS_DEV_EH;
  1265. rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
  1266. if (rc == TMF_RESP_FUNC_COMPLETE) {
  1267. spin_lock_irqsave(&mvi->lock, flags);
  1268. mvs_release_task(mvi, dev);
  1269. spin_unlock_irqrestore(&mvi->lock, flags);
  1270. }
  1271. /* If failed, fall-through I_T_Nexus reset */
  1272. mv_printk("%s for device[%x]:rc= %d\n", __func__,
  1273. mvi_dev->device_id, rc);
  1274. return rc;
  1275. }
  1276. int mvs_I_T_nexus_reset(struct domain_device *dev)
  1277. {
  1278. unsigned long flags;
  1279. int rc = TMF_RESP_FUNC_FAILED;
  1280. struct mvs_device * mvi_dev = (struct mvs_device *)dev->lldd_dev;
  1281. struct mvs_info *mvi = mvi_dev->mvi_info;
  1282. if (mvi_dev->dev_status != MVS_DEV_EH)
  1283. return TMF_RESP_FUNC_COMPLETE;
  1284. else
  1285. mvi_dev->dev_status = MVS_DEV_NORMAL;
  1286. rc = mvs_debug_I_T_nexus_reset(dev);
  1287. mv_printk("%s for device[%x]:rc= %d\n",
  1288. __func__, mvi_dev->device_id, rc);
  1289. spin_lock_irqsave(&mvi->lock, flags);
  1290. mvs_release_task(mvi, dev);
  1291. spin_unlock_irqrestore(&mvi->lock, flags);
  1292. return rc;
  1293. }
  1294. /* optional SAM-3 */
  1295. int mvs_query_task(struct sas_task *task)
  1296. {
  1297. u32 tag;
  1298. struct scsi_lun lun;
  1299. struct mvs_tmf_task tmf_task;
  1300. int rc = TMF_RESP_FUNC_FAILED;
  1301. if (task->lldd_task && task->task_proto & SAS_PROTOCOL_SSP) {
  1302. struct scsi_cmnd * cmnd = (struct scsi_cmnd *)task->uldd_task;
  1303. struct domain_device *dev = task->dev;
  1304. struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
  1305. struct mvs_info *mvi = mvi_dev->mvi_info;
  1306. int_to_scsilun(cmnd->device->lun, &lun);
  1307. rc = mvs_find_tag(mvi, task, &tag);
  1308. if (rc == 0) {
  1309. rc = TMF_RESP_FUNC_FAILED;
  1310. return rc;
  1311. }
  1312. tmf_task.tmf = TMF_QUERY_TASK;
  1313. tmf_task.tag_of_task_to_be_managed = cpu_to_le16(tag);
  1314. rc = mvs_debug_issue_ssp_tmf(dev, lun.scsi_lun, &tmf_task);
  1315. switch (rc) {
  1316. /* The task is still in Lun, release it then */
  1317. case TMF_RESP_FUNC_SUCC:
  1318. /* The task is not in Lun or failed, reset the phy */
  1319. case TMF_RESP_FUNC_FAILED:
  1320. case TMF_RESP_FUNC_COMPLETE:
  1321. break;
  1322. }
  1323. }
  1324. mv_printk("%s:rc= %d\n", __func__, rc);
  1325. return rc;
  1326. }
  1327. /* mandatory SAM-3, still need free task/slot info */
  1328. int mvs_abort_task(struct sas_task *task)
  1329. {
  1330. struct scsi_lun lun;
  1331. struct mvs_tmf_task tmf_task;
  1332. struct domain_device *dev = task->dev;
  1333. struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
  1334. struct mvs_info *mvi;
  1335. int rc = TMF_RESP_FUNC_FAILED;
  1336. unsigned long flags;
  1337. u32 tag;
  1338. if (!mvi_dev) {
  1339. mv_printk("Device has removed\n");
  1340. return TMF_RESP_FUNC_FAILED;
  1341. }
  1342. mvi = mvi_dev->mvi_info;
  1343. spin_lock_irqsave(&task->task_state_lock, flags);
  1344. if (task->task_state_flags & SAS_TASK_STATE_DONE) {
  1345. spin_unlock_irqrestore(&task->task_state_lock, flags);
  1346. rc = TMF_RESP_FUNC_COMPLETE;
  1347. goto out;
  1348. }
  1349. spin_unlock_irqrestore(&task->task_state_lock, flags);
  1350. mvi_dev->dev_status = MVS_DEV_EH;
  1351. if (task->lldd_task && task->task_proto & SAS_PROTOCOL_SSP) {
  1352. struct scsi_cmnd * cmnd = (struct scsi_cmnd *)task->uldd_task;
  1353. int_to_scsilun(cmnd->device->lun, &lun);
  1354. rc = mvs_find_tag(mvi, task, &tag);
  1355. if (rc == 0) {
  1356. mv_printk("No such tag in %s\n", __func__);
  1357. rc = TMF_RESP_FUNC_FAILED;
  1358. return rc;
  1359. }
  1360. tmf_task.tmf = TMF_ABORT_TASK;
  1361. tmf_task.tag_of_task_to_be_managed = cpu_to_le16(tag);
  1362. rc = mvs_debug_issue_ssp_tmf(dev, lun.scsi_lun, &tmf_task);
  1363. /* if successful, clear the task and callback forwards.*/
  1364. if (rc == TMF_RESP_FUNC_COMPLETE) {
  1365. u32 slot_no;
  1366. struct mvs_slot_info *slot;
  1367. if (task->lldd_task) {
  1368. slot = task->lldd_task;
  1369. slot_no = (u32) (slot - mvi->slot_info);
  1370. spin_lock_irqsave(&mvi->lock, flags);
  1371. mvs_slot_complete(mvi, slot_no, 1);
  1372. spin_unlock_irqrestore(&mvi->lock, flags);
  1373. }
  1374. }
  1375. } else if (task->task_proto & SAS_PROTOCOL_SATA ||
  1376. task->task_proto & SAS_PROTOCOL_STP) {
  1377. if (SATA_DEV == dev->dev_type) {
  1378. struct mvs_slot_info *slot = task->lldd_task;
  1379. u32 slot_idx = (u32)(slot - mvi->slot_info);
  1380. mv_dprintk("mvs_abort_task() mvi=%p task=%p "
  1381. "slot=%p slot_idx=x%x\n",
  1382. mvi, task, slot, slot_idx);
  1383. mvs_tmf_timedout((unsigned long)task);
  1384. mvs_slot_task_free(mvi, task, slot, slot_idx);
  1385. rc = TMF_RESP_FUNC_COMPLETE;
  1386. goto out;
  1387. }
  1388. }
  1389. out:
  1390. if (rc != TMF_RESP_FUNC_COMPLETE)
  1391. mv_printk("%s:rc= %d\n", __func__, rc);
  1392. return rc;
  1393. }
  1394. int mvs_abort_task_set(struct domain_device *dev, u8 *lun)
  1395. {
  1396. int rc = TMF_RESP_FUNC_FAILED;
  1397. struct mvs_tmf_task tmf_task;
  1398. tmf_task.tmf = TMF_ABORT_TASK_SET;
  1399. rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
  1400. return rc;
  1401. }
  1402. int mvs_clear_aca(struct domain_device *dev, u8 *lun)
  1403. {
  1404. int rc = TMF_RESP_FUNC_FAILED;
  1405. struct mvs_tmf_task tmf_task;
  1406. tmf_task.tmf = TMF_CLEAR_ACA;
  1407. rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
  1408. return rc;
  1409. }
  1410. int mvs_clear_task_set(struct domain_device *dev, u8 *lun)
  1411. {
  1412. int rc = TMF_RESP_FUNC_FAILED;
  1413. struct mvs_tmf_task tmf_task;
  1414. tmf_task.tmf = TMF_CLEAR_TASK_SET;
  1415. rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
  1416. return rc;
  1417. }
  1418. static int mvs_sata_done(struct mvs_info *mvi, struct sas_task *task,
  1419. u32 slot_idx, int err)
  1420. {
  1421. struct mvs_device *mvi_dev = task->dev->lldd_dev;
  1422. struct task_status_struct *tstat = &task->task_status;
  1423. struct ata_task_resp *resp = (struct ata_task_resp *)tstat->buf;
  1424. int stat = SAM_STAT_GOOD;
  1425. resp->frame_len = sizeof(struct dev_to_host_fis);
  1426. memcpy(&resp->ending_fis[0],
  1427. SATA_RECEIVED_D2H_FIS(mvi_dev->taskfileset),
  1428. sizeof(struct dev_to_host_fis));
  1429. tstat->buf_valid_size = sizeof(*resp);
  1430. if (unlikely(err)) {
  1431. if (unlikely(err & CMD_ISS_STPD))
  1432. stat = SAS_OPEN_REJECT;
  1433. else
  1434. stat = SAS_PROTO_RESPONSE;
  1435. }
  1436. return stat;
  1437. }
  1438. void mvs_set_sense(u8 *buffer, int len, int d_sense,
  1439. int key, int asc, int ascq)
  1440. {
  1441. memset(buffer, 0, len);
  1442. if (d_sense) {
  1443. /* Descriptor format */
  1444. if (len < 4) {
  1445. mv_printk("Length %d of sense buffer too small to "
  1446. "fit sense %x:%x:%x", len, key, asc, ascq);
  1447. }
  1448. buffer[0] = 0x72; /* Response Code */
  1449. if (len > 1)
  1450. buffer[1] = key; /* Sense Key */
  1451. if (len > 2)
  1452. buffer[2] = asc; /* ASC */
  1453. if (len > 3)
  1454. buffer[3] = ascq; /* ASCQ */
  1455. } else {
  1456. if (len < 14) {
  1457. mv_printk("Length %d of sense buffer too small to "
  1458. "fit sense %x:%x:%x", len, key, asc, ascq);
  1459. }
  1460. buffer[0] = 0x70; /* Response Code */
  1461. if (len > 2)
  1462. buffer[2] = key; /* Sense Key */
  1463. if (len > 7)
  1464. buffer[7] = 0x0a; /* Additional Sense Length */
  1465. if (len > 12)
  1466. buffer[12] = asc; /* ASC */
  1467. if (len > 13)
  1468. buffer[13] = ascq; /* ASCQ */
  1469. }
  1470. return;
  1471. }
  1472. void mvs_fill_ssp_resp_iu(struct ssp_response_iu *iu,
  1473. u8 key, u8 asc, u8 asc_q)
  1474. {
  1475. iu->datapres = 2;
  1476. iu->response_data_len = 0;
  1477. iu->sense_data_len = 17;
  1478. iu->status = 02;
  1479. mvs_set_sense(iu->sense_data, 17, 0,
  1480. key, asc, asc_q);
  1481. }
  1482. static int mvs_slot_err(struct mvs_info *mvi, struct sas_task *task,
  1483. u32 slot_idx)
  1484. {
  1485. struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
  1486. int stat;
  1487. u32 err_dw0 = le32_to_cpu(*(u32 *)slot->response);
  1488. u32 err_dw1 = le32_to_cpu(*((u32 *)slot->response + 1));
  1489. u32 tfs = 0;
  1490. enum mvs_port_type type = PORT_TYPE_SAS;
  1491. if (err_dw0 & CMD_ISS_STPD)
  1492. MVS_CHIP_DISP->issue_stop(mvi, type, tfs);
  1493. MVS_CHIP_DISP->command_active(mvi, slot_idx);
  1494. stat = SAM_STAT_CHECK_CONDITION;
  1495. switch (task->task_proto) {
  1496. case SAS_PROTOCOL_SSP:
  1497. {
  1498. stat = SAS_ABORTED_TASK;
  1499. if ((err_dw0 & NO_DEST) || err_dw1 & bit(31)) {
  1500. struct ssp_response_iu *iu = slot->response +
  1501. sizeof(struct mvs_err_info);
  1502. mvs_fill_ssp_resp_iu(iu, NOT_READY, 0x04, 01);
  1503. sas_ssp_task_response(mvi->dev, task, iu);
  1504. stat = SAM_STAT_CHECK_CONDITION;
  1505. }
  1506. if (err_dw1 & bit(31))
  1507. mv_printk("reuse same slot, retry command.\n");
  1508. break;
  1509. }
  1510. case SAS_PROTOCOL_SMP:
  1511. stat = SAM_STAT_CHECK_CONDITION;
  1512. break;
  1513. case SAS_PROTOCOL_SATA:
  1514. case SAS_PROTOCOL_STP:
  1515. case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
  1516. {
  1517. task->ata_task.use_ncq = 0;
  1518. stat = SAS_PROTO_RESPONSE;
  1519. mvs_sata_done(mvi, task, slot_idx, err_dw0);
  1520. }
  1521. break;
  1522. default:
  1523. break;
  1524. }
  1525. return stat;
  1526. }
  1527. int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc, u32 flags)
  1528. {
  1529. u32 slot_idx = rx_desc & RXQ_SLOT_MASK;
  1530. struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
  1531. struct sas_task *task = slot->task;
  1532. struct mvs_device *mvi_dev = NULL;
  1533. struct task_status_struct *tstat;
  1534. struct domain_device *dev;
  1535. u32 aborted;
  1536. void *to;
  1537. enum exec_status sts;
  1538. if (unlikely(!task || !task->lldd_task || !task->dev))
  1539. return -1;
  1540. tstat = &task->task_status;
  1541. dev = task->dev;
  1542. mvi_dev = dev->lldd_dev;
  1543. spin_lock(&task->task_state_lock);
  1544. task->task_state_flags &=
  1545. ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
  1546. task->task_state_flags |= SAS_TASK_STATE_DONE;
  1547. /* race condition*/
  1548. aborted = task->task_state_flags & SAS_TASK_STATE_ABORTED;
  1549. spin_unlock(&task->task_state_lock);
  1550. memset(tstat, 0, sizeof(*tstat));
  1551. tstat->resp = SAS_TASK_COMPLETE;
  1552. if (unlikely(aborted)) {
  1553. tstat->stat = SAS_ABORTED_TASK;
  1554. if (mvi_dev && mvi_dev->running_req)
  1555. mvi_dev->running_req--;
  1556. if (sas_protocol_ata(task->task_proto))
  1557. mvs_free_reg_set(mvi, mvi_dev);
  1558. mvs_slot_task_free(mvi, task, slot, slot_idx);
  1559. return -1;
  1560. }
  1561. /* when no device attaching, go ahead and complete by error handling*/
  1562. if (unlikely(!mvi_dev || flags)) {
  1563. if (!mvi_dev)
  1564. mv_dprintk("port has not device.\n");
  1565. tstat->stat = SAS_PHY_DOWN;
  1566. goto out;
  1567. }
  1568. /* error info record present */
  1569. if (unlikely((rx_desc & RXQ_ERR) && (*(u64 *) slot->response))) {
  1570. mv_dprintk("port %d slot %d rx_desc %X has error info"
  1571. "%016llX.\n", slot->port->sas_port.id, slot_idx,
  1572. rx_desc, (u64)(*(u64 *)slot->response));
  1573. tstat->stat = mvs_slot_err(mvi, task, slot_idx);
  1574. tstat->resp = SAS_TASK_COMPLETE;
  1575. goto out;
  1576. }
  1577. switch (task->task_proto) {
  1578. case SAS_PROTOCOL_SSP:
  1579. /* hw says status == 0, datapres == 0 */
  1580. if (rx_desc & RXQ_GOOD) {
  1581. tstat->stat = SAM_STAT_GOOD;
  1582. tstat->resp = SAS_TASK_COMPLETE;
  1583. }
  1584. /* response frame present */
  1585. else if (rx_desc & RXQ_RSP) {
  1586. struct ssp_response_iu *iu = slot->response +
  1587. sizeof(struct mvs_err_info);
  1588. sas_ssp_task_response(mvi->dev, task, iu);
  1589. } else
  1590. tstat->stat = SAM_STAT_CHECK_CONDITION;
  1591. break;
  1592. case SAS_PROTOCOL_SMP: {
  1593. struct scatterlist *sg_resp = &task->smp_task.smp_resp;
  1594. tstat->stat = SAM_STAT_GOOD;
  1595. to = kmap_atomic(sg_page(sg_resp), KM_IRQ0);
  1596. memcpy(to + sg_resp->offset,
  1597. slot->response + sizeof(struct mvs_err_info),
  1598. sg_dma_len(sg_resp));
  1599. kunmap_atomic(to, KM_IRQ0);
  1600. break;
  1601. }
  1602. case SAS_PROTOCOL_SATA:
  1603. case SAS_PROTOCOL_STP:
  1604. case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: {
  1605. tstat->stat = mvs_sata_done(mvi, task, slot_idx, 0);
  1606. break;
  1607. }
  1608. default:
  1609. tstat->stat = SAM_STAT_CHECK_CONDITION;
  1610. break;
  1611. }
  1612. if (!slot->port->port_attached) {
  1613. mv_dprintk("port %d has removed.\n", slot->port->sas_port.id);
  1614. tstat->stat = SAS_PHY_DOWN;
  1615. }
  1616. out:
  1617. if (mvi_dev && mvi_dev->running_req) {
  1618. mvi_dev->running_req--;
  1619. if (sas_protocol_ata(task->task_proto) && !mvi_dev->running_req)
  1620. mvs_free_reg_set(mvi, mvi_dev);
  1621. }
  1622. mvs_slot_task_free(mvi, task, slot, slot_idx);
  1623. sts = tstat->stat;
  1624. spin_unlock(&mvi->lock);
  1625. if (task->task_done)
  1626. task->task_done(task);
  1627. spin_lock(&mvi->lock);
  1628. return sts;
  1629. }
  1630. void mvs_do_release_task(struct mvs_info *mvi,
  1631. int phy_no, struct domain_device *dev)
  1632. {
  1633. u32 slot_idx;
  1634. struct mvs_phy *phy;
  1635. struct mvs_port *port;
  1636. struct mvs_slot_info *slot, *slot2;
  1637. phy = &mvi->phy[phy_no];
  1638. port = phy->port;
  1639. if (!port)
  1640. return;
  1641. /* clean cmpl queue in case request is already finished */
  1642. mvs_int_rx(mvi, false);
  1643. list_for_each_entry_safe(slot, slot2, &port->list, entry) {
  1644. struct sas_task *task;
  1645. slot_idx = (u32) (slot - mvi->slot_info);
  1646. task = slot->task;
  1647. if (dev && task->dev != dev)
  1648. continue;
  1649. mv_printk("Release slot [%x] tag[%x], task [%p]:\n",
  1650. slot_idx, slot->slot_tag, task);
  1651. MVS_CHIP_DISP->command_active(mvi, slot_idx);
  1652. mvs_slot_complete(mvi, slot_idx, 1);
  1653. }
  1654. }
  1655. void mvs_release_task(struct mvs_info *mvi,
  1656. struct domain_device *dev)
  1657. {
  1658. int i, phyno[WIDE_PORT_MAX_PHY], num;
  1659. num = mvs_find_dev_phyno(dev, phyno);
  1660. for (i = 0; i < num; i++)
  1661. mvs_do_release_task(mvi, phyno[i], dev);
  1662. }
  1663. static void mvs_phy_disconnected(struct mvs_phy *phy)
  1664. {
  1665. phy->phy_attached = 0;
  1666. phy->att_dev_info = 0;
  1667. phy->att_dev_sas_addr = 0;
  1668. }
  1669. static void mvs_work_queue(struct work_struct *work)
  1670. {
  1671. struct delayed_work *dw = container_of(work, struct delayed_work, work);
  1672. struct mvs_wq *mwq = container_of(dw, struct mvs_wq, work_q);
  1673. struct mvs_info *mvi = mwq->mvi;
  1674. unsigned long flags;
  1675. u32 phy_no = (unsigned long) mwq->data;
  1676. struct sas_ha_struct *sas_ha = mvi->sas;
  1677. struct mvs_phy *phy = &mvi->phy[phy_no];
  1678. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  1679. spin_lock_irqsave(&mvi->lock, flags);
  1680. if (mwq->handler & PHY_PLUG_EVENT) {
  1681. if (phy->phy_event & PHY_PLUG_OUT) {
  1682. u32 tmp;
  1683. struct sas_identify_frame *id;
  1684. id = (struct sas_identify_frame *)phy->frame_rcvd;
  1685. tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_no);
  1686. phy->phy_event &= ~PHY_PLUG_OUT;
  1687. if (!(tmp & PHY_READY_MASK)) {
  1688. sas_phy_disconnected(sas_phy);
  1689. mvs_phy_disconnected(phy);
  1690. sas_ha->notify_phy_event(sas_phy,
  1691. PHYE_LOSS_OF_SIGNAL);
  1692. mv_dprintk("phy%d Removed Device\n", phy_no);
  1693. } else {
  1694. MVS_CHIP_DISP->detect_porttype(mvi, phy_no);
  1695. mvs_update_phyinfo(mvi, phy_no, 1);
  1696. mvs_bytes_dmaed(mvi, phy_no);
  1697. mvs_port_notify_formed(sas_phy, 0);
  1698. mv_dprintk("phy%d Attached Device\n", phy_no);
  1699. }
  1700. }
  1701. } else if (mwq->handler & EXP_BRCT_CHG) {
  1702. phy->phy_event &= ~EXP_BRCT_CHG;
  1703. sas_ha->notify_port_event(sas_phy,
  1704. PORTE_BROADCAST_RCVD);
  1705. mv_dprintk("phy%d Got Broadcast Change\n", phy_no);
  1706. }
  1707. list_del(&mwq->entry);
  1708. spin_unlock_irqrestore(&mvi->lock, flags);
  1709. kfree(mwq);
  1710. }
  1711. static int mvs_handle_event(struct mvs_info *mvi, void *data, int handler)
  1712. {
  1713. struct mvs_wq *mwq;
  1714. int ret = 0;
  1715. mwq = kmalloc(sizeof(struct mvs_wq), GFP_ATOMIC);
  1716. if (mwq) {
  1717. mwq->mvi = mvi;
  1718. mwq->data = data;
  1719. mwq->handler = handler;
  1720. MV_INIT_DELAYED_WORK(&mwq->work_q, mvs_work_queue, mwq);
  1721. list_add_tail(&mwq->entry, &mvi->wq_list);
  1722. schedule_delayed_work(&mwq->work_q, HZ * 2);
  1723. } else
  1724. ret = -ENOMEM;
  1725. return ret;
  1726. }
  1727. static void mvs_sig_time_out(unsigned long tphy)
  1728. {
  1729. struct mvs_phy *phy = (struct mvs_phy *)tphy;
  1730. struct mvs_info *mvi = phy->mvi;
  1731. u8 phy_no;
  1732. for (phy_no = 0; phy_no < mvi->chip->n_phy; phy_no++) {
  1733. if (&mvi->phy[phy_no] == phy) {
  1734. mv_dprintk("Get signature time out, reset phy %d\n",
  1735. phy_no+mvi->id*mvi->chip->n_phy);
  1736. MVS_CHIP_DISP->phy_reset(mvi, phy_no, MVS_HARD_RESET);
  1737. }
  1738. }
  1739. }
  1740. void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events)
  1741. {
  1742. u32 tmp;
  1743. struct mvs_phy *phy = &mvi->phy[phy_no];
  1744. phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, phy_no);
  1745. MVS_CHIP_DISP->write_port_irq_stat(mvi, phy_no, phy->irq_status);
  1746. mv_dprintk("phy %d ctrl sts=0x%08X.\n", phy_no+mvi->id*mvi->chip->n_phy,
  1747. MVS_CHIP_DISP->read_phy_ctl(mvi, phy_no));
  1748. mv_dprintk("phy %d irq sts = 0x%08X\n", phy_no+mvi->id*mvi->chip->n_phy,
  1749. phy->irq_status);
  1750. /*
  1751. * events is port event now ,
  1752. * we need check the interrupt status which belongs to per port.
  1753. */
  1754. if (phy->irq_status & PHYEV_DCDR_ERR) {
  1755. mv_dprintk("phy %d STP decoding error.\n",
  1756. phy_no + mvi->id*mvi->chip->n_phy);
  1757. }
  1758. if (phy->irq_status & PHYEV_POOF) {
  1759. mdelay(500);
  1760. if (!(phy->phy_event & PHY_PLUG_OUT)) {
  1761. int dev_sata = phy->phy_type & PORT_TYPE_SATA;
  1762. int ready;
  1763. mvs_do_release_task(mvi, phy_no, NULL);
  1764. phy->phy_event |= PHY_PLUG_OUT;
  1765. MVS_CHIP_DISP->clear_srs_irq(mvi, 0, 1);
  1766. mvs_handle_event(mvi,
  1767. (void *)(unsigned long)phy_no,
  1768. PHY_PLUG_EVENT);
  1769. ready = mvs_is_phy_ready(mvi, phy_no);
  1770. if (ready || dev_sata) {
  1771. if (MVS_CHIP_DISP->stp_reset)
  1772. MVS_CHIP_DISP->stp_reset(mvi,
  1773. phy_no);
  1774. else
  1775. MVS_CHIP_DISP->phy_reset(mvi,
  1776. phy_no, MVS_SOFT_RESET);
  1777. return;
  1778. }
  1779. }
  1780. }
  1781. if (phy->irq_status & PHYEV_COMWAKE) {
  1782. tmp = MVS_CHIP_DISP->read_port_irq_mask(mvi, phy_no);
  1783. MVS_CHIP_DISP->write_port_irq_mask(mvi, phy_no,
  1784. tmp | PHYEV_SIG_FIS);
  1785. if (phy->timer.function == NULL) {
  1786. phy->timer.data = (unsigned long)phy;
  1787. phy->timer.function = mvs_sig_time_out;
  1788. phy->timer.expires = jiffies + 5*HZ;
  1789. add_timer(&phy->timer);
  1790. }
  1791. }
  1792. if (phy->irq_status & (PHYEV_SIG_FIS | PHYEV_ID_DONE)) {
  1793. phy->phy_status = mvs_is_phy_ready(mvi, phy_no);
  1794. mv_dprintk("notify plug in on phy[%d]\n", phy_no);
  1795. if (phy->phy_status) {
  1796. mdelay(10);
  1797. MVS_CHIP_DISP->detect_porttype(mvi, phy_no);
  1798. if (phy->phy_type & PORT_TYPE_SATA) {
  1799. tmp = MVS_CHIP_DISP->read_port_irq_mask(
  1800. mvi, phy_no);
  1801. tmp &= ~PHYEV_SIG_FIS;
  1802. MVS_CHIP_DISP->write_port_irq_mask(mvi,
  1803. phy_no, tmp);
  1804. }
  1805. mvs_update_phyinfo(mvi, phy_no, 0);
  1806. if (phy->phy_type & PORT_TYPE_SAS) {
  1807. MVS_CHIP_DISP->phy_reset(mvi, phy_no, MVS_PHY_TUNE);
  1808. mdelay(10);
  1809. }
  1810. mvs_bytes_dmaed(mvi, phy_no);
  1811. /* whether driver is going to handle hot plug */
  1812. if (phy->phy_event & PHY_PLUG_OUT) {
  1813. mvs_port_notify_formed(&phy->sas_phy, 0);
  1814. phy->phy_event &= ~PHY_PLUG_OUT;
  1815. }
  1816. } else {
  1817. mv_dprintk("plugin interrupt but phy%d is gone\n",
  1818. phy_no + mvi->id*mvi->chip->n_phy);
  1819. }
  1820. } else if (phy->irq_status & PHYEV_BROAD_CH) {
  1821. mv_dprintk("phy %d broadcast change.\n",
  1822. phy_no + mvi->id*mvi->chip->n_phy);
  1823. mvs_handle_event(mvi, (void *)(unsigned long)phy_no,
  1824. EXP_BRCT_CHG);
  1825. }
  1826. }
  1827. int mvs_int_rx(struct mvs_info *mvi, bool self_clear)
  1828. {
  1829. u32 rx_prod_idx, rx_desc;
  1830. bool attn = false;
  1831. /* the first dword in the RX ring is special: it contains
  1832. * a mirror of the hardware's RX producer index, so that
  1833. * we don't have to stall the CPU reading that register.
  1834. * The actual RX ring is offset by one dword, due to this.
  1835. */
  1836. rx_prod_idx = mvi->rx_cons;
  1837. mvi->rx_cons = le32_to_cpu(mvi->rx[0]);
  1838. if (mvi->rx_cons == 0xfff) /* h/w hasn't touched RX ring yet */
  1839. return 0;
  1840. /* The CMPL_Q may come late, read from register and try again
  1841. * note: if coalescing is enabled,
  1842. * it will need to read from register every time for sure
  1843. */
  1844. if (unlikely(mvi->rx_cons == rx_prod_idx))
  1845. mvi->rx_cons = MVS_CHIP_DISP->rx_update(mvi) & RX_RING_SZ_MASK;
  1846. if (mvi->rx_cons == rx_prod_idx)
  1847. return 0;
  1848. while (mvi->rx_cons != rx_prod_idx) {
  1849. /* increment our internal RX consumer pointer */
  1850. rx_prod_idx = (rx_prod_idx + 1) & (MVS_RX_RING_SZ - 1);
  1851. rx_desc = le32_to_cpu(mvi->rx[rx_prod_idx + 1]);
  1852. if (likely(rx_desc & RXQ_DONE))
  1853. mvs_slot_complete(mvi, rx_desc, 0);
  1854. if (rx_desc & RXQ_ATTN) {
  1855. attn = true;
  1856. } else if (rx_desc & RXQ_ERR) {
  1857. if (!(rx_desc & RXQ_DONE))
  1858. mvs_slot_complete(mvi, rx_desc, 0);
  1859. } else if (rx_desc & RXQ_SLOT_RESET) {
  1860. mvs_slot_free(mvi, rx_desc);
  1861. }
  1862. }
  1863. if (attn && self_clear)
  1864. MVS_CHIP_DISP->int_full(mvi);
  1865. return 0;
  1866. }