qeth_core_main.c 150 KB

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  1. /*
  2. * drivers/s390/net/qeth_core_main.c
  3. *
  4. * Copyright IBM Corp. 2007, 2009
  5. * Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
  6. * Frank Pavlic <fpavlic@de.ibm.com>,
  7. * Thomas Spatzier <tspat@de.ibm.com>,
  8. * Frank Blaschka <frank.blaschka@de.ibm.com>
  9. */
  10. #define KMSG_COMPONENT "qeth"
  11. #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/string.h>
  15. #include <linux/errno.h>
  16. #include <linux/kernel.h>
  17. #include <linux/ip.h>
  18. #include <linux/tcp.h>
  19. #include <linux/mii.h>
  20. #include <linux/kthread.h>
  21. #include <linux/slab.h>
  22. #include <net/iucv/af_iucv.h>
  23. #include <asm/ebcdic.h>
  24. #include <asm/io.h>
  25. #include <asm/sysinfo.h>
  26. #include "qeth_core.h"
  27. struct qeth_dbf_info qeth_dbf[QETH_DBF_INFOS] = {
  28. /* define dbf - Name, Pages, Areas, Maxlen, Level, View, Handle */
  29. /* N P A M L V H */
  30. [QETH_DBF_SETUP] = {"qeth_setup",
  31. 8, 1, 8, 5, &debug_hex_ascii_view, NULL},
  32. [QETH_DBF_MSG] = {"qeth_msg",
  33. 8, 1, 128, 3, &debug_sprintf_view, NULL},
  34. [QETH_DBF_CTRL] = {"qeth_control",
  35. 8, 1, QETH_DBF_CTRL_LEN, 5, &debug_hex_ascii_view, NULL},
  36. };
  37. EXPORT_SYMBOL_GPL(qeth_dbf);
  38. struct qeth_card_list_struct qeth_core_card_list;
  39. EXPORT_SYMBOL_GPL(qeth_core_card_list);
  40. struct kmem_cache *qeth_core_header_cache;
  41. EXPORT_SYMBOL_GPL(qeth_core_header_cache);
  42. static struct kmem_cache *qeth_qdio_outbuf_cache;
  43. static struct device *qeth_core_root_dev;
  44. static unsigned int known_devices[][6] = QETH_MODELLIST_ARRAY;
  45. static struct lock_class_key qdio_out_skb_queue_key;
  46. static void qeth_send_control_data_cb(struct qeth_channel *,
  47. struct qeth_cmd_buffer *);
  48. static int qeth_issue_next_read(struct qeth_card *);
  49. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *);
  50. static void qeth_setup_ccw(struct qeth_channel *, unsigned char *, __u32);
  51. static void qeth_free_buffer_pool(struct qeth_card *);
  52. static int qeth_qdio_establish(struct qeth_card *);
  53. static void qeth_free_qdio_buffers(struct qeth_card *);
  54. static void qeth_notify_skbs(struct qeth_qdio_out_q *queue,
  55. struct qeth_qdio_out_buffer *buf,
  56. enum iucv_tx_notify notification);
  57. static void qeth_release_skbs(struct qeth_qdio_out_buffer *buf);
  58. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  59. struct qeth_qdio_out_buffer *buf,
  60. enum qeth_qdio_buffer_states newbufstate);
  61. static int qeth_init_qdio_out_buf(struct qeth_qdio_out_q *, int);
  62. static inline const char *qeth_get_cardname(struct qeth_card *card)
  63. {
  64. if (card->info.guestlan) {
  65. switch (card->info.type) {
  66. case QETH_CARD_TYPE_OSD:
  67. return " Guest LAN QDIO";
  68. case QETH_CARD_TYPE_IQD:
  69. return " Guest LAN Hiper";
  70. case QETH_CARD_TYPE_OSM:
  71. return " Guest LAN QDIO - OSM";
  72. case QETH_CARD_TYPE_OSX:
  73. return " Guest LAN QDIO - OSX";
  74. default:
  75. return " unknown";
  76. }
  77. } else {
  78. switch (card->info.type) {
  79. case QETH_CARD_TYPE_OSD:
  80. return " OSD Express";
  81. case QETH_CARD_TYPE_IQD:
  82. return " HiperSockets";
  83. case QETH_CARD_TYPE_OSN:
  84. return " OSN QDIO";
  85. case QETH_CARD_TYPE_OSM:
  86. return " OSM QDIO";
  87. case QETH_CARD_TYPE_OSX:
  88. return " OSX QDIO";
  89. default:
  90. return " unknown";
  91. }
  92. }
  93. return " n/a";
  94. }
  95. /* max length to be returned: 14 */
  96. const char *qeth_get_cardname_short(struct qeth_card *card)
  97. {
  98. if (card->info.guestlan) {
  99. switch (card->info.type) {
  100. case QETH_CARD_TYPE_OSD:
  101. return "GuestLAN QDIO";
  102. case QETH_CARD_TYPE_IQD:
  103. return "GuestLAN Hiper";
  104. case QETH_CARD_TYPE_OSM:
  105. return "GuestLAN OSM";
  106. case QETH_CARD_TYPE_OSX:
  107. return "GuestLAN OSX";
  108. default:
  109. return "unknown";
  110. }
  111. } else {
  112. switch (card->info.type) {
  113. case QETH_CARD_TYPE_OSD:
  114. switch (card->info.link_type) {
  115. case QETH_LINK_TYPE_FAST_ETH:
  116. return "OSD_100";
  117. case QETH_LINK_TYPE_HSTR:
  118. return "HSTR";
  119. case QETH_LINK_TYPE_GBIT_ETH:
  120. return "OSD_1000";
  121. case QETH_LINK_TYPE_10GBIT_ETH:
  122. return "OSD_10GIG";
  123. case QETH_LINK_TYPE_LANE_ETH100:
  124. return "OSD_FE_LANE";
  125. case QETH_LINK_TYPE_LANE_TR:
  126. return "OSD_TR_LANE";
  127. case QETH_LINK_TYPE_LANE_ETH1000:
  128. return "OSD_GbE_LANE";
  129. case QETH_LINK_TYPE_LANE:
  130. return "OSD_ATM_LANE";
  131. default:
  132. return "OSD_Express";
  133. }
  134. case QETH_CARD_TYPE_IQD:
  135. return "HiperSockets";
  136. case QETH_CARD_TYPE_OSN:
  137. return "OSN";
  138. case QETH_CARD_TYPE_OSM:
  139. return "OSM_1000";
  140. case QETH_CARD_TYPE_OSX:
  141. return "OSX_10GIG";
  142. default:
  143. return "unknown";
  144. }
  145. }
  146. return "n/a";
  147. }
  148. void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads,
  149. int clear_start_mask)
  150. {
  151. unsigned long flags;
  152. spin_lock_irqsave(&card->thread_mask_lock, flags);
  153. card->thread_allowed_mask = threads;
  154. if (clear_start_mask)
  155. card->thread_start_mask &= threads;
  156. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  157. wake_up(&card->wait_q);
  158. }
  159. EXPORT_SYMBOL_GPL(qeth_set_allowed_threads);
  160. int qeth_threads_running(struct qeth_card *card, unsigned long threads)
  161. {
  162. unsigned long flags;
  163. int rc = 0;
  164. spin_lock_irqsave(&card->thread_mask_lock, flags);
  165. rc = (card->thread_running_mask & threads);
  166. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  167. return rc;
  168. }
  169. EXPORT_SYMBOL_GPL(qeth_threads_running);
  170. int qeth_wait_for_threads(struct qeth_card *card, unsigned long threads)
  171. {
  172. return wait_event_interruptible(card->wait_q,
  173. qeth_threads_running(card, threads) == 0);
  174. }
  175. EXPORT_SYMBOL_GPL(qeth_wait_for_threads);
  176. void qeth_clear_working_pool_list(struct qeth_card *card)
  177. {
  178. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  179. QETH_CARD_TEXT(card, 5, "clwrklst");
  180. list_for_each_entry_safe(pool_entry, tmp,
  181. &card->qdio.in_buf_pool.entry_list, list){
  182. list_del(&pool_entry->list);
  183. }
  184. }
  185. EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list);
  186. static int qeth_alloc_buffer_pool(struct qeth_card *card)
  187. {
  188. struct qeth_buffer_pool_entry *pool_entry;
  189. void *ptr;
  190. int i, j;
  191. QETH_CARD_TEXT(card, 5, "alocpool");
  192. for (i = 0; i < card->qdio.init_pool.buf_count; ++i) {
  193. pool_entry = kzalloc(sizeof(*pool_entry), GFP_KERNEL);
  194. if (!pool_entry) {
  195. qeth_free_buffer_pool(card);
  196. return -ENOMEM;
  197. }
  198. for (j = 0; j < QETH_MAX_BUFFER_ELEMENTS(card); ++j) {
  199. ptr = (void *) __get_free_page(GFP_KERNEL);
  200. if (!ptr) {
  201. while (j > 0)
  202. free_page((unsigned long)
  203. pool_entry->elements[--j]);
  204. kfree(pool_entry);
  205. qeth_free_buffer_pool(card);
  206. return -ENOMEM;
  207. }
  208. pool_entry->elements[j] = ptr;
  209. }
  210. list_add(&pool_entry->init_list,
  211. &card->qdio.init_pool.entry_list);
  212. }
  213. return 0;
  214. }
  215. int qeth_realloc_buffer_pool(struct qeth_card *card, int bufcnt)
  216. {
  217. QETH_CARD_TEXT(card, 2, "realcbp");
  218. if ((card->state != CARD_STATE_DOWN) &&
  219. (card->state != CARD_STATE_RECOVER))
  220. return -EPERM;
  221. /* TODO: steel/add buffers from/to a running card's buffer pool (?) */
  222. qeth_clear_working_pool_list(card);
  223. qeth_free_buffer_pool(card);
  224. card->qdio.in_buf_pool.buf_count = bufcnt;
  225. card->qdio.init_pool.buf_count = bufcnt;
  226. return qeth_alloc_buffer_pool(card);
  227. }
  228. EXPORT_SYMBOL_GPL(qeth_realloc_buffer_pool);
  229. static inline int qeth_cq_init(struct qeth_card *card)
  230. {
  231. int rc;
  232. if (card->options.cq == QETH_CQ_ENABLED) {
  233. QETH_DBF_TEXT(SETUP, 2, "cqinit");
  234. memset(card->qdio.c_q->qdio_bufs, 0,
  235. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  236. card->qdio.c_q->next_buf_to_init = 127;
  237. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT,
  238. card->qdio.no_in_queues - 1, 0,
  239. 127);
  240. if (rc) {
  241. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  242. goto out;
  243. }
  244. }
  245. rc = 0;
  246. out:
  247. return rc;
  248. }
  249. static inline int qeth_alloc_cq(struct qeth_card *card)
  250. {
  251. int rc;
  252. if (card->options.cq == QETH_CQ_ENABLED) {
  253. int i;
  254. struct qdio_outbuf_state *outbuf_states;
  255. QETH_DBF_TEXT(SETUP, 2, "cqon");
  256. card->qdio.c_q = kzalloc(sizeof(struct qeth_qdio_q),
  257. GFP_KERNEL);
  258. if (!card->qdio.c_q) {
  259. rc = -1;
  260. goto kmsg_out;
  261. }
  262. QETH_DBF_HEX(SETUP, 2, &card->qdio.c_q, sizeof(void *));
  263. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i) {
  264. card->qdio.c_q->bufs[i].buffer =
  265. &card->qdio.c_q->qdio_bufs[i];
  266. }
  267. card->qdio.no_in_queues = 2;
  268. card->qdio.out_bufstates = (struct qdio_outbuf_state *)
  269. kzalloc(card->qdio.no_out_queues *
  270. QDIO_MAX_BUFFERS_PER_Q *
  271. sizeof(struct qdio_outbuf_state), GFP_KERNEL);
  272. outbuf_states = card->qdio.out_bufstates;
  273. if (outbuf_states == NULL) {
  274. rc = -1;
  275. goto free_cq_out;
  276. }
  277. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  278. card->qdio.out_qs[i]->bufstates = outbuf_states;
  279. outbuf_states += QDIO_MAX_BUFFERS_PER_Q;
  280. }
  281. } else {
  282. QETH_DBF_TEXT(SETUP, 2, "nocq");
  283. card->qdio.c_q = NULL;
  284. card->qdio.no_in_queues = 1;
  285. }
  286. QETH_DBF_TEXT_(SETUP, 2, "iqc%d", card->qdio.no_in_queues);
  287. rc = 0;
  288. out:
  289. return rc;
  290. free_cq_out:
  291. kfree(card->qdio.c_q);
  292. card->qdio.c_q = NULL;
  293. kmsg_out:
  294. dev_err(&card->gdev->dev, "Failed to create completion queue\n");
  295. goto out;
  296. }
  297. static inline void qeth_free_cq(struct qeth_card *card)
  298. {
  299. if (card->qdio.c_q) {
  300. --card->qdio.no_in_queues;
  301. kfree(card->qdio.c_q);
  302. card->qdio.c_q = NULL;
  303. }
  304. kfree(card->qdio.out_bufstates);
  305. card->qdio.out_bufstates = NULL;
  306. }
  307. static inline enum iucv_tx_notify qeth_compute_cq_notification(int sbalf15,
  308. int delayed) {
  309. enum iucv_tx_notify n;
  310. switch (sbalf15) {
  311. case 0:
  312. n = delayed ? TX_NOTIFY_DELAYED_OK : TX_NOTIFY_OK;
  313. break;
  314. case 4:
  315. case 16:
  316. case 17:
  317. case 18:
  318. n = delayed ? TX_NOTIFY_DELAYED_UNREACHABLE :
  319. TX_NOTIFY_UNREACHABLE;
  320. break;
  321. default:
  322. n = delayed ? TX_NOTIFY_DELAYED_GENERALERROR :
  323. TX_NOTIFY_GENERALERROR;
  324. break;
  325. }
  326. return n;
  327. }
  328. static inline void qeth_cleanup_handled_pending(struct qeth_qdio_out_q *q,
  329. int bidx, int forced_cleanup)
  330. {
  331. if (q->card->options.cq != QETH_CQ_ENABLED)
  332. return;
  333. if (q->bufs[bidx]->next_pending != NULL) {
  334. struct qeth_qdio_out_buffer *head = q->bufs[bidx];
  335. struct qeth_qdio_out_buffer *c = q->bufs[bidx]->next_pending;
  336. while (c) {
  337. if (forced_cleanup ||
  338. atomic_read(&c->state) ==
  339. QETH_QDIO_BUF_HANDLED_DELAYED) {
  340. struct qeth_qdio_out_buffer *f = c;
  341. QETH_CARD_TEXT(f->q->card, 5, "fp");
  342. QETH_CARD_TEXT_(f->q->card, 5, "%lx", (long) f);
  343. /* release here to avoid interleaving between
  344. outbound tasklet and inbound tasklet
  345. regarding notifications and lifecycle */
  346. qeth_release_skbs(c);
  347. c = f->next_pending;
  348. BUG_ON(head->next_pending != f);
  349. head->next_pending = c;
  350. kmem_cache_free(qeth_qdio_outbuf_cache, f);
  351. } else {
  352. head = c;
  353. c = c->next_pending;
  354. }
  355. }
  356. }
  357. if (forced_cleanup && (atomic_read(&(q->bufs[bidx]->state)) ==
  358. QETH_QDIO_BUF_HANDLED_DELAYED)) {
  359. /* for recovery situations */
  360. q->bufs[bidx]->aob = q->bufstates[bidx].aob;
  361. qeth_init_qdio_out_buf(q, bidx);
  362. QETH_CARD_TEXT(q->card, 2, "clprecov");
  363. }
  364. }
  365. static inline void qeth_qdio_handle_aob(struct qeth_card *card,
  366. unsigned long phys_aob_addr) {
  367. struct qaob *aob;
  368. struct qeth_qdio_out_buffer *buffer;
  369. enum iucv_tx_notify notification;
  370. aob = (struct qaob *) phys_to_virt(phys_aob_addr);
  371. QETH_CARD_TEXT(card, 5, "haob");
  372. QETH_CARD_TEXT_(card, 5, "%lx", phys_aob_addr);
  373. buffer = (struct qeth_qdio_out_buffer *) aob->user1;
  374. QETH_CARD_TEXT_(card, 5, "%lx", aob->user1);
  375. BUG_ON(buffer == NULL);
  376. if (atomic_cmpxchg(&buffer->state, QETH_QDIO_BUF_PRIMED,
  377. QETH_QDIO_BUF_IN_CQ) == QETH_QDIO_BUF_PRIMED) {
  378. notification = TX_NOTIFY_OK;
  379. } else {
  380. BUG_ON(atomic_read(&buffer->state) != QETH_QDIO_BUF_PENDING);
  381. atomic_set(&buffer->state, QETH_QDIO_BUF_IN_CQ);
  382. notification = TX_NOTIFY_DELAYED_OK;
  383. }
  384. if (aob->aorc != 0) {
  385. QETH_CARD_TEXT_(card, 2, "aorc%02X", aob->aorc);
  386. notification = qeth_compute_cq_notification(aob->aorc, 1);
  387. }
  388. qeth_notify_skbs(buffer->q, buffer, notification);
  389. buffer->aob = NULL;
  390. qeth_clear_output_buffer(buffer->q, buffer,
  391. QETH_QDIO_BUF_HANDLED_DELAYED);
  392. /* from here on: do not touch buffer anymore */
  393. qdio_release_aob(aob);
  394. }
  395. static inline int qeth_is_cq(struct qeth_card *card, unsigned int queue)
  396. {
  397. return card->options.cq == QETH_CQ_ENABLED &&
  398. card->qdio.c_q != NULL &&
  399. queue != 0 &&
  400. queue == card->qdio.no_in_queues - 1;
  401. }
  402. static int qeth_issue_next_read(struct qeth_card *card)
  403. {
  404. int rc;
  405. struct qeth_cmd_buffer *iob;
  406. QETH_CARD_TEXT(card, 5, "issnxrd");
  407. if (card->read.state != CH_STATE_UP)
  408. return -EIO;
  409. iob = qeth_get_buffer(&card->read);
  410. if (!iob) {
  411. dev_warn(&card->gdev->dev, "The qeth device driver "
  412. "failed to recover an error on the device\n");
  413. QETH_DBF_MESSAGE(2, "%s issue_next_read failed: no iob "
  414. "available\n", dev_name(&card->gdev->dev));
  415. return -ENOMEM;
  416. }
  417. qeth_setup_ccw(&card->read, iob->data, QETH_BUFSIZE);
  418. QETH_CARD_TEXT(card, 6, "noirqpnd");
  419. rc = ccw_device_start(card->read.ccwdev, &card->read.ccw,
  420. (addr_t) iob, 0, 0);
  421. if (rc) {
  422. QETH_DBF_MESSAGE(2, "%s error in starting next read ccw! "
  423. "rc=%i\n", dev_name(&card->gdev->dev), rc);
  424. atomic_set(&card->read.irq_pending, 0);
  425. card->read_or_write_problem = 1;
  426. qeth_schedule_recovery(card);
  427. wake_up(&card->wait_q);
  428. }
  429. return rc;
  430. }
  431. static struct qeth_reply *qeth_alloc_reply(struct qeth_card *card)
  432. {
  433. struct qeth_reply *reply;
  434. reply = kzalloc(sizeof(struct qeth_reply), GFP_ATOMIC);
  435. if (reply) {
  436. atomic_set(&reply->refcnt, 1);
  437. atomic_set(&reply->received, 0);
  438. reply->card = card;
  439. };
  440. return reply;
  441. }
  442. static void qeth_get_reply(struct qeth_reply *reply)
  443. {
  444. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  445. atomic_inc(&reply->refcnt);
  446. }
  447. static void qeth_put_reply(struct qeth_reply *reply)
  448. {
  449. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  450. if (atomic_dec_and_test(&reply->refcnt))
  451. kfree(reply);
  452. }
  453. static void qeth_issue_ipa_msg(struct qeth_ipa_cmd *cmd, int rc,
  454. struct qeth_card *card)
  455. {
  456. char *ipa_name;
  457. int com = cmd->hdr.command;
  458. ipa_name = qeth_get_ipa_cmd_name(com);
  459. if (rc)
  460. QETH_DBF_MESSAGE(2, "IPA: %s(x%X) for %s/%s returned "
  461. "x%X \"%s\"\n",
  462. ipa_name, com, dev_name(&card->gdev->dev),
  463. QETH_CARD_IFNAME(card), rc,
  464. qeth_get_ipa_msg(rc));
  465. else
  466. QETH_DBF_MESSAGE(5, "IPA: %s(x%X) for %s/%s succeeded\n",
  467. ipa_name, com, dev_name(&card->gdev->dev),
  468. QETH_CARD_IFNAME(card));
  469. }
  470. static struct qeth_ipa_cmd *qeth_check_ipa_data(struct qeth_card *card,
  471. struct qeth_cmd_buffer *iob)
  472. {
  473. struct qeth_ipa_cmd *cmd = NULL;
  474. QETH_CARD_TEXT(card, 5, "chkipad");
  475. if (IS_IPA(iob->data)) {
  476. cmd = (struct qeth_ipa_cmd *) PDU_ENCAPSULATION(iob->data);
  477. if (IS_IPA_REPLY(cmd)) {
  478. if (cmd->hdr.command != IPA_CMD_SETCCID &&
  479. cmd->hdr.command != IPA_CMD_DELCCID &&
  480. cmd->hdr.command != IPA_CMD_MODCCID &&
  481. cmd->hdr.command != IPA_CMD_SET_DIAG_ASS)
  482. qeth_issue_ipa_msg(cmd,
  483. cmd->hdr.return_code, card);
  484. return cmd;
  485. } else {
  486. switch (cmd->hdr.command) {
  487. case IPA_CMD_STOPLAN:
  488. dev_warn(&card->gdev->dev,
  489. "The link for interface %s on CHPID"
  490. " 0x%X failed\n",
  491. QETH_CARD_IFNAME(card),
  492. card->info.chpid);
  493. card->lan_online = 0;
  494. if (card->dev && netif_carrier_ok(card->dev))
  495. netif_carrier_off(card->dev);
  496. return NULL;
  497. case IPA_CMD_STARTLAN:
  498. dev_info(&card->gdev->dev,
  499. "The link for %s on CHPID 0x%X has"
  500. " been restored\n",
  501. QETH_CARD_IFNAME(card),
  502. card->info.chpid);
  503. netif_carrier_on(card->dev);
  504. card->lan_online = 1;
  505. if (card->info.hwtrap)
  506. card->info.hwtrap = 2;
  507. qeth_schedule_recovery(card);
  508. return NULL;
  509. case IPA_CMD_MODCCID:
  510. return cmd;
  511. case IPA_CMD_REGISTER_LOCAL_ADDR:
  512. QETH_CARD_TEXT(card, 3, "irla");
  513. break;
  514. case IPA_CMD_UNREGISTER_LOCAL_ADDR:
  515. QETH_CARD_TEXT(card, 3, "urla");
  516. break;
  517. default:
  518. QETH_DBF_MESSAGE(2, "Received data is IPA "
  519. "but not a reply!\n");
  520. break;
  521. }
  522. }
  523. }
  524. return cmd;
  525. }
  526. void qeth_clear_ipacmd_list(struct qeth_card *card)
  527. {
  528. struct qeth_reply *reply, *r;
  529. unsigned long flags;
  530. QETH_CARD_TEXT(card, 4, "clipalst");
  531. spin_lock_irqsave(&card->lock, flags);
  532. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  533. qeth_get_reply(reply);
  534. reply->rc = -EIO;
  535. atomic_inc(&reply->received);
  536. list_del_init(&reply->list);
  537. wake_up(&reply->wait_q);
  538. qeth_put_reply(reply);
  539. }
  540. spin_unlock_irqrestore(&card->lock, flags);
  541. atomic_set(&card->write.irq_pending, 0);
  542. }
  543. EXPORT_SYMBOL_GPL(qeth_clear_ipacmd_list);
  544. static int qeth_check_idx_response(struct qeth_card *card,
  545. unsigned char *buffer)
  546. {
  547. if (!buffer)
  548. return 0;
  549. QETH_DBF_HEX(CTRL, 2, buffer, QETH_DBF_CTRL_LEN);
  550. if ((buffer[2] & 0xc0) == 0xc0) {
  551. QETH_DBF_MESSAGE(2, "received an IDX TERMINATE "
  552. "with cause code 0x%02x%s\n",
  553. buffer[4],
  554. ((buffer[4] == 0x22) ?
  555. " -- try another portname" : ""));
  556. QETH_CARD_TEXT(card, 2, "ckidxres");
  557. QETH_CARD_TEXT(card, 2, " idxterm");
  558. QETH_CARD_TEXT_(card, 2, " rc%d", -EIO);
  559. if (buffer[4] == 0xf6) {
  560. dev_err(&card->gdev->dev,
  561. "The qeth device is not configured "
  562. "for the OSI layer required by z/VM\n");
  563. return -EPERM;
  564. }
  565. return -EIO;
  566. }
  567. return 0;
  568. }
  569. static void qeth_setup_ccw(struct qeth_channel *channel, unsigned char *iob,
  570. __u32 len)
  571. {
  572. struct qeth_card *card;
  573. card = CARD_FROM_CDEV(channel->ccwdev);
  574. QETH_CARD_TEXT(card, 4, "setupccw");
  575. if (channel == &card->read)
  576. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  577. else
  578. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  579. channel->ccw.count = len;
  580. channel->ccw.cda = (__u32) __pa(iob);
  581. }
  582. static struct qeth_cmd_buffer *__qeth_get_buffer(struct qeth_channel *channel)
  583. {
  584. __u8 index;
  585. QETH_CARD_TEXT(CARD_FROM_CDEV(channel->ccwdev), 6, "getbuff");
  586. index = channel->io_buf_no;
  587. do {
  588. if (channel->iob[index].state == BUF_STATE_FREE) {
  589. channel->iob[index].state = BUF_STATE_LOCKED;
  590. channel->io_buf_no = (channel->io_buf_no + 1) %
  591. QETH_CMD_BUFFER_NO;
  592. memset(channel->iob[index].data, 0, QETH_BUFSIZE);
  593. return channel->iob + index;
  594. }
  595. index = (index + 1) % QETH_CMD_BUFFER_NO;
  596. } while (index != channel->io_buf_no);
  597. return NULL;
  598. }
  599. void qeth_release_buffer(struct qeth_channel *channel,
  600. struct qeth_cmd_buffer *iob)
  601. {
  602. unsigned long flags;
  603. QETH_CARD_TEXT(CARD_FROM_CDEV(channel->ccwdev), 6, "relbuff");
  604. spin_lock_irqsave(&channel->iob_lock, flags);
  605. memset(iob->data, 0, QETH_BUFSIZE);
  606. iob->state = BUF_STATE_FREE;
  607. iob->callback = qeth_send_control_data_cb;
  608. iob->rc = 0;
  609. spin_unlock_irqrestore(&channel->iob_lock, flags);
  610. }
  611. EXPORT_SYMBOL_GPL(qeth_release_buffer);
  612. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *channel)
  613. {
  614. struct qeth_cmd_buffer *buffer = NULL;
  615. unsigned long flags;
  616. spin_lock_irqsave(&channel->iob_lock, flags);
  617. buffer = __qeth_get_buffer(channel);
  618. spin_unlock_irqrestore(&channel->iob_lock, flags);
  619. return buffer;
  620. }
  621. struct qeth_cmd_buffer *qeth_wait_for_buffer(struct qeth_channel *channel)
  622. {
  623. struct qeth_cmd_buffer *buffer;
  624. wait_event(channel->wait_q,
  625. ((buffer = qeth_get_buffer(channel)) != NULL));
  626. return buffer;
  627. }
  628. EXPORT_SYMBOL_GPL(qeth_wait_for_buffer);
  629. void qeth_clear_cmd_buffers(struct qeth_channel *channel)
  630. {
  631. int cnt;
  632. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  633. qeth_release_buffer(channel, &channel->iob[cnt]);
  634. channel->buf_no = 0;
  635. channel->io_buf_no = 0;
  636. }
  637. EXPORT_SYMBOL_GPL(qeth_clear_cmd_buffers);
  638. static void qeth_send_control_data_cb(struct qeth_channel *channel,
  639. struct qeth_cmd_buffer *iob)
  640. {
  641. struct qeth_card *card;
  642. struct qeth_reply *reply, *r;
  643. struct qeth_ipa_cmd *cmd;
  644. unsigned long flags;
  645. int keep_reply;
  646. int rc = 0;
  647. card = CARD_FROM_CDEV(channel->ccwdev);
  648. QETH_CARD_TEXT(card, 4, "sndctlcb");
  649. rc = qeth_check_idx_response(card, iob->data);
  650. switch (rc) {
  651. case 0:
  652. break;
  653. case -EIO:
  654. qeth_clear_ipacmd_list(card);
  655. qeth_schedule_recovery(card);
  656. /* fall through */
  657. default:
  658. goto out;
  659. }
  660. cmd = qeth_check_ipa_data(card, iob);
  661. if ((cmd == NULL) && (card->state != CARD_STATE_DOWN))
  662. goto out;
  663. /*in case of OSN : check if cmd is set */
  664. if (card->info.type == QETH_CARD_TYPE_OSN &&
  665. cmd &&
  666. cmd->hdr.command != IPA_CMD_STARTLAN &&
  667. card->osn_info.assist_cb != NULL) {
  668. card->osn_info.assist_cb(card->dev, cmd);
  669. goto out;
  670. }
  671. spin_lock_irqsave(&card->lock, flags);
  672. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  673. if ((reply->seqno == QETH_IDX_COMMAND_SEQNO) ||
  674. ((cmd) && (reply->seqno == cmd->hdr.seqno))) {
  675. qeth_get_reply(reply);
  676. list_del_init(&reply->list);
  677. spin_unlock_irqrestore(&card->lock, flags);
  678. keep_reply = 0;
  679. if (reply->callback != NULL) {
  680. if (cmd) {
  681. reply->offset = (__u16)((char *)cmd -
  682. (char *)iob->data);
  683. keep_reply = reply->callback(card,
  684. reply,
  685. (unsigned long)cmd);
  686. } else
  687. keep_reply = reply->callback(card,
  688. reply,
  689. (unsigned long)iob);
  690. }
  691. if (cmd)
  692. reply->rc = (u16) cmd->hdr.return_code;
  693. else if (iob->rc)
  694. reply->rc = iob->rc;
  695. if (keep_reply) {
  696. spin_lock_irqsave(&card->lock, flags);
  697. list_add_tail(&reply->list,
  698. &card->cmd_waiter_list);
  699. spin_unlock_irqrestore(&card->lock, flags);
  700. } else {
  701. atomic_inc(&reply->received);
  702. wake_up(&reply->wait_q);
  703. }
  704. qeth_put_reply(reply);
  705. goto out;
  706. }
  707. }
  708. spin_unlock_irqrestore(&card->lock, flags);
  709. out:
  710. memcpy(&card->seqno.pdu_hdr_ack,
  711. QETH_PDU_HEADER_SEQ_NO(iob->data),
  712. QETH_SEQ_NO_LENGTH);
  713. qeth_release_buffer(channel, iob);
  714. }
  715. static int qeth_setup_channel(struct qeth_channel *channel)
  716. {
  717. int cnt;
  718. QETH_DBF_TEXT(SETUP, 2, "setupch");
  719. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) {
  720. channel->iob[cnt].data =
  721. kzalloc(QETH_BUFSIZE, GFP_DMA|GFP_KERNEL);
  722. if (channel->iob[cnt].data == NULL)
  723. break;
  724. channel->iob[cnt].state = BUF_STATE_FREE;
  725. channel->iob[cnt].channel = channel;
  726. channel->iob[cnt].callback = qeth_send_control_data_cb;
  727. channel->iob[cnt].rc = 0;
  728. }
  729. if (cnt < QETH_CMD_BUFFER_NO) {
  730. while (cnt-- > 0)
  731. kfree(channel->iob[cnt].data);
  732. return -ENOMEM;
  733. }
  734. channel->buf_no = 0;
  735. channel->io_buf_no = 0;
  736. atomic_set(&channel->irq_pending, 0);
  737. spin_lock_init(&channel->iob_lock);
  738. init_waitqueue_head(&channel->wait_q);
  739. return 0;
  740. }
  741. static int qeth_set_thread_start_bit(struct qeth_card *card,
  742. unsigned long thread)
  743. {
  744. unsigned long flags;
  745. spin_lock_irqsave(&card->thread_mask_lock, flags);
  746. if (!(card->thread_allowed_mask & thread) ||
  747. (card->thread_start_mask & thread)) {
  748. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  749. return -EPERM;
  750. }
  751. card->thread_start_mask |= thread;
  752. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  753. return 0;
  754. }
  755. void qeth_clear_thread_start_bit(struct qeth_card *card, unsigned long thread)
  756. {
  757. unsigned long flags;
  758. spin_lock_irqsave(&card->thread_mask_lock, flags);
  759. card->thread_start_mask &= ~thread;
  760. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  761. wake_up(&card->wait_q);
  762. }
  763. EXPORT_SYMBOL_GPL(qeth_clear_thread_start_bit);
  764. void qeth_clear_thread_running_bit(struct qeth_card *card, unsigned long thread)
  765. {
  766. unsigned long flags;
  767. spin_lock_irqsave(&card->thread_mask_lock, flags);
  768. card->thread_running_mask &= ~thread;
  769. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  770. wake_up(&card->wait_q);
  771. }
  772. EXPORT_SYMBOL_GPL(qeth_clear_thread_running_bit);
  773. static int __qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  774. {
  775. unsigned long flags;
  776. int rc = 0;
  777. spin_lock_irqsave(&card->thread_mask_lock, flags);
  778. if (card->thread_start_mask & thread) {
  779. if ((card->thread_allowed_mask & thread) &&
  780. !(card->thread_running_mask & thread)) {
  781. rc = 1;
  782. card->thread_start_mask &= ~thread;
  783. card->thread_running_mask |= thread;
  784. } else
  785. rc = -EPERM;
  786. }
  787. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  788. return rc;
  789. }
  790. int qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  791. {
  792. int rc = 0;
  793. wait_event(card->wait_q,
  794. (rc = __qeth_do_run_thread(card, thread)) >= 0);
  795. return rc;
  796. }
  797. EXPORT_SYMBOL_GPL(qeth_do_run_thread);
  798. void qeth_schedule_recovery(struct qeth_card *card)
  799. {
  800. QETH_CARD_TEXT(card, 2, "startrec");
  801. if (qeth_set_thread_start_bit(card, QETH_RECOVER_THREAD) == 0)
  802. schedule_work(&card->kernel_thread_starter);
  803. }
  804. EXPORT_SYMBOL_GPL(qeth_schedule_recovery);
  805. static int qeth_get_problem(struct ccw_device *cdev, struct irb *irb)
  806. {
  807. int dstat, cstat;
  808. char *sense;
  809. struct qeth_card *card;
  810. sense = (char *) irb->ecw;
  811. cstat = irb->scsw.cmd.cstat;
  812. dstat = irb->scsw.cmd.dstat;
  813. card = CARD_FROM_CDEV(cdev);
  814. if (cstat & (SCHN_STAT_CHN_CTRL_CHK | SCHN_STAT_INTF_CTRL_CHK |
  815. SCHN_STAT_CHN_DATA_CHK | SCHN_STAT_CHAIN_CHECK |
  816. SCHN_STAT_PROT_CHECK | SCHN_STAT_PROG_CHECK)) {
  817. QETH_CARD_TEXT(card, 2, "CGENCHK");
  818. dev_warn(&cdev->dev, "The qeth device driver "
  819. "failed to recover an error on the device\n");
  820. QETH_DBF_MESSAGE(2, "%s check on device dstat=x%x, cstat=x%x\n",
  821. dev_name(&cdev->dev), dstat, cstat);
  822. print_hex_dump(KERN_WARNING, "qeth: irb ", DUMP_PREFIX_OFFSET,
  823. 16, 1, irb, 64, 1);
  824. return 1;
  825. }
  826. if (dstat & DEV_STAT_UNIT_CHECK) {
  827. if (sense[SENSE_RESETTING_EVENT_BYTE] &
  828. SENSE_RESETTING_EVENT_FLAG) {
  829. QETH_CARD_TEXT(card, 2, "REVIND");
  830. return 1;
  831. }
  832. if (sense[SENSE_COMMAND_REJECT_BYTE] &
  833. SENSE_COMMAND_REJECT_FLAG) {
  834. QETH_CARD_TEXT(card, 2, "CMDREJi");
  835. return 1;
  836. }
  837. if ((sense[2] == 0xaf) && (sense[3] == 0xfe)) {
  838. QETH_CARD_TEXT(card, 2, "AFFE");
  839. return 1;
  840. }
  841. if ((!sense[0]) && (!sense[1]) && (!sense[2]) && (!sense[3])) {
  842. QETH_CARD_TEXT(card, 2, "ZEROSEN");
  843. return 0;
  844. }
  845. QETH_CARD_TEXT(card, 2, "DGENCHK");
  846. return 1;
  847. }
  848. return 0;
  849. }
  850. static long __qeth_check_irb_error(struct ccw_device *cdev,
  851. unsigned long intparm, struct irb *irb)
  852. {
  853. struct qeth_card *card;
  854. card = CARD_FROM_CDEV(cdev);
  855. if (!IS_ERR(irb))
  856. return 0;
  857. switch (PTR_ERR(irb)) {
  858. case -EIO:
  859. QETH_DBF_MESSAGE(2, "%s i/o-error on device\n",
  860. dev_name(&cdev->dev));
  861. QETH_CARD_TEXT(card, 2, "ckirberr");
  862. QETH_CARD_TEXT_(card, 2, " rc%d", -EIO);
  863. break;
  864. case -ETIMEDOUT:
  865. dev_warn(&cdev->dev, "A hardware operation timed out"
  866. " on the device\n");
  867. QETH_CARD_TEXT(card, 2, "ckirberr");
  868. QETH_CARD_TEXT_(card, 2, " rc%d", -ETIMEDOUT);
  869. if (intparm == QETH_RCD_PARM) {
  870. if (card && (card->data.ccwdev == cdev)) {
  871. card->data.state = CH_STATE_DOWN;
  872. wake_up(&card->wait_q);
  873. }
  874. }
  875. break;
  876. default:
  877. QETH_DBF_MESSAGE(2, "%s unknown error %ld on device\n",
  878. dev_name(&cdev->dev), PTR_ERR(irb));
  879. QETH_CARD_TEXT(card, 2, "ckirberr");
  880. QETH_CARD_TEXT(card, 2, " rc???");
  881. }
  882. return PTR_ERR(irb);
  883. }
  884. static void qeth_irq(struct ccw_device *cdev, unsigned long intparm,
  885. struct irb *irb)
  886. {
  887. int rc;
  888. int cstat, dstat;
  889. struct qeth_cmd_buffer *buffer;
  890. struct qeth_channel *channel;
  891. struct qeth_card *card;
  892. struct qeth_cmd_buffer *iob;
  893. __u8 index;
  894. if (__qeth_check_irb_error(cdev, intparm, irb))
  895. return;
  896. cstat = irb->scsw.cmd.cstat;
  897. dstat = irb->scsw.cmd.dstat;
  898. card = CARD_FROM_CDEV(cdev);
  899. if (!card)
  900. return;
  901. QETH_CARD_TEXT(card, 5, "irq");
  902. if (card->read.ccwdev == cdev) {
  903. channel = &card->read;
  904. QETH_CARD_TEXT(card, 5, "read");
  905. } else if (card->write.ccwdev == cdev) {
  906. channel = &card->write;
  907. QETH_CARD_TEXT(card, 5, "write");
  908. } else {
  909. channel = &card->data;
  910. QETH_CARD_TEXT(card, 5, "data");
  911. }
  912. atomic_set(&channel->irq_pending, 0);
  913. if (irb->scsw.cmd.fctl & (SCSW_FCTL_CLEAR_FUNC))
  914. channel->state = CH_STATE_STOPPED;
  915. if (irb->scsw.cmd.fctl & (SCSW_FCTL_HALT_FUNC))
  916. channel->state = CH_STATE_HALTED;
  917. /*let's wake up immediately on data channel*/
  918. if ((channel == &card->data) && (intparm != 0) &&
  919. (intparm != QETH_RCD_PARM))
  920. goto out;
  921. if (intparm == QETH_CLEAR_CHANNEL_PARM) {
  922. QETH_CARD_TEXT(card, 6, "clrchpar");
  923. /* we don't have to handle this further */
  924. intparm = 0;
  925. }
  926. if (intparm == QETH_HALT_CHANNEL_PARM) {
  927. QETH_CARD_TEXT(card, 6, "hltchpar");
  928. /* we don't have to handle this further */
  929. intparm = 0;
  930. }
  931. if ((dstat & DEV_STAT_UNIT_EXCEP) ||
  932. (dstat & DEV_STAT_UNIT_CHECK) ||
  933. (cstat)) {
  934. if (irb->esw.esw0.erw.cons) {
  935. dev_warn(&channel->ccwdev->dev,
  936. "The qeth device driver failed to recover "
  937. "an error on the device\n");
  938. QETH_DBF_MESSAGE(2, "%s sense data available. cstat "
  939. "0x%X dstat 0x%X\n",
  940. dev_name(&channel->ccwdev->dev), cstat, dstat);
  941. print_hex_dump(KERN_WARNING, "qeth: irb ",
  942. DUMP_PREFIX_OFFSET, 16, 1, irb, 32, 1);
  943. print_hex_dump(KERN_WARNING, "qeth: sense data ",
  944. DUMP_PREFIX_OFFSET, 16, 1, irb->ecw, 32, 1);
  945. }
  946. if (intparm == QETH_RCD_PARM) {
  947. channel->state = CH_STATE_DOWN;
  948. goto out;
  949. }
  950. rc = qeth_get_problem(cdev, irb);
  951. if (rc) {
  952. qeth_clear_ipacmd_list(card);
  953. qeth_schedule_recovery(card);
  954. goto out;
  955. }
  956. }
  957. if (intparm == QETH_RCD_PARM) {
  958. channel->state = CH_STATE_RCD_DONE;
  959. goto out;
  960. }
  961. if (intparm) {
  962. buffer = (struct qeth_cmd_buffer *) __va((addr_t)intparm);
  963. buffer->state = BUF_STATE_PROCESSED;
  964. }
  965. if (channel == &card->data)
  966. return;
  967. if (channel == &card->read &&
  968. channel->state == CH_STATE_UP)
  969. qeth_issue_next_read(card);
  970. iob = channel->iob;
  971. index = channel->buf_no;
  972. while (iob[index].state == BUF_STATE_PROCESSED) {
  973. if (iob[index].callback != NULL)
  974. iob[index].callback(channel, iob + index);
  975. index = (index + 1) % QETH_CMD_BUFFER_NO;
  976. }
  977. channel->buf_no = index;
  978. out:
  979. wake_up(&card->wait_q);
  980. return;
  981. }
  982. static void qeth_notify_skbs(struct qeth_qdio_out_q *q,
  983. struct qeth_qdio_out_buffer *buf,
  984. enum iucv_tx_notify notification)
  985. {
  986. struct sk_buff *skb;
  987. if (skb_queue_empty(&buf->skb_list))
  988. goto out;
  989. skb = skb_peek(&buf->skb_list);
  990. while (skb) {
  991. QETH_CARD_TEXT_(q->card, 5, "skbn%d", notification);
  992. QETH_CARD_TEXT_(q->card, 5, "%lx", (long) skb);
  993. if (skb->protocol == ETH_P_AF_IUCV) {
  994. if (skb->sk) {
  995. struct iucv_sock *iucv = iucv_sk(skb->sk);
  996. iucv->sk_txnotify(skb, notification);
  997. }
  998. }
  999. if (skb_queue_is_last(&buf->skb_list, skb))
  1000. skb = NULL;
  1001. else
  1002. skb = skb_queue_next(&buf->skb_list, skb);
  1003. }
  1004. out:
  1005. return;
  1006. }
  1007. static void qeth_release_skbs(struct qeth_qdio_out_buffer *buf)
  1008. {
  1009. struct sk_buff *skb;
  1010. struct iucv_sock *iucv;
  1011. int notify_general_error = 0;
  1012. if (atomic_read(&buf->state) == QETH_QDIO_BUF_PENDING)
  1013. notify_general_error = 1;
  1014. /* release may never happen from within CQ tasklet scope */
  1015. BUG_ON(atomic_read(&buf->state) == QETH_QDIO_BUF_IN_CQ);
  1016. skb = skb_dequeue(&buf->skb_list);
  1017. while (skb) {
  1018. QETH_CARD_TEXT(buf->q->card, 5, "skbr");
  1019. QETH_CARD_TEXT_(buf->q->card, 5, "%lx", (long) skb);
  1020. if (notify_general_error && skb->protocol == ETH_P_AF_IUCV) {
  1021. if (skb->sk) {
  1022. iucv = iucv_sk(skb->sk);
  1023. iucv->sk_txnotify(skb, TX_NOTIFY_GENERALERROR);
  1024. }
  1025. }
  1026. atomic_dec(&skb->users);
  1027. dev_kfree_skb_any(skb);
  1028. skb = skb_dequeue(&buf->skb_list);
  1029. }
  1030. }
  1031. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  1032. struct qeth_qdio_out_buffer *buf,
  1033. enum qeth_qdio_buffer_states newbufstate)
  1034. {
  1035. int i;
  1036. /* is PCI flag set on buffer? */
  1037. if (buf->buffer->element[0].sflags & SBAL_SFLAGS0_PCI_REQ)
  1038. atomic_dec(&queue->set_pci_flags_count);
  1039. if (newbufstate == QETH_QDIO_BUF_EMPTY) {
  1040. qeth_release_skbs(buf);
  1041. }
  1042. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(queue->card); ++i) {
  1043. if (buf->buffer->element[i].addr && buf->is_header[i])
  1044. kmem_cache_free(qeth_core_header_cache,
  1045. buf->buffer->element[i].addr);
  1046. buf->is_header[i] = 0;
  1047. buf->buffer->element[i].length = 0;
  1048. buf->buffer->element[i].addr = NULL;
  1049. buf->buffer->element[i].eflags = 0;
  1050. buf->buffer->element[i].sflags = 0;
  1051. }
  1052. buf->buffer->element[15].eflags = 0;
  1053. buf->buffer->element[15].sflags = 0;
  1054. buf->next_element_to_fill = 0;
  1055. atomic_set(&buf->state, newbufstate);
  1056. }
  1057. static void qeth_clear_outq_buffers(struct qeth_qdio_out_q *q, int free)
  1058. {
  1059. int j;
  1060. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  1061. if (!q->bufs[j])
  1062. continue;
  1063. qeth_cleanup_handled_pending(q, j, 1);
  1064. qeth_clear_output_buffer(q, q->bufs[j], QETH_QDIO_BUF_EMPTY);
  1065. if (free) {
  1066. kmem_cache_free(qeth_qdio_outbuf_cache, q->bufs[j]);
  1067. q->bufs[j] = NULL;
  1068. }
  1069. }
  1070. }
  1071. void qeth_clear_qdio_buffers(struct qeth_card *card)
  1072. {
  1073. int i;
  1074. QETH_CARD_TEXT(card, 2, "clearqdbf");
  1075. /* clear outbound buffers to free skbs */
  1076. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  1077. if (card->qdio.out_qs[i]) {
  1078. qeth_clear_outq_buffers(card->qdio.out_qs[i], 0);
  1079. }
  1080. }
  1081. }
  1082. EXPORT_SYMBOL_GPL(qeth_clear_qdio_buffers);
  1083. static void qeth_free_buffer_pool(struct qeth_card *card)
  1084. {
  1085. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  1086. int i = 0;
  1087. list_for_each_entry_safe(pool_entry, tmp,
  1088. &card->qdio.init_pool.entry_list, init_list){
  1089. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i)
  1090. free_page((unsigned long)pool_entry->elements[i]);
  1091. list_del(&pool_entry->init_list);
  1092. kfree(pool_entry);
  1093. }
  1094. }
  1095. static void qeth_free_qdio_buffers(struct qeth_card *card)
  1096. {
  1097. int i, j;
  1098. if (atomic_xchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED) ==
  1099. QETH_QDIO_UNINITIALIZED)
  1100. return;
  1101. qeth_free_cq(card);
  1102. cancel_delayed_work_sync(&card->buffer_reclaim_work);
  1103. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  1104. dev_kfree_skb_any(card->qdio.in_q->bufs[j].rx_skb);
  1105. kfree(card->qdio.in_q);
  1106. card->qdio.in_q = NULL;
  1107. /* inbound buffer pool */
  1108. qeth_free_buffer_pool(card);
  1109. /* free outbound qdio_qs */
  1110. if (card->qdio.out_qs) {
  1111. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  1112. qeth_clear_outq_buffers(card->qdio.out_qs[i], 1);
  1113. kfree(card->qdio.out_qs[i]);
  1114. }
  1115. kfree(card->qdio.out_qs);
  1116. card->qdio.out_qs = NULL;
  1117. }
  1118. }
  1119. static void qeth_clean_channel(struct qeth_channel *channel)
  1120. {
  1121. int cnt;
  1122. QETH_DBF_TEXT(SETUP, 2, "freech");
  1123. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  1124. kfree(channel->iob[cnt].data);
  1125. }
  1126. static void qeth_get_channel_path_desc(struct qeth_card *card)
  1127. {
  1128. struct ccw_device *ccwdev;
  1129. struct channelPath_dsc {
  1130. u8 flags;
  1131. u8 lsn;
  1132. u8 desc;
  1133. u8 chpid;
  1134. u8 swla;
  1135. u8 zeroes;
  1136. u8 chla;
  1137. u8 chpp;
  1138. } *chp_dsc;
  1139. QETH_DBF_TEXT(SETUP, 2, "chp_desc");
  1140. ccwdev = card->data.ccwdev;
  1141. chp_dsc = (struct channelPath_dsc *)ccw_device_get_chp_desc(ccwdev, 0);
  1142. if (chp_dsc != NULL) {
  1143. if (card->info.type != QETH_CARD_TYPE_IQD) {
  1144. /* CHPP field bit 6 == 1 -> single queue */
  1145. if ((chp_dsc->chpp & 0x02) == 0x02) {
  1146. if ((atomic_read(&card->qdio.state) !=
  1147. QETH_QDIO_UNINITIALIZED) &&
  1148. (card->qdio.no_out_queues == 4))
  1149. /* change from 4 to 1 outbound queues */
  1150. qeth_free_qdio_buffers(card);
  1151. card->qdio.no_out_queues = 1;
  1152. if (card->qdio.default_out_queue != 0)
  1153. dev_info(&card->gdev->dev,
  1154. "Priority Queueing not supported\n");
  1155. card->qdio.default_out_queue = 0;
  1156. } else {
  1157. if ((atomic_read(&card->qdio.state) !=
  1158. QETH_QDIO_UNINITIALIZED) &&
  1159. (card->qdio.no_out_queues == 1)) {
  1160. /* change from 1 to 4 outbound queues */
  1161. qeth_free_qdio_buffers(card);
  1162. card->qdio.default_out_queue = 2;
  1163. }
  1164. card->qdio.no_out_queues = 4;
  1165. }
  1166. }
  1167. card->info.func_level = 0x4100 + chp_dsc->desc;
  1168. kfree(chp_dsc);
  1169. }
  1170. QETH_DBF_TEXT_(SETUP, 2, "nr:%x", card->qdio.no_out_queues);
  1171. QETH_DBF_TEXT_(SETUP, 2, "lvl:%02x", card->info.func_level);
  1172. return;
  1173. }
  1174. static void qeth_init_qdio_info(struct qeth_card *card)
  1175. {
  1176. QETH_DBF_TEXT(SETUP, 4, "intqdinf");
  1177. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  1178. /* inbound */
  1179. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  1180. if (card->info.type == QETH_CARD_TYPE_IQD)
  1181. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_HSDEFAULT;
  1182. else
  1183. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_DEFAULT;
  1184. card->qdio.in_buf_pool.buf_count = card->qdio.init_pool.buf_count;
  1185. INIT_LIST_HEAD(&card->qdio.in_buf_pool.entry_list);
  1186. INIT_LIST_HEAD(&card->qdio.init_pool.entry_list);
  1187. }
  1188. static void qeth_set_intial_options(struct qeth_card *card)
  1189. {
  1190. card->options.route4.type = NO_ROUTER;
  1191. card->options.route6.type = NO_ROUTER;
  1192. card->options.broadcast_mode = QETH_TR_BROADCAST_ALLRINGS;
  1193. card->options.macaddr_mode = QETH_TR_MACADDR_NONCANONICAL;
  1194. card->options.fake_broadcast = 0;
  1195. card->options.add_hhlen = DEFAULT_ADD_HHLEN;
  1196. card->options.performance_stats = 0;
  1197. card->options.rx_sg_cb = QETH_RX_SG_CB;
  1198. card->options.isolation = ISOLATION_MODE_NONE;
  1199. card->options.cq = QETH_CQ_DISABLED;
  1200. }
  1201. static int qeth_do_start_thread(struct qeth_card *card, unsigned long thread)
  1202. {
  1203. unsigned long flags;
  1204. int rc = 0;
  1205. spin_lock_irqsave(&card->thread_mask_lock, flags);
  1206. QETH_CARD_TEXT_(card, 4, " %02x%02x%02x",
  1207. (u8) card->thread_start_mask,
  1208. (u8) card->thread_allowed_mask,
  1209. (u8) card->thread_running_mask);
  1210. rc = (card->thread_start_mask & thread);
  1211. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  1212. return rc;
  1213. }
  1214. static void qeth_start_kernel_thread(struct work_struct *work)
  1215. {
  1216. struct task_struct *ts;
  1217. struct qeth_card *card = container_of(work, struct qeth_card,
  1218. kernel_thread_starter);
  1219. QETH_CARD_TEXT(card , 2, "strthrd");
  1220. if (card->read.state != CH_STATE_UP &&
  1221. card->write.state != CH_STATE_UP)
  1222. return;
  1223. if (qeth_do_start_thread(card, QETH_RECOVER_THREAD)) {
  1224. ts = kthread_run(card->discipline.recover, (void *)card,
  1225. "qeth_recover");
  1226. if (IS_ERR(ts)) {
  1227. qeth_clear_thread_start_bit(card, QETH_RECOVER_THREAD);
  1228. qeth_clear_thread_running_bit(card,
  1229. QETH_RECOVER_THREAD);
  1230. }
  1231. }
  1232. }
  1233. static int qeth_setup_card(struct qeth_card *card)
  1234. {
  1235. QETH_DBF_TEXT(SETUP, 2, "setupcrd");
  1236. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1237. card->read.state = CH_STATE_DOWN;
  1238. card->write.state = CH_STATE_DOWN;
  1239. card->data.state = CH_STATE_DOWN;
  1240. card->state = CARD_STATE_DOWN;
  1241. card->lan_online = 0;
  1242. card->read_or_write_problem = 0;
  1243. card->dev = NULL;
  1244. spin_lock_init(&card->vlanlock);
  1245. spin_lock_init(&card->mclock);
  1246. spin_lock_init(&card->lock);
  1247. spin_lock_init(&card->ip_lock);
  1248. spin_lock_init(&card->thread_mask_lock);
  1249. mutex_init(&card->conf_mutex);
  1250. mutex_init(&card->discipline_mutex);
  1251. card->thread_start_mask = 0;
  1252. card->thread_allowed_mask = 0;
  1253. card->thread_running_mask = 0;
  1254. INIT_WORK(&card->kernel_thread_starter, qeth_start_kernel_thread);
  1255. INIT_LIST_HEAD(&card->ip_list);
  1256. INIT_LIST_HEAD(card->ip_tbd_list);
  1257. INIT_LIST_HEAD(&card->cmd_waiter_list);
  1258. init_waitqueue_head(&card->wait_q);
  1259. /* initial options */
  1260. qeth_set_intial_options(card);
  1261. /* IP address takeover */
  1262. INIT_LIST_HEAD(&card->ipato.entries);
  1263. card->ipato.enabled = 0;
  1264. card->ipato.invert4 = 0;
  1265. card->ipato.invert6 = 0;
  1266. /* init QDIO stuff */
  1267. qeth_init_qdio_info(card);
  1268. INIT_DELAYED_WORK(&card->buffer_reclaim_work, qeth_buffer_reclaim_work);
  1269. return 0;
  1270. }
  1271. static void qeth_core_sl_print(struct seq_file *m, struct service_level *slr)
  1272. {
  1273. struct qeth_card *card = container_of(slr, struct qeth_card,
  1274. qeth_service_level);
  1275. if (card->info.mcl_level[0])
  1276. seq_printf(m, "qeth: %s firmware level %s\n",
  1277. CARD_BUS_ID(card), card->info.mcl_level);
  1278. }
  1279. static struct qeth_card *qeth_alloc_card(void)
  1280. {
  1281. struct qeth_card *card;
  1282. QETH_DBF_TEXT(SETUP, 2, "alloccrd");
  1283. card = kzalloc(sizeof(struct qeth_card), GFP_DMA|GFP_KERNEL);
  1284. if (!card)
  1285. goto out;
  1286. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1287. card->ip_tbd_list = kzalloc(sizeof(struct list_head), GFP_KERNEL);
  1288. if (!card->ip_tbd_list) {
  1289. QETH_DBF_TEXT(SETUP, 0, "iptbdnom");
  1290. goto out_card;
  1291. }
  1292. if (qeth_setup_channel(&card->read))
  1293. goto out_ip;
  1294. if (qeth_setup_channel(&card->write))
  1295. goto out_channel;
  1296. card->options.layer2 = -1;
  1297. card->qeth_service_level.seq_print = qeth_core_sl_print;
  1298. register_service_level(&card->qeth_service_level);
  1299. return card;
  1300. out_channel:
  1301. qeth_clean_channel(&card->read);
  1302. out_ip:
  1303. kfree(card->ip_tbd_list);
  1304. out_card:
  1305. kfree(card);
  1306. out:
  1307. return NULL;
  1308. }
  1309. static int qeth_determine_card_type(struct qeth_card *card)
  1310. {
  1311. int i = 0;
  1312. QETH_DBF_TEXT(SETUP, 2, "detcdtyp");
  1313. card->qdio.do_prio_queueing = QETH_PRIOQ_DEFAULT;
  1314. card->qdio.default_out_queue = QETH_DEFAULT_QUEUE;
  1315. while (known_devices[i][QETH_DEV_MODEL_IND]) {
  1316. if ((CARD_RDEV(card)->id.dev_type ==
  1317. known_devices[i][QETH_DEV_TYPE_IND]) &&
  1318. (CARD_RDEV(card)->id.dev_model ==
  1319. known_devices[i][QETH_DEV_MODEL_IND])) {
  1320. card->info.type = known_devices[i][QETH_DEV_MODEL_IND];
  1321. card->qdio.no_out_queues =
  1322. known_devices[i][QETH_QUEUE_NO_IND];
  1323. card->qdio.no_in_queues = 1;
  1324. card->info.is_multicast_different =
  1325. known_devices[i][QETH_MULTICAST_IND];
  1326. qeth_get_channel_path_desc(card);
  1327. return 0;
  1328. }
  1329. i++;
  1330. }
  1331. card->info.type = QETH_CARD_TYPE_UNKNOWN;
  1332. dev_err(&card->gdev->dev, "The adapter hardware is of an "
  1333. "unknown type\n");
  1334. return -ENOENT;
  1335. }
  1336. static int qeth_clear_channel(struct qeth_channel *channel)
  1337. {
  1338. unsigned long flags;
  1339. struct qeth_card *card;
  1340. int rc;
  1341. card = CARD_FROM_CDEV(channel->ccwdev);
  1342. QETH_CARD_TEXT(card, 3, "clearch");
  1343. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1344. rc = ccw_device_clear(channel->ccwdev, QETH_CLEAR_CHANNEL_PARM);
  1345. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1346. if (rc)
  1347. return rc;
  1348. rc = wait_event_interruptible_timeout(card->wait_q,
  1349. channel->state == CH_STATE_STOPPED, QETH_TIMEOUT);
  1350. if (rc == -ERESTARTSYS)
  1351. return rc;
  1352. if (channel->state != CH_STATE_STOPPED)
  1353. return -ETIME;
  1354. channel->state = CH_STATE_DOWN;
  1355. return 0;
  1356. }
  1357. static int qeth_halt_channel(struct qeth_channel *channel)
  1358. {
  1359. unsigned long flags;
  1360. struct qeth_card *card;
  1361. int rc;
  1362. card = CARD_FROM_CDEV(channel->ccwdev);
  1363. QETH_CARD_TEXT(card, 3, "haltch");
  1364. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1365. rc = ccw_device_halt(channel->ccwdev, QETH_HALT_CHANNEL_PARM);
  1366. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1367. if (rc)
  1368. return rc;
  1369. rc = wait_event_interruptible_timeout(card->wait_q,
  1370. channel->state == CH_STATE_HALTED, QETH_TIMEOUT);
  1371. if (rc == -ERESTARTSYS)
  1372. return rc;
  1373. if (channel->state != CH_STATE_HALTED)
  1374. return -ETIME;
  1375. return 0;
  1376. }
  1377. static int qeth_halt_channels(struct qeth_card *card)
  1378. {
  1379. int rc1 = 0, rc2 = 0, rc3 = 0;
  1380. QETH_CARD_TEXT(card, 3, "haltchs");
  1381. rc1 = qeth_halt_channel(&card->read);
  1382. rc2 = qeth_halt_channel(&card->write);
  1383. rc3 = qeth_halt_channel(&card->data);
  1384. if (rc1)
  1385. return rc1;
  1386. if (rc2)
  1387. return rc2;
  1388. return rc3;
  1389. }
  1390. static int qeth_clear_channels(struct qeth_card *card)
  1391. {
  1392. int rc1 = 0, rc2 = 0, rc3 = 0;
  1393. QETH_CARD_TEXT(card, 3, "clearchs");
  1394. rc1 = qeth_clear_channel(&card->read);
  1395. rc2 = qeth_clear_channel(&card->write);
  1396. rc3 = qeth_clear_channel(&card->data);
  1397. if (rc1)
  1398. return rc1;
  1399. if (rc2)
  1400. return rc2;
  1401. return rc3;
  1402. }
  1403. static int qeth_clear_halt_card(struct qeth_card *card, int halt)
  1404. {
  1405. int rc = 0;
  1406. QETH_CARD_TEXT(card, 3, "clhacrd");
  1407. if (halt)
  1408. rc = qeth_halt_channels(card);
  1409. if (rc)
  1410. return rc;
  1411. return qeth_clear_channels(card);
  1412. }
  1413. int qeth_qdio_clear_card(struct qeth_card *card, int use_halt)
  1414. {
  1415. int rc = 0;
  1416. QETH_CARD_TEXT(card, 3, "qdioclr");
  1417. switch (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ESTABLISHED,
  1418. QETH_QDIO_CLEANING)) {
  1419. case QETH_QDIO_ESTABLISHED:
  1420. if (card->info.type == QETH_CARD_TYPE_IQD)
  1421. rc = qdio_shutdown(CARD_DDEV(card),
  1422. QDIO_FLAG_CLEANUP_USING_HALT);
  1423. else
  1424. rc = qdio_shutdown(CARD_DDEV(card),
  1425. QDIO_FLAG_CLEANUP_USING_CLEAR);
  1426. if (rc)
  1427. QETH_CARD_TEXT_(card, 3, "1err%d", rc);
  1428. qdio_free(CARD_DDEV(card));
  1429. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  1430. break;
  1431. case QETH_QDIO_CLEANING:
  1432. return rc;
  1433. default:
  1434. break;
  1435. }
  1436. rc = qeth_clear_halt_card(card, use_halt);
  1437. if (rc)
  1438. QETH_CARD_TEXT_(card, 3, "2err%d", rc);
  1439. card->state = CARD_STATE_DOWN;
  1440. return rc;
  1441. }
  1442. EXPORT_SYMBOL_GPL(qeth_qdio_clear_card);
  1443. static int qeth_read_conf_data(struct qeth_card *card, void **buffer,
  1444. int *length)
  1445. {
  1446. struct ciw *ciw;
  1447. char *rcd_buf;
  1448. int ret;
  1449. struct qeth_channel *channel = &card->data;
  1450. unsigned long flags;
  1451. /*
  1452. * scan for RCD command in extended SenseID data
  1453. */
  1454. ciw = ccw_device_get_ciw(channel->ccwdev, CIW_TYPE_RCD);
  1455. if (!ciw || ciw->cmd == 0)
  1456. return -EOPNOTSUPP;
  1457. rcd_buf = kzalloc(ciw->count, GFP_KERNEL | GFP_DMA);
  1458. if (!rcd_buf)
  1459. return -ENOMEM;
  1460. channel->ccw.cmd_code = ciw->cmd;
  1461. channel->ccw.cda = (__u32) __pa(rcd_buf);
  1462. channel->ccw.count = ciw->count;
  1463. channel->ccw.flags = CCW_FLAG_SLI;
  1464. channel->state = CH_STATE_RCD;
  1465. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1466. ret = ccw_device_start_timeout(channel->ccwdev, &channel->ccw,
  1467. QETH_RCD_PARM, LPM_ANYPATH, 0,
  1468. QETH_RCD_TIMEOUT);
  1469. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1470. if (!ret)
  1471. wait_event(card->wait_q,
  1472. (channel->state == CH_STATE_RCD_DONE ||
  1473. channel->state == CH_STATE_DOWN));
  1474. if (channel->state == CH_STATE_DOWN)
  1475. ret = -EIO;
  1476. else
  1477. channel->state = CH_STATE_DOWN;
  1478. if (ret) {
  1479. kfree(rcd_buf);
  1480. *buffer = NULL;
  1481. *length = 0;
  1482. } else {
  1483. *length = ciw->count;
  1484. *buffer = rcd_buf;
  1485. }
  1486. return ret;
  1487. }
  1488. static void qeth_configure_unitaddr(struct qeth_card *card, char *prcd)
  1489. {
  1490. QETH_DBF_TEXT(SETUP, 2, "cfgunit");
  1491. card->info.chpid = prcd[30];
  1492. card->info.unit_addr2 = prcd[31];
  1493. card->info.cula = prcd[63];
  1494. card->info.guestlan = ((prcd[0x10] == _ascebc['V']) &&
  1495. (prcd[0x11] == _ascebc['M']));
  1496. }
  1497. static void qeth_configure_blkt_default(struct qeth_card *card, char *prcd)
  1498. {
  1499. QETH_DBF_TEXT(SETUP, 2, "cfgblkt");
  1500. if (prcd[74] == 0xF0 && prcd[75] == 0xF0 && prcd[76] == 0xF5) {
  1501. card->info.blkt.time_total = 250;
  1502. card->info.blkt.inter_packet = 5;
  1503. card->info.blkt.inter_packet_jumbo = 15;
  1504. } else {
  1505. card->info.blkt.time_total = 0;
  1506. card->info.blkt.inter_packet = 0;
  1507. card->info.blkt.inter_packet_jumbo = 0;
  1508. }
  1509. }
  1510. static void qeth_init_tokens(struct qeth_card *card)
  1511. {
  1512. card->token.issuer_rm_w = 0x00010103UL;
  1513. card->token.cm_filter_w = 0x00010108UL;
  1514. card->token.cm_connection_w = 0x0001010aUL;
  1515. card->token.ulp_filter_w = 0x0001010bUL;
  1516. card->token.ulp_connection_w = 0x0001010dUL;
  1517. }
  1518. static void qeth_init_func_level(struct qeth_card *card)
  1519. {
  1520. switch (card->info.type) {
  1521. case QETH_CARD_TYPE_IQD:
  1522. card->info.func_level = QETH_IDX_FUNC_LEVEL_IQD;
  1523. break;
  1524. case QETH_CARD_TYPE_OSD:
  1525. case QETH_CARD_TYPE_OSN:
  1526. card->info.func_level = QETH_IDX_FUNC_LEVEL_OSD;
  1527. break;
  1528. default:
  1529. break;
  1530. }
  1531. }
  1532. static int qeth_idx_activate_get_answer(struct qeth_channel *channel,
  1533. void (*idx_reply_cb)(struct qeth_channel *,
  1534. struct qeth_cmd_buffer *))
  1535. {
  1536. struct qeth_cmd_buffer *iob;
  1537. unsigned long flags;
  1538. int rc;
  1539. struct qeth_card *card;
  1540. QETH_DBF_TEXT(SETUP, 2, "idxanswr");
  1541. card = CARD_FROM_CDEV(channel->ccwdev);
  1542. iob = qeth_get_buffer(channel);
  1543. iob->callback = idx_reply_cb;
  1544. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  1545. channel->ccw.count = QETH_BUFSIZE;
  1546. channel->ccw.cda = (__u32) __pa(iob->data);
  1547. wait_event(card->wait_q,
  1548. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1549. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1550. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1551. rc = ccw_device_start(channel->ccwdev,
  1552. &channel->ccw, (addr_t) iob, 0, 0);
  1553. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1554. if (rc) {
  1555. QETH_DBF_MESSAGE(2, "Error2 in activating channel rc=%d\n", rc);
  1556. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1557. atomic_set(&channel->irq_pending, 0);
  1558. wake_up(&card->wait_q);
  1559. return rc;
  1560. }
  1561. rc = wait_event_interruptible_timeout(card->wait_q,
  1562. channel->state == CH_STATE_UP, QETH_TIMEOUT);
  1563. if (rc == -ERESTARTSYS)
  1564. return rc;
  1565. if (channel->state != CH_STATE_UP) {
  1566. rc = -ETIME;
  1567. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1568. qeth_clear_cmd_buffers(channel);
  1569. } else
  1570. rc = 0;
  1571. return rc;
  1572. }
  1573. static int qeth_idx_activate_channel(struct qeth_channel *channel,
  1574. void (*idx_reply_cb)(struct qeth_channel *,
  1575. struct qeth_cmd_buffer *))
  1576. {
  1577. struct qeth_card *card;
  1578. struct qeth_cmd_buffer *iob;
  1579. unsigned long flags;
  1580. __u16 temp;
  1581. __u8 tmp;
  1582. int rc;
  1583. struct ccw_dev_id temp_devid;
  1584. card = CARD_FROM_CDEV(channel->ccwdev);
  1585. QETH_DBF_TEXT(SETUP, 2, "idxactch");
  1586. iob = qeth_get_buffer(channel);
  1587. iob->callback = idx_reply_cb;
  1588. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  1589. channel->ccw.count = IDX_ACTIVATE_SIZE;
  1590. channel->ccw.cda = (__u32) __pa(iob->data);
  1591. if (channel == &card->write) {
  1592. memcpy(iob->data, IDX_ACTIVATE_WRITE, IDX_ACTIVATE_SIZE);
  1593. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1594. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1595. card->seqno.trans_hdr++;
  1596. } else {
  1597. memcpy(iob->data, IDX_ACTIVATE_READ, IDX_ACTIVATE_SIZE);
  1598. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1599. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1600. }
  1601. tmp = ((__u8)card->info.portno) | 0x80;
  1602. memcpy(QETH_IDX_ACT_PNO(iob->data), &tmp, 1);
  1603. memcpy(QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1604. &card->token.issuer_rm_w, QETH_MPC_TOKEN_LENGTH);
  1605. memcpy(QETH_IDX_ACT_FUNC_LEVEL(iob->data),
  1606. &card->info.func_level, sizeof(__u16));
  1607. ccw_device_get_id(CARD_DDEV(card), &temp_devid);
  1608. memcpy(QETH_IDX_ACT_QDIO_DEV_CUA(iob->data), &temp_devid.devno, 2);
  1609. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1610. memcpy(QETH_IDX_ACT_QDIO_DEV_REALADDR(iob->data), &temp, 2);
  1611. wait_event(card->wait_q,
  1612. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1613. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1614. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1615. rc = ccw_device_start(channel->ccwdev,
  1616. &channel->ccw, (addr_t) iob, 0, 0);
  1617. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1618. if (rc) {
  1619. QETH_DBF_MESSAGE(2, "Error1 in activating channel. rc=%d\n",
  1620. rc);
  1621. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1622. atomic_set(&channel->irq_pending, 0);
  1623. wake_up(&card->wait_q);
  1624. return rc;
  1625. }
  1626. rc = wait_event_interruptible_timeout(card->wait_q,
  1627. channel->state == CH_STATE_ACTIVATING, QETH_TIMEOUT);
  1628. if (rc == -ERESTARTSYS)
  1629. return rc;
  1630. if (channel->state != CH_STATE_ACTIVATING) {
  1631. dev_warn(&channel->ccwdev->dev, "The qeth device driver"
  1632. " failed to recover an error on the device\n");
  1633. QETH_DBF_MESSAGE(2, "%s IDX activate timed out\n",
  1634. dev_name(&channel->ccwdev->dev));
  1635. QETH_DBF_TEXT_(SETUP, 2, "2err%d", -ETIME);
  1636. qeth_clear_cmd_buffers(channel);
  1637. return -ETIME;
  1638. }
  1639. return qeth_idx_activate_get_answer(channel, idx_reply_cb);
  1640. }
  1641. static int qeth_peer_func_level(int level)
  1642. {
  1643. if ((level & 0xff) == 8)
  1644. return (level & 0xff) + 0x400;
  1645. if (((level >> 8) & 3) == 1)
  1646. return (level & 0xff) + 0x200;
  1647. return level;
  1648. }
  1649. static void qeth_idx_write_cb(struct qeth_channel *channel,
  1650. struct qeth_cmd_buffer *iob)
  1651. {
  1652. struct qeth_card *card;
  1653. __u16 temp;
  1654. QETH_DBF_TEXT(SETUP , 2, "idxwrcb");
  1655. if (channel->state == CH_STATE_DOWN) {
  1656. channel->state = CH_STATE_ACTIVATING;
  1657. goto out;
  1658. }
  1659. card = CARD_FROM_CDEV(channel->ccwdev);
  1660. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1661. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == QETH_IDX_ACT_ERR_EXCL)
  1662. dev_err(&card->write.ccwdev->dev,
  1663. "The adapter is used exclusively by another "
  1664. "host\n");
  1665. else
  1666. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel:"
  1667. " negative reply\n",
  1668. dev_name(&card->write.ccwdev->dev));
  1669. goto out;
  1670. }
  1671. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1672. if ((temp & ~0x0100) != qeth_peer_func_level(card->info.func_level)) {
  1673. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel: "
  1674. "function level mismatch (sent: 0x%x, received: "
  1675. "0x%x)\n", dev_name(&card->write.ccwdev->dev),
  1676. card->info.func_level, temp);
  1677. goto out;
  1678. }
  1679. channel->state = CH_STATE_UP;
  1680. out:
  1681. qeth_release_buffer(channel, iob);
  1682. }
  1683. static void qeth_idx_read_cb(struct qeth_channel *channel,
  1684. struct qeth_cmd_buffer *iob)
  1685. {
  1686. struct qeth_card *card;
  1687. __u16 temp;
  1688. QETH_DBF_TEXT(SETUP , 2, "idxrdcb");
  1689. if (channel->state == CH_STATE_DOWN) {
  1690. channel->state = CH_STATE_ACTIVATING;
  1691. goto out;
  1692. }
  1693. card = CARD_FROM_CDEV(channel->ccwdev);
  1694. if (qeth_check_idx_response(card, iob->data))
  1695. goto out;
  1696. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1697. switch (QETH_IDX_ACT_CAUSE_CODE(iob->data)) {
  1698. case QETH_IDX_ACT_ERR_EXCL:
  1699. dev_err(&card->write.ccwdev->dev,
  1700. "The adapter is used exclusively by another "
  1701. "host\n");
  1702. break;
  1703. case QETH_IDX_ACT_ERR_AUTH:
  1704. case QETH_IDX_ACT_ERR_AUTH_USER:
  1705. dev_err(&card->read.ccwdev->dev,
  1706. "Setting the device online failed because of "
  1707. "insufficient authorization\n");
  1708. break;
  1709. default:
  1710. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel:"
  1711. " negative reply\n",
  1712. dev_name(&card->read.ccwdev->dev));
  1713. }
  1714. QETH_CARD_TEXT_(card, 2, "idxread%c",
  1715. QETH_IDX_ACT_CAUSE_CODE(iob->data));
  1716. goto out;
  1717. }
  1718. /**
  1719. * * temporary fix for microcode bug
  1720. * * to revert it,replace OR by AND
  1721. * */
  1722. if ((!QETH_IDX_NO_PORTNAME_REQUIRED(iob->data)) ||
  1723. (card->info.type == QETH_CARD_TYPE_OSD))
  1724. card->info.portname_required = 1;
  1725. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1726. if (temp != qeth_peer_func_level(card->info.func_level)) {
  1727. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel: function "
  1728. "level mismatch (sent: 0x%x, received: 0x%x)\n",
  1729. dev_name(&card->read.ccwdev->dev),
  1730. card->info.func_level, temp);
  1731. goto out;
  1732. }
  1733. memcpy(&card->token.issuer_rm_r,
  1734. QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1735. QETH_MPC_TOKEN_LENGTH);
  1736. memcpy(&card->info.mcl_level[0],
  1737. QETH_IDX_REPLY_LEVEL(iob->data), QETH_MCL_LENGTH);
  1738. channel->state = CH_STATE_UP;
  1739. out:
  1740. qeth_release_buffer(channel, iob);
  1741. }
  1742. void qeth_prepare_control_data(struct qeth_card *card, int len,
  1743. struct qeth_cmd_buffer *iob)
  1744. {
  1745. qeth_setup_ccw(&card->write, iob->data, len);
  1746. iob->callback = qeth_release_buffer;
  1747. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1748. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1749. card->seqno.trans_hdr++;
  1750. memcpy(QETH_PDU_HEADER_SEQ_NO(iob->data),
  1751. &card->seqno.pdu_hdr, QETH_SEQ_NO_LENGTH);
  1752. card->seqno.pdu_hdr++;
  1753. memcpy(QETH_PDU_HEADER_ACK_SEQ_NO(iob->data),
  1754. &card->seqno.pdu_hdr_ack, QETH_SEQ_NO_LENGTH);
  1755. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1756. }
  1757. EXPORT_SYMBOL_GPL(qeth_prepare_control_data);
  1758. int qeth_send_control_data(struct qeth_card *card, int len,
  1759. struct qeth_cmd_buffer *iob,
  1760. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  1761. unsigned long),
  1762. void *reply_param)
  1763. {
  1764. int rc;
  1765. unsigned long flags;
  1766. struct qeth_reply *reply = NULL;
  1767. unsigned long timeout, event_timeout;
  1768. struct qeth_ipa_cmd *cmd;
  1769. QETH_CARD_TEXT(card, 2, "sendctl");
  1770. if (card->read_or_write_problem) {
  1771. qeth_release_buffer(iob->channel, iob);
  1772. return -EIO;
  1773. }
  1774. reply = qeth_alloc_reply(card);
  1775. if (!reply) {
  1776. return -ENOMEM;
  1777. }
  1778. reply->callback = reply_cb;
  1779. reply->param = reply_param;
  1780. if (card->state == CARD_STATE_DOWN)
  1781. reply->seqno = QETH_IDX_COMMAND_SEQNO;
  1782. else
  1783. reply->seqno = card->seqno.ipa++;
  1784. init_waitqueue_head(&reply->wait_q);
  1785. spin_lock_irqsave(&card->lock, flags);
  1786. list_add_tail(&reply->list, &card->cmd_waiter_list);
  1787. spin_unlock_irqrestore(&card->lock, flags);
  1788. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1789. while (atomic_cmpxchg(&card->write.irq_pending, 0, 1)) ;
  1790. qeth_prepare_control_data(card, len, iob);
  1791. if (IS_IPA(iob->data))
  1792. event_timeout = QETH_IPA_TIMEOUT;
  1793. else
  1794. event_timeout = QETH_TIMEOUT;
  1795. timeout = jiffies + event_timeout;
  1796. QETH_CARD_TEXT(card, 6, "noirqpnd");
  1797. spin_lock_irqsave(get_ccwdev_lock(card->write.ccwdev), flags);
  1798. rc = ccw_device_start(card->write.ccwdev, &card->write.ccw,
  1799. (addr_t) iob, 0, 0);
  1800. spin_unlock_irqrestore(get_ccwdev_lock(card->write.ccwdev), flags);
  1801. if (rc) {
  1802. QETH_DBF_MESSAGE(2, "%s qeth_send_control_data: "
  1803. "ccw_device_start rc = %i\n",
  1804. dev_name(&card->write.ccwdev->dev), rc);
  1805. QETH_CARD_TEXT_(card, 2, " err%d", rc);
  1806. spin_lock_irqsave(&card->lock, flags);
  1807. list_del_init(&reply->list);
  1808. qeth_put_reply(reply);
  1809. spin_unlock_irqrestore(&card->lock, flags);
  1810. qeth_release_buffer(iob->channel, iob);
  1811. atomic_set(&card->write.irq_pending, 0);
  1812. wake_up(&card->wait_q);
  1813. return rc;
  1814. }
  1815. /* we have only one long running ipassist, since we can ensure
  1816. process context of this command we can sleep */
  1817. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  1818. if ((cmd->hdr.command == IPA_CMD_SETIP) &&
  1819. (cmd->hdr.prot_version == QETH_PROT_IPV4)) {
  1820. if (!wait_event_timeout(reply->wait_q,
  1821. atomic_read(&reply->received), event_timeout))
  1822. goto time_err;
  1823. } else {
  1824. while (!atomic_read(&reply->received)) {
  1825. if (time_after(jiffies, timeout))
  1826. goto time_err;
  1827. cpu_relax();
  1828. };
  1829. }
  1830. if (reply->rc == -EIO)
  1831. goto error;
  1832. rc = reply->rc;
  1833. qeth_put_reply(reply);
  1834. return rc;
  1835. time_err:
  1836. reply->rc = -ETIME;
  1837. spin_lock_irqsave(&reply->card->lock, flags);
  1838. list_del_init(&reply->list);
  1839. spin_unlock_irqrestore(&reply->card->lock, flags);
  1840. atomic_inc(&reply->received);
  1841. error:
  1842. atomic_set(&card->write.irq_pending, 0);
  1843. qeth_release_buffer(iob->channel, iob);
  1844. card->write.buf_no = (card->write.buf_no + 1) % QETH_CMD_BUFFER_NO;
  1845. rc = reply->rc;
  1846. qeth_put_reply(reply);
  1847. return rc;
  1848. }
  1849. EXPORT_SYMBOL_GPL(qeth_send_control_data);
  1850. static int qeth_cm_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1851. unsigned long data)
  1852. {
  1853. struct qeth_cmd_buffer *iob;
  1854. QETH_DBF_TEXT(SETUP, 2, "cmenblcb");
  1855. iob = (struct qeth_cmd_buffer *) data;
  1856. memcpy(&card->token.cm_filter_r,
  1857. QETH_CM_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1858. QETH_MPC_TOKEN_LENGTH);
  1859. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1860. return 0;
  1861. }
  1862. static int qeth_cm_enable(struct qeth_card *card)
  1863. {
  1864. int rc;
  1865. struct qeth_cmd_buffer *iob;
  1866. QETH_DBF_TEXT(SETUP, 2, "cmenable");
  1867. iob = qeth_wait_for_buffer(&card->write);
  1868. memcpy(iob->data, CM_ENABLE, CM_ENABLE_SIZE);
  1869. memcpy(QETH_CM_ENABLE_ISSUER_RM_TOKEN(iob->data),
  1870. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1871. memcpy(QETH_CM_ENABLE_FILTER_TOKEN(iob->data),
  1872. &card->token.cm_filter_w, QETH_MPC_TOKEN_LENGTH);
  1873. rc = qeth_send_control_data(card, CM_ENABLE_SIZE, iob,
  1874. qeth_cm_enable_cb, NULL);
  1875. return rc;
  1876. }
  1877. static int qeth_cm_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1878. unsigned long data)
  1879. {
  1880. struct qeth_cmd_buffer *iob;
  1881. QETH_DBF_TEXT(SETUP, 2, "cmsetpcb");
  1882. iob = (struct qeth_cmd_buffer *) data;
  1883. memcpy(&card->token.cm_connection_r,
  1884. QETH_CM_SETUP_RESP_DEST_ADDR(iob->data),
  1885. QETH_MPC_TOKEN_LENGTH);
  1886. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1887. return 0;
  1888. }
  1889. static int qeth_cm_setup(struct qeth_card *card)
  1890. {
  1891. int rc;
  1892. struct qeth_cmd_buffer *iob;
  1893. QETH_DBF_TEXT(SETUP, 2, "cmsetup");
  1894. iob = qeth_wait_for_buffer(&card->write);
  1895. memcpy(iob->data, CM_SETUP, CM_SETUP_SIZE);
  1896. memcpy(QETH_CM_SETUP_DEST_ADDR(iob->data),
  1897. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1898. memcpy(QETH_CM_SETUP_CONNECTION_TOKEN(iob->data),
  1899. &card->token.cm_connection_w, QETH_MPC_TOKEN_LENGTH);
  1900. memcpy(QETH_CM_SETUP_FILTER_TOKEN(iob->data),
  1901. &card->token.cm_filter_r, QETH_MPC_TOKEN_LENGTH);
  1902. rc = qeth_send_control_data(card, CM_SETUP_SIZE, iob,
  1903. qeth_cm_setup_cb, NULL);
  1904. return rc;
  1905. }
  1906. static inline int qeth_get_initial_mtu_for_card(struct qeth_card *card)
  1907. {
  1908. switch (card->info.type) {
  1909. case QETH_CARD_TYPE_UNKNOWN:
  1910. return 1500;
  1911. case QETH_CARD_TYPE_IQD:
  1912. return card->info.max_mtu;
  1913. case QETH_CARD_TYPE_OSD:
  1914. switch (card->info.link_type) {
  1915. case QETH_LINK_TYPE_HSTR:
  1916. case QETH_LINK_TYPE_LANE_TR:
  1917. return 2000;
  1918. default:
  1919. return 1492;
  1920. }
  1921. case QETH_CARD_TYPE_OSM:
  1922. case QETH_CARD_TYPE_OSX:
  1923. return 1492;
  1924. default:
  1925. return 1500;
  1926. }
  1927. }
  1928. static inline int qeth_get_mtu_outof_framesize(int framesize)
  1929. {
  1930. switch (framesize) {
  1931. case 0x4000:
  1932. return 8192;
  1933. case 0x6000:
  1934. return 16384;
  1935. case 0xa000:
  1936. return 32768;
  1937. case 0xffff:
  1938. return 57344;
  1939. default:
  1940. return 0;
  1941. }
  1942. }
  1943. static inline int qeth_mtu_is_valid(struct qeth_card *card, int mtu)
  1944. {
  1945. switch (card->info.type) {
  1946. case QETH_CARD_TYPE_OSD:
  1947. case QETH_CARD_TYPE_OSM:
  1948. case QETH_CARD_TYPE_OSX:
  1949. case QETH_CARD_TYPE_IQD:
  1950. return ((mtu >= 576) &&
  1951. (mtu <= card->info.max_mtu));
  1952. case QETH_CARD_TYPE_OSN:
  1953. case QETH_CARD_TYPE_UNKNOWN:
  1954. default:
  1955. return 1;
  1956. }
  1957. }
  1958. static int qeth_ulp_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1959. unsigned long data)
  1960. {
  1961. __u16 mtu, framesize;
  1962. __u16 len;
  1963. __u8 link_type;
  1964. struct qeth_cmd_buffer *iob;
  1965. QETH_DBF_TEXT(SETUP, 2, "ulpenacb");
  1966. iob = (struct qeth_cmd_buffer *) data;
  1967. memcpy(&card->token.ulp_filter_r,
  1968. QETH_ULP_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1969. QETH_MPC_TOKEN_LENGTH);
  1970. if (card->info.type == QETH_CARD_TYPE_IQD) {
  1971. memcpy(&framesize, QETH_ULP_ENABLE_RESP_MAX_MTU(iob->data), 2);
  1972. mtu = qeth_get_mtu_outof_framesize(framesize);
  1973. if (!mtu) {
  1974. iob->rc = -EINVAL;
  1975. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1976. return 0;
  1977. }
  1978. if (card->info.initial_mtu && (card->info.initial_mtu != mtu)) {
  1979. /* frame size has changed */
  1980. if (card->dev &&
  1981. ((card->dev->mtu == card->info.initial_mtu) ||
  1982. (card->dev->mtu > mtu)))
  1983. card->dev->mtu = mtu;
  1984. qeth_free_qdio_buffers(card);
  1985. }
  1986. card->info.initial_mtu = mtu;
  1987. card->info.max_mtu = mtu;
  1988. card->qdio.in_buf_size = mtu + 2 * PAGE_SIZE;
  1989. } else {
  1990. card->info.initial_mtu = qeth_get_initial_mtu_for_card(card);
  1991. card->info.max_mtu = *(__u16 *)QETH_ULP_ENABLE_RESP_MAX_MTU(
  1992. iob->data);
  1993. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  1994. }
  1995. memcpy(&len, QETH_ULP_ENABLE_RESP_DIFINFO_LEN(iob->data), 2);
  1996. if (len >= QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE) {
  1997. memcpy(&link_type,
  1998. QETH_ULP_ENABLE_RESP_LINK_TYPE(iob->data), 1);
  1999. card->info.link_type = link_type;
  2000. } else
  2001. card->info.link_type = 0;
  2002. QETH_DBF_TEXT_(SETUP, 2, "link%d", card->info.link_type);
  2003. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  2004. return 0;
  2005. }
  2006. static int qeth_ulp_enable(struct qeth_card *card)
  2007. {
  2008. int rc;
  2009. char prot_type;
  2010. struct qeth_cmd_buffer *iob;
  2011. /*FIXME: trace view callbacks*/
  2012. QETH_DBF_TEXT(SETUP, 2, "ulpenabl");
  2013. iob = qeth_wait_for_buffer(&card->write);
  2014. memcpy(iob->data, ULP_ENABLE, ULP_ENABLE_SIZE);
  2015. *(QETH_ULP_ENABLE_LINKNUM(iob->data)) =
  2016. (__u8) card->info.portno;
  2017. if (card->options.layer2)
  2018. if (card->info.type == QETH_CARD_TYPE_OSN)
  2019. prot_type = QETH_PROT_OSN2;
  2020. else
  2021. prot_type = QETH_PROT_LAYER2;
  2022. else
  2023. prot_type = QETH_PROT_TCPIP;
  2024. memcpy(QETH_ULP_ENABLE_PROT_TYPE(iob->data), &prot_type, 1);
  2025. memcpy(QETH_ULP_ENABLE_DEST_ADDR(iob->data),
  2026. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  2027. memcpy(QETH_ULP_ENABLE_FILTER_TOKEN(iob->data),
  2028. &card->token.ulp_filter_w, QETH_MPC_TOKEN_LENGTH);
  2029. memcpy(QETH_ULP_ENABLE_PORTNAME_AND_LL(iob->data),
  2030. card->info.portname, 9);
  2031. rc = qeth_send_control_data(card, ULP_ENABLE_SIZE, iob,
  2032. qeth_ulp_enable_cb, NULL);
  2033. return rc;
  2034. }
  2035. static int qeth_ulp_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  2036. unsigned long data)
  2037. {
  2038. struct qeth_cmd_buffer *iob;
  2039. int rc = 0;
  2040. QETH_DBF_TEXT(SETUP, 2, "ulpstpcb");
  2041. iob = (struct qeth_cmd_buffer *) data;
  2042. memcpy(&card->token.ulp_connection_r,
  2043. QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  2044. QETH_MPC_TOKEN_LENGTH);
  2045. if (!strncmp("00S", QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  2046. 3)) {
  2047. QETH_DBF_TEXT(SETUP, 2, "olmlimit");
  2048. dev_err(&card->gdev->dev, "A connection could not be "
  2049. "established because of an OLM limit\n");
  2050. iob->rc = -EMLINK;
  2051. }
  2052. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  2053. return rc;
  2054. }
  2055. static int qeth_ulp_setup(struct qeth_card *card)
  2056. {
  2057. int rc;
  2058. __u16 temp;
  2059. struct qeth_cmd_buffer *iob;
  2060. struct ccw_dev_id dev_id;
  2061. QETH_DBF_TEXT(SETUP, 2, "ulpsetup");
  2062. iob = qeth_wait_for_buffer(&card->write);
  2063. memcpy(iob->data, ULP_SETUP, ULP_SETUP_SIZE);
  2064. memcpy(QETH_ULP_SETUP_DEST_ADDR(iob->data),
  2065. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  2066. memcpy(QETH_ULP_SETUP_CONNECTION_TOKEN(iob->data),
  2067. &card->token.ulp_connection_w, QETH_MPC_TOKEN_LENGTH);
  2068. memcpy(QETH_ULP_SETUP_FILTER_TOKEN(iob->data),
  2069. &card->token.ulp_filter_r, QETH_MPC_TOKEN_LENGTH);
  2070. ccw_device_get_id(CARD_DDEV(card), &dev_id);
  2071. memcpy(QETH_ULP_SETUP_CUA(iob->data), &dev_id.devno, 2);
  2072. temp = (card->info.cula << 8) + card->info.unit_addr2;
  2073. memcpy(QETH_ULP_SETUP_REAL_DEVADDR(iob->data), &temp, 2);
  2074. rc = qeth_send_control_data(card, ULP_SETUP_SIZE, iob,
  2075. qeth_ulp_setup_cb, NULL);
  2076. return rc;
  2077. }
  2078. static int qeth_init_qdio_out_buf(struct qeth_qdio_out_q *q, int bidx)
  2079. {
  2080. int rc;
  2081. struct qeth_qdio_out_buffer *newbuf;
  2082. rc = 0;
  2083. newbuf = kmem_cache_zalloc(qeth_qdio_outbuf_cache, GFP_ATOMIC);
  2084. if (!newbuf) {
  2085. rc = -ENOMEM;
  2086. goto out;
  2087. }
  2088. newbuf->buffer = &q->qdio_bufs[bidx];
  2089. skb_queue_head_init(&newbuf->skb_list);
  2090. lockdep_set_class(&newbuf->skb_list.lock, &qdio_out_skb_queue_key);
  2091. newbuf->q = q;
  2092. newbuf->aob = NULL;
  2093. newbuf->next_pending = q->bufs[bidx];
  2094. atomic_set(&newbuf->state, QETH_QDIO_BUF_EMPTY);
  2095. q->bufs[bidx] = newbuf;
  2096. if (q->bufstates) {
  2097. q->bufstates[bidx].user = newbuf;
  2098. QETH_CARD_TEXT_(q->card, 2, "nbs%d", bidx);
  2099. QETH_CARD_TEXT_(q->card, 2, "%lx", (long) newbuf);
  2100. QETH_CARD_TEXT_(q->card, 2, "%lx",
  2101. (long) newbuf->next_pending);
  2102. }
  2103. out:
  2104. return rc;
  2105. }
  2106. static int qeth_alloc_qdio_buffers(struct qeth_card *card)
  2107. {
  2108. int i, j;
  2109. QETH_DBF_TEXT(SETUP, 2, "allcqdbf");
  2110. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED,
  2111. QETH_QDIO_ALLOCATED) != QETH_QDIO_UNINITIALIZED)
  2112. return 0;
  2113. card->qdio.in_q = kzalloc(sizeof(struct qeth_qdio_q),
  2114. GFP_KERNEL);
  2115. if (!card->qdio.in_q)
  2116. goto out_nomem;
  2117. QETH_DBF_TEXT(SETUP, 2, "inq");
  2118. QETH_DBF_HEX(SETUP, 2, &card->qdio.in_q, sizeof(void *));
  2119. memset(card->qdio.in_q, 0, sizeof(struct qeth_qdio_q));
  2120. /* give inbound qeth_qdio_buffers their qdio_buffers */
  2121. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i) {
  2122. card->qdio.in_q->bufs[i].buffer =
  2123. &card->qdio.in_q->qdio_bufs[i];
  2124. card->qdio.in_q->bufs[i].rx_skb = NULL;
  2125. }
  2126. /* inbound buffer pool */
  2127. if (qeth_alloc_buffer_pool(card))
  2128. goto out_freeinq;
  2129. /* outbound */
  2130. card->qdio.out_qs =
  2131. kzalloc(card->qdio.no_out_queues *
  2132. sizeof(struct qeth_qdio_out_q *), GFP_KERNEL);
  2133. if (!card->qdio.out_qs)
  2134. goto out_freepool;
  2135. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2136. card->qdio.out_qs[i] = kzalloc(sizeof(struct qeth_qdio_out_q),
  2137. GFP_KERNEL);
  2138. if (!card->qdio.out_qs[i])
  2139. goto out_freeoutq;
  2140. QETH_DBF_TEXT_(SETUP, 2, "outq %i", i);
  2141. QETH_DBF_HEX(SETUP, 2, &card->qdio.out_qs[i], sizeof(void *));
  2142. card->qdio.out_qs[i]->queue_no = i;
  2143. /* give outbound qeth_qdio_buffers their qdio_buffers */
  2144. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2145. BUG_ON(card->qdio.out_qs[i]->bufs[j] != NULL);
  2146. if (qeth_init_qdio_out_buf(card->qdio.out_qs[i], j))
  2147. goto out_freeoutqbufs;
  2148. }
  2149. }
  2150. /* completion */
  2151. if (qeth_alloc_cq(card))
  2152. goto out_freeoutq;
  2153. return 0;
  2154. out_freeoutqbufs:
  2155. while (j > 0) {
  2156. --j;
  2157. kmem_cache_free(qeth_qdio_outbuf_cache,
  2158. card->qdio.out_qs[i]->bufs[j]);
  2159. card->qdio.out_qs[i]->bufs[j] = NULL;
  2160. }
  2161. out_freeoutq:
  2162. while (i > 0) {
  2163. kfree(card->qdio.out_qs[--i]);
  2164. qeth_clear_outq_buffers(card->qdio.out_qs[i], 1);
  2165. }
  2166. kfree(card->qdio.out_qs);
  2167. card->qdio.out_qs = NULL;
  2168. out_freepool:
  2169. qeth_free_buffer_pool(card);
  2170. out_freeinq:
  2171. kfree(card->qdio.in_q);
  2172. card->qdio.in_q = NULL;
  2173. out_nomem:
  2174. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  2175. return -ENOMEM;
  2176. }
  2177. static void qeth_create_qib_param_field(struct qeth_card *card,
  2178. char *param_field)
  2179. {
  2180. param_field[0] = _ascebc['P'];
  2181. param_field[1] = _ascebc['C'];
  2182. param_field[2] = _ascebc['I'];
  2183. param_field[3] = _ascebc['T'];
  2184. *((unsigned int *) (&param_field[4])) = QETH_PCI_THRESHOLD_A(card);
  2185. *((unsigned int *) (&param_field[8])) = QETH_PCI_THRESHOLD_B(card);
  2186. *((unsigned int *) (&param_field[12])) = QETH_PCI_TIMER_VALUE(card);
  2187. }
  2188. static void qeth_create_qib_param_field_blkt(struct qeth_card *card,
  2189. char *param_field)
  2190. {
  2191. param_field[16] = _ascebc['B'];
  2192. param_field[17] = _ascebc['L'];
  2193. param_field[18] = _ascebc['K'];
  2194. param_field[19] = _ascebc['T'];
  2195. *((unsigned int *) (&param_field[20])) = card->info.blkt.time_total;
  2196. *((unsigned int *) (&param_field[24])) = card->info.blkt.inter_packet;
  2197. *((unsigned int *) (&param_field[28])) =
  2198. card->info.blkt.inter_packet_jumbo;
  2199. }
  2200. static int qeth_qdio_activate(struct qeth_card *card)
  2201. {
  2202. QETH_DBF_TEXT(SETUP, 3, "qdioact");
  2203. return qdio_activate(CARD_DDEV(card));
  2204. }
  2205. static int qeth_dm_act(struct qeth_card *card)
  2206. {
  2207. int rc;
  2208. struct qeth_cmd_buffer *iob;
  2209. QETH_DBF_TEXT(SETUP, 2, "dmact");
  2210. iob = qeth_wait_for_buffer(&card->write);
  2211. memcpy(iob->data, DM_ACT, DM_ACT_SIZE);
  2212. memcpy(QETH_DM_ACT_DEST_ADDR(iob->data),
  2213. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  2214. memcpy(QETH_DM_ACT_CONNECTION_TOKEN(iob->data),
  2215. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2216. rc = qeth_send_control_data(card, DM_ACT_SIZE, iob, NULL, NULL);
  2217. return rc;
  2218. }
  2219. static int qeth_mpc_initialize(struct qeth_card *card)
  2220. {
  2221. int rc;
  2222. QETH_DBF_TEXT(SETUP, 2, "mpcinit");
  2223. rc = qeth_issue_next_read(card);
  2224. if (rc) {
  2225. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  2226. return rc;
  2227. }
  2228. rc = qeth_cm_enable(card);
  2229. if (rc) {
  2230. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  2231. goto out_qdio;
  2232. }
  2233. rc = qeth_cm_setup(card);
  2234. if (rc) {
  2235. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  2236. goto out_qdio;
  2237. }
  2238. rc = qeth_ulp_enable(card);
  2239. if (rc) {
  2240. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  2241. goto out_qdio;
  2242. }
  2243. rc = qeth_ulp_setup(card);
  2244. if (rc) {
  2245. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  2246. goto out_qdio;
  2247. }
  2248. rc = qeth_alloc_qdio_buffers(card);
  2249. if (rc) {
  2250. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  2251. goto out_qdio;
  2252. }
  2253. rc = qeth_qdio_establish(card);
  2254. if (rc) {
  2255. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  2256. qeth_free_qdio_buffers(card);
  2257. goto out_qdio;
  2258. }
  2259. rc = qeth_qdio_activate(card);
  2260. if (rc) {
  2261. QETH_DBF_TEXT_(SETUP, 2, "7err%d", rc);
  2262. goto out_qdio;
  2263. }
  2264. rc = qeth_dm_act(card);
  2265. if (rc) {
  2266. QETH_DBF_TEXT_(SETUP, 2, "8err%d", rc);
  2267. goto out_qdio;
  2268. }
  2269. return 0;
  2270. out_qdio:
  2271. qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  2272. return rc;
  2273. }
  2274. static void qeth_print_status_with_portname(struct qeth_card *card)
  2275. {
  2276. char dbf_text[15];
  2277. int i;
  2278. sprintf(dbf_text, "%s", card->info.portname + 1);
  2279. for (i = 0; i < 8; i++)
  2280. dbf_text[i] =
  2281. (char) _ebcasc[(__u8) dbf_text[i]];
  2282. dbf_text[8] = 0;
  2283. dev_info(&card->gdev->dev, "Device is a%s card%s%s%s\n"
  2284. "with link type %s (portname: %s)\n",
  2285. qeth_get_cardname(card),
  2286. (card->info.mcl_level[0]) ? " (level: " : "",
  2287. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2288. (card->info.mcl_level[0]) ? ")" : "",
  2289. qeth_get_cardname_short(card),
  2290. dbf_text);
  2291. }
  2292. static void qeth_print_status_no_portname(struct qeth_card *card)
  2293. {
  2294. if (card->info.portname[0])
  2295. dev_info(&card->gdev->dev, "Device is a%s "
  2296. "card%s%s%s\nwith link type %s "
  2297. "(no portname needed by interface).\n",
  2298. qeth_get_cardname(card),
  2299. (card->info.mcl_level[0]) ? " (level: " : "",
  2300. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2301. (card->info.mcl_level[0]) ? ")" : "",
  2302. qeth_get_cardname_short(card));
  2303. else
  2304. dev_info(&card->gdev->dev, "Device is a%s "
  2305. "card%s%s%s\nwith link type %s.\n",
  2306. qeth_get_cardname(card),
  2307. (card->info.mcl_level[0]) ? " (level: " : "",
  2308. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2309. (card->info.mcl_level[0]) ? ")" : "",
  2310. qeth_get_cardname_short(card));
  2311. }
  2312. void qeth_print_status_message(struct qeth_card *card)
  2313. {
  2314. switch (card->info.type) {
  2315. case QETH_CARD_TYPE_OSD:
  2316. case QETH_CARD_TYPE_OSM:
  2317. case QETH_CARD_TYPE_OSX:
  2318. /* VM will use a non-zero first character
  2319. * to indicate a HiperSockets like reporting
  2320. * of the level OSA sets the first character to zero
  2321. * */
  2322. if (!card->info.mcl_level[0]) {
  2323. sprintf(card->info.mcl_level, "%02x%02x",
  2324. card->info.mcl_level[2],
  2325. card->info.mcl_level[3]);
  2326. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2327. break;
  2328. }
  2329. /* fallthrough */
  2330. case QETH_CARD_TYPE_IQD:
  2331. if ((card->info.guestlan) ||
  2332. (card->info.mcl_level[0] & 0x80)) {
  2333. card->info.mcl_level[0] = (char) _ebcasc[(__u8)
  2334. card->info.mcl_level[0]];
  2335. card->info.mcl_level[1] = (char) _ebcasc[(__u8)
  2336. card->info.mcl_level[1]];
  2337. card->info.mcl_level[2] = (char) _ebcasc[(__u8)
  2338. card->info.mcl_level[2]];
  2339. card->info.mcl_level[3] = (char) _ebcasc[(__u8)
  2340. card->info.mcl_level[3]];
  2341. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2342. }
  2343. break;
  2344. default:
  2345. memset(&card->info.mcl_level[0], 0, QETH_MCL_LENGTH + 1);
  2346. }
  2347. if (card->info.portname_required)
  2348. qeth_print_status_with_portname(card);
  2349. else
  2350. qeth_print_status_no_portname(card);
  2351. }
  2352. EXPORT_SYMBOL_GPL(qeth_print_status_message);
  2353. static void qeth_initialize_working_pool_list(struct qeth_card *card)
  2354. {
  2355. struct qeth_buffer_pool_entry *entry;
  2356. QETH_CARD_TEXT(card, 5, "inwrklst");
  2357. list_for_each_entry(entry,
  2358. &card->qdio.init_pool.entry_list, init_list) {
  2359. qeth_put_buffer_pool_entry(card, entry);
  2360. }
  2361. }
  2362. static inline struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry(
  2363. struct qeth_card *card)
  2364. {
  2365. struct list_head *plh;
  2366. struct qeth_buffer_pool_entry *entry;
  2367. int i, free;
  2368. struct page *page;
  2369. if (list_empty(&card->qdio.in_buf_pool.entry_list))
  2370. return NULL;
  2371. list_for_each(plh, &card->qdio.in_buf_pool.entry_list) {
  2372. entry = list_entry(plh, struct qeth_buffer_pool_entry, list);
  2373. free = 1;
  2374. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2375. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2376. free = 0;
  2377. break;
  2378. }
  2379. }
  2380. if (free) {
  2381. list_del_init(&entry->list);
  2382. return entry;
  2383. }
  2384. }
  2385. /* no free buffer in pool so take first one and swap pages */
  2386. entry = list_entry(card->qdio.in_buf_pool.entry_list.next,
  2387. struct qeth_buffer_pool_entry, list);
  2388. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2389. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2390. page = alloc_page(GFP_ATOMIC);
  2391. if (!page) {
  2392. return NULL;
  2393. } else {
  2394. free_page((unsigned long)entry->elements[i]);
  2395. entry->elements[i] = page_address(page);
  2396. if (card->options.performance_stats)
  2397. card->perf_stats.sg_alloc_page_rx++;
  2398. }
  2399. }
  2400. }
  2401. list_del_init(&entry->list);
  2402. return entry;
  2403. }
  2404. static int qeth_init_input_buffer(struct qeth_card *card,
  2405. struct qeth_qdio_buffer *buf)
  2406. {
  2407. struct qeth_buffer_pool_entry *pool_entry;
  2408. int i;
  2409. if ((card->options.cq == QETH_CQ_ENABLED) && (!buf->rx_skb)) {
  2410. buf->rx_skb = dev_alloc_skb(QETH_RX_PULL_LEN + ETH_HLEN);
  2411. if (!buf->rx_skb)
  2412. return 1;
  2413. }
  2414. pool_entry = qeth_find_free_buffer_pool_entry(card);
  2415. if (!pool_entry)
  2416. return 1;
  2417. /*
  2418. * since the buffer is accessed only from the input_tasklet
  2419. * there shouldn't be a need to synchronize; also, since we use
  2420. * the QETH_IN_BUF_REQUEUE_THRESHOLD we should never run out off
  2421. * buffers
  2422. */
  2423. buf->pool_entry = pool_entry;
  2424. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2425. buf->buffer->element[i].length = PAGE_SIZE;
  2426. buf->buffer->element[i].addr = pool_entry->elements[i];
  2427. if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1)
  2428. buf->buffer->element[i].eflags = SBAL_EFLAGS_LAST_ENTRY;
  2429. else
  2430. buf->buffer->element[i].eflags = 0;
  2431. buf->buffer->element[i].sflags = 0;
  2432. }
  2433. return 0;
  2434. }
  2435. int qeth_init_qdio_queues(struct qeth_card *card)
  2436. {
  2437. int i, j;
  2438. int rc;
  2439. QETH_DBF_TEXT(SETUP, 2, "initqdqs");
  2440. /* inbound queue */
  2441. memset(card->qdio.in_q->qdio_bufs, 0,
  2442. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2443. qeth_initialize_working_pool_list(card);
  2444. /*give only as many buffers to hardware as we have buffer pool entries*/
  2445. for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; ++i)
  2446. qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]);
  2447. card->qdio.in_q->next_buf_to_init =
  2448. card->qdio.in_buf_pool.buf_count - 1;
  2449. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0,
  2450. card->qdio.in_buf_pool.buf_count - 1);
  2451. if (rc) {
  2452. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  2453. return rc;
  2454. }
  2455. /* completion */
  2456. rc = qeth_cq_init(card);
  2457. if (rc) {
  2458. return rc;
  2459. }
  2460. /* outbound queue */
  2461. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2462. memset(card->qdio.out_qs[i]->qdio_bufs, 0,
  2463. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2464. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2465. qeth_clear_output_buffer(card->qdio.out_qs[i],
  2466. card->qdio.out_qs[i]->bufs[j],
  2467. QETH_QDIO_BUF_EMPTY);
  2468. }
  2469. card->qdio.out_qs[i]->card = card;
  2470. card->qdio.out_qs[i]->next_buf_to_fill = 0;
  2471. card->qdio.out_qs[i]->do_pack = 0;
  2472. atomic_set(&card->qdio.out_qs[i]->used_buffers, 0);
  2473. atomic_set(&card->qdio.out_qs[i]->set_pci_flags_count, 0);
  2474. atomic_set(&card->qdio.out_qs[i]->state,
  2475. QETH_OUT_Q_UNLOCKED);
  2476. }
  2477. return 0;
  2478. }
  2479. EXPORT_SYMBOL_GPL(qeth_init_qdio_queues);
  2480. static inline __u8 qeth_get_ipa_adp_type(enum qeth_link_types link_type)
  2481. {
  2482. switch (link_type) {
  2483. case QETH_LINK_TYPE_HSTR:
  2484. return 2;
  2485. default:
  2486. return 1;
  2487. }
  2488. }
  2489. static void qeth_fill_ipacmd_header(struct qeth_card *card,
  2490. struct qeth_ipa_cmd *cmd, __u8 command,
  2491. enum qeth_prot_versions prot)
  2492. {
  2493. memset(cmd, 0, sizeof(struct qeth_ipa_cmd));
  2494. cmd->hdr.command = command;
  2495. cmd->hdr.initiator = IPA_CMD_INITIATOR_HOST;
  2496. cmd->hdr.seqno = card->seqno.ipa;
  2497. cmd->hdr.adapter_type = qeth_get_ipa_adp_type(card->info.link_type);
  2498. cmd->hdr.rel_adapter_no = (__u8) card->info.portno;
  2499. if (card->options.layer2)
  2500. cmd->hdr.prim_version_no = 2;
  2501. else
  2502. cmd->hdr.prim_version_no = 1;
  2503. cmd->hdr.param_count = 1;
  2504. cmd->hdr.prot_version = prot;
  2505. cmd->hdr.ipa_supported = 0;
  2506. cmd->hdr.ipa_enabled = 0;
  2507. }
  2508. struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *card,
  2509. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2510. {
  2511. struct qeth_cmd_buffer *iob;
  2512. struct qeth_ipa_cmd *cmd;
  2513. iob = qeth_wait_for_buffer(&card->write);
  2514. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2515. qeth_fill_ipacmd_header(card, cmd, ipacmd, prot);
  2516. return iob;
  2517. }
  2518. EXPORT_SYMBOL_GPL(qeth_get_ipacmd_buffer);
  2519. void qeth_prepare_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2520. char prot_type)
  2521. {
  2522. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  2523. memcpy(QETH_IPA_CMD_PROT_TYPE(iob->data), &prot_type, 1);
  2524. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  2525. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2526. }
  2527. EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd);
  2528. int qeth_send_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2529. int (*reply_cb)(struct qeth_card *, struct qeth_reply*,
  2530. unsigned long),
  2531. void *reply_param)
  2532. {
  2533. int rc;
  2534. char prot_type;
  2535. QETH_CARD_TEXT(card, 4, "sendipa");
  2536. if (card->options.layer2)
  2537. if (card->info.type == QETH_CARD_TYPE_OSN)
  2538. prot_type = QETH_PROT_OSN2;
  2539. else
  2540. prot_type = QETH_PROT_LAYER2;
  2541. else
  2542. prot_type = QETH_PROT_TCPIP;
  2543. qeth_prepare_ipa_cmd(card, iob, prot_type);
  2544. rc = qeth_send_control_data(card, IPA_CMD_LENGTH,
  2545. iob, reply_cb, reply_param);
  2546. if (rc == -ETIME) {
  2547. qeth_clear_ipacmd_list(card);
  2548. qeth_schedule_recovery(card);
  2549. }
  2550. return rc;
  2551. }
  2552. EXPORT_SYMBOL_GPL(qeth_send_ipa_cmd);
  2553. int qeth_send_startlan(struct qeth_card *card)
  2554. {
  2555. int rc;
  2556. struct qeth_cmd_buffer *iob;
  2557. QETH_DBF_TEXT(SETUP, 2, "strtlan");
  2558. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_STARTLAN, 0);
  2559. rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);
  2560. return rc;
  2561. }
  2562. EXPORT_SYMBOL_GPL(qeth_send_startlan);
  2563. int qeth_default_setadapterparms_cb(struct qeth_card *card,
  2564. struct qeth_reply *reply, unsigned long data)
  2565. {
  2566. struct qeth_ipa_cmd *cmd;
  2567. QETH_CARD_TEXT(card, 4, "defadpcb");
  2568. cmd = (struct qeth_ipa_cmd *) data;
  2569. if (cmd->hdr.return_code == 0)
  2570. cmd->hdr.return_code =
  2571. cmd->data.setadapterparms.hdr.return_code;
  2572. return 0;
  2573. }
  2574. EXPORT_SYMBOL_GPL(qeth_default_setadapterparms_cb);
  2575. static int qeth_query_setadapterparms_cb(struct qeth_card *card,
  2576. struct qeth_reply *reply, unsigned long data)
  2577. {
  2578. struct qeth_ipa_cmd *cmd;
  2579. QETH_CARD_TEXT(card, 3, "quyadpcb");
  2580. cmd = (struct qeth_ipa_cmd *) data;
  2581. if (cmd->data.setadapterparms.data.query_cmds_supp.lan_type & 0x7f) {
  2582. card->info.link_type =
  2583. cmd->data.setadapterparms.data.query_cmds_supp.lan_type;
  2584. QETH_DBF_TEXT_(SETUP, 2, "lnk %d", card->info.link_type);
  2585. }
  2586. card->options.adp.supported_funcs =
  2587. cmd->data.setadapterparms.data.query_cmds_supp.supported_cmds;
  2588. return qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2589. }
  2590. struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *card,
  2591. __u32 command, __u32 cmdlen)
  2592. {
  2593. struct qeth_cmd_buffer *iob;
  2594. struct qeth_ipa_cmd *cmd;
  2595. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS,
  2596. QETH_PROT_IPV4);
  2597. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2598. cmd->data.setadapterparms.hdr.cmdlength = cmdlen;
  2599. cmd->data.setadapterparms.hdr.command_code = command;
  2600. cmd->data.setadapterparms.hdr.used_total = 1;
  2601. cmd->data.setadapterparms.hdr.seq_no = 1;
  2602. return iob;
  2603. }
  2604. EXPORT_SYMBOL_GPL(qeth_get_adapter_cmd);
  2605. int qeth_query_setadapterparms(struct qeth_card *card)
  2606. {
  2607. int rc;
  2608. struct qeth_cmd_buffer *iob;
  2609. QETH_CARD_TEXT(card, 3, "queryadp");
  2610. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED,
  2611. sizeof(struct qeth_ipacmd_setadpparms));
  2612. rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL);
  2613. return rc;
  2614. }
  2615. EXPORT_SYMBOL_GPL(qeth_query_setadapterparms);
  2616. static int qeth_query_ipassists_cb(struct qeth_card *card,
  2617. struct qeth_reply *reply, unsigned long data)
  2618. {
  2619. struct qeth_ipa_cmd *cmd;
  2620. QETH_DBF_TEXT(SETUP, 2, "qipasscb");
  2621. cmd = (struct qeth_ipa_cmd *) data;
  2622. if (cmd->hdr.prot_version == QETH_PROT_IPV4) {
  2623. card->options.ipa4.supported_funcs = cmd->hdr.ipa_supported;
  2624. card->options.ipa4.enabled_funcs = cmd->hdr.ipa_enabled;
  2625. } else {
  2626. card->options.ipa6.supported_funcs = cmd->hdr.ipa_supported;
  2627. card->options.ipa6.enabled_funcs = cmd->hdr.ipa_enabled;
  2628. }
  2629. QETH_DBF_TEXT(SETUP, 2, "suppenbl");
  2630. QETH_DBF_TEXT_(SETUP, 2, "%x", cmd->hdr.ipa_supported);
  2631. QETH_DBF_TEXT_(SETUP, 2, "%x", cmd->hdr.ipa_enabled);
  2632. return 0;
  2633. }
  2634. int qeth_query_ipassists(struct qeth_card *card, enum qeth_prot_versions prot)
  2635. {
  2636. int rc;
  2637. struct qeth_cmd_buffer *iob;
  2638. QETH_DBF_TEXT_(SETUP, 2, "qipassi%i", prot);
  2639. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_QIPASSIST, prot);
  2640. rc = qeth_send_ipa_cmd(card, iob, qeth_query_ipassists_cb, NULL);
  2641. return rc;
  2642. }
  2643. EXPORT_SYMBOL_GPL(qeth_query_ipassists);
  2644. static int qeth_query_setdiagass_cb(struct qeth_card *card,
  2645. struct qeth_reply *reply, unsigned long data)
  2646. {
  2647. struct qeth_ipa_cmd *cmd;
  2648. __u16 rc;
  2649. cmd = (struct qeth_ipa_cmd *)data;
  2650. rc = cmd->hdr.return_code;
  2651. if (rc)
  2652. QETH_CARD_TEXT_(card, 2, "diagq:%x", rc);
  2653. else
  2654. card->info.diagass_support = cmd->data.diagass.ext;
  2655. return 0;
  2656. }
  2657. static int qeth_query_setdiagass(struct qeth_card *card)
  2658. {
  2659. struct qeth_cmd_buffer *iob;
  2660. struct qeth_ipa_cmd *cmd;
  2661. QETH_DBF_TEXT(SETUP, 2, "qdiagass");
  2662. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SET_DIAG_ASS, 0);
  2663. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2664. cmd->data.diagass.subcmd_len = 16;
  2665. cmd->data.diagass.subcmd = QETH_DIAGS_CMD_QUERY;
  2666. return qeth_send_ipa_cmd(card, iob, qeth_query_setdiagass_cb, NULL);
  2667. }
  2668. static void qeth_get_trap_id(struct qeth_card *card, struct qeth_trap_id *tid)
  2669. {
  2670. unsigned long info = get_zeroed_page(GFP_KERNEL);
  2671. struct sysinfo_2_2_2 *info222 = (struct sysinfo_2_2_2 *)info;
  2672. struct sysinfo_3_2_2 *info322 = (struct sysinfo_3_2_2 *)info;
  2673. struct ccw_dev_id ccwid;
  2674. int level, rc;
  2675. tid->chpid = card->info.chpid;
  2676. ccw_device_get_id(CARD_RDEV(card), &ccwid);
  2677. tid->ssid = ccwid.ssid;
  2678. tid->devno = ccwid.devno;
  2679. if (!info)
  2680. return;
  2681. rc = stsi(NULL, 0, 0, 0);
  2682. if (rc == -ENOSYS)
  2683. level = rc;
  2684. else
  2685. level = (((unsigned int) rc) >> 28);
  2686. if ((level >= 2) && (stsi(info222, 2, 2, 2) != -ENOSYS))
  2687. tid->lparnr = info222->lpar_number;
  2688. if ((level >= 3) && (stsi(info322, 3, 2, 2) != -ENOSYS)) {
  2689. EBCASC(info322->vm[0].name, sizeof(info322->vm[0].name));
  2690. memcpy(tid->vmname, info322->vm[0].name, sizeof(tid->vmname));
  2691. }
  2692. free_page(info);
  2693. return;
  2694. }
  2695. static int qeth_hw_trap_cb(struct qeth_card *card,
  2696. struct qeth_reply *reply, unsigned long data)
  2697. {
  2698. struct qeth_ipa_cmd *cmd;
  2699. __u16 rc;
  2700. cmd = (struct qeth_ipa_cmd *)data;
  2701. rc = cmd->hdr.return_code;
  2702. if (rc)
  2703. QETH_CARD_TEXT_(card, 2, "trapc:%x", rc);
  2704. return 0;
  2705. }
  2706. int qeth_hw_trap(struct qeth_card *card, enum qeth_diags_trap_action action)
  2707. {
  2708. struct qeth_cmd_buffer *iob;
  2709. struct qeth_ipa_cmd *cmd;
  2710. QETH_DBF_TEXT(SETUP, 2, "diagtrap");
  2711. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SET_DIAG_ASS, 0);
  2712. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2713. cmd->data.diagass.subcmd_len = 80;
  2714. cmd->data.diagass.subcmd = QETH_DIAGS_CMD_TRAP;
  2715. cmd->data.diagass.type = 1;
  2716. cmd->data.diagass.action = action;
  2717. switch (action) {
  2718. case QETH_DIAGS_TRAP_ARM:
  2719. cmd->data.diagass.options = 0x0003;
  2720. cmd->data.diagass.ext = 0x00010000 +
  2721. sizeof(struct qeth_trap_id);
  2722. qeth_get_trap_id(card,
  2723. (struct qeth_trap_id *)cmd->data.diagass.cdata);
  2724. break;
  2725. case QETH_DIAGS_TRAP_DISARM:
  2726. cmd->data.diagass.options = 0x0001;
  2727. break;
  2728. case QETH_DIAGS_TRAP_CAPTURE:
  2729. break;
  2730. }
  2731. return qeth_send_ipa_cmd(card, iob, qeth_hw_trap_cb, NULL);
  2732. }
  2733. EXPORT_SYMBOL_GPL(qeth_hw_trap);
  2734. int qeth_check_qdio_errors(struct qeth_card *card, struct qdio_buffer *buf,
  2735. unsigned int qdio_error, const char *dbftext)
  2736. {
  2737. if (qdio_error) {
  2738. QETH_CARD_TEXT(card, 2, dbftext);
  2739. QETH_CARD_TEXT_(card, 2, " F15=%02X",
  2740. buf->element[15].sflags);
  2741. QETH_CARD_TEXT_(card, 2, " F14=%02X",
  2742. buf->element[14].sflags);
  2743. QETH_CARD_TEXT_(card, 2, " qerr=%X", qdio_error);
  2744. if ((buf->element[15].sflags) == 0x12) {
  2745. card->stats.rx_dropped++;
  2746. return 0;
  2747. } else
  2748. return 1;
  2749. }
  2750. return 0;
  2751. }
  2752. EXPORT_SYMBOL_GPL(qeth_check_qdio_errors);
  2753. void qeth_buffer_reclaim_work(struct work_struct *work)
  2754. {
  2755. struct qeth_card *card = container_of(work, struct qeth_card,
  2756. buffer_reclaim_work.work);
  2757. QETH_CARD_TEXT_(card, 2, "brw:%x", card->reclaim_index);
  2758. qeth_queue_input_buffer(card, card->reclaim_index);
  2759. }
  2760. void qeth_queue_input_buffer(struct qeth_card *card, int index)
  2761. {
  2762. struct qeth_qdio_q *queue = card->qdio.in_q;
  2763. struct list_head *lh;
  2764. int count;
  2765. int i;
  2766. int rc;
  2767. int newcount = 0;
  2768. count = (index < queue->next_buf_to_init)?
  2769. card->qdio.in_buf_pool.buf_count -
  2770. (queue->next_buf_to_init - index) :
  2771. card->qdio.in_buf_pool.buf_count -
  2772. (queue->next_buf_to_init + QDIO_MAX_BUFFERS_PER_Q - index);
  2773. /* only requeue at a certain threshold to avoid SIGAs */
  2774. if (count >= QETH_IN_BUF_REQUEUE_THRESHOLD(card)) {
  2775. for (i = queue->next_buf_to_init;
  2776. i < queue->next_buf_to_init + count; ++i) {
  2777. if (qeth_init_input_buffer(card,
  2778. &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q])) {
  2779. break;
  2780. } else {
  2781. newcount++;
  2782. }
  2783. }
  2784. if (newcount < count) {
  2785. /* we are in memory shortage so we switch back to
  2786. traditional skb allocation and drop packages */
  2787. atomic_set(&card->force_alloc_skb, 3);
  2788. count = newcount;
  2789. } else {
  2790. atomic_add_unless(&card->force_alloc_skb, -1, 0);
  2791. }
  2792. if (!count) {
  2793. i = 0;
  2794. list_for_each(lh, &card->qdio.in_buf_pool.entry_list)
  2795. i++;
  2796. if (i == card->qdio.in_buf_pool.buf_count) {
  2797. QETH_CARD_TEXT(card, 2, "qsarbw");
  2798. card->reclaim_index = index;
  2799. schedule_delayed_work(
  2800. &card->buffer_reclaim_work,
  2801. QETH_RECLAIM_WORK_TIME);
  2802. }
  2803. return;
  2804. }
  2805. /*
  2806. * according to old code it should be avoided to requeue all
  2807. * 128 buffers in order to benefit from PCI avoidance.
  2808. * this function keeps at least one buffer (the buffer at
  2809. * 'index') un-requeued -> this buffer is the first buffer that
  2810. * will be requeued the next time
  2811. */
  2812. if (card->options.performance_stats) {
  2813. card->perf_stats.inbound_do_qdio_cnt++;
  2814. card->perf_stats.inbound_do_qdio_start_time =
  2815. qeth_get_micros();
  2816. }
  2817. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0,
  2818. queue->next_buf_to_init, count);
  2819. if (card->options.performance_stats)
  2820. card->perf_stats.inbound_do_qdio_time +=
  2821. qeth_get_micros() -
  2822. card->perf_stats.inbound_do_qdio_start_time;
  2823. if (rc) {
  2824. QETH_CARD_TEXT(card, 2, "qinberr");
  2825. }
  2826. queue->next_buf_to_init = (queue->next_buf_to_init + count) %
  2827. QDIO_MAX_BUFFERS_PER_Q;
  2828. }
  2829. }
  2830. EXPORT_SYMBOL_GPL(qeth_queue_input_buffer);
  2831. static int qeth_handle_send_error(struct qeth_card *card,
  2832. struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err)
  2833. {
  2834. int sbalf15 = buffer->buffer->element[15].sflags;
  2835. QETH_CARD_TEXT(card, 6, "hdsnderr");
  2836. if (card->info.type == QETH_CARD_TYPE_IQD) {
  2837. if (sbalf15 == 0) {
  2838. qdio_err = 0;
  2839. } else {
  2840. qdio_err = 1;
  2841. }
  2842. }
  2843. qeth_check_qdio_errors(card, buffer->buffer, qdio_err, "qouterr");
  2844. if (!qdio_err)
  2845. return QETH_SEND_ERROR_NONE;
  2846. if ((sbalf15 >= 15) && (sbalf15 <= 31))
  2847. return QETH_SEND_ERROR_RETRY;
  2848. QETH_CARD_TEXT(card, 1, "lnkfail");
  2849. QETH_CARD_TEXT_(card, 1, "%04x %02x",
  2850. (u16)qdio_err, (u8)sbalf15);
  2851. return QETH_SEND_ERROR_LINK_FAILURE;
  2852. }
  2853. /*
  2854. * Switched to packing state if the number of used buffers on a queue
  2855. * reaches a certain limit.
  2856. */
  2857. static void qeth_switch_to_packing_if_needed(struct qeth_qdio_out_q *queue)
  2858. {
  2859. if (!queue->do_pack) {
  2860. if (atomic_read(&queue->used_buffers)
  2861. >= QETH_HIGH_WATERMARK_PACK){
  2862. /* switch non-PACKING -> PACKING */
  2863. QETH_CARD_TEXT(queue->card, 6, "np->pack");
  2864. if (queue->card->options.performance_stats)
  2865. queue->card->perf_stats.sc_dp_p++;
  2866. queue->do_pack = 1;
  2867. }
  2868. }
  2869. }
  2870. /*
  2871. * Switches from packing to non-packing mode. If there is a packing
  2872. * buffer on the queue this buffer will be prepared to be flushed.
  2873. * In that case 1 is returned to inform the caller. If no buffer
  2874. * has to be flushed, zero is returned.
  2875. */
  2876. static int qeth_switch_to_nonpacking_if_needed(struct qeth_qdio_out_q *queue)
  2877. {
  2878. struct qeth_qdio_out_buffer *buffer;
  2879. int flush_count = 0;
  2880. if (queue->do_pack) {
  2881. if (atomic_read(&queue->used_buffers)
  2882. <= QETH_LOW_WATERMARK_PACK) {
  2883. /* switch PACKING -> non-PACKING */
  2884. QETH_CARD_TEXT(queue->card, 6, "pack->np");
  2885. if (queue->card->options.performance_stats)
  2886. queue->card->perf_stats.sc_p_dp++;
  2887. queue->do_pack = 0;
  2888. /* flush packing buffers */
  2889. buffer = queue->bufs[queue->next_buf_to_fill];
  2890. if ((atomic_read(&buffer->state) ==
  2891. QETH_QDIO_BUF_EMPTY) &&
  2892. (buffer->next_element_to_fill > 0)) {
  2893. atomic_set(&buffer->state,
  2894. QETH_QDIO_BUF_PRIMED);
  2895. flush_count++;
  2896. queue->next_buf_to_fill =
  2897. (queue->next_buf_to_fill + 1) %
  2898. QDIO_MAX_BUFFERS_PER_Q;
  2899. }
  2900. }
  2901. }
  2902. return flush_count;
  2903. }
  2904. /*
  2905. * Called to flush a packing buffer if no more pci flags are on the queue.
  2906. * Checks if there is a packing buffer and prepares it to be flushed.
  2907. * In that case returns 1, otherwise zero.
  2908. */
  2909. static int qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q *queue)
  2910. {
  2911. struct qeth_qdio_out_buffer *buffer;
  2912. buffer = queue->bufs[queue->next_buf_to_fill];
  2913. if ((atomic_read(&buffer->state) == QETH_QDIO_BUF_EMPTY) &&
  2914. (buffer->next_element_to_fill > 0)) {
  2915. /* it's a packing buffer */
  2916. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2917. queue->next_buf_to_fill =
  2918. (queue->next_buf_to_fill + 1) % QDIO_MAX_BUFFERS_PER_Q;
  2919. return 1;
  2920. }
  2921. return 0;
  2922. }
  2923. static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int index,
  2924. int count)
  2925. {
  2926. struct qeth_qdio_out_buffer *buf;
  2927. int rc;
  2928. int i;
  2929. unsigned int qdio_flags;
  2930. for (i = index; i < index + count; ++i) {
  2931. int bidx = i % QDIO_MAX_BUFFERS_PER_Q;
  2932. buf = queue->bufs[bidx];
  2933. buf->buffer->element[buf->next_element_to_fill - 1].eflags |=
  2934. SBAL_EFLAGS_LAST_ENTRY;
  2935. if (queue->bufstates)
  2936. queue->bufstates[bidx].user = buf;
  2937. if (queue->card->info.type == QETH_CARD_TYPE_IQD)
  2938. continue;
  2939. if (!queue->do_pack) {
  2940. if ((atomic_read(&queue->used_buffers) >=
  2941. (QETH_HIGH_WATERMARK_PACK -
  2942. QETH_WATERMARK_PACK_FUZZ)) &&
  2943. !atomic_read(&queue->set_pci_flags_count)) {
  2944. /* it's likely that we'll go to packing
  2945. * mode soon */
  2946. atomic_inc(&queue->set_pci_flags_count);
  2947. buf->buffer->element[0].sflags |= SBAL_SFLAGS0_PCI_REQ;
  2948. }
  2949. } else {
  2950. if (!atomic_read(&queue->set_pci_flags_count)) {
  2951. /*
  2952. * there's no outstanding PCI any more, so we
  2953. * have to request a PCI to be sure the the PCI
  2954. * will wake at some time in the future then we
  2955. * can flush packed buffers that might still be
  2956. * hanging around, which can happen if no
  2957. * further send was requested by the stack
  2958. */
  2959. atomic_inc(&queue->set_pci_flags_count);
  2960. buf->buffer->element[0].sflags |= SBAL_SFLAGS0_PCI_REQ;
  2961. }
  2962. }
  2963. }
  2964. queue->card->dev->trans_start = jiffies;
  2965. if (queue->card->options.performance_stats) {
  2966. queue->card->perf_stats.outbound_do_qdio_cnt++;
  2967. queue->card->perf_stats.outbound_do_qdio_start_time =
  2968. qeth_get_micros();
  2969. }
  2970. qdio_flags = QDIO_FLAG_SYNC_OUTPUT;
  2971. if (atomic_read(&queue->set_pci_flags_count))
  2972. qdio_flags |= QDIO_FLAG_PCI_OUT;
  2973. rc = do_QDIO(CARD_DDEV(queue->card), qdio_flags,
  2974. queue->queue_no, index, count);
  2975. if (queue->card->options.performance_stats)
  2976. queue->card->perf_stats.outbound_do_qdio_time +=
  2977. qeth_get_micros() -
  2978. queue->card->perf_stats.outbound_do_qdio_start_time;
  2979. atomic_add(count, &queue->used_buffers);
  2980. if (rc) {
  2981. queue->card->stats.tx_errors += count;
  2982. /* ignore temporary SIGA errors without busy condition */
  2983. if (rc == QDIO_ERROR_SIGA_TARGET)
  2984. return;
  2985. QETH_CARD_TEXT(queue->card, 2, "flushbuf");
  2986. QETH_CARD_TEXT_(queue->card, 2, " q%d", queue->queue_no);
  2987. QETH_CARD_TEXT_(queue->card, 2, " idx%d", index);
  2988. QETH_CARD_TEXT_(queue->card, 2, " c%d", count);
  2989. QETH_CARD_TEXT_(queue->card, 2, " err%d", rc);
  2990. /* this must not happen under normal circumstances. if it
  2991. * happens something is really wrong -> recover */
  2992. qeth_schedule_recovery(queue->card);
  2993. return;
  2994. }
  2995. if (queue->card->options.performance_stats)
  2996. queue->card->perf_stats.bufs_sent += count;
  2997. }
  2998. static void qeth_check_outbound_queue(struct qeth_qdio_out_q *queue)
  2999. {
  3000. int index;
  3001. int flush_cnt = 0;
  3002. int q_was_packing = 0;
  3003. /*
  3004. * check if weed have to switch to non-packing mode or if
  3005. * we have to get a pci flag out on the queue
  3006. */
  3007. if ((atomic_read(&queue->used_buffers) <= QETH_LOW_WATERMARK_PACK) ||
  3008. !atomic_read(&queue->set_pci_flags_count)) {
  3009. if (atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH) ==
  3010. QETH_OUT_Q_UNLOCKED) {
  3011. /*
  3012. * If we get in here, there was no action in
  3013. * do_send_packet. So, we check if there is a
  3014. * packing buffer to be flushed here.
  3015. */
  3016. netif_stop_queue(queue->card->dev);
  3017. index = queue->next_buf_to_fill;
  3018. q_was_packing = queue->do_pack;
  3019. /* queue->do_pack may change */
  3020. barrier();
  3021. flush_cnt += qeth_switch_to_nonpacking_if_needed(queue);
  3022. if (!flush_cnt &&
  3023. !atomic_read(&queue->set_pci_flags_count))
  3024. flush_cnt +=
  3025. qeth_flush_buffers_on_no_pci(queue);
  3026. if (queue->card->options.performance_stats &&
  3027. q_was_packing)
  3028. queue->card->perf_stats.bufs_sent_pack +=
  3029. flush_cnt;
  3030. if (flush_cnt)
  3031. qeth_flush_buffers(queue, index, flush_cnt);
  3032. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  3033. }
  3034. }
  3035. }
  3036. void qeth_qdio_start_poll(struct ccw_device *ccwdev, int queue,
  3037. unsigned long card_ptr)
  3038. {
  3039. struct qeth_card *card = (struct qeth_card *)card_ptr;
  3040. if (card->dev && (card->dev->flags & IFF_UP))
  3041. napi_schedule(&card->napi);
  3042. }
  3043. EXPORT_SYMBOL_GPL(qeth_qdio_start_poll);
  3044. int qeth_configure_cq(struct qeth_card *card, enum qeth_cq cq)
  3045. {
  3046. int rc;
  3047. if (card->options.cq == QETH_CQ_NOTAVAILABLE) {
  3048. rc = -1;
  3049. goto out;
  3050. } else {
  3051. if (card->options.cq == cq) {
  3052. rc = 0;
  3053. goto out;
  3054. }
  3055. if (card->state != CARD_STATE_DOWN &&
  3056. card->state != CARD_STATE_RECOVER) {
  3057. rc = -1;
  3058. goto out;
  3059. }
  3060. qeth_free_qdio_buffers(card);
  3061. card->options.cq = cq;
  3062. rc = 0;
  3063. }
  3064. out:
  3065. return rc;
  3066. }
  3067. EXPORT_SYMBOL_GPL(qeth_configure_cq);
  3068. static void qeth_qdio_cq_handler(struct qeth_card *card,
  3069. unsigned int qdio_err,
  3070. unsigned int queue, int first_element, int count) {
  3071. struct qeth_qdio_q *cq = card->qdio.c_q;
  3072. int i;
  3073. int rc;
  3074. if (!qeth_is_cq(card, queue))
  3075. goto out;
  3076. QETH_CARD_TEXT_(card, 5, "qcqhe%d", first_element);
  3077. QETH_CARD_TEXT_(card, 5, "qcqhc%d", count);
  3078. QETH_CARD_TEXT_(card, 5, "qcqherr%d", qdio_err);
  3079. if (qdio_err) {
  3080. netif_stop_queue(card->dev);
  3081. qeth_schedule_recovery(card);
  3082. goto out;
  3083. }
  3084. if (card->options.performance_stats) {
  3085. card->perf_stats.cq_cnt++;
  3086. card->perf_stats.cq_start_time = qeth_get_micros();
  3087. }
  3088. for (i = first_element; i < first_element + count; ++i) {
  3089. int bidx = i % QDIO_MAX_BUFFERS_PER_Q;
  3090. struct qdio_buffer *buffer = &cq->qdio_bufs[bidx];
  3091. int e;
  3092. e = 0;
  3093. while (buffer->element[e].addr) {
  3094. unsigned long phys_aob_addr;
  3095. phys_aob_addr = (unsigned long) buffer->element[e].addr;
  3096. qeth_qdio_handle_aob(card, phys_aob_addr);
  3097. buffer->element[e].addr = NULL;
  3098. buffer->element[e].eflags = 0;
  3099. buffer->element[e].sflags = 0;
  3100. buffer->element[e].length = 0;
  3101. ++e;
  3102. }
  3103. buffer->element[15].eflags = 0;
  3104. buffer->element[15].sflags = 0;
  3105. }
  3106. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, queue,
  3107. card->qdio.c_q->next_buf_to_init,
  3108. count);
  3109. if (rc) {
  3110. dev_warn(&card->gdev->dev,
  3111. "QDIO reported an error, rc=%i\n", rc);
  3112. QETH_CARD_TEXT(card, 2, "qcqherr");
  3113. }
  3114. card->qdio.c_q->next_buf_to_init = (card->qdio.c_q->next_buf_to_init
  3115. + count) % QDIO_MAX_BUFFERS_PER_Q;
  3116. netif_wake_queue(card->dev);
  3117. if (card->options.performance_stats) {
  3118. int delta_t = qeth_get_micros();
  3119. delta_t -= card->perf_stats.cq_start_time;
  3120. card->perf_stats.cq_time += delta_t;
  3121. }
  3122. out:
  3123. return;
  3124. }
  3125. void qeth_qdio_input_handler(struct ccw_device *ccwdev, unsigned int qdio_err,
  3126. unsigned int queue, int first_elem, int count,
  3127. unsigned long card_ptr)
  3128. {
  3129. struct qeth_card *card = (struct qeth_card *)card_ptr;
  3130. QETH_CARD_TEXT_(card, 2, "qihq%d", queue);
  3131. QETH_CARD_TEXT_(card, 2, "qiec%d", qdio_err);
  3132. if (qeth_is_cq(card, queue))
  3133. qeth_qdio_cq_handler(card, qdio_err, queue, first_elem, count);
  3134. else if (qdio_err)
  3135. qeth_schedule_recovery(card);
  3136. }
  3137. EXPORT_SYMBOL_GPL(qeth_qdio_input_handler);
  3138. void qeth_qdio_output_handler(struct ccw_device *ccwdev,
  3139. unsigned int qdio_error, int __queue, int first_element,
  3140. int count, unsigned long card_ptr)
  3141. {
  3142. struct qeth_card *card = (struct qeth_card *) card_ptr;
  3143. struct qeth_qdio_out_q *queue = card->qdio.out_qs[__queue];
  3144. struct qeth_qdio_out_buffer *buffer;
  3145. int i;
  3146. QETH_CARD_TEXT(card, 6, "qdouhdl");
  3147. if (qdio_error & QDIO_ERROR_ACTIVATE_CHECK_CONDITION) {
  3148. QETH_CARD_TEXT(card, 2, "achkcond");
  3149. netif_stop_queue(card->dev);
  3150. qeth_schedule_recovery(card);
  3151. return;
  3152. }
  3153. if (card->options.performance_stats) {
  3154. card->perf_stats.outbound_handler_cnt++;
  3155. card->perf_stats.outbound_handler_start_time =
  3156. qeth_get_micros();
  3157. }
  3158. for (i = first_element; i < (first_element + count); ++i) {
  3159. int bidx = i % QDIO_MAX_BUFFERS_PER_Q;
  3160. buffer = queue->bufs[bidx];
  3161. qeth_handle_send_error(card, buffer, qdio_error);
  3162. if (queue->bufstates &&
  3163. (queue->bufstates[bidx].flags &
  3164. QDIO_OUTBUF_STATE_FLAG_PENDING) != 0) {
  3165. BUG_ON(card->options.cq != QETH_CQ_ENABLED);
  3166. if (atomic_cmpxchg(&buffer->state,
  3167. QETH_QDIO_BUF_PRIMED,
  3168. QETH_QDIO_BUF_PENDING) ==
  3169. QETH_QDIO_BUF_PRIMED) {
  3170. qeth_notify_skbs(queue, buffer,
  3171. TX_NOTIFY_PENDING);
  3172. }
  3173. buffer->aob = queue->bufstates[bidx].aob;
  3174. QETH_CARD_TEXT_(queue->card, 5, "pel%d", bidx);
  3175. QETH_CARD_TEXT(queue->card, 5, "aob");
  3176. QETH_CARD_TEXT_(queue->card, 5, "%lx",
  3177. virt_to_phys(buffer->aob));
  3178. BUG_ON(bidx < 0 || bidx >= QDIO_MAX_BUFFERS_PER_Q);
  3179. if (qeth_init_qdio_out_buf(queue, bidx)) {
  3180. QETH_CARD_TEXT(card, 2, "outofbuf");
  3181. qeth_schedule_recovery(card);
  3182. }
  3183. } else {
  3184. if (card->options.cq == QETH_CQ_ENABLED) {
  3185. enum iucv_tx_notify n;
  3186. n = qeth_compute_cq_notification(
  3187. buffer->buffer->element[15].sflags, 0);
  3188. qeth_notify_skbs(queue, buffer, n);
  3189. }
  3190. qeth_clear_output_buffer(queue, buffer,
  3191. QETH_QDIO_BUF_EMPTY);
  3192. }
  3193. qeth_cleanup_handled_pending(queue, bidx, 0);
  3194. }
  3195. atomic_sub(count, &queue->used_buffers);
  3196. /* check if we need to do something on this outbound queue */
  3197. if (card->info.type != QETH_CARD_TYPE_IQD)
  3198. qeth_check_outbound_queue(queue);
  3199. netif_wake_queue(queue->card->dev);
  3200. if (card->options.performance_stats)
  3201. card->perf_stats.outbound_handler_time += qeth_get_micros() -
  3202. card->perf_stats.outbound_handler_start_time;
  3203. }
  3204. EXPORT_SYMBOL_GPL(qeth_qdio_output_handler);
  3205. int qeth_get_priority_queue(struct qeth_card *card, struct sk_buff *skb,
  3206. int ipv, int cast_type)
  3207. {
  3208. if (!ipv && (card->info.type == QETH_CARD_TYPE_OSD ||
  3209. card->info.type == QETH_CARD_TYPE_OSX))
  3210. return card->qdio.default_out_queue;
  3211. switch (card->qdio.no_out_queues) {
  3212. case 4:
  3213. if (cast_type && card->info.is_multicast_different)
  3214. return card->info.is_multicast_different &
  3215. (card->qdio.no_out_queues - 1);
  3216. if (card->qdio.do_prio_queueing && (ipv == 4)) {
  3217. const u8 tos = ip_hdr(skb)->tos;
  3218. if (card->qdio.do_prio_queueing ==
  3219. QETH_PRIO_Q_ING_TOS) {
  3220. if (tos & IP_TOS_NOTIMPORTANT)
  3221. return 3;
  3222. if (tos & IP_TOS_HIGHRELIABILITY)
  3223. return 2;
  3224. if (tos & IP_TOS_HIGHTHROUGHPUT)
  3225. return 1;
  3226. if (tos & IP_TOS_LOWDELAY)
  3227. return 0;
  3228. }
  3229. if (card->qdio.do_prio_queueing ==
  3230. QETH_PRIO_Q_ING_PREC)
  3231. return 3 - (tos >> 6);
  3232. } else if (card->qdio.do_prio_queueing && (ipv == 6)) {
  3233. /* TODO: IPv6!!! */
  3234. }
  3235. return card->qdio.default_out_queue;
  3236. case 1: /* fallthrough for single-out-queue 1920-device */
  3237. default:
  3238. return card->qdio.default_out_queue;
  3239. }
  3240. }
  3241. EXPORT_SYMBOL_GPL(qeth_get_priority_queue);
  3242. int qeth_get_elements_no(struct qeth_card *card, void *hdr,
  3243. struct sk_buff *skb, int elems)
  3244. {
  3245. int dlen = skb->len - skb->data_len;
  3246. int elements_needed = PFN_UP((unsigned long)skb->data + dlen - 1) -
  3247. PFN_DOWN((unsigned long)skb->data);
  3248. elements_needed += skb_shinfo(skb)->nr_frags;
  3249. if ((elements_needed + elems) > QETH_MAX_BUFFER_ELEMENTS(card)) {
  3250. QETH_DBF_MESSAGE(2, "Invalid size of IP packet "
  3251. "(Number=%d / Length=%d). Discarded.\n",
  3252. (elements_needed+elems), skb->len);
  3253. return 0;
  3254. }
  3255. return elements_needed;
  3256. }
  3257. EXPORT_SYMBOL_GPL(qeth_get_elements_no);
  3258. int qeth_hdr_chk_and_bounce(struct sk_buff *skb, int len)
  3259. {
  3260. int hroom, inpage, rest;
  3261. if (((unsigned long)skb->data & PAGE_MASK) !=
  3262. (((unsigned long)skb->data + len - 1) & PAGE_MASK)) {
  3263. hroom = skb_headroom(skb);
  3264. inpage = PAGE_SIZE - ((unsigned long) skb->data % PAGE_SIZE);
  3265. rest = len - inpage;
  3266. if (rest > hroom)
  3267. return 1;
  3268. memmove(skb->data - rest, skb->data, skb->len - skb->data_len);
  3269. skb->data -= rest;
  3270. QETH_DBF_MESSAGE(2, "skb bounce len: %d rest: %d\n", len, rest);
  3271. }
  3272. return 0;
  3273. }
  3274. EXPORT_SYMBOL_GPL(qeth_hdr_chk_and_bounce);
  3275. static inline void __qeth_fill_buffer(struct sk_buff *skb,
  3276. struct qdio_buffer *buffer, int is_tso, int *next_element_to_fill,
  3277. int offset)
  3278. {
  3279. int length = skb->len - skb->data_len;
  3280. int length_here;
  3281. int element;
  3282. char *data;
  3283. int first_lap, cnt;
  3284. struct skb_frag_struct *frag;
  3285. element = *next_element_to_fill;
  3286. data = skb->data;
  3287. first_lap = (is_tso == 0 ? 1 : 0);
  3288. if (offset >= 0) {
  3289. data = skb->data + offset;
  3290. length -= offset;
  3291. first_lap = 0;
  3292. }
  3293. while (length > 0) {
  3294. /* length_here is the remaining amount of data in this page */
  3295. length_here = PAGE_SIZE - ((unsigned long) data % PAGE_SIZE);
  3296. if (length < length_here)
  3297. length_here = length;
  3298. buffer->element[element].addr = data;
  3299. buffer->element[element].length = length_here;
  3300. length -= length_here;
  3301. if (!length) {
  3302. if (first_lap)
  3303. if (skb_shinfo(skb)->nr_frags)
  3304. buffer->element[element].eflags =
  3305. SBAL_EFLAGS_FIRST_FRAG;
  3306. else
  3307. buffer->element[element].eflags = 0;
  3308. else
  3309. buffer->element[element].eflags =
  3310. SBAL_EFLAGS_MIDDLE_FRAG;
  3311. } else {
  3312. if (first_lap)
  3313. buffer->element[element].eflags =
  3314. SBAL_EFLAGS_FIRST_FRAG;
  3315. else
  3316. buffer->element[element].eflags =
  3317. SBAL_EFLAGS_MIDDLE_FRAG;
  3318. }
  3319. data += length_here;
  3320. element++;
  3321. first_lap = 0;
  3322. }
  3323. for (cnt = 0; cnt < skb_shinfo(skb)->nr_frags; cnt++) {
  3324. frag = &skb_shinfo(skb)->frags[cnt];
  3325. buffer->element[element].addr = (char *)
  3326. page_to_phys(skb_frag_page(frag))
  3327. + frag->page_offset;
  3328. buffer->element[element].length = frag->size;
  3329. buffer->element[element].eflags = SBAL_EFLAGS_MIDDLE_FRAG;
  3330. element++;
  3331. }
  3332. if (buffer->element[element - 1].eflags)
  3333. buffer->element[element - 1].eflags = SBAL_EFLAGS_LAST_FRAG;
  3334. *next_element_to_fill = element;
  3335. }
  3336. static inline int qeth_fill_buffer(struct qeth_qdio_out_q *queue,
  3337. struct qeth_qdio_out_buffer *buf, struct sk_buff *skb,
  3338. struct qeth_hdr *hdr, int offset, int hd_len)
  3339. {
  3340. struct qdio_buffer *buffer;
  3341. int flush_cnt = 0, hdr_len, large_send = 0;
  3342. buffer = buf->buffer;
  3343. atomic_inc(&skb->users);
  3344. skb_queue_tail(&buf->skb_list, skb);
  3345. /*check first on TSO ....*/
  3346. if (hdr->hdr.l3.id == QETH_HEADER_TYPE_TSO) {
  3347. int element = buf->next_element_to_fill;
  3348. hdr_len = sizeof(struct qeth_hdr_tso) +
  3349. ((struct qeth_hdr_tso *)hdr)->ext.dg_hdr_len;
  3350. /*fill first buffer entry only with header information */
  3351. buffer->element[element].addr = skb->data;
  3352. buffer->element[element].length = hdr_len;
  3353. buffer->element[element].eflags = SBAL_EFLAGS_FIRST_FRAG;
  3354. buf->next_element_to_fill++;
  3355. skb->data += hdr_len;
  3356. skb->len -= hdr_len;
  3357. large_send = 1;
  3358. }
  3359. if (offset >= 0) {
  3360. int element = buf->next_element_to_fill;
  3361. buffer->element[element].addr = hdr;
  3362. buffer->element[element].length = sizeof(struct qeth_hdr) +
  3363. hd_len;
  3364. buffer->element[element].eflags = SBAL_EFLAGS_FIRST_FRAG;
  3365. buf->is_header[element] = 1;
  3366. buf->next_element_to_fill++;
  3367. }
  3368. __qeth_fill_buffer(skb, buffer, large_send,
  3369. (int *)&buf->next_element_to_fill, offset);
  3370. if (!queue->do_pack) {
  3371. QETH_CARD_TEXT(queue->card, 6, "fillbfnp");
  3372. /* set state to PRIMED -> will be flushed */
  3373. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  3374. flush_cnt = 1;
  3375. } else {
  3376. QETH_CARD_TEXT(queue->card, 6, "fillbfpa");
  3377. if (queue->card->options.performance_stats)
  3378. queue->card->perf_stats.skbs_sent_pack++;
  3379. if (buf->next_element_to_fill >=
  3380. QETH_MAX_BUFFER_ELEMENTS(queue->card)) {
  3381. /*
  3382. * packed buffer if full -> set state PRIMED
  3383. * -> will be flushed
  3384. */
  3385. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  3386. flush_cnt = 1;
  3387. }
  3388. }
  3389. return flush_cnt;
  3390. }
  3391. int qeth_do_send_packet_fast(struct qeth_card *card,
  3392. struct qeth_qdio_out_q *queue, struct sk_buff *skb,
  3393. struct qeth_hdr *hdr, int elements_needed,
  3394. int offset, int hd_len)
  3395. {
  3396. struct qeth_qdio_out_buffer *buffer;
  3397. int index;
  3398. /* spin until we get the queue ... */
  3399. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  3400. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  3401. /* ... now we've got the queue */
  3402. index = queue->next_buf_to_fill;
  3403. buffer = queue->bufs[queue->next_buf_to_fill];
  3404. /*
  3405. * check if buffer is empty to make sure that we do not 'overtake'
  3406. * ourselves and try to fill a buffer that is already primed
  3407. */
  3408. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY)
  3409. goto out;
  3410. queue->next_buf_to_fill = (queue->next_buf_to_fill + 1) %
  3411. QDIO_MAX_BUFFERS_PER_Q;
  3412. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  3413. qeth_fill_buffer(queue, buffer, skb, hdr, offset, hd_len);
  3414. qeth_flush_buffers(queue, index, 1);
  3415. return 0;
  3416. out:
  3417. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  3418. return -EBUSY;
  3419. }
  3420. EXPORT_SYMBOL_GPL(qeth_do_send_packet_fast);
  3421. int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue,
  3422. struct sk_buff *skb, struct qeth_hdr *hdr,
  3423. int elements_needed)
  3424. {
  3425. struct qeth_qdio_out_buffer *buffer;
  3426. int start_index;
  3427. int flush_count = 0;
  3428. int do_pack = 0;
  3429. int tmp;
  3430. int rc = 0;
  3431. /* spin until we get the queue ... */
  3432. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  3433. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  3434. start_index = queue->next_buf_to_fill;
  3435. buffer = queue->bufs[queue->next_buf_to_fill];
  3436. /*
  3437. * check if buffer is empty to make sure that we do not 'overtake'
  3438. * ourselves and try to fill a buffer that is already primed
  3439. */
  3440. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY) {
  3441. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  3442. return -EBUSY;
  3443. }
  3444. /* check if we need to switch packing state of this queue */
  3445. qeth_switch_to_packing_if_needed(queue);
  3446. if (queue->do_pack) {
  3447. do_pack = 1;
  3448. /* does packet fit in current buffer? */
  3449. if ((QETH_MAX_BUFFER_ELEMENTS(card) -
  3450. buffer->next_element_to_fill) < elements_needed) {
  3451. /* ... no -> set state PRIMED */
  3452. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  3453. flush_count++;
  3454. queue->next_buf_to_fill =
  3455. (queue->next_buf_to_fill + 1) %
  3456. QDIO_MAX_BUFFERS_PER_Q;
  3457. buffer = queue->bufs[queue->next_buf_to_fill];
  3458. /* we did a step forward, so check buffer state
  3459. * again */
  3460. if (atomic_read(&buffer->state) !=
  3461. QETH_QDIO_BUF_EMPTY) {
  3462. qeth_flush_buffers(queue, start_index,
  3463. flush_count);
  3464. atomic_set(&queue->state,
  3465. QETH_OUT_Q_UNLOCKED);
  3466. return -EBUSY;
  3467. }
  3468. }
  3469. }
  3470. tmp = qeth_fill_buffer(queue, buffer, skb, hdr, -1, 0);
  3471. queue->next_buf_to_fill = (queue->next_buf_to_fill + tmp) %
  3472. QDIO_MAX_BUFFERS_PER_Q;
  3473. flush_count += tmp;
  3474. if (flush_count)
  3475. qeth_flush_buffers(queue, start_index, flush_count);
  3476. else if (!atomic_read(&queue->set_pci_flags_count))
  3477. atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH);
  3478. /*
  3479. * queue->state will go from LOCKED -> UNLOCKED or from
  3480. * LOCKED_FLUSH -> LOCKED if output_handler wanted to 'notify' us
  3481. * (switch packing state or flush buffer to get another pci flag out).
  3482. * In that case we will enter this loop
  3483. */
  3484. while (atomic_dec_return(&queue->state)) {
  3485. flush_count = 0;
  3486. start_index = queue->next_buf_to_fill;
  3487. /* check if we can go back to non-packing state */
  3488. flush_count += qeth_switch_to_nonpacking_if_needed(queue);
  3489. /*
  3490. * check if we need to flush a packing buffer to get a pci
  3491. * flag out on the queue
  3492. */
  3493. if (!flush_count && !atomic_read(&queue->set_pci_flags_count))
  3494. flush_count += qeth_flush_buffers_on_no_pci(queue);
  3495. if (flush_count)
  3496. qeth_flush_buffers(queue, start_index, flush_count);
  3497. }
  3498. /* at this point the queue is UNLOCKED again */
  3499. if (queue->card->options.performance_stats && do_pack)
  3500. queue->card->perf_stats.bufs_sent_pack += flush_count;
  3501. return rc;
  3502. }
  3503. EXPORT_SYMBOL_GPL(qeth_do_send_packet);
  3504. static int qeth_setadp_promisc_mode_cb(struct qeth_card *card,
  3505. struct qeth_reply *reply, unsigned long data)
  3506. {
  3507. struct qeth_ipa_cmd *cmd;
  3508. struct qeth_ipacmd_setadpparms *setparms;
  3509. QETH_CARD_TEXT(card, 4, "prmadpcb");
  3510. cmd = (struct qeth_ipa_cmd *) data;
  3511. setparms = &(cmd->data.setadapterparms);
  3512. qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  3513. if (cmd->hdr.return_code) {
  3514. QETH_CARD_TEXT_(card, 4, "prmrc%2.2x", cmd->hdr.return_code);
  3515. setparms->data.mode = SET_PROMISC_MODE_OFF;
  3516. }
  3517. card->info.promisc_mode = setparms->data.mode;
  3518. return 0;
  3519. }
  3520. void qeth_setadp_promisc_mode(struct qeth_card *card)
  3521. {
  3522. enum qeth_ipa_promisc_modes mode;
  3523. struct net_device *dev = card->dev;
  3524. struct qeth_cmd_buffer *iob;
  3525. struct qeth_ipa_cmd *cmd;
  3526. QETH_CARD_TEXT(card, 4, "setprom");
  3527. if (((dev->flags & IFF_PROMISC) &&
  3528. (card->info.promisc_mode == SET_PROMISC_MODE_ON)) ||
  3529. (!(dev->flags & IFF_PROMISC) &&
  3530. (card->info.promisc_mode == SET_PROMISC_MODE_OFF)))
  3531. return;
  3532. mode = SET_PROMISC_MODE_OFF;
  3533. if (dev->flags & IFF_PROMISC)
  3534. mode = SET_PROMISC_MODE_ON;
  3535. QETH_CARD_TEXT_(card, 4, "mode:%x", mode);
  3536. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE,
  3537. sizeof(struct qeth_ipacmd_setadpparms));
  3538. cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE);
  3539. cmd->data.setadapterparms.data.mode = mode;
  3540. qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL);
  3541. }
  3542. EXPORT_SYMBOL_GPL(qeth_setadp_promisc_mode);
  3543. int qeth_change_mtu(struct net_device *dev, int new_mtu)
  3544. {
  3545. struct qeth_card *card;
  3546. char dbf_text[15];
  3547. card = dev->ml_priv;
  3548. QETH_CARD_TEXT(card, 4, "chgmtu");
  3549. sprintf(dbf_text, "%8x", new_mtu);
  3550. QETH_CARD_TEXT(card, 4, dbf_text);
  3551. if (new_mtu < 64)
  3552. return -EINVAL;
  3553. if (new_mtu > 65535)
  3554. return -EINVAL;
  3555. if ((!qeth_is_supported(card, IPA_IP_FRAGMENTATION)) &&
  3556. (!qeth_mtu_is_valid(card, new_mtu)))
  3557. return -EINVAL;
  3558. dev->mtu = new_mtu;
  3559. return 0;
  3560. }
  3561. EXPORT_SYMBOL_GPL(qeth_change_mtu);
  3562. struct net_device_stats *qeth_get_stats(struct net_device *dev)
  3563. {
  3564. struct qeth_card *card;
  3565. card = dev->ml_priv;
  3566. QETH_CARD_TEXT(card, 5, "getstat");
  3567. return &card->stats;
  3568. }
  3569. EXPORT_SYMBOL_GPL(qeth_get_stats);
  3570. static int qeth_setadpparms_change_macaddr_cb(struct qeth_card *card,
  3571. struct qeth_reply *reply, unsigned long data)
  3572. {
  3573. struct qeth_ipa_cmd *cmd;
  3574. QETH_CARD_TEXT(card, 4, "chgmaccb");
  3575. cmd = (struct qeth_ipa_cmd *) data;
  3576. if (!card->options.layer2 ||
  3577. !(card->info.mac_bits & QETH_LAYER2_MAC_READ)) {
  3578. memcpy(card->dev->dev_addr,
  3579. &cmd->data.setadapterparms.data.change_addr.addr,
  3580. OSA_ADDR_LEN);
  3581. card->info.mac_bits |= QETH_LAYER2_MAC_READ;
  3582. }
  3583. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3584. return 0;
  3585. }
  3586. int qeth_setadpparms_change_macaddr(struct qeth_card *card)
  3587. {
  3588. int rc;
  3589. struct qeth_cmd_buffer *iob;
  3590. struct qeth_ipa_cmd *cmd;
  3591. QETH_CARD_TEXT(card, 4, "chgmac");
  3592. iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS,
  3593. sizeof(struct qeth_ipacmd_setadpparms));
  3594. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3595. cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC;
  3596. cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN;
  3597. memcpy(&cmd->data.setadapterparms.data.change_addr.addr,
  3598. card->dev->dev_addr, OSA_ADDR_LEN);
  3599. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_change_macaddr_cb,
  3600. NULL);
  3601. return rc;
  3602. }
  3603. EXPORT_SYMBOL_GPL(qeth_setadpparms_change_macaddr);
  3604. static int qeth_setadpparms_set_access_ctrl_cb(struct qeth_card *card,
  3605. struct qeth_reply *reply, unsigned long data)
  3606. {
  3607. struct qeth_ipa_cmd *cmd;
  3608. struct qeth_set_access_ctrl *access_ctrl_req;
  3609. QETH_CARD_TEXT(card, 4, "setaccb");
  3610. cmd = (struct qeth_ipa_cmd *) data;
  3611. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3612. QETH_DBF_TEXT_(SETUP, 2, "setaccb");
  3613. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3614. QETH_DBF_TEXT_(SETUP, 2, "rc=%d",
  3615. cmd->data.setadapterparms.hdr.return_code);
  3616. switch (cmd->data.setadapterparms.hdr.return_code) {
  3617. case SET_ACCESS_CTRL_RC_SUCCESS:
  3618. case SET_ACCESS_CTRL_RC_ALREADY_NOT_ISOLATED:
  3619. case SET_ACCESS_CTRL_RC_ALREADY_ISOLATED:
  3620. {
  3621. card->options.isolation = access_ctrl_req->subcmd_code;
  3622. if (card->options.isolation == ISOLATION_MODE_NONE) {
  3623. dev_info(&card->gdev->dev,
  3624. "QDIO data connection isolation is deactivated\n");
  3625. } else {
  3626. dev_info(&card->gdev->dev,
  3627. "QDIO data connection isolation is activated\n");
  3628. }
  3629. QETH_DBF_MESSAGE(3, "OK:SET_ACCESS_CTRL(%s, %d)==%d\n",
  3630. card->gdev->dev.kobj.name,
  3631. access_ctrl_req->subcmd_code,
  3632. cmd->data.setadapterparms.hdr.return_code);
  3633. break;
  3634. }
  3635. case SET_ACCESS_CTRL_RC_NOT_SUPPORTED:
  3636. {
  3637. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_CTRL(%s,%d)==%d\n",
  3638. card->gdev->dev.kobj.name,
  3639. access_ctrl_req->subcmd_code,
  3640. cmd->data.setadapterparms.hdr.return_code);
  3641. dev_err(&card->gdev->dev, "Adapter does not "
  3642. "support QDIO data connection isolation\n");
  3643. /* ensure isolation mode is "none" */
  3644. card->options.isolation = ISOLATION_MODE_NONE;
  3645. break;
  3646. }
  3647. case SET_ACCESS_CTRL_RC_NONE_SHARED_ADAPTER:
  3648. {
  3649. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d\n",
  3650. card->gdev->dev.kobj.name,
  3651. access_ctrl_req->subcmd_code,
  3652. cmd->data.setadapterparms.hdr.return_code);
  3653. dev_err(&card->gdev->dev,
  3654. "Adapter is dedicated. "
  3655. "QDIO data connection isolation not supported\n");
  3656. /* ensure isolation mode is "none" */
  3657. card->options.isolation = ISOLATION_MODE_NONE;
  3658. break;
  3659. }
  3660. case SET_ACCESS_CTRL_RC_ACTIVE_CHECKSUM_OFF:
  3661. {
  3662. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d\n",
  3663. card->gdev->dev.kobj.name,
  3664. access_ctrl_req->subcmd_code,
  3665. cmd->data.setadapterparms.hdr.return_code);
  3666. dev_err(&card->gdev->dev,
  3667. "TSO does not permit QDIO data connection isolation\n");
  3668. /* ensure isolation mode is "none" */
  3669. card->options.isolation = ISOLATION_MODE_NONE;
  3670. break;
  3671. }
  3672. default:
  3673. {
  3674. /* this should never happen */
  3675. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d"
  3676. "==UNKNOWN\n",
  3677. card->gdev->dev.kobj.name,
  3678. access_ctrl_req->subcmd_code,
  3679. cmd->data.setadapterparms.hdr.return_code);
  3680. /* ensure isolation mode is "none" */
  3681. card->options.isolation = ISOLATION_MODE_NONE;
  3682. break;
  3683. }
  3684. }
  3685. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3686. return 0;
  3687. }
  3688. static int qeth_setadpparms_set_access_ctrl(struct qeth_card *card,
  3689. enum qeth_ipa_isolation_modes isolation)
  3690. {
  3691. int rc;
  3692. struct qeth_cmd_buffer *iob;
  3693. struct qeth_ipa_cmd *cmd;
  3694. struct qeth_set_access_ctrl *access_ctrl_req;
  3695. QETH_CARD_TEXT(card, 4, "setacctl");
  3696. QETH_DBF_TEXT_(SETUP, 2, "setacctl");
  3697. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3698. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_ACCESS_CONTROL,
  3699. sizeof(struct qeth_ipacmd_setadpparms_hdr) +
  3700. sizeof(struct qeth_set_access_ctrl));
  3701. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3702. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3703. access_ctrl_req->subcmd_code = isolation;
  3704. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_set_access_ctrl_cb,
  3705. NULL);
  3706. QETH_DBF_TEXT_(SETUP, 2, "rc=%d", rc);
  3707. return rc;
  3708. }
  3709. int qeth_set_access_ctrl_online(struct qeth_card *card)
  3710. {
  3711. int rc = 0;
  3712. QETH_CARD_TEXT(card, 4, "setactlo");
  3713. if ((card->info.type == QETH_CARD_TYPE_OSD ||
  3714. card->info.type == QETH_CARD_TYPE_OSX) &&
  3715. qeth_adp_supported(card, IPA_SETADP_SET_ACCESS_CONTROL)) {
  3716. rc = qeth_setadpparms_set_access_ctrl(card,
  3717. card->options.isolation);
  3718. if (rc) {
  3719. QETH_DBF_MESSAGE(3,
  3720. "IPA(SET_ACCESS_CTRL,%s,%d) sent failed\n",
  3721. card->gdev->dev.kobj.name,
  3722. rc);
  3723. }
  3724. } else if (card->options.isolation != ISOLATION_MODE_NONE) {
  3725. card->options.isolation = ISOLATION_MODE_NONE;
  3726. dev_err(&card->gdev->dev, "Adapter does not "
  3727. "support QDIO data connection isolation\n");
  3728. rc = -EOPNOTSUPP;
  3729. }
  3730. return rc;
  3731. }
  3732. EXPORT_SYMBOL_GPL(qeth_set_access_ctrl_online);
  3733. void qeth_tx_timeout(struct net_device *dev)
  3734. {
  3735. struct qeth_card *card;
  3736. card = dev->ml_priv;
  3737. QETH_CARD_TEXT(card, 4, "txtimeo");
  3738. card->stats.tx_errors++;
  3739. qeth_schedule_recovery(card);
  3740. }
  3741. EXPORT_SYMBOL_GPL(qeth_tx_timeout);
  3742. int qeth_mdio_read(struct net_device *dev, int phy_id, int regnum)
  3743. {
  3744. struct qeth_card *card = dev->ml_priv;
  3745. int rc = 0;
  3746. switch (regnum) {
  3747. case MII_BMCR: /* Basic mode control register */
  3748. rc = BMCR_FULLDPLX;
  3749. if ((card->info.link_type != QETH_LINK_TYPE_GBIT_ETH) &&
  3750. (card->info.link_type != QETH_LINK_TYPE_OSN) &&
  3751. (card->info.link_type != QETH_LINK_TYPE_10GBIT_ETH))
  3752. rc |= BMCR_SPEED100;
  3753. break;
  3754. case MII_BMSR: /* Basic mode status register */
  3755. rc = BMSR_ERCAP | BMSR_ANEGCOMPLETE | BMSR_LSTATUS |
  3756. BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL |
  3757. BMSR_100BASE4;
  3758. break;
  3759. case MII_PHYSID1: /* PHYS ID 1 */
  3760. rc = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 8) |
  3761. dev->dev_addr[2];
  3762. rc = (rc >> 5) & 0xFFFF;
  3763. break;
  3764. case MII_PHYSID2: /* PHYS ID 2 */
  3765. rc = (dev->dev_addr[2] << 10) & 0xFFFF;
  3766. break;
  3767. case MII_ADVERTISE: /* Advertisement control reg */
  3768. rc = ADVERTISE_ALL;
  3769. break;
  3770. case MII_LPA: /* Link partner ability reg */
  3771. rc = LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL |
  3772. LPA_100BASE4 | LPA_LPACK;
  3773. break;
  3774. case MII_EXPANSION: /* Expansion register */
  3775. break;
  3776. case MII_DCOUNTER: /* disconnect counter */
  3777. break;
  3778. case MII_FCSCOUNTER: /* false carrier counter */
  3779. break;
  3780. case MII_NWAYTEST: /* N-way auto-neg test register */
  3781. break;
  3782. case MII_RERRCOUNTER: /* rx error counter */
  3783. rc = card->stats.rx_errors;
  3784. break;
  3785. case MII_SREVISION: /* silicon revision */
  3786. break;
  3787. case MII_RESV1: /* reserved 1 */
  3788. break;
  3789. case MII_LBRERROR: /* loopback, rx, bypass error */
  3790. break;
  3791. case MII_PHYADDR: /* physical address */
  3792. break;
  3793. case MII_RESV2: /* reserved 2 */
  3794. break;
  3795. case MII_TPISTATUS: /* TPI status for 10mbps */
  3796. break;
  3797. case MII_NCONFIG: /* network interface config */
  3798. break;
  3799. default:
  3800. break;
  3801. }
  3802. return rc;
  3803. }
  3804. EXPORT_SYMBOL_GPL(qeth_mdio_read);
  3805. static int qeth_send_ipa_snmp_cmd(struct qeth_card *card,
  3806. struct qeth_cmd_buffer *iob, int len,
  3807. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  3808. unsigned long),
  3809. void *reply_param)
  3810. {
  3811. u16 s1, s2;
  3812. QETH_CARD_TEXT(card, 4, "sendsnmp");
  3813. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  3814. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  3815. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  3816. /* adjust PDU length fields in IPA_PDU_HEADER */
  3817. s1 = (u32) IPA_PDU_HEADER_SIZE + len;
  3818. s2 = (u32) len;
  3819. memcpy(QETH_IPA_PDU_LEN_TOTAL(iob->data), &s1, 2);
  3820. memcpy(QETH_IPA_PDU_LEN_PDU1(iob->data), &s2, 2);
  3821. memcpy(QETH_IPA_PDU_LEN_PDU2(iob->data), &s2, 2);
  3822. memcpy(QETH_IPA_PDU_LEN_PDU3(iob->data), &s2, 2);
  3823. return qeth_send_control_data(card, IPA_PDU_HEADER_SIZE + len, iob,
  3824. reply_cb, reply_param);
  3825. }
  3826. static int qeth_snmp_command_cb(struct qeth_card *card,
  3827. struct qeth_reply *reply, unsigned long sdata)
  3828. {
  3829. struct qeth_ipa_cmd *cmd;
  3830. struct qeth_arp_query_info *qinfo;
  3831. struct qeth_snmp_cmd *snmp;
  3832. unsigned char *data;
  3833. __u16 data_len;
  3834. QETH_CARD_TEXT(card, 3, "snpcmdcb");
  3835. cmd = (struct qeth_ipa_cmd *) sdata;
  3836. data = (unsigned char *)((char *)cmd - reply->offset);
  3837. qinfo = (struct qeth_arp_query_info *) reply->param;
  3838. snmp = &cmd->data.setadapterparms.data.snmp;
  3839. if (cmd->hdr.return_code) {
  3840. QETH_CARD_TEXT_(card, 4, "scer1%i", cmd->hdr.return_code);
  3841. return 0;
  3842. }
  3843. if (cmd->data.setadapterparms.hdr.return_code) {
  3844. cmd->hdr.return_code =
  3845. cmd->data.setadapterparms.hdr.return_code;
  3846. QETH_CARD_TEXT_(card, 4, "scer2%i", cmd->hdr.return_code);
  3847. return 0;
  3848. }
  3849. data_len = *((__u16 *)QETH_IPA_PDU_LEN_PDU1(data));
  3850. if (cmd->data.setadapterparms.hdr.seq_no == 1)
  3851. data_len -= (__u16)((char *)&snmp->data - (char *)cmd);
  3852. else
  3853. data_len -= (__u16)((char *)&snmp->request - (char *)cmd);
  3854. /* check if there is enough room in userspace */
  3855. if ((qinfo->udata_len - qinfo->udata_offset) < data_len) {
  3856. QETH_CARD_TEXT_(card, 4, "scer3%i", -ENOMEM);
  3857. cmd->hdr.return_code = -ENOMEM;
  3858. return 0;
  3859. }
  3860. QETH_CARD_TEXT_(card, 4, "snore%i",
  3861. cmd->data.setadapterparms.hdr.used_total);
  3862. QETH_CARD_TEXT_(card, 4, "sseqn%i",
  3863. cmd->data.setadapterparms.hdr.seq_no);
  3864. /*copy entries to user buffer*/
  3865. if (cmd->data.setadapterparms.hdr.seq_no == 1) {
  3866. memcpy(qinfo->udata + qinfo->udata_offset,
  3867. (char *)snmp,
  3868. data_len + offsetof(struct qeth_snmp_cmd, data));
  3869. qinfo->udata_offset += offsetof(struct qeth_snmp_cmd, data);
  3870. } else {
  3871. memcpy(qinfo->udata + qinfo->udata_offset,
  3872. (char *)&snmp->request, data_len);
  3873. }
  3874. qinfo->udata_offset += data_len;
  3875. /* check if all replies received ... */
  3876. QETH_CARD_TEXT_(card, 4, "srtot%i",
  3877. cmd->data.setadapterparms.hdr.used_total);
  3878. QETH_CARD_TEXT_(card, 4, "srseq%i",
  3879. cmd->data.setadapterparms.hdr.seq_no);
  3880. if (cmd->data.setadapterparms.hdr.seq_no <
  3881. cmd->data.setadapterparms.hdr.used_total)
  3882. return 1;
  3883. return 0;
  3884. }
  3885. int qeth_snmp_command(struct qeth_card *card, char __user *udata)
  3886. {
  3887. struct qeth_cmd_buffer *iob;
  3888. struct qeth_ipa_cmd *cmd;
  3889. struct qeth_snmp_ureq *ureq;
  3890. int req_len;
  3891. struct qeth_arp_query_info qinfo = {0, };
  3892. int rc = 0;
  3893. QETH_CARD_TEXT(card, 3, "snmpcmd");
  3894. if (card->info.guestlan)
  3895. return -EOPNOTSUPP;
  3896. if ((!qeth_adp_supported(card, IPA_SETADP_SET_SNMP_CONTROL)) &&
  3897. (!card->options.layer2)) {
  3898. return -EOPNOTSUPP;
  3899. }
  3900. /* skip 4 bytes (data_len struct member) to get req_len */
  3901. if (copy_from_user(&req_len, udata + sizeof(int), sizeof(int)))
  3902. return -EFAULT;
  3903. ureq = memdup_user(udata, req_len + sizeof(struct qeth_snmp_ureq_hdr));
  3904. if (IS_ERR(ureq)) {
  3905. QETH_CARD_TEXT(card, 2, "snmpnome");
  3906. return PTR_ERR(ureq);
  3907. }
  3908. qinfo.udata_len = ureq->hdr.data_len;
  3909. qinfo.udata = kzalloc(qinfo.udata_len, GFP_KERNEL);
  3910. if (!qinfo.udata) {
  3911. kfree(ureq);
  3912. return -ENOMEM;
  3913. }
  3914. qinfo.udata_offset = sizeof(struct qeth_snmp_ureq_hdr);
  3915. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL,
  3916. QETH_SNMP_SETADP_CMDLENGTH + req_len);
  3917. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3918. memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len);
  3919. rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len,
  3920. qeth_snmp_command_cb, (void *)&qinfo);
  3921. if (rc)
  3922. QETH_DBF_MESSAGE(2, "SNMP command failed on %s: (0x%x)\n",
  3923. QETH_CARD_IFNAME(card), rc);
  3924. else {
  3925. if (copy_to_user(udata, qinfo.udata, qinfo.udata_len))
  3926. rc = -EFAULT;
  3927. }
  3928. kfree(ureq);
  3929. kfree(qinfo.udata);
  3930. return rc;
  3931. }
  3932. EXPORT_SYMBOL_GPL(qeth_snmp_command);
  3933. static inline int qeth_get_qdio_q_format(struct qeth_card *card)
  3934. {
  3935. switch (card->info.type) {
  3936. case QETH_CARD_TYPE_IQD:
  3937. return 2;
  3938. default:
  3939. return 0;
  3940. }
  3941. }
  3942. static void qeth_determine_capabilities(struct qeth_card *card)
  3943. {
  3944. int rc;
  3945. int length;
  3946. char *prcd;
  3947. struct ccw_device *ddev;
  3948. int ddev_offline = 0;
  3949. QETH_DBF_TEXT(SETUP, 2, "detcapab");
  3950. ddev = CARD_DDEV(card);
  3951. if (!ddev->online) {
  3952. ddev_offline = 1;
  3953. rc = ccw_device_set_online(ddev);
  3954. if (rc) {
  3955. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3956. goto out;
  3957. }
  3958. }
  3959. rc = qeth_read_conf_data(card, (void **) &prcd, &length);
  3960. if (rc) {
  3961. QETH_DBF_MESSAGE(2, "%s qeth_read_conf_data returned %i\n",
  3962. dev_name(&card->gdev->dev), rc);
  3963. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  3964. goto out_offline;
  3965. }
  3966. qeth_configure_unitaddr(card, prcd);
  3967. qeth_configure_blkt_default(card, prcd);
  3968. kfree(prcd);
  3969. rc = qdio_get_ssqd_desc(ddev, &card->ssqd);
  3970. if (rc)
  3971. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  3972. QETH_DBF_TEXT_(SETUP, 2, "qfmt%d", card->ssqd.qfmt);
  3973. QETH_DBF_TEXT_(SETUP, 2, "%d", card->ssqd.qdioac1);
  3974. QETH_DBF_TEXT_(SETUP, 2, "%d", card->ssqd.qdioac3);
  3975. QETH_DBF_TEXT_(SETUP, 2, "icnt%d", card->ssqd.icnt);
  3976. if (!((card->ssqd.qfmt != QDIO_IQDIO_QFMT) ||
  3977. ((card->ssqd.qdioac1 & CHSC_AC1_INITIATE_INPUTQ) == 0) ||
  3978. ((card->ssqd.qdioac3 & CHSC_AC3_FORMAT2_CQ_AVAILABLE) == 0))) {
  3979. dev_info(&card->gdev->dev,
  3980. "Completion Queueing supported\n");
  3981. } else {
  3982. card->options.cq = QETH_CQ_NOTAVAILABLE;
  3983. }
  3984. out_offline:
  3985. if (ddev_offline == 1)
  3986. ccw_device_set_offline(ddev);
  3987. out:
  3988. return;
  3989. }
  3990. static inline void qeth_qdio_establish_cq(struct qeth_card *card,
  3991. struct qdio_buffer **in_sbal_ptrs,
  3992. void (**queue_start_poll) (struct ccw_device *, int, unsigned long)) {
  3993. int i;
  3994. if (card->options.cq == QETH_CQ_ENABLED) {
  3995. int offset = QDIO_MAX_BUFFERS_PER_Q *
  3996. (card->qdio.no_in_queues - 1);
  3997. i = QDIO_MAX_BUFFERS_PER_Q * (card->qdio.no_in_queues - 1);
  3998. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i) {
  3999. in_sbal_ptrs[offset + i] = (struct qdio_buffer *)
  4000. virt_to_phys(card->qdio.c_q->bufs[i].buffer);
  4001. }
  4002. queue_start_poll[card->qdio.no_in_queues - 1] = NULL;
  4003. }
  4004. }
  4005. static int qeth_qdio_establish(struct qeth_card *card)
  4006. {
  4007. struct qdio_initialize init_data;
  4008. char *qib_param_field;
  4009. struct qdio_buffer **in_sbal_ptrs;
  4010. void (**queue_start_poll) (struct ccw_device *, int, unsigned long);
  4011. struct qdio_buffer **out_sbal_ptrs;
  4012. int i, j, k;
  4013. int rc = 0;
  4014. QETH_DBF_TEXT(SETUP, 2, "qdioest");
  4015. qib_param_field = kzalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(char),
  4016. GFP_KERNEL);
  4017. if (!qib_param_field) {
  4018. rc = -ENOMEM;
  4019. goto out_free_nothing;
  4020. }
  4021. qeth_create_qib_param_field(card, qib_param_field);
  4022. qeth_create_qib_param_field_blkt(card, qib_param_field);
  4023. in_sbal_ptrs = kzalloc(card->qdio.no_in_queues *
  4024. QDIO_MAX_BUFFERS_PER_Q * sizeof(void *),
  4025. GFP_KERNEL);
  4026. if (!in_sbal_ptrs) {
  4027. rc = -ENOMEM;
  4028. goto out_free_qib_param;
  4029. }
  4030. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i) {
  4031. in_sbal_ptrs[i] = (struct qdio_buffer *)
  4032. virt_to_phys(card->qdio.in_q->bufs[i].buffer);
  4033. }
  4034. queue_start_poll = kzalloc(sizeof(void *) * card->qdio.no_in_queues,
  4035. GFP_KERNEL);
  4036. if (!queue_start_poll) {
  4037. rc = -ENOMEM;
  4038. goto out_free_in_sbals;
  4039. }
  4040. for (i = 0; i < card->qdio.no_in_queues; ++i)
  4041. queue_start_poll[i] = card->discipline.start_poll;
  4042. qeth_qdio_establish_cq(card, in_sbal_ptrs, queue_start_poll);
  4043. out_sbal_ptrs =
  4044. kzalloc(card->qdio.no_out_queues * QDIO_MAX_BUFFERS_PER_Q *
  4045. sizeof(void *), GFP_KERNEL);
  4046. if (!out_sbal_ptrs) {
  4047. rc = -ENOMEM;
  4048. goto out_free_queue_start_poll;
  4049. }
  4050. for (i = 0, k = 0; i < card->qdio.no_out_queues; ++i)
  4051. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j, ++k) {
  4052. out_sbal_ptrs[k] = (struct qdio_buffer *)virt_to_phys(
  4053. card->qdio.out_qs[i]->bufs[j]->buffer);
  4054. }
  4055. memset(&init_data, 0, sizeof(struct qdio_initialize));
  4056. init_data.cdev = CARD_DDEV(card);
  4057. init_data.q_format = qeth_get_qdio_q_format(card);
  4058. init_data.qib_param_field_format = 0;
  4059. init_data.qib_param_field = qib_param_field;
  4060. init_data.no_input_qs = card->qdio.no_in_queues;
  4061. init_data.no_output_qs = card->qdio.no_out_queues;
  4062. init_data.input_handler = card->discipline.input_handler;
  4063. init_data.output_handler = card->discipline.output_handler;
  4064. init_data.queue_start_poll_array = queue_start_poll;
  4065. init_data.int_parm = (unsigned long) card;
  4066. init_data.input_sbal_addr_array = (void **) in_sbal_ptrs;
  4067. init_data.output_sbal_addr_array = (void **) out_sbal_ptrs;
  4068. init_data.output_sbal_state_array = card->qdio.out_bufstates;
  4069. init_data.scan_threshold =
  4070. (card->info.type == QETH_CARD_TYPE_IQD) ? 8 : 32;
  4071. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ALLOCATED,
  4072. QETH_QDIO_ESTABLISHED) == QETH_QDIO_ALLOCATED) {
  4073. rc = qdio_allocate(&init_data);
  4074. if (rc) {
  4075. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  4076. goto out;
  4077. }
  4078. rc = qdio_establish(&init_data);
  4079. if (rc) {
  4080. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  4081. qdio_free(CARD_DDEV(card));
  4082. }
  4083. }
  4084. switch (card->options.cq) {
  4085. case QETH_CQ_ENABLED:
  4086. dev_info(&card->gdev->dev, "Completion Queue support enabled");
  4087. break;
  4088. case QETH_CQ_DISABLED:
  4089. dev_info(&card->gdev->dev, "Completion Queue support disabled");
  4090. break;
  4091. default:
  4092. break;
  4093. }
  4094. out:
  4095. kfree(out_sbal_ptrs);
  4096. out_free_queue_start_poll:
  4097. kfree(queue_start_poll);
  4098. out_free_in_sbals:
  4099. kfree(in_sbal_ptrs);
  4100. out_free_qib_param:
  4101. kfree(qib_param_field);
  4102. out_free_nothing:
  4103. return rc;
  4104. }
  4105. static void qeth_core_free_card(struct qeth_card *card)
  4106. {
  4107. QETH_DBF_TEXT(SETUP, 2, "freecrd");
  4108. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  4109. qeth_clean_channel(&card->read);
  4110. qeth_clean_channel(&card->write);
  4111. if (card->dev)
  4112. free_netdev(card->dev);
  4113. kfree(card->ip_tbd_list);
  4114. qeth_free_qdio_buffers(card);
  4115. unregister_service_level(&card->qeth_service_level);
  4116. kfree(card);
  4117. }
  4118. static struct ccw_device_id qeth_ids[] = {
  4119. {CCW_DEVICE_DEVTYPE(0x1731, 0x01, 0x1732, 0x01),
  4120. .driver_info = QETH_CARD_TYPE_OSD},
  4121. {CCW_DEVICE_DEVTYPE(0x1731, 0x05, 0x1732, 0x05),
  4122. .driver_info = QETH_CARD_TYPE_IQD},
  4123. {CCW_DEVICE_DEVTYPE(0x1731, 0x06, 0x1732, 0x06),
  4124. .driver_info = QETH_CARD_TYPE_OSN},
  4125. {CCW_DEVICE_DEVTYPE(0x1731, 0x02, 0x1732, 0x03),
  4126. .driver_info = QETH_CARD_TYPE_OSM},
  4127. {CCW_DEVICE_DEVTYPE(0x1731, 0x02, 0x1732, 0x02),
  4128. .driver_info = QETH_CARD_TYPE_OSX},
  4129. {},
  4130. };
  4131. MODULE_DEVICE_TABLE(ccw, qeth_ids);
  4132. static struct ccw_driver qeth_ccw_driver = {
  4133. .driver = {
  4134. .owner = THIS_MODULE,
  4135. .name = "qeth",
  4136. },
  4137. .ids = qeth_ids,
  4138. .probe = ccwgroup_probe_ccwdev,
  4139. .remove = ccwgroup_remove_ccwdev,
  4140. };
  4141. static int qeth_core_driver_group(const char *buf, struct device *root_dev,
  4142. unsigned long driver_id)
  4143. {
  4144. return ccwgroup_create_from_string(root_dev, driver_id,
  4145. &qeth_ccw_driver, 3, buf);
  4146. }
  4147. int qeth_core_hardsetup_card(struct qeth_card *card)
  4148. {
  4149. int retries = 0;
  4150. int rc;
  4151. QETH_DBF_TEXT(SETUP, 2, "hrdsetup");
  4152. atomic_set(&card->force_alloc_skb, 0);
  4153. qeth_get_channel_path_desc(card);
  4154. retry:
  4155. if (retries)
  4156. QETH_DBF_MESSAGE(2, "%s Retrying to do IDX activates.\n",
  4157. dev_name(&card->gdev->dev));
  4158. ccw_device_set_offline(CARD_DDEV(card));
  4159. ccw_device_set_offline(CARD_WDEV(card));
  4160. ccw_device_set_offline(CARD_RDEV(card));
  4161. rc = ccw_device_set_online(CARD_RDEV(card));
  4162. if (rc)
  4163. goto retriable;
  4164. rc = ccw_device_set_online(CARD_WDEV(card));
  4165. if (rc)
  4166. goto retriable;
  4167. rc = ccw_device_set_online(CARD_DDEV(card));
  4168. if (rc)
  4169. goto retriable;
  4170. rc = qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  4171. retriable:
  4172. if (rc == -ERESTARTSYS) {
  4173. QETH_DBF_TEXT(SETUP, 2, "break1");
  4174. return rc;
  4175. } else if (rc) {
  4176. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  4177. if (++retries > 3)
  4178. goto out;
  4179. else
  4180. goto retry;
  4181. }
  4182. qeth_determine_capabilities(card);
  4183. qeth_init_tokens(card);
  4184. qeth_init_func_level(card);
  4185. rc = qeth_idx_activate_channel(&card->read, qeth_idx_read_cb);
  4186. if (rc == -ERESTARTSYS) {
  4187. QETH_DBF_TEXT(SETUP, 2, "break2");
  4188. return rc;
  4189. } else if (rc) {
  4190. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  4191. if (--retries < 0)
  4192. goto out;
  4193. else
  4194. goto retry;
  4195. }
  4196. rc = qeth_idx_activate_channel(&card->write, qeth_idx_write_cb);
  4197. if (rc == -ERESTARTSYS) {
  4198. QETH_DBF_TEXT(SETUP, 2, "break3");
  4199. return rc;
  4200. } else if (rc) {
  4201. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  4202. if (--retries < 0)
  4203. goto out;
  4204. else
  4205. goto retry;
  4206. }
  4207. card->read_or_write_problem = 0;
  4208. rc = qeth_mpc_initialize(card);
  4209. if (rc) {
  4210. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  4211. goto out;
  4212. }
  4213. card->options.ipa4.supported_funcs = 0;
  4214. card->options.adp.supported_funcs = 0;
  4215. card->info.diagass_support = 0;
  4216. qeth_query_ipassists(card, QETH_PROT_IPV4);
  4217. if (qeth_is_supported(card, IPA_SETADAPTERPARMS))
  4218. qeth_query_setadapterparms(card);
  4219. if (qeth_adp_supported(card, IPA_SETADP_SET_DIAG_ASSIST))
  4220. qeth_query_setdiagass(card);
  4221. return 0;
  4222. out:
  4223. dev_warn(&card->gdev->dev, "The qeth device driver failed to recover "
  4224. "an error on the device\n");
  4225. QETH_DBF_MESSAGE(2, "%s Initialization in hardsetup failed! rc=%d\n",
  4226. dev_name(&card->gdev->dev), rc);
  4227. return rc;
  4228. }
  4229. EXPORT_SYMBOL_GPL(qeth_core_hardsetup_card);
  4230. static inline int qeth_create_skb_frag(struct qeth_qdio_buffer *qethbuffer,
  4231. struct qdio_buffer_element *element,
  4232. struct sk_buff **pskb, int offset, int *pfrag, int data_len)
  4233. {
  4234. struct page *page = virt_to_page(element->addr);
  4235. if (*pskb == NULL) {
  4236. if (qethbuffer->rx_skb) {
  4237. /* only if qeth_card.options.cq == QETH_CQ_ENABLED */
  4238. *pskb = qethbuffer->rx_skb;
  4239. qethbuffer->rx_skb = NULL;
  4240. } else {
  4241. *pskb = dev_alloc_skb(QETH_RX_PULL_LEN + ETH_HLEN);
  4242. if (!(*pskb))
  4243. return -ENOMEM;
  4244. }
  4245. skb_reserve(*pskb, ETH_HLEN);
  4246. if (data_len <= QETH_RX_PULL_LEN) {
  4247. memcpy(skb_put(*pskb, data_len), element->addr + offset,
  4248. data_len);
  4249. } else {
  4250. get_page(page);
  4251. memcpy(skb_put(*pskb, QETH_RX_PULL_LEN),
  4252. element->addr + offset, QETH_RX_PULL_LEN);
  4253. skb_fill_page_desc(*pskb, *pfrag, page,
  4254. offset + QETH_RX_PULL_LEN,
  4255. data_len - QETH_RX_PULL_LEN);
  4256. (*pskb)->data_len += data_len - QETH_RX_PULL_LEN;
  4257. (*pskb)->len += data_len - QETH_RX_PULL_LEN;
  4258. (*pskb)->truesize += data_len - QETH_RX_PULL_LEN;
  4259. (*pfrag)++;
  4260. }
  4261. } else {
  4262. get_page(page);
  4263. skb_fill_page_desc(*pskb, *pfrag, page, offset, data_len);
  4264. (*pskb)->data_len += data_len;
  4265. (*pskb)->len += data_len;
  4266. (*pskb)->truesize += data_len;
  4267. (*pfrag)++;
  4268. }
  4269. return 0;
  4270. }
  4271. struct sk_buff *qeth_core_get_next_skb(struct qeth_card *card,
  4272. struct qeth_qdio_buffer *qethbuffer,
  4273. struct qdio_buffer_element **__element, int *__offset,
  4274. struct qeth_hdr **hdr)
  4275. {
  4276. struct qdio_buffer_element *element = *__element;
  4277. struct qdio_buffer *buffer = qethbuffer->buffer;
  4278. int offset = *__offset;
  4279. struct sk_buff *skb = NULL;
  4280. int skb_len = 0;
  4281. void *data_ptr;
  4282. int data_len;
  4283. int headroom = 0;
  4284. int use_rx_sg = 0;
  4285. int frag = 0;
  4286. /* qeth_hdr must not cross element boundaries */
  4287. if (element->length < offset + sizeof(struct qeth_hdr)) {
  4288. if (qeth_is_last_sbale(element))
  4289. return NULL;
  4290. element++;
  4291. offset = 0;
  4292. if (element->length < sizeof(struct qeth_hdr))
  4293. return NULL;
  4294. }
  4295. *hdr = element->addr + offset;
  4296. offset += sizeof(struct qeth_hdr);
  4297. switch ((*hdr)->hdr.l2.id) {
  4298. case QETH_HEADER_TYPE_LAYER2:
  4299. skb_len = (*hdr)->hdr.l2.pkt_length;
  4300. break;
  4301. case QETH_HEADER_TYPE_LAYER3:
  4302. skb_len = (*hdr)->hdr.l3.length;
  4303. if ((card->info.link_type == QETH_LINK_TYPE_LANE_TR) ||
  4304. (card->info.link_type == QETH_LINK_TYPE_HSTR))
  4305. headroom = TR_HLEN;
  4306. else
  4307. headroom = ETH_HLEN;
  4308. break;
  4309. case QETH_HEADER_TYPE_OSN:
  4310. skb_len = (*hdr)->hdr.osn.pdu_length;
  4311. headroom = sizeof(struct qeth_hdr);
  4312. break;
  4313. default:
  4314. break;
  4315. }
  4316. if (!skb_len)
  4317. return NULL;
  4318. if (((skb_len >= card->options.rx_sg_cb) &&
  4319. (!(card->info.type == QETH_CARD_TYPE_OSN)) &&
  4320. (!atomic_read(&card->force_alloc_skb))) ||
  4321. (card->options.cq == QETH_CQ_ENABLED)) {
  4322. use_rx_sg = 1;
  4323. } else {
  4324. skb = dev_alloc_skb(skb_len + headroom);
  4325. if (!skb)
  4326. goto no_mem;
  4327. if (headroom)
  4328. skb_reserve(skb, headroom);
  4329. }
  4330. data_ptr = element->addr + offset;
  4331. while (skb_len) {
  4332. data_len = min(skb_len, (int)(element->length - offset));
  4333. if (data_len) {
  4334. if (use_rx_sg) {
  4335. if (qeth_create_skb_frag(qethbuffer, element,
  4336. &skb, offset, &frag, data_len))
  4337. goto no_mem;
  4338. } else {
  4339. memcpy(skb_put(skb, data_len), data_ptr,
  4340. data_len);
  4341. }
  4342. }
  4343. skb_len -= data_len;
  4344. if (skb_len) {
  4345. if (qeth_is_last_sbale(element)) {
  4346. QETH_CARD_TEXT(card, 4, "unexeob");
  4347. QETH_CARD_HEX(card, 2, buffer, sizeof(void *));
  4348. dev_kfree_skb_any(skb);
  4349. card->stats.rx_errors++;
  4350. return NULL;
  4351. }
  4352. element++;
  4353. offset = 0;
  4354. data_ptr = element->addr;
  4355. } else {
  4356. offset += data_len;
  4357. }
  4358. }
  4359. *__element = element;
  4360. *__offset = offset;
  4361. if (use_rx_sg && card->options.performance_stats) {
  4362. card->perf_stats.sg_skbs_rx++;
  4363. card->perf_stats.sg_frags_rx += skb_shinfo(skb)->nr_frags;
  4364. }
  4365. return skb;
  4366. no_mem:
  4367. if (net_ratelimit()) {
  4368. QETH_CARD_TEXT(card, 2, "noskbmem");
  4369. }
  4370. card->stats.rx_dropped++;
  4371. return NULL;
  4372. }
  4373. EXPORT_SYMBOL_GPL(qeth_core_get_next_skb);
  4374. static void qeth_unregister_dbf_views(void)
  4375. {
  4376. int x;
  4377. for (x = 0; x < QETH_DBF_INFOS; x++) {
  4378. debug_unregister(qeth_dbf[x].id);
  4379. qeth_dbf[x].id = NULL;
  4380. }
  4381. }
  4382. void qeth_dbf_longtext(debug_info_t *id, int level, char *fmt, ...)
  4383. {
  4384. char dbf_txt_buf[32];
  4385. va_list args;
  4386. if (level > id->level)
  4387. return;
  4388. va_start(args, fmt);
  4389. vsnprintf(dbf_txt_buf, sizeof(dbf_txt_buf), fmt, args);
  4390. va_end(args);
  4391. debug_text_event(id, level, dbf_txt_buf);
  4392. }
  4393. EXPORT_SYMBOL_GPL(qeth_dbf_longtext);
  4394. static int qeth_register_dbf_views(void)
  4395. {
  4396. int ret;
  4397. int x;
  4398. for (x = 0; x < QETH_DBF_INFOS; x++) {
  4399. /* register the areas */
  4400. qeth_dbf[x].id = debug_register(qeth_dbf[x].name,
  4401. qeth_dbf[x].pages,
  4402. qeth_dbf[x].areas,
  4403. qeth_dbf[x].len);
  4404. if (qeth_dbf[x].id == NULL) {
  4405. qeth_unregister_dbf_views();
  4406. return -ENOMEM;
  4407. }
  4408. /* register a view */
  4409. ret = debug_register_view(qeth_dbf[x].id, qeth_dbf[x].view);
  4410. if (ret) {
  4411. qeth_unregister_dbf_views();
  4412. return ret;
  4413. }
  4414. /* set a passing level */
  4415. debug_set_level(qeth_dbf[x].id, qeth_dbf[x].level);
  4416. }
  4417. return 0;
  4418. }
  4419. int qeth_core_load_discipline(struct qeth_card *card,
  4420. enum qeth_discipline_id discipline)
  4421. {
  4422. int rc = 0;
  4423. switch (discipline) {
  4424. case QETH_DISCIPLINE_LAYER3:
  4425. card->discipline.ccwgdriver = try_then_request_module(
  4426. symbol_get(qeth_l3_ccwgroup_driver),
  4427. "qeth_l3");
  4428. break;
  4429. case QETH_DISCIPLINE_LAYER2:
  4430. card->discipline.ccwgdriver = try_then_request_module(
  4431. symbol_get(qeth_l2_ccwgroup_driver),
  4432. "qeth_l2");
  4433. break;
  4434. }
  4435. if (!card->discipline.ccwgdriver) {
  4436. dev_err(&card->gdev->dev, "There is no kernel module to "
  4437. "support discipline %d\n", discipline);
  4438. rc = -EINVAL;
  4439. }
  4440. return rc;
  4441. }
  4442. void qeth_core_free_discipline(struct qeth_card *card)
  4443. {
  4444. if (card->options.layer2)
  4445. symbol_put(qeth_l2_ccwgroup_driver);
  4446. else
  4447. symbol_put(qeth_l3_ccwgroup_driver);
  4448. card->discipline.ccwgdriver = NULL;
  4449. }
  4450. static int qeth_core_probe_device(struct ccwgroup_device *gdev)
  4451. {
  4452. struct qeth_card *card;
  4453. struct device *dev;
  4454. int rc;
  4455. unsigned long flags;
  4456. char dbf_name[20];
  4457. QETH_DBF_TEXT(SETUP, 2, "probedev");
  4458. dev = &gdev->dev;
  4459. if (!get_device(dev))
  4460. return -ENODEV;
  4461. QETH_DBF_TEXT_(SETUP, 2, "%s", dev_name(&gdev->dev));
  4462. card = qeth_alloc_card();
  4463. if (!card) {
  4464. QETH_DBF_TEXT_(SETUP, 2, "1err%d", -ENOMEM);
  4465. rc = -ENOMEM;
  4466. goto err_dev;
  4467. }
  4468. snprintf(dbf_name, sizeof(dbf_name), "qeth_card_%s",
  4469. dev_name(&gdev->dev));
  4470. card->debug = debug_register(dbf_name, 2, 1, 8);
  4471. if (!card->debug) {
  4472. QETH_DBF_TEXT_(SETUP, 2, "%s", "qcdbf");
  4473. rc = -ENOMEM;
  4474. goto err_card;
  4475. }
  4476. debug_register_view(card->debug, &debug_hex_ascii_view);
  4477. card->read.ccwdev = gdev->cdev[0];
  4478. card->write.ccwdev = gdev->cdev[1];
  4479. card->data.ccwdev = gdev->cdev[2];
  4480. dev_set_drvdata(&gdev->dev, card);
  4481. card->gdev = gdev;
  4482. gdev->cdev[0]->handler = qeth_irq;
  4483. gdev->cdev[1]->handler = qeth_irq;
  4484. gdev->cdev[2]->handler = qeth_irq;
  4485. rc = qeth_determine_card_type(card);
  4486. if (rc) {
  4487. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  4488. goto err_dbf;
  4489. }
  4490. rc = qeth_setup_card(card);
  4491. if (rc) {
  4492. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  4493. goto err_dbf;
  4494. }
  4495. if (card->info.type == QETH_CARD_TYPE_OSN)
  4496. rc = qeth_core_create_osn_attributes(dev);
  4497. else
  4498. rc = qeth_core_create_device_attributes(dev);
  4499. if (rc)
  4500. goto err_dbf;
  4501. switch (card->info.type) {
  4502. case QETH_CARD_TYPE_OSN:
  4503. case QETH_CARD_TYPE_OSM:
  4504. rc = qeth_core_load_discipline(card, QETH_DISCIPLINE_LAYER2);
  4505. if (rc)
  4506. goto err_attr;
  4507. rc = card->discipline.ccwgdriver->probe(card->gdev);
  4508. if (rc)
  4509. goto err_disc;
  4510. case QETH_CARD_TYPE_OSD:
  4511. case QETH_CARD_TYPE_OSX:
  4512. default:
  4513. break;
  4514. }
  4515. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  4516. list_add_tail(&card->list, &qeth_core_card_list.list);
  4517. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  4518. qeth_determine_capabilities(card);
  4519. return 0;
  4520. err_disc:
  4521. qeth_core_free_discipline(card);
  4522. err_attr:
  4523. if (card->info.type == QETH_CARD_TYPE_OSN)
  4524. qeth_core_remove_osn_attributes(dev);
  4525. else
  4526. qeth_core_remove_device_attributes(dev);
  4527. err_dbf:
  4528. debug_unregister(card->debug);
  4529. err_card:
  4530. qeth_core_free_card(card);
  4531. err_dev:
  4532. put_device(dev);
  4533. return rc;
  4534. }
  4535. static void qeth_core_remove_device(struct ccwgroup_device *gdev)
  4536. {
  4537. unsigned long flags;
  4538. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4539. QETH_DBF_TEXT(SETUP, 2, "removedv");
  4540. if (card->info.type == QETH_CARD_TYPE_OSN) {
  4541. qeth_core_remove_osn_attributes(&gdev->dev);
  4542. } else {
  4543. qeth_core_remove_device_attributes(&gdev->dev);
  4544. }
  4545. if (card->discipline.ccwgdriver) {
  4546. card->discipline.ccwgdriver->remove(gdev);
  4547. qeth_core_free_discipline(card);
  4548. }
  4549. debug_unregister(card->debug);
  4550. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  4551. list_del(&card->list);
  4552. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  4553. qeth_core_free_card(card);
  4554. dev_set_drvdata(&gdev->dev, NULL);
  4555. put_device(&gdev->dev);
  4556. return;
  4557. }
  4558. static int qeth_core_set_online(struct ccwgroup_device *gdev)
  4559. {
  4560. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4561. int rc = 0;
  4562. int def_discipline;
  4563. if (!card->discipline.ccwgdriver) {
  4564. if (card->info.type == QETH_CARD_TYPE_IQD)
  4565. def_discipline = QETH_DISCIPLINE_LAYER3;
  4566. else
  4567. def_discipline = QETH_DISCIPLINE_LAYER2;
  4568. rc = qeth_core_load_discipline(card, def_discipline);
  4569. if (rc)
  4570. goto err;
  4571. rc = card->discipline.ccwgdriver->probe(card->gdev);
  4572. if (rc)
  4573. goto err;
  4574. }
  4575. rc = card->discipline.ccwgdriver->set_online(gdev);
  4576. err:
  4577. return rc;
  4578. }
  4579. static int qeth_core_set_offline(struct ccwgroup_device *gdev)
  4580. {
  4581. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4582. return card->discipline.ccwgdriver->set_offline(gdev);
  4583. }
  4584. static void qeth_core_shutdown(struct ccwgroup_device *gdev)
  4585. {
  4586. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4587. if (card->discipline.ccwgdriver &&
  4588. card->discipline.ccwgdriver->shutdown)
  4589. card->discipline.ccwgdriver->shutdown(gdev);
  4590. }
  4591. static int qeth_core_prepare(struct ccwgroup_device *gdev)
  4592. {
  4593. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4594. if (card->discipline.ccwgdriver &&
  4595. card->discipline.ccwgdriver->prepare)
  4596. return card->discipline.ccwgdriver->prepare(gdev);
  4597. return 0;
  4598. }
  4599. static void qeth_core_complete(struct ccwgroup_device *gdev)
  4600. {
  4601. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4602. if (card->discipline.ccwgdriver &&
  4603. card->discipline.ccwgdriver->complete)
  4604. card->discipline.ccwgdriver->complete(gdev);
  4605. }
  4606. static int qeth_core_freeze(struct ccwgroup_device *gdev)
  4607. {
  4608. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4609. if (card->discipline.ccwgdriver &&
  4610. card->discipline.ccwgdriver->freeze)
  4611. return card->discipline.ccwgdriver->freeze(gdev);
  4612. return 0;
  4613. }
  4614. static int qeth_core_thaw(struct ccwgroup_device *gdev)
  4615. {
  4616. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4617. if (card->discipline.ccwgdriver &&
  4618. card->discipline.ccwgdriver->thaw)
  4619. return card->discipline.ccwgdriver->thaw(gdev);
  4620. return 0;
  4621. }
  4622. static int qeth_core_restore(struct ccwgroup_device *gdev)
  4623. {
  4624. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4625. if (card->discipline.ccwgdriver &&
  4626. card->discipline.ccwgdriver->restore)
  4627. return card->discipline.ccwgdriver->restore(gdev);
  4628. return 0;
  4629. }
  4630. static struct ccwgroup_driver qeth_core_ccwgroup_driver = {
  4631. .driver = {
  4632. .owner = THIS_MODULE,
  4633. .name = "qeth",
  4634. },
  4635. .driver_id = 0xD8C5E3C8,
  4636. .probe = qeth_core_probe_device,
  4637. .remove = qeth_core_remove_device,
  4638. .set_online = qeth_core_set_online,
  4639. .set_offline = qeth_core_set_offline,
  4640. .shutdown = qeth_core_shutdown,
  4641. .prepare = qeth_core_prepare,
  4642. .complete = qeth_core_complete,
  4643. .freeze = qeth_core_freeze,
  4644. .thaw = qeth_core_thaw,
  4645. .restore = qeth_core_restore,
  4646. };
  4647. static ssize_t
  4648. qeth_core_driver_group_store(struct device_driver *ddrv, const char *buf,
  4649. size_t count)
  4650. {
  4651. int err;
  4652. err = qeth_core_driver_group(buf, qeth_core_root_dev,
  4653. qeth_core_ccwgroup_driver.driver_id);
  4654. if (err)
  4655. return err;
  4656. else
  4657. return count;
  4658. }
  4659. static DRIVER_ATTR(group, 0200, NULL, qeth_core_driver_group_store);
  4660. static struct {
  4661. const char str[ETH_GSTRING_LEN];
  4662. } qeth_ethtool_stats_keys[] = {
  4663. /* 0 */{"rx skbs"},
  4664. {"rx buffers"},
  4665. {"tx skbs"},
  4666. {"tx buffers"},
  4667. {"tx skbs no packing"},
  4668. {"tx buffers no packing"},
  4669. {"tx skbs packing"},
  4670. {"tx buffers packing"},
  4671. {"tx sg skbs"},
  4672. {"tx sg frags"},
  4673. /* 10 */{"rx sg skbs"},
  4674. {"rx sg frags"},
  4675. {"rx sg page allocs"},
  4676. {"tx large kbytes"},
  4677. {"tx large count"},
  4678. {"tx pk state ch n->p"},
  4679. {"tx pk state ch p->n"},
  4680. {"tx pk watermark low"},
  4681. {"tx pk watermark high"},
  4682. {"queue 0 buffer usage"},
  4683. /* 20 */{"queue 1 buffer usage"},
  4684. {"queue 2 buffer usage"},
  4685. {"queue 3 buffer usage"},
  4686. {"rx poll time"},
  4687. {"rx poll count"},
  4688. {"rx do_QDIO time"},
  4689. {"rx do_QDIO count"},
  4690. {"tx handler time"},
  4691. {"tx handler count"},
  4692. {"tx time"},
  4693. /* 30 */{"tx count"},
  4694. {"tx do_QDIO time"},
  4695. {"tx do_QDIO count"},
  4696. {"tx csum"},
  4697. {"tx lin"},
  4698. {"cq handler count"},
  4699. {"cq handler time"}
  4700. };
  4701. int qeth_core_get_sset_count(struct net_device *dev, int stringset)
  4702. {
  4703. switch (stringset) {
  4704. case ETH_SS_STATS:
  4705. return (sizeof(qeth_ethtool_stats_keys) / ETH_GSTRING_LEN);
  4706. default:
  4707. return -EINVAL;
  4708. }
  4709. }
  4710. EXPORT_SYMBOL_GPL(qeth_core_get_sset_count);
  4711. void qeth_core_get_ethtool_stats(struct net_device *dev,
  4712. struct ethtool_stats *stats, u64 *data)
  4713. {
  4714. struct qeth_card *card = dev->ml_priv;
  4715. data[0] = card->stats.rx_packets -
  4716. card->perf_stats.initial_rx_packets;
  4717. data[1] = card->perf_stats.bufs_rec;
  4718. data[2] = card->stats.tx_packets -
  4719. card->perf_stats.initial_tx_packets;
  4720. data[3] = card->perf_stats.bufs_sent;
  4721. data[4] = card->stats.tx_packets - card->perf_stats.initial_tx_packets
  4722. - card->perf_stats.skbs_sent_pack;
  4723. data[5] = card->perf_stats.bufs_sent - card->perf_stats.bufs_sent_pack;
  4724. data[6] = card->perf_stats.skbs_sent_pack;
  4725. data[7] = card->perf_stats.bufs_sent_pack;
  4726. data[8] = card->perf_stats.sg_skbs_sent;
  4727. data[9] = card->perf_stats.sg_frags_sent;
  4728. data[10] = card->perf_stats.sg_skbs_rx;
  4729. data[11] = card->perf_stats.sg_frags_rx;
  4730. data[12] = card->perf_stats.sg_alloc_page_rx;
  4731. data[13] = (card->perf_stats.large_send_bytes >> 10);
  4732. data[14] = card->perf_stats.large_send_cnt;
  4733. data[15] = card->perf_stats.sc_dp_p;
  4734. data[16] = card->perf_stats.sc_p_dp;
  4735. data[17] = QETH_LOW_WATERMARK_PACK;
  4736. data[18] = QETH_HIGH_WATERMARK_PACK;
  4737. data[19] = atomic_read(&card->qdio.out_qs[0]->used_buffers);
  4738. data[20] = (card->qdio.no_out_queues > 1) ?
  4739. atomic_read(&card->qdio.out_qs[1]->used_buffers) : 0;
  4740. data[21] = (card->qdio.no_out_queues > 2) ?
  4741. atomic_read(&card->qdio.out_qs[2]->used_buffers) : 0;
  4742. data[22] = (card->qdio.no_out_queues > 3) ?
  4743. atomic_read(&card->qdio.out_qs[3]->used_buffers) : 0;
  4744. data[23] = card->perf_stats.inbound_time;
  4745. data[24] = card->perf_stats.inbound_cnt;
  4746. data[25] = card->perf_stats.inbound_do_qdio_time;
  4747. data[26] = card->perf_stats.inbound_do_qdio_cnt;
  4748. data[27] = card->perf_stats.outbound_handler_time;
  4749. data[28] = card->perf_stats.outbound_handler_cnt;
  4750. data[29] = card->perf_stats.outbound_time;
  4751. data[30] = card->perf_stats.outbound_cnt;
  4752. data[31] = card->perf_stats.outbound_do_qdio_time;
  4753. data[32] = card->perf_stats.outbound_do_qdio_cnt;
  4754. data[33] = card->perf_stats.tx_csum;
  4755. data[34] = card->perf_stats.tx_lin;
  4756. data[35] = card->perf_stats.cq_cnt;
  4757. data[36] = card->perf_stats.cq_time;
  4758. }
  4759. EXPORT_SYMBOL_GPL(qeth_core_get_ethtool_stats);
  4760. void qeth_core_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  4761. {
  4762. switch (stringset) {
  4763. case ETH_SS_STATS:
  4764. memcpy(data, &qeth_ethtool_stats_keys,
  4765. sizeof(qeth_ethtool_stats_keys));
  4766. break;
  4767. default:
  4768. WARN_ON(1);
  4769. break;
  4770. }
  4771. }
  4772. EXPORT_SYMBOL_GPL(qeth_core_get_strings);
  4773. void qeth_core_get_drvinfo(struct net_device *dev,
  4774. struct ethtool_drvinfo *info)
  4775. {
  4776. struct qeth_card *card = dev->ml_priv;
  4777. if (card->options.layer2)
  4778. strcpy(info->driver, "qeth_l2");
  4779. else
  4780. strcpy(info->driver, "qeth_l3");
  4781. strcpy(info->version, "1.0");
  4782. strcpy(info->fw_version, card->info.mcl_level);
  4783. sprintf(info->bus_info, "%s/%s/%s",
  4784. CARD_RDEV_ID(card),
  4785. CARD_WDEV_ID(card),
  4786. CARD_DDEV_ID(card));
  4787. }
  4788. EXPORT_SYMBOL_GPL(qeth_core_get_drvinfo);
  4789. int qeth_core_ethtool_get_settings(struct net_device *netdev,
  4790. struct ethtool_cmd *ecmd)
  4791. {
  4792. struct qeth_card *card = netdev->ml_priv;
  4793. enum qeth_link_types link_type;
  4794. if ((card->info.type == QETH_CARD_TYPE_IQD) || (card->info.guestlan))
  4795. link_type = QETH_LINK_TYPE_10GBIT_ETH;
  4796. else
  4797. link_type = card->info.link_type;
  4798. ecmd->transceiver = XCVR_INTERNAL;
  4799. ecmd->supported = SUPPORTED_Autoneg;
  4800. ecmd->advertising = ADVERTISED_Autoneg;
  4801. ecmd->duplex = DUPLEX_FULL;
  4802. ecmd->autoneg = AUTONEG_ENABLE;
  4803. switch (link_type) {
  4804. case QETH_LINK_TYPE_FAST_ETH:
  4805. case QETH_LINK_TYPE_LANE_ETH100:
  4806. ecmd->supported |= SUPPORTED_10baseT_Half |
  4807. SUPPORTED_10baseT_Full |
  4808. SUPPORTED_100baseT_Half |
  4809. SUPPORTED_100baseT_Full |
  4810. SUPPORTED_TP;
  4811. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4812. ADVERTISED_10baseT_Full |
  4813. ADVERTISED_100baseT_Half |
  4814. ADVERTISED_100baseT_Full |
  4815. ADVERTISED_TP;
  4816. ecmd->speed = SPEED_100;
  4817. ecmd->port = PORT_TP;
  4818. break;
  4819. case QETH_LINK_TYPE_GBIT_ETH:
  4820. case QETH_LINK_TYPE_LANE_ETH1000:
  4821. ecmd->supported |= SUPPORTED_10baseT_Half |
  4822. SUPPORTED_10baseT_Full |
  4823. SUPPORTED_100baseT_Half |
  4824. SUPPORTED_100baseT_Full |
  4825. SUPPORTED_1000baseT_Half |
  4826. SUPPORTED_1000baseT_Full |
  4827. SUPPORTED_FIBRE;
  4828. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4829. ADVERTISED_10baseT_Full |
  4830. ADVERTISED_100baseT_Half |
  4831. ADVERTISED_100baseT_Full |
  4832. ADVERTISED_1000baseT_Half |
  4833. ADVERTISED_1000baseT_Full |
  4834. ADVERTISED_FIBRE;
  4835. ecmd->speed = SPEED_1000;
  4836. ecmd->port = PORT_FIBRE;
  4837. break;
  4838. case QETH_LINK_TYPE_10GBIT_ETH:
  4839. ecmd->supported |= SUPPORTED_10baseT_Half |
  4840. SUPPORTED_10baseT_Full |
  4841. SUPPORTED_100baseT_Half |
  4842. SUPPORTED_100baseT_Full |
  4843. SUPPORTED_1000baseT_Half |
  4844. SUPPORTED_1000baseT_Full |
  4845. SUPPORTED_10000baseT_Full |
  4846. SUPPORTED_FIBRE;
  4847. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4848. ADVERTISED_10baseT_Full |
  4849. ADVERTISED_100baseT_Half |
  4850. ADVERTISED_100baseT_Full |
  4851. ADVERTISED_1000baseT_Half |
  4852. ADVERTISED_1000baseT_Full |
  4853. ADVERTISED_10000baseT_Full |
  4854. ADVERTISED_FIBRE;
  4855. ecmd->speed = SPEED_10000;
  4856. ecmd->port = PORT_FIBRE;
  4857. break;
  4858. default:
  4859. ecmd->supported |= SUPPORTED_10baseT_Half |
  4860. SUPPORTED_10baseT_Full |
  4861. SUPPORTED_TP;
  4862. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4863. ADVERTISED_10baseT_Full |
  4864. ADVERTISED_TP;
  4865. ecmd->speed = SPEED_10;
  4866. ecmd->port = PORT_TP;
  4867. }
  4868. return 0;
  4869. }
  4870. EXPORT_SYMBOL_GPL(qeth_core_ethtool_get_settings);
  4871. static int __init qeth_core_init(void)
  4872. {
  4873. int rc;
  4874. pr_info("loading core functions\n");
  4875. INIT_LIST_HEAD(&qeth_core_card_list.list);
  4876. rwlock_init(&qeth_core_card_list.rwlock);
  4877. rc = qeth_register_dbf_views();
  4878. if (rc)
  4879. goto out_err;
  4880. rc = ccw_driver_register(&qeth_ccw_driver);
  4881. if (rc)
  4882. goto ccw_err;
  4883. rc = ccwgroup_driver_register(&qeth_core_ccwgroup_driver);
  4884. if (rc)
  4885. goto ccwgroup_err;
  4886. rc = driver_create_file(&qeth_core_ccwgroup_driver.driver,
  4887. &driver_attr_group);
  4888. if (rc)
  4889. goto driver_err;
  4890. qeth_core_root_dev = root_device_register("qeth");
  4891. rc = IS_ERR(qeth_core_root_dev) ? PTR_ERR(qeth_core_root_dev) : 0;
  4892. if (rc)
  4893. goto register_err;
  4894. qeth_core_header_cache = kmem_cache_create("qeth_hdr",
  4895. sizeof(struct qeth_hdr) + ETH_HLEN, 64, 0, NULL);
  4896. if (!qeth_core_header_cache) {
  4897. rc = -ENOMEM;
  4898. goto slab_err;
  4899. }
  4900. qeth_qdio_outbuf_cache = kmem_cache_create("qeth_buf",
  4901. sizeof(struct qeth_qdio_out_buffer), 0, 0, NULL);
  4902. if (!qeth_qdio_outbuf_cache) {
  4903. rc = -ENOMEM;
  4904. goto cqslab_err;
  4905. }
  4906. return 0;
  4907. cqslab_err:
  4908. kmem_cache_destroy(qeth_core_header_cache);
  4909. slab_err:
  4910. root_device_unregister(qeth_core_root_dev);
  4911. register_err:
  4912. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4913. &driver_attr_group);
  4914. driver_err:
  4915. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4916. ccwgroup_err:
  4917. ccw_driver_unregister(&qeth_ccw_driver);
  4918. ccw_err:
  4919. QETH_DBF_MESSAGE(2, "Initialization failed with code %d\n", rc);
  4920. qeth_unregister_dbf_views();
  4921. out_err:
  4922. pr_err("Initializing the qeth device driver failed\n");
  4923. return rc;
  4924. }
  4925. static void __exit qeth_core_exit(void)
  4926. {
  4927. root_device_unregister(qeth_core_root_dev);
  4928. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4929. &driver_attr_group);
  4930. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4931. ccw_driver_unregister(&qeth_ccw_driver);
  4932. kmem_cache_destroy(qeth_qdio_outbuf_cache);
  4933. kmem_cache_destroy(qeth_core_header_cache);
  4934. qeth_unregister_dbf_views();
  4935. pr_info("core functions removed\n");
  4936. }
  4937. module_init(qeth_core_init);
  4938. module_exit(qeth_core_exit);
  4939. MODULE_AUTHOR("Frank Blaschka <frank.blaschka@de.ibm.com>");
  4940. MODULE_DESCRIPTION("qeth core functions");
  4941. MODULE_LICENSE("GPL");