iwl-ucode.c 21 KB

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  1. /******************************************************************************
  2. *
  3. * GPL LICENSE SUMMARY
  4. *
  5. * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of version 2 of the GNU General Public License as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14. * General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  19. * USA
  20. *
  21. * The full GNU General Public License is included in this distribution
  22. * in the file called LICENSE.GPL.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/sched.h>
  33. #include <linux/dma-mapping.h>
  34. #include "iwl-wifi.h"
  35. #include "iwl-dev.h"
  36. #include "iwl-core.h"
  37. #include "iwl-io.h"
  38. #include "iwl-agn-hw.h"
  39. #include "iwl-agn.h"
  40. #include "iwl-agn-calib.h"
  41. #include "iwl-trans.h"
  42. #include "iwl-fh.h"
  43. static struct iwl_wimax_coex_event_entry cu_priorities[COEX_NUM_OF_EVENTS] = {
  44. {COEX_CU_UNASSOC_IDLE_RP, COEX_CU_UNASSOC_IDLE_WP,
  45. 0, COEX_UNASSOC_IDLE_FLAGS},
  46. {COEX_CU_UNASSOC_MANUAL_SCAN_RP, COEX_CU_UNASSOC_MANUAL_SCAN_WP,
  47. 0, COEX_UNASSOC_MANUAL_SCAN_FLAGS},
  48. {COEX_CU_UNASSOC_AUTO_SCAN_RP, COEX_CU_UNASSOC_AUTO_SCAN_WP,
  49. 0, COEX_UNASSOC_AUTO_SCAN_FLAGS},
  50. {COEX_CU_CALIBRATION_RP, COEX_CU_CALIBRATION_WP,
  51. 0, COEX_CALIBRATION_FLAGS},
  52. {COEX_CU_PERIODIC_CALIBRATION_RP, COEX_CU_PERIODIC_CALIBRATION_WP,
  53. 0, COEX_PERIODIC_CALIBRATION_FLAGS},
  54. {COEX_CU_CONNECTION_ESTAB_RP, COEX_CU_CONNECTION_ESTAB_WP,
  55. 0, COEX_CONNECTION_ESTAB_FLAGS},
  56. {COEX_CU_ASSOCIATED_IDLE_RP, COEX_CU_ASSOCIATED_IDLE_WP,
  57. 0, COEX_ASSOCIATED_IDLE_FLAGS},
  58. {COEX_CU_ASSOC_MANUAL_SCAN_RP, COEX_CU_ASSOC_MANUAL_SCAN_WP,
  59. 0, COEX_ASSOC_MANUAL_SCAN_FLAGS},
  60. {COEX_CU_ASSOC_AUTO_SCAN_RP, COEX_CU_ASSOC_AUTO_SCAN_WP,
  61. 0, COEX_ASSOC_AUTO_SCAN_FLAGS},
  62. {COEX_CU_ASSOC_ACTIVE_LEVEL_RP, COEX_CU_ASSOC_ACTIVE_LEVEL_WP,
  63. 0, COEX_ASSOC_ACTIVE_LEVEL_FLAGS},
  64. {COEX_CU_RF_ON_RP, COEX_CU_RF_ON_WP, 0, COEX_CU_RF_ON_FLAGS},
  65. {COEX_CU_RF_OFF_RP, COEX_CU_RF_OFF_WP, 0, COEX_RF_OFF_FLAGS},
  66. {COEX_CU_STAND_ALONE_DEBUG_RP, COEX_CU_STAND_ALONE_DEBUG_WP,
  67. 0, COEX_STAND_ALONE_DEBUG_FLAGS},
  68. {COEX_CU_IPAN_ASSOC_LEVEL_RP, COEX_CU_IPAN_ASSOC_LEVEL_WP,
  69. 0, COEX_IPAN_ASSOC_LEVEL_FLAGS},
  70. {COEX_CU_RSRVD1_RP, COEX_CU_RSRVD1_WP, 0, COEX_RSRVD1_FLAGS},
  71. {COEX_CU_RSRVD2_RP, COEX_CU_RSRVD2_WP, 0, COEX_RSRVD2_FLAGS}
  72. };
  73. /******************************************************************************
  74. *
  75. * uCode download functions
  76. *
  77. ******************************************************************************/
  78. static void iwl_free_fw_desc(struct iwl_bus *bus, struct fw_desc *desc)
  79. {
  80. if (desc->v_addr)
  81. dma_free_coherent(bus->dev, desc->len,
  82. desc->v_addr, desc->p_addr);
  83. desc->v_addr = NULL;
  84. desc->len = 0;
  85. }
  86. static void iwl_free_fw_img(struct iwl_bus *bus, struct fw_img *img)
  87. {
  88. iwl_free_fw_desc(bus, &img->code);
  89. iwl_free_fw_desc(bus, &img->data);
  90. }
  91. void iwl_dealloc_ucode(struct iwl_trans *trans)
  92. {
  93. iwl_free_fw_img(bus(trans), &trans->ucode_rt);
  94. iwl_free_fw_img(bus(trans), &trans->ucode_init);
  95. iwl_free_fw_img(bus(trans), &trans->ucode_wowlan);
  96. }
  97. int iwl_alloc_fw_desc(struct iwl_bus *bus, struct fw_desc *desc,
  98. const void *data, size_t len)
  99. {
  100. if (!len) {
  101. desc->v_addr = NULL;
  102. return -EINVAL;
  103. }
  104. desc->v_addr = dma_alloc_coherent(bus->dev, len,
  105. &desc->p_addr, GFP_KERNEL);
  106. if (!desc->v_addr)
  107. return -ENOMEM;
  108. desc->len = len;
  109. memcpy(desc->v_addr, data, len);
  110. return 0;
  111. }
  112. /*
  113. * ucode
  114. */
  115. static int iwl_load_section(struct iwl_trans *trans, const char *name,
  116. struct fw_desc *image, u32 dst_addr)
  117. {
  118. struct iwl_bus *bus = bus(trans);
  119. dma_addr_t phy_addr = image->p_addr;
  120. u32 byte_cnt = image->len;
  121. int ret;
  122. trans->ucode_write_complete = 0;
  123. iwl_write_direct32(bus,
  124. FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
  125. FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
  126. iwl_write_direct32(bus,
  127. FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
  128. iwl_write_direct32(bus,
  129. FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
  130. phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
  131. iwl_write_direct32(bus,
  132. FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
  133. (iwl_get_dma_hi_addr(phy_addr)
  134. << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
  135. iwl_write_direct32(bus,
  136. FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
  137. 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
  138. 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
  139. FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
  140. iwl_write_direct32(bus,
  141. FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
  142. FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
  143. FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
  144. FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
  145. IWL_DEBUG_FW(bus, "%s uCode section being loaded...\n", name);
  146. ret = wait_event_timeout(trans->shrd->wait_command_queue,
  147. trans->ucode_write_complete, 5 * HZ);
  148. if (!ret) {
  149. IWL_ERR(trans, "Could not load the %s uCode section\n",
  150. name);
  151. return -ETIMEDOUT;
  152. }
  153. return 0;
  154. }
  155. static inline struct fw_img *iwl_get_ucode_image(struct iwl_trans *trans,
  156. enum iwl_ucode_type ucode_type)
  157. {
  158. switch (ucode_type) {
  159. case IWL_UCODE_INIT:
  160. return &trans->ucode_init;
  161. case IWL_UCODE_WOWLAN:
  162. return &trans->ucode_wowlan;
  163. case IWL_UCODE_REGULAR:
  164. return &trans->ucode_rt;
  165. case IWL_UCODE_NONE:
  166. break;
  167. }
  168. return NULL;
  169. }
  170. static int iwl_load_given_ucode(struct iwl_trans *trans,
  171. enum iwl_ucode_type ucode_type)
  172. {
  173. int ret = 0;
  174. struct fw_img *image = iwl_get_ucode_image(trans, ucode_type);
  175. if (!image) {
  176. IWL_ERR(trans, "Invalid ucode requested (%d)\n",
  177. ucode_type);
  178. return -EINVAL;
  179. }
  180. ret = iwl_load_section(trans, "INST", &image->code,
  181. IWLAGN_RTC_INST_LOWER_BOUND);
  182. if (ret)
  183. return ret;
  184. return iwl_load_section(trans, "DATA", &image->data,
  185. IWLAGN_RTC_DATA_LOWER_BOUND);
  186. }
  187. /*
  188. * Calibration
  189. */
  190. static int iwl_set_Xtal_calib(struct iwl_trans *trans)
  191. {
  192. struct iwl_calib_xtal_freq_cmd cmd;
  193. __le16 *xtal_calib =
  194. (__le16 *)iwl_eeprom_query_addr(trans->shrd, EEPROM_XTAL);
  195. iwl_set_calib_hdr(&cmd.hdr, IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD);
  196. cmd.cap_pin1 = le16_to_cpu(xtal_calib[0]);
  197. cmd.cap_pin2 = le16_to_cpu(xtal_calib[1]);
  198. return iwl_calib_set(trans, (void *)&cmd, sizeof(cmd));
  199. }
  200. static int iwl_set_temperature_offset_calib(struct iwl_trans *trans)
  201. {
  202. struct iwl_calib_temperature_offset_cmd cmd;
  203. __le16 *offset_calib =
  204. (__le16 *)iwl_eeprom_query_addr(trans->shrd,
  205. EEPROM_RAW_TEMPERATURE);
  206. memset(&cmd, 0, sizeof(cmd));
  207. iwl_set_calib_hdr(&cmd.hdr, IWL_PHY_CALIBRATE_TEMP_OFFSET_CMD);
  208. memcpy(&cmd.radio_sensor_offset, offset_calib, sizeof(*offset_calib));
  209. if (!(cmd.radio_sensor_offset))
  210. cmd.radio_sensor_offset = DEFAULT_RADIO_SENSOR_OFFSET;
  211. IWL_DEBUG_CALIB(trans, "Radio sensor offset: %d\n",
  212. le16_to_cpu(cmd.radio_sensor_offset));
  213. return iwl_calib_set(trans, (void *)&cmd, sizeof(cmd));
  214. }
  215. static int iwl_set_temperature_offset_calib_v2(struct iwl_trans *trans)
  216. {
  217. struct iwl_calib_temperature_offset_v2_cmd cmd;
  218. __le16 *offset_calib_high = (__le16 *)iwl_eeprom_query_addr(trans->shrd,
  219. EEPROM_KELVIN_TEMPERATURE);
  220. __le16 *offset_calib_low =
  221. (__le16 *)iwl_eeprom_query_addr(trans->shrd,
  222. EEPROM_RAW_TEMPERATURE);
  223. struct iwl_eeprom_calib_hdr *hdr;
  224. memset(&cmd, 0, sizeof(cmd));
  225. iwl_set_calib_hdr(&cmd.hdr, IWL_PHY_CALIBRATE_TEMP_OFFSET_CMD);
  226. hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(trans->shrd,
  227. EEPROM_CALIB_ALL);
  228. memcpy(&cmd.radio_sensor_offset_high, offset_calib_high,
  229. sizeof(*offset_calib_high));
  230. memcpy(&cmd.radio_sensor_offset_low, offset_calib_low,
  231. sizeof(*offset_calib_low));
  232. if (!(cmd.radio_sensor_offset_low)) {
  233. IWL_DEBUG_CALIB(trans, "no info in EEPROM, use default\n");
  234. cmd.radio_sensor_offset_low = DEFAULT_RADIO_SENSOR_OFFSET;
  235. cmd.radio_sensor_offset_high = DEFAULT_RADIO_SENSOR_OFFSET;
  236. }
  237. memcpy(&cmd.burntVoltageRef, &hdr->voltage,
  238. sizeof(hdr->voltage));
  239. IWL_DEBUG_CALIB(trans, "Radio sensor offset high: %d\n",
  240. le16_to_cpu(cmd.radio_sensor_offset_high));
  241. IWL_DEBUG_CALIB(trans, "Radio sensor offset low: %d\n",
  242. le16_to_cpu(cmd.radio_sensor_offset_low));
  243. IWL_DEBUG_CALIB(trans, "Voltage Ref: %d\n",
  244. le16_to_cpu(cmd.burntVoltageRef));
  245. return iwl_calib_set(trans, (void *)&cmd, sizeof(cmd));
  246. }
  247. static int iwl_send_calib_cfg(struct iwl_trans *trans)
  248. {
  249. struct iwl_calib_cfg_cmd calib_cfg_cmd;
  250. struct iwl_host_cmd cmd = {
  251. .id = CALIBRATION_CFG_CMD,
  252. .len = { sizeof(struct iwl_calib_cfg_cmd), },
  253. .data = { &calib_cfg_cmd, },
  254. };
  255. memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
  256. calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
  257. calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
  258. calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
  259. calib_cfg_cmd.ucd_calib_cfg.flags =
  260. IWL_CALIB_CFG_FLAG_SEND_COMPLETE_NTFY_MSK;
  261. return iwl_trans_send_cmd(trans, &cmd);
  262. }
  263. int iwlagn_rx_calib_result(struct iwl_priv *priv,
  264. struct iwl_rx_mem_buffer *rxb,
  265. struct iwl_device_cmd *cmd)
  266. {
  267. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  268. struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
  269. int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
  270. /* reduce the size of the length field itself */
  271. len -= 4;
  272. if (iwl_calib_set(trans(priv), hdr, len))
  273. IWL_ERR(priv, "Failed to record calibration data %d\n",
  274. hdr->op_code);
  275. return 0;
  276. }
  277. int iwl_init_alive_start(struct iwl_trans *trans)
  278. {
  279. int ret;
  280. if (cfg(trans)->bt_params &&
  281. cfg(trans)->bt_params->advanced_bt_coexist) {
  282. /*
  283. * Tell uCode we are ready to perform calibration
  284. * need to perform this before any calibration
  285. * no need to close the envlope since we are going
  286. * to load the runtime uCode later.
  287. */
  288. ret = iwl_send_bt_env(trans, IWL_BT_COEX_ENV_OPEN,
  289. BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
  290. if (ret)
  291. return ret;
  292. }
  293. ret = iwl_send_calib_cfg(trans);
  294. if (ret)
  295. return ret;
  296. /**
  297. * temperature offset calibration is only needed for runtime ucode,
  298. * so prepare the value now.
  299. */
  300. if (cfg(trans)->need_temp_offset_calib) {
  301. if (cfg(trans)->temp_offset_v2)
  302. return iwl_set_temperature_offset_calib_v2(trans);
  303. else
  304. return iwl_set_temperature_offset_calib(trans);
  305. }
  306. return 0;
  307. }
  308. static int iwl_send_wimax_coex(struct iwl_trans *trans)
  309. {
  310. struct iwl_wimax_coex_cmd coex_cmd;
  311. if (cfg(trans)->base_params->support_wimax_coexist) {
  312. /* UnMask wake up src at associated sleep */
  313. coex_cmd.flags = COEX_FLAGS_ASSOC_WA_UNMASK_MSK;
  314. /* UnMask wake up src at unassociated sleep */
  315. coex_cmd.flags |= COEX_FLAGS_UNASSOC_WA_UNMASK_MSK;
  316. memcpy(coex_cmd.sta_prio, cu_priorities,
  317. sizeof(struct iwl_wimax_coex_event_entry) *
  318. COEX_NUM_OF_EVENTS);
  319. /* enabling the coexistence feature */
  320. coex_cmd.flags |= COEX_FLAGS_COEX_ENABLE_MSK;
  321. /* enabling the priorities tables */
  322. coex_cmd.flags |= COEX_FLAGS_STA_TABLE_VALID_MSK;
  323. } else {
  324. /* coexistence is disabled */
  325. memset(&coex_cmd, 0, sizeof(coex_cmd));
  326. }
  327. return iwl_trans_send_cmd_pdu(trans,
  328. COEX_PRIORITY_TABLE_CMD, CMD_SYNC,
  329. sizeof(coex_cmd), &coex_cmd);
  330. }
  331. static const u8 iwl_bt_prio_tbl[BT_COEX_PRIO_TBL_EVT_MAX] = {
  332. ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  333. (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  334. ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  335. (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  336. ((BT_COEX_PRIO_TBL_PRIO_LOW << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  337. (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  338. ((BT_COEX_PRIO_TBL_PRIO_LOW << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  339. (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  340. ((BT_COEX_PRIO_TBL_PRIO_HIGH << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  341. (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  342. ((BT_COEX_PRIO_TBL_PRIO_HIGH << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  343. (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  344. ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  345. (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  346. ((BT_COEX_PRIO_TBL_PRIO_COEX_OFF << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  347. (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  348. ((BT_COEX_PRIO_TBL_PRIO_COEX_ON << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  349. (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  350. 0, 0, 0, 0, 0, 0, 0
  351. };
  352. void iwl_send_prio_tbl(struct iwl_trans *trans)
  353. {
  354. struct iwl_bt_coex_prio_table_cmd prio_tbl_cmd;
  355. memcpy(prio_tbl_cmd.prio_tbl, iwl_bt_prio_tbl,
  356. sizeof(iwl_bt_prio_tbl));
  357. if (iwl_trans_send_cmd_pdu(trans,
  358. REPLY_BT_COEX_PRIO_TABLE, CMD_SYNC,
  359. sizeof(prio_tbl_cmd), &prio_tbl_cmd))
  360. IWL_ERR(trans, "failed to send BT prio tbl command\n");
  361. }
  362. int iwl_send_bt_env(struct iwl_trans *trans, u8 action, u8 type)
  363. {
  364. struct iwl_bt_coex_prot_env_cmd env_cmd;
  365. int ret;
  366. env_cmd.action = action;
  367. env_cmd.type = type;
  368. ret = iwl_trans_send_cmd_pdu(trans,
  369. REPLY_BT_COEX_PROT_ENV, CMD_SYNC,
  370. sizeof(env_cmd), &env_cmd);
  371. if (ret)
  372. IWL_ERR(trans, "failed to send BT env command\n");
  373. return ret;
  374. }
  375. static int iwl_alive_notify(struct iwl_trans *trans)
  376. {
  377. struct iwl_priv *priv = priv(trans);
  378. struct iwl_rxon_context *ctx;
  379. int ret;
  380. if (!priv->tx_cmd_pool)
  381. priv->tx_cmd_pool =
  382. kmem_cache_create("iwl_dev_cmd",
  383. sizeof(struct iwl_device_cmd),
  384. sizeof(void *), 0, NULL);
  385. if (!priv->tx_cmd_pool)
  386. return -ENOMEM;
  387. iwl_trans_tx_start(trans);
  388. for_each_context(priv, ctx)
  389. ctx->last_tx_rejected = false;
  390. ret = iwl_send_wimax_coex(trans);
  391. if (ret)
  392. return ret;
  393. if (!cfg(priv)->no_xtal_calib) {
  394. ret = iwl_set_Xtal_calib(trans);
  395. if (ret)
  396. return ret;
  397. }
  398. return iwl_send_calib_results(trans);
  399. }
  400. /**
  401. * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
  402. * using sample data 100 bytes apart. If these sample points are good,
  403. * it's a pretty good bet that everything between them is good, too.
  404. */
  405. static int iwl_verify_inst_sparse(struct iwl_bus *bus,
  406. struct fw_desc *fw_desc)
  407. {
  408. __le32 *image = (__le32 *)fw_desc->v_addr;
  409. u32 len = fw_desc->len;
  410. u32 val;
  411. u32 i;
  412. IWL_DEBUG_FW(bus, "ucode inst image size is %u\n", len);
  413. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  414. /* read data comes through single port, auto-incr addr */
  415. /* NOTE: Use the debugless read so we don't flood kernel log
  416. * if IWL_DL_IO is set */
  417. iwl_write_direct32(bus, HBUS_TARG_MEM_RADDR,
  418. i + IWLAGN_RTC_INST_LOWER_BOUND);
  419. val = iwl_read32(bus, HBUS_TARG_MEM_RDAT);
  420. if (val != le32_to_cpu(*image))
  421. return -EIO;
  422. }
  423. return 0;
  424. }
  425. static void iwl_print_mismatch_inst(struct iwl_bus *bus,
  426. struct fw_desc *fw_desc)
  427. {
  428. __le32 *image = (__le32 *)fw_desc->v_addr;
  429. u32 len = fw_desc->len;
  430. u32 val;
  431. u32 offs;
  432. int errors = 0;
  433. IWL_DEBUG_FW(bus, "ucode inst image size is %u\n", len);
  434. iwl_write_direct32(bus, HBUS_TARG_MEM_RADDR,
  435. IWLAGN_RTC_INST_LOWER_BOUND);
  436. for (offs = 0;
  437. offs < len && errors < 20;
  438. offs += sizeof(u32), image++) {
  439. /* read data comes through single port, auto-incr addr */
  440. val = iwl_read32(bus, HBUS_TARG_MEM_RDAT);
  441. if (val != le32_to_cpu(*image)) {
  442. IWL_ERR(bus, "uCode INST section at "
  443. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  444. offs, val, le32_to_cpu(*image));
  445. errors++;
  446. }
  447. }
  448. }
  449. /**
  450. * iwl_verify_ucode - determine which instruction image is in SRAM,
  451. * and verify its contents
  452. */
  453. static int iwl_verify_ucode(struct iwl_trans *trans,
  454. enum iwl_ucode_type ucode_type)
  455. {
  456. struct fw_img *img = iwl_get_ucode_image(trans, ucode_type);
  457. if (!img) {
  458. IWL_ERR(trans, "Invalid ucode requested (%d)\n", ucode_type);
  459. return -EINVAL;
  460. }
  461. if (!iwl_verify_inst_sparse(bus(trans), &img->code)) {
  462. IWL_DEBUG_FW(trans, "uCode is good in inst SRAM\n");
  463. return 0;
  464. }
  465. IWL_ERR(trans, "UCODE IMAGE IN INSTRUCTION SRAM NOT VALID!!\n");
  466. iwl_print_mismatch_inst(bus(trans), &img->code);
  467. return -EIO;
  468. }
  469. struct iwl_alive_data {
  470. bool valid;
  471. u8 subtype;
  472. };
  473. static void iwl_alive_fn(struct iwl_trans *trans,
  474. struct iwl_rx_packet *pkt,
  475. void *data)
  476. {
  477. struct iwl_alive_data *alive_data = data;
  478. struct iwl_alive_resp *palive;
  479. palive = &pkt->u.alive_frame;
  480. IWL_DEBUG_FW(trans, "Alive ucode status 0x%08X revision "
  481. "0x%01X 0x%01X\n",
  482. palive->is_valid, palive->ver_type,
  483. palive->ver_subtype);
  484. trans->shrd->device_pointers.error_event_table =
  485. le32_to_cpu(palive->error_event_table_ptr);
  486. trans->shrd->device_pointers.log_event_table =
  487. le32_to_cpu(palive->log_event_table_ptr);
  488. alive_data->subtype = palive->ver_subtype;
  489. alive_data->valid = palive->is_valid == UCODE_VALID_OK;
  490. }
  491. /* notification wait support */
  492. void iwl_init_notification_wait(struct iwl_shared *shrd,
  493. struct iwl_notification_wait *wait_entry,
  494. u8 cmd,
  495. void (*fn)(struct iwl_trans *trans,
  496. struct iwl_rx_packet *pkt,
  497. void *data),
  498. void *fn_data)
  499. {
  500. wait_entry->fn = fn;
  501. wait_entry->fn_data = fn_data;
  502. wait_entry->cmd = cmd;
  503. wait_entry->triggered = false;
  504. wait_entry->aborted = false;
  505. spin_lock_bh(&shrd->notif_wait_lock);
  506. list_add(&wait_entry->list, &shrd->notif_waits);
  507. spin_unlock_bh(&shrd->notif_wait_lock);
  508. }
  509. int iwl_wait_notification(struct iwl_shared *shrd,
  510. struct iwl_notification_wait *wait_entry,
  511. unsigned long timeout)
  512. {
  513. int ret;
  514. ret = wait_event_timeout(shrd->notif_waitq,
  515. wait_entry->triggered || wait_entry->aborted,
  516. timeout);
  517. spin_lock_bh(&shrd->notif_wait_lock);
  518. list_del(&wait_entry->list);
  519. spin_unlock_bh(&shrd->notif_wait_lock);
  520. if (wait_entry->aborted)
  521. return -EIO;
  522. /* return value is always >= 0 */
  523. if (ret <= 0)
  524. return -ETIMEDOUT;
  525. return 0;
  526. }
  527. void iwl_remove_notification(struct iwl_shared *shrd,
  528. struct iwl_notification_wait *wait_entry)
  529. {
  530. spin_lock_bh(&shrd->notif_wait_lock);
  531. list_del(&wait_entry->list);
  532. spin_unlock_bh(&shrd->notif_wait_lock);
  533. }
  534. void iwl_abort_notification_waits(struct iwl_shared *shrd)
  535. {
  536. unsigned long flags;
  537. struct iwl_notification_wait *wait_entry;
  538. spin_lock_irqsave(&shrd->notif_wait_lock, flags);
  539. list_for_each_entry(wait_entry, &shrd->notif_waits, list)
  540. wait_entry->aborted = true;
  541. spin_unlock_irqrestore(&shrd->notif_wait_lock, flags);
  542. wake_up_all(&shrd->notif_waitq);
  543. }
  544. #define UCODE_ALIVE_TIMEOUT HZ
  545. #define UCODE_CALIB_TIMEOUT (2*HZ)
  546. int iwl_load_ucode_wait_alive(struct iwl_trans *trans,
  547. enum iwl_ucode_type ucode_type)
  548. {
  549. struct iwl_notification_wait alive_wait;
  550. struct iwl_alive_data alive_data;
  551. int ret;
  552. enum iwl_ucode_type old_type;
  553. ret = iwl_trans_start_device(trans);
  554. if (ret)
  555. return ret;
  556. iwl_init_notification_wait(trans->shrd, &alive_wait, REPLY_ALIVE,
  557. iwl_alive_fn, &alive_data);
  558. old_type = trans->shrd->ucode_type;
  559. trans->shrd->ucode_type = ucode_type;
  560. ret = iwl_load_given_ucode(trans, ucode_type);
  561. if (ret) {
  562. trans->shrd->ucode_type = old_type;
  563. iwl_remove_notification(trans->shrd, &alive_wait);
  564. return ret;
  565. }
  566. iwl_trans_kick_nic(trans);
  567. /*
  568. * Some things may run in the background now, but we
  569. * just wait for the ALIVE notification here.
  570. */
  571. ret = iwl_wait_notification(trans->shrd, &alive_wait,
  572. UCODE_ALIVE_TIMEOUT);
  573. if (ret) {
  574. trans->shrd->ucode_type = old_type;
  575. return ret;
  576. }
  577. if (!alive_data.valid) {
  578. IWL_ERR(trans, "Loaded ucode is not valid!\n");
  579. trans->shrd->ucode_type = old_type;
  580. return -EIO;
  581. }
  582. /*
  583. * This step takes a long time (60-80ms!!) and
  584. * WoWLAN image should be loaded quickly, so
  585. * skip it for WoWLAN.
  586. */
  587. if (ucode_type != IWL_UCODE_WOWLAN) {
  588. ret = iwl_verify_ucode(trans, ucode_type);
  589. if (ret) {
  590. trans->shrd->ucode_type = old_type;
  591. return ret;
  592. }
  593. /* delay a bit to give rfkill time to run */
  594. msleep(5);
  595. }
  596. ret = iwl_alive_notify(trans);
  597. if (ret) {
  598. IWL_WARN(trans,
  599. "Could not complete ALIVE transition: %d\n", ret);
  600. trans->shrd->ucode_type = old_type;
  601. return ret;
  602. }
  603. return 0;
  604. }
  605. int iwl_run_init_ucode(struct iwl_trans *trans)
  606. {
  607. struct iwl_notification_wait calib_wait;
  608. int ret;
  609. lockdep_assert_held(&trans->shrd->mutex);
  610. /* No init ucode required? Curious, but maybe ok */
  611. if (!trans->ucode_init.code.len)
  612. return 0;
  613. if (trans->shrd->ucode_type != IWL_UCODE_NONE)
  614. return 0;
  615. iwl_init_notification_wait(trans->shrd, &calib_wait,
  616. CALIBRATION_COMPLETE_NOTIFICATION,
  617. NULL, NULL);
  618. /* Will also start the device */
  619. ret = iwl_load_ucode_wait_alive(trans, IWL_UCODE_INIT);
  620. if (ret)
  621. goto error;
  622. ret = iwl_init_alive_start(trans);
  623. if (ret)
  624. goto error;
  625. /*
  626. * Some things may run in the background now, but we
  627. * just wait for the calibration complete notification.
  628. */
  629. ret = iwl_wait_notification(trans->shrd, &calib_wait,
  630. UCODE_CALIB_TIMEOUT);
  631. goto out;
  632. error:
  633. iwl_remove_notification(trans->shrd, &calib_wait);
  634. out:
  635. /* Whatever happened, stop the device */
  636. iwl_trans_stop_device(trans);
  637. return ret;
  638. }