i810_dma.c 33 KB

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  1. /* i810_dma.c -- DMA support for the i810 -*- linux-c -*-
  2. * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
  3. *
  4. * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
  5. * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  6. * All Rights Reserved.
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a
  9. * copy of this software and associated documentation files (the "Software"),
  10. * to deal in the Software without restriction, including without limitation
  11. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12. * and/or sell copies of the Software, and to permit persons to whom the
  13. * Software is furnished to do so, subject to the following conditions:
  14. *
  15. * The above copyright notice and this permission notice (including the next
  16. * paragraph) shall be included in all copies or substantial portions of the
  17. * Software.
  18. *
  19. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22. * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25. * DEALINGS IN THE SOFTWARE.
  26. *
  27. * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
  28. * Jeff Hartmann <jhartmann@valinux.com>
  29. * Keith Whitwell <keith@tungstengraphics.com>
  30. *
  31. */
  32. #include "drmP.h"
  33. #include "drm.h"
  34. #include "i810_drm.h"
  35. #include "i810_drv.h"
  36. #include <linux/interrupt.h> /* For task queue support */
  37. #include <linux/delay.h>
  38. #include <linux/slab.h>
  39. #include <linux/pagemap.h>
  40. #define I810_BUF_FREE 2
  41. #define I810_BUF_CLIENT 1
  42. #define I810_BUF_HARDWARE 0
  43. #define I810_BUF_UNMAPPED 0
  44. #define I810_BUF_MAPPED 1
  45. static struct drm_buf *i810_freelist_get(struct drm_device * dev)
  46. {
  47. struct drm_device_dma *dma = dev->dma;
  48. int i;
  49. int used;
  50. /* Linear search might not be the best solution */
  51. for (i = 0; i < dma->buf_count; i++) {
  52. struct drm_buf *buf = dma->buflist[i];
  53. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  54. /* In use is already a pointer */
  55. used = cmpxchg(buf_priv->in_use, I810_BUF_FREE,
  56. I810_BUF_CLIENT);
  57. if (used == I810_BUF_FREE)
  58. return buf;
  59. }
  60. return NULL;
  61. }
  62. /* This should only be called if the buffer is not sent to the hardware
  63. * yet, the hardware updates in use for us once its on the ring buffer.
  64. */
  65. static int i810_freelist_put(struct drm_device *dev, struct drm_buf *buf)
  66. {
  67. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  68. int used;
  69. /* In use is already a pointer */
  70. used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_FREE);
  71. if (used != I810_BUF_CLIENT) {
  72. DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx);
  73. return -EINVAL;
  74. }
  75. return 0;
  76. }
  77. static int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma)
  78. {
  79. struct drm_file *priv = filp->private_data;
  80. struct drm_device *dev;
  81. drm_i810_private_t *dev_priv;
  82. struct drm_buf *buf;
  83. drm_i810_buf_priv_t *buf_priv;
  84. dev = priv->minor->dev;
  85. dev_priv = dev->dev_private;
  86. buf = dev_priv->mmap_buffer;
  87. buf_priv = buf->dev_private;
  88. vma->vm_flags |= (VM_IO | VM_DONTCOPY);
  89. vma->vm_file = filp;
  90. buf_priv->currently_mapped = I810_BUF_MAPPED;
  91. if (io_remap_pfn_range(vma, vma->vm_start,
  92. vma->vm_pgoff,
  93. vma->vm_end - vma->vm_start, vma->vm_page_prot))
  94. return -EAGAIN;
  95. return 0;
  96. }
  97. static const struct file_operations i810_buffer_fops = {
  98. .open = drm_open,
  99. .release = drm_release,
  100. .unlocked_ioctl = drm_ioctl,
  101. .mmap = i810_mmap_buffers,
  102. .fasync = drm_fasync,
  103. .llseek = noop_llseek,
  104. };
  105. static int i810_map_buffer(struct drm_buf *buf, struct drm_file *file_priv)
  106. {
  107. struct drm_device *dev = file_priv->minor->dev;
  108. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  109. drm_i810_private_t *dev_priv = dev->dev_private;
  110. const struct file_operations *old_fops;
  111. int retcode = 0;
  112. if (buf_priv->currently_mapped == I810_BUF_MAPPED)
  113. return -EINVAL;
  114. down_write(&current->mm->mmap_sem);
  115. old_fops = file_priv->filp->f_op;
  116. file_priv->filp->f_op = &i810_buffer_fops;
  117. dev_priv->mmap_buffer = buf;
  118. buf_priv->virtual = (void *)do_mmap(file_priv->filp, 0, buf->total,
  119. PROT_READ | PROT_WRITE,
  120. MAP_SHARED, buf->bus_address);
  121. dev_priv->mmap_buffer = NULL;
  122. file_priv->filp->f_op = old_fops;
  123. if (IS_ERR(buf_priv->virtual)) {
  124. /* Real error */
  125. DRM_ERROR("mmap error\n");
  126. retcode = PTR_ERR(buf_priv->virtual);
  127. buf_priv->virtual = NULL;
  128. }
  129. up_write(&current->mm->mmap_sem);
  130. return retcode;
  131. }
  132. static int i810_unmap_buffer(struct drm_buf *buf)
  133. {
  134. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  135. int retcode = 0;
  136. if (buf_priv->currently_mapped != I810_BUF_MAPPED)
  137. return -EINVAL;
  138. down_write(&current->mm->mmap_sem);
  139. retcode = do_munmap(current->mm,
  140. (unsigned long)buf_priv->virtual,
  141. (size_t) buf->total);
  142. up_write(&current->mm->mmap_sem);
  143. buf_priv->currently_mapped = I810_BUF_UNMAPPED;
  144. buf_priv->virtual = NULL;
  145. return retcode;
  146. }
  147. static int i810_dma_get_buffer(struct drm_device *dev, drm_i810_dma_t *d,
  148. struct drm_file *file_priv)
  149. {
  150. struct drm_buf *buf;
  151. drm_i810_buf_priv_t *buf_priv;
  152. int retcode = 0;
  153. buf = i810_freelist_get(dev);
  154. if (!buf) {
  155. retcode = -ENOMEM;
  156. DRM_DEBUG("retcode=%d\n", retcode);
  157. return retcode;
  158. }
  159. retcode = i810_map_buffer(buf, file_priv);
  160. if (retcode) {
  161. i810_freelist_put(dev, buf);
  162. DRM_ERROR("mapbuf failed, retcode %d\n", retcode);
  163. return retcode;
  164. }
  165. buf->file_priv = file_priv;
  166. buf_priv = buf->dev_private;
  167. d->granted = 1;
  168. d->request_idx = buf->idx;
  169. d->request_size = buf->total;
  170. d->virtual = buf_priv->virtual;
  171. return retcode;
  172. }
  173. static int i810_dma_cleanup(struct drm_device *dev)
  174. {
  175. struct drm_device_dma *dma = dev->dma;
  176. /* Make sure interrupts are disabled here because the uninstall ioctl
  177. * may not have been called from userspace and after dev_private
  178. * is freed, it's too late.
  179. */
  180. if (drm_core_check_feature(dev, DRIVER_HAVE_IRQ) && dev->irq_enabled)
  181. drm_irq_uninstall(dev);
  182. if (dev->dev_private) {
  183. int i;
  184. drm_i810_private_t *dev_priv =
  185. (drm_i810_private_t *) dev->dev_private;
  186. if (dev_priv->ring.virtual_start)
  187. drm_core_ioremapfree(&dev_priv->ring.map, dev);
  188. if (dev_priv->hw_status_page) {
  189. pci_free_consistent(dev->pdev, PAGE_SIZE,
  190. dev_priv->hw_status_page,
  191. dev_priv->dma_status_page);
  192. }
  193. kfree(dev->dev_private);
  194. dev->dev_private = NULL;
  195. for (i = 0; i < dma->buf_count; i++) {
  196. struct drm_buf *buf = dma->buflist[i];
  197. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  198. if (buf_priv->kernel_virtual && buf->total)
  199. drm_core_ioremapfree(&buf_priv->map, dev);
  200. }
  201. }
  202. return 0;
  203. }
  204. static int i810_wait_ring(struct drm_device *dev, int n)
  205. {
  206. drm_i810_private_t *dev_priv = dev->dev_private;
  207. drm_i810_ring_buffer_t *ring = &(dev_priv->ring);
  208. int iters = 0;
  209. unsigned long end;
  210. unsigned int last_head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  211. end = jiffies + (HZ * 3);
  212. while (ring->space < n) {
  213. ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  214. ring->space = ring->head - (ring->tail + 8);
  215. if (ring->space < 0)
  216. ring->space += ring->Size;
  217. if (ring->head != last_head) {
  218. end = jiffies + (HZ * 3);
  219. last_head = ring->head;
  220. }
  221. iters++;
  222. if (time_before(end, jiffies)) {
  223. DRM_ERROR("space: %d wanted %d\n", ring->space, n);
  224. DRM_ERROR("lockup\n");
  225. goto out_wait_ring;
  226. }
  227. udelay(1);
  228. }
  229. out_wait_ring:
  230. return iters;
  231. }
  232. static void i810_kernel_lost_context(struct drm_device *dev)
  233. {
  234. drm_i810_private_t *dev_priv = dev->dev_private;
  235. drm_i810_ring_buffer_t *ring = &(dev_priv->ring);
  236. ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  237. ring->tail = I810_READ(LP_RING + RING_TAIL);
  238. ring->space = ring->head - (ring->tail + 8);
  239. if (ring->space < 0)
  240. ring->space += ring->Size;
  241. }
  242. static int i810_freelist_init(struct drm_device *dev, drm_i810_private_t *dev_priv)
  243. {
  244. struct drm_device_dma *dma = dev->dma;
  245. int my_idx = 24;
  246. u32 *hw_status = (u32 *) (dev_priv->hw_status_page + my_idx);
  247. int i;
  248. if (dma->buf_count > 1019) {
  249. /* Not enough space in the status page for the freelist */
  250. return -EINVAL;
  251. }
  252. for (i = 0; i < dma->buf_count; i++) {
  253. struct drm_buf *buf = dma->buflist[i];
  254. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  255. buf_priv->in_use = hw_status++;
  256. buf_priv->my_use_idx = my_idx;
  257. my_idx += 4;
  258. *buf_priv->in_use = I810_BUF_FREE;
  259. buf_priv->map.offset = buf->bus_address;
  260. buf_priv->map.size = buf->total;
  261. buf_priv->map.type = _DRM_AGP;
  262. buf_priv->map.flags = 0;
  263. buf_priv->map.mtrr = 0;
  264. drm_core_ioremap(&buf_priv->map, dev);
  265. buf_priv->kernel_virtual = buf_priv->map.handle;
  266. }
  267. return 0;
  268. }
  269. static int i810_dma_initialize(struct drm_device *dev,
  270. drm_i810_private_t *dev_priv,
  271. drm_i810_init_t *init)
  272. {
  273. struct drm_map_list *r_list;
  274. memset(dev_priv, 0, sizeof(drm_i810_private_t));
  275. list_for_each_entry(r_list, &dev->maplist, head) {
  276. if (r_list->map &&
  277. r_list->map->type == _DRM_SHM &&
  278. r_list->map->flags & _DRM_CONTAINS_LOCK) {
  279. dev_priv->sarea_map = r_list->map;
  280. break;
  281. }
  282. }
  283. if (!dev_priv->sarea_map) {
  284. dev->dev_private = (void *)dev_priv;
  285. i810_dma_cleanup(dev);
  286. DRM_ERROR("can not find sarea!\n");
  287. return -EINVAL;
  288. }
  289. dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
  290. if (!dev_priv->mmio_map) {
  291. dev->dev_private = (void *)dev_priv;
  292. i810_dma_cleanup(dev);
  293. DRM_ERROR("can not find mmio map!\n");
  294. return -EINVAL;
  295. }
  296. dev->agp_buffer_token = init->buffers_offset;
  297. dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
  298. if (!dev->agp_buffer_map) {
  299. dev->dev_private = (void *)dev_priv;
  300. i810_dma_cleanup(dev);
  301. DRM_ERROR("can not find dma buffer map!\n");
  302. return -EINVAL;
  303. }
  304. dev_priv->sarea_priv = (drm_i810_sarea_t *)
  305. ((u8 *) dev_priv->sarea_map->handle + init->sarea_priv_offset);
  306. dev_priv->ring.Start = init->ring_start;
  307. dev_priv->ring.End = init->ring_end;
  308. dev_priv->ring.Size = init->ring_size;
  309. dev_priv->ring.map.offset = dev->agp->base + init->ring_start;
  310. dev_priv->ring.map.size = init->ring_size;
  311. dev_priv->ring.map.type = _DRM_AGP;
  312. dev_priv->ring.map.flags = 0;
  313. dev_priv->ring.map.mtrr = 0;
  314. drm_core_ioremap(&dev_priv->ring.map, dev);
  315. if (dev_priv->ring.map.handle == NULL) {
  316. dev->dev_private = (void *)dev_priv;
  317. i810_dma_cleanup(dev);
  318. DRM_ERROR("can not ioremap virtual address for"
  319. " ring buffer\n");
  320. return -ENOMEM;
  321. }
  322. dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
  323. dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
  324. dev_priv->w = init->w;
  325. dev_priv->h = init->h;
  326. dev_priv->pitch = init->pitch;
  327. dev_priv->back_offset = init->back_offset;
  328. dev_priv->depth_offset = init->depth_offset;
  329. dev_priv->front_offset = init->front_offset;
  330. dev_priv->overlay_offset = init->overlay_offset;
  331. dev_priv->overlay_physical = init->overlay_physical;
  332. dev_priv->front_di1 = init->front_offset | init->pitch_bits;
  333. dev_priv->back_di1 = init->back_offset | init->pitch_bits;
  334. dev_priv->zi1 = init->depth_offset | init->pitch_bits;
  335. /* Program Hardware Status Page */
  336. dev_priv->hw_status_page =
  337. pci_alloc_consistent(dev->pdev, PAGE_SIZE,
  338. &dev_priv->dma_status_page);
  339. if (!dev_priv->hw_status_page) {
  340. dev->dev_private = (void *)dev_priv;
  341. i810_dma_cleanup(dev);
  342. DRM_ERROR("Can not allocate hardware status page\n");
  343. return -ENOMEM;
  344. }
  345. memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
  346. DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
  347. I810_WRITE(0x02080, dev_priv->dma_status_page);
  348. DRM_DEBUG("Enabled hardware status page\n");
  349. /* Now we need to init our freelist */
  350. if (i810_freelist_init(dev, dev_priv) != 0) {
  351. dev->dev_private = (void *)dev_priv;
  352. i810_dma_cleanup(dev);
  353. DRM_ERROR("Not enough space in the status page for"
  354. " the freelist\n");
  355. return -ENOMEM;
  356. }
  357. dev->dev_private = (void *)dev_priv;
  358. return 0;
  359. }
  360. static int i810_dma_init(struct drm_device *dev, void *data,
  361. struct drm_file *file_priv)
  362. {
  363. drm_i810_private_t *dev_priv;
  364. drm_i810_init_t *init = data;
  365. int retcode = 0;
  366. switch (init->func) {
  367. case I810_INIT_DMA_1_4:
  368. DRM_INFO("Using v1.4 init.\n");
  369. dev_priv = kmalloc(sizeof(drm_i810_private_t), GFP_KERNEL);
  370. if (dev_priv == NULL)
  371. return -ENOMEM;
  372. retcode = i810_dma_initialize(dev, dev_priv, init);
  373. break;
  374. case I810_CLEANUP_DMA:
  375. DRM_INFO("DMA Cleanup\n");
  376. retcode = i810_dma_cleanup(dev);
  377. break;
  378. default:
  379. return -EINVAL;
  380. }
  381. return retcode;
  382. }
  383. /* Most efficient way to verify state for the i810 is as it is
  384. * emitted. Non-conformant state is silently dropped.
  385. *
  386. * Use 'volatile' & local var tmp to force the emitted values to be
  387. * identical to the verified ones.
  388. */
  389. static void i810EmitContextVerified(struct drm_device *dev,
  390. volatile unsigned int *code)
  391. {
  392. drm_i810_private_t *dev_priv = dev->dev_private;
  393. int i, j = 0;
  394. unsigned int tmp;
  395. RING_LOCALS;
  396. BEGIN_LP_RING(I810_CTX_SETUP_SIZE);
  397. OUT_RING(GFX_OP_COLOR_FACTOR);
  398. OUT_RING(code[I810_CTXREG_CF1]);
  399. OUT_RING(GFX_OP_STIPPLE);
  400. OUT_RING(code[I810_CTXREG_ST1]);
  401. for (i = 4; i < I810_CTX_SETUP_SIZE; i++) {
  402. tmp = code[i];
  403. if ((tmp & (7 << 29)) == (3 << 29) &&
  404. (tmp & (0x1f << 24)) < (0x1d << 24)) {
  405. OUT_RING(tmp);
  406. j++;
  407. } else
  408. printk("constext state dropped!!!\n");
  409. }
  410. if (j & 1)
  411. OUT_RING(0);
  412. ADVANCE_LP_RING();
  413. }
  414. static void i810EmitTexVerified(struct drm_device *dev, volatile unsigned int *code)
  415. {
  416. drm_i810_private_t *dev_priv = dev->dev_private;
  417. int i, j = 0;
  418. unsigned int tmp;
  419. RING_LOCALS;
  420. BEGIN_LP_RING(I810_TEX_SETUP_SIZE);
  421. OUT_RING(GFX_OP_MAP_INFO);
  422. OUT_RING(code[I810_TEXREG_MI1]);
  423. OUT_RING(code[I810_TEXREG_MI2]);
  424. OUT_RING(code[I810_TEXREG_MI3]);
  425. for (i = 4; i < I810_TEX_SETUP_SIZE; i++) {
  426. tmp = code[i];
  427. if ((tmp & (7 << 29)) == (3 << 29) &&
  428. (tmp & (0x1f << 24)) < (0x1d << 24)) {
  429. OUT_RING(tmp);
  430. j++;
  431. } else
  432. printk("texture state dropped!!!\n");
  433. }
  434. if (j & 1)
  435. OUT_RING(0);
  436. ADVANCE_LP_RING();
  437. }
  438. /* Need to do some additional checking when setting the dest buffer.
  439. */
  440. static void i810EmitDestVerified(struct drm_device *dev,
  441. volatile unsigned int *code)
  442. {
  443. drm_i810_private_t *dev_priv = dev->dev_private;
  444. unsigned int tmp;
  445. RING_LOCALS;
  446. BEGIN_LP_RING(I810_DEST_SETUP_SIZE + 2);
  447. tmp = code[I810_DESTREG_DI1];
  448. if (tmp == dev_priv->front_di1 || tmp == dev_priv->back_di1) {
  449. OUT_RING(CMD_OP_DESTBUFFER_INFO);
  450. OUT_RING(tmp);
  451. } else
  452. DRM_DEBUG("bad di1 %x (allow %x or %x)\n",
  453. tmp, dev_priv->front_di1, dev_priv->back_di1);
  454. /* invarient:
  455. */
  456. OUT_RING(CMD_OP_Z_BUFFER_INFO);
  457. OUT_RING(dev_priv->zi1);
  458. OUT_RING(GFX_OP_DESTBUFFER_VARS);
  459. OUT_RING(code[I810_DESTREG_DV1]);
  460. OUT_RING(GFX_OP_DRAWRECT_INFO);
  461. OUT_RING(code[I810_DESTREG_DR1]);
  462. OUT_RING(code[I810_DESTREG_DR2]);
  463. OUT_RING(code[I810_DESTREG_DR3]);
  464. OUT_RING(code[I810_DESTREG_DR4]);
  465. OUT_RING(0);
  466. ADVANCE_LP_RING();
  467. }
  468. static void i810EmitState(struct drm_device *dev)
  469. {
  470. drm_i810_private_t *dev_priv = dev->dev_private;
  471. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  472. unsigned int dirty = sarea_priv->dirty;
  473. DRM_DEBUG("%x\n", dirty);
  474. if (dirty & I810_UPLOAD_BUFFERS) {
  475. i810EmitDestVerified(dev, sarea_priv->BufferState);
  476. sarea_priv->dirty &= ~I810_UPLOAD_BUFFERS;
  477. }
  478. if (dirty & I810_UPLOAD_CTX) {
  479. i810EmitContextVerified(dev, sarea_priv->ContextState);
  480. sarea_priv->dirty &= ~I810_UPLOAD_CTX;
  481. }
  482. if (dirty & I810_UPLOAD_TEX0) {
  483. i810EmitTexVerified(dev, sarea_priv->TexState[0]);
  484. sarea_priv->dirty &= ~I810_UPLOAD_TEX0;
  485. }
  486. if (dirty & I810_UPLOAD_TEX1) {
  487. i810EmitTexVerified(dev, sarea_priv->TexState[1]);
  488. sarea_priv->dirty &= ~I810_UPLOAD_TEX1;
  489. }
  490. }
  491. /* need to verify
  492. */
  493. static void i810_dma_dispatch_clear(struct drm_device *dev, int flags,
  494. unsigned int clear_color,
  495. unsigned int clear_zval)
  496. {
  497. drm_i810_private_t *dev_priv = dev->dev_private;
  498. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  499. int nbox = sarea_priv->nbox;
  500. struct drm_clip_rect *pbox = sarea_priv->boxes;
  501. int pitch = dev_priv->pitch;
  502. int cpp = 2;
  503. int i;
  504. RING_LOCALS;
  505. if (dev_priv->current_page == 1) {
  506. unsigned int tmp = flags;
  507. flags &= ~(I810_FRONT | I810_BACK);
  508. if (tmp & I810_FRONT)
  509. flags |= I810_BACK;
  510. if (tmp & I810_BACK)
  511. flags |= I810_FRONT;
  512. }
  513. i810_kernel_lost_context(dev);
  514. if (nbox > I810_NR_SAREA_CLIPRECTS)
  515. nbox = I810_NR_SAREA_CLIPRECTS;
  516. for (i = 0; i < nbox; i++, pbox++) {
  517. unsigned int x = pbox->x1;
  518. unsigned int y = pbox->y1;
  519. unsigned int width = (pbox->x2 - x) * cpp;
  520. unsigned int height = pbox->y2 - y;
  521. unsigned int start = y * pitch + x * cpp;
  522. if (pbox->x1 > pbox->x2 ||
  523. pbox->y1 > pbox->y2 ||
  524. pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h)
  525. continue;
  526. if (flags & I810_FRONT) {
  527. BEGIN_LP_RING(6);
  528. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
  529. OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
  530. OUT_RING((height << 16) | width);
  531. OUT_RING(start);
  532. OUT_RING(clear_color);
  533. OUT_RING(0);
  534. ADVANCE_LP_RING();
  535. }
  536. if (flags & I810_BACK) {
  537. BEGIN_LP_RING(6);
  538. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
  539. OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
  540. OUT_RING((height << 16) | width);
  541. OUT_RING(dev_priv->back_offset + start);
  542. OUT_RING(clear_color);
  543. OUT_RING(0);
  544. ADVANCE_LP_RING();
  545. }
  546. if (flags & I810_DEPTH) {
  547. BEGIN_LP_RING(6);
  548. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
  549. OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
  550. OUT_RING((height << 16) | width);
  551. OUT_RING(dev_priv->depth_offset + start);
  552. OUT_RING(clear_zval);
  553. OUT_RING(0);
  554. ADVANCE_LP_RING();
  555. }
  556. }
  557. }
  558. static void i810_dma_dispatch_swap(struct drm_device *dev)
  559. {
  560. drm_i810_private_t *dev_priv = dev->dev_private;
  561. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  562. int nbox = sarea_priv->nbox;
  563. struct drm_clip_rect *pbox = sarea_priv->boxes;
  564. int pitch = dev_priv->pitch;
  565. int cpp = 2;
  566. int i;
  567. RING_LOCALS;
  568. DRM_DEBUG("swapbuffers\n");
  569. i810_kernel_lost_context(dev);
  570. if (nbox > I810_NR_SAREA_CLIPRECTS)
  571. nbox = I810_NR_SAREA_CLIPRECTS;
  572. for (i = 0; i < nbox; i++, pbox++) {
  573. unsigned int w = pbox->x2 - pbox->x1;
  574. unsigned int h = pbox->y2 - pbox->y1;
  575. unsigned int dst = pbox->x1 * cpp + pbox->y1 * pitch;
  576. unsigned int start = dst;
  577. if (pbox->x1 > pbox->x2 ||
  578. pbox->y1 > pbox->y2 ||
  579. pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h)
  580. continue;
  581. BEGIN_LP_RING(6);
  582. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_SRC_COPY_BLT | 0x4);
  583. OUT_RING(pitch | (0xCC << 16));
  584. OUT_RING((h << 16) | (w * cpp));
  585. if (dev_priv->current_page == 0)
  586. OUT_RING(dev_priv->front_offset + start);
  587. else
  588. OUT_RING(dev_priv->back_offset + start);
  589. OUT_RING(pitch);
  590. if (dev_priv->current_page == 0)
  591. OUT_RING(dev_priv->back_offset + start);
  592. else
  593. OUT_RING(dev_priv->front_offset + start);
  594. ADVANCE_LP_RING();
  595. }
  596. }
  597. static void i810_dma_dispatch_vertex(struct drm_device *dev,
  598. struct drm_buf *buf, int discard, int used)
  599. {
  600. drm_i810_private_t *dev_priv = dev->dev_private;
  601. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  602. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  603. struct drm_clip_rect *box = sarea_priv->boxes;
  604. int nbox = sarea_priv->nbox;
  605. unsigned long address = (unsigned long)buf->bus_address;
  606. unsigned long start = address - dev->agp->base;
  607. int i = 0;
  608. RING_LOCALS;
  609. i810_kernel_lost_context(dev);
  610. if (nbox > I810_NR_SAREA_CLIPRECTS)
  611. nbox = I810_NR_SAREA_CLIPRECTS;
  612. if (used > 4 * 1024)
  613. used = 0;
  614. if (sarea_priv->dirty)
  615. i810EmitState(dev);
  616. if (buf_priv->currently_mapped == I810_BUF_MAPPED) {
  617. unsigned int prim = (sarea_priv->vertex_prim & PR_MASK);
  618. *(u32 *) buf_priv->kernel_virtual =
  619. ((GFX_OP_PRIMITIVE | prim | ((used / 4) - 2)));
  620. if (used & 4) {
  621. *(u32 *) ((char *) buf_priv->kernel_virtual + used) = 0;
  622. used += 4;
  623. }
  624. i810_unmap_buffer(buf);
  625. }
  626. if (used) {
  627. do {
  628. if (i < nbox) {
  629. BEGIN_LP_RING(4);
  630. OUT_RING(GFX_OP_SCISSOR | SC_UPDATE_SCISSOR |
  631. SC_ENABLE);
  632. OUT_RING(GFX_OP_SCISSOR_INFO);
  633. OUT_RING(box[i].x1 | (box[i].y1 << 16));
  634. OUT_RING((box[i].x2 -
  635. 1) | ((box[i].y2 - 1) << 16));
  636. ADVANCE_LP_RING();
  637. }
  638. BEGIN_LP_RING(4);
  639. OUT_RING(CMD_OP_BATCH_BUFFER);
  640. OUT_RING(start | BB1_PROTECTED);
  641. OUT_RING(start + used - 4);
  642. OUT_RING(0);
  643. ADVANCE_LP_RING();
  644. } while (++i < nbox);
  645. }
  646. if (discard) {
  647. dev_priv->counter++;
  648. (void)cmpxchg(buf_priv->in_use, I810_BUF_CLIENT,
  649. I810_BUF_HARDWARE);
  650. BEGIN_LP_RING(8);
  651. OUT_RING(CMD_STORE_DWORD_IDX);
  652. OUT_RING(20);
  653. OUT_RING(dev_priv->counter);
  654. OUT_RING(CMD_STORE_DWORD_IDX);
  655. OUT_RING(buf_priv->my_use_idx);
  656. OUT_RING(I810_BUF_FREE);
  657. OUT_RING(CMD_REPORT_HEAD);
  658. OUT_RING(0);
  659. ADVANCE_LP_RING();
  660. }
  661. }
  662. static void i810_dma_dispatch_flip(struct drm_device *dev)
  663. {
  664. drm_i810_private_t *dev_priv = dev->dev_private;
  665. int pitch = dev_priv->pitch;
  666. RING_LOCALS;
  667. DRM_DEBUG("page=%d pfCurrentPage=%d\n",
  668. dev_priv->current_page,
  669. dev_priv->sarea_priv->pf_current_page);
  670. i810_kernel_lost_context(dev);
  671. BEGIN_LP_RING(2);
  672. OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
  673. OUT_RING(0);
  674. ADVANCE_LP_RING();
  675. BEGIN_LP_RING(I810_DEST_SETUP_SIZE + 2);
  676. /* On i815 at least ASYNC is buggy */
  677. /* pitch<<5 is from 11.2.8 p158,
  678. its the pitch / 8 then left shifted 8,
  679. so (pitch >> 3) << 8 */
  680. OUT_RING(CMD_OP_FRONTBUFFER_INFO | (pitch << 5) /*| ASYNC_FLIP */ );
  681. if (dev_priv->current_page == 0) {
  682. OUT_RING(dev_priv->back_offset);
  683. dev_priv->current_page = 1;
  684. } else {
  685. OUT_RING(dev_priv->front_offset);
  686. dev_priv->current_page = 0;
  687. }
  688. OUT_RING(0);
  689. ADVANCE_LP_RING();
  690. BEGIN_LP_RING(2);
  691. OUT_RING(CMD_OP_WAIT_FOR_EVENT | WAIT_FOR_PLANE_A_FLIP);
  692. OUT_RING(0);
  693. ADVANCE_LP_RING();
  694. /* Increment the frame counter. The client-side 3D driver must
  695. * throttle the framerate by waiting for this value before
  696. * performing the swapbuffer ioctl.
  697. */
  698. dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
  699. }
  700. static void i810_dma_quiescent(struct drm_device *dev)
  701. {
  702. drm_i810_private_t *dev_priv = dev->dev_private;
  703. RING_LOCALS;
  704. i810_kernel_lost_context(dev);
  705. BEGIN_LP_RING(4);
  706. OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
  707. OUT_RING(CMD_REPORT_HEAD);
  708. OUT_RING(0);
  709. OUT_RING(0);
  710. ADVANCE_LP_RING();
  711. i810_wait_ring(dev, dev_priv->ring.Size - 8);
  712. }
  713. static int i810_flush_queue(struct drm_device *dev)
  714. {
  715. drm_i810_private_t *dev_priv = dev->dev_private;
  716. struct drm_device_dma *dma = dev->dma;
  717. int i, ret = 0;
  718. RING_LOCALS;
  719. i810_kernel_lost_context(dev);
  720. BEGIN_LP_RING(2);
  721. OUT_RING(CMD_REPORT_HEAD);
  722. OUT_RING(0);
  723. ADVANCE_LP_RING();
  724. i810_wait_ring(dev, dev_priv->ring.Size - 8);
  725. for (i = 0; i < dma->buf_count; i++) {
  726. struct drm_buf *buf = dma->buflist[i];
  727. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  728. int used = cmpxchg(buf_priv->in_use, I810_BUF_HARDWARE,
  729. I810_BUF_FREE);
  730. if (used == I810_BUF_HARDWARE)
  731. DRM_DEBUG("reclaimed from HARDWARE\n");
  732. if (used == I810_BUF_CLIENT)
  733. DRM_DEBUG("still on client\n");
  734. }
  735. return ret;
  736. }
  737. /* Must be called with the lock held */
  738. static void i810_reclaim_buffers(struct drm_device *dev,
  739. struct drm_file *file_priv)
  740. {
  741. struct drm_device_dma *dma = dev->dma;
  742. int i;
  743. if (!dma)
  744. return;
  745. if (!dev->dev_private)
  746. return;
  747. if (!dma->buflist)
  748. return;
  749. i810_flush_queue(dev);
  750. for (i = 0; i < dma->buf_count; i++) {
  751. struct drm_buf *buf = dma->buflist[i];
  752. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  753. if (buf->file_priv == file_priv && buf_priv) {
  754. int used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT,
  755. I810_BUF_FREE);
  756. if (used == I810_BUF_CLIENT)
  757. DRM_DEBUG("reclaimed from client\n");
  758. if (buf_priv->currently_mapped == I810_BUF_MAPPED)
  759. buf_priv->currently_mapped = I810_BUF_UNMAPPED;
  760. }
  761. }
  762. }
  763. static int i810_flush_ioctl(struct drm_device *dev, void *data,
  764. struct drm_file *file_priv)
  765. {
  766. LOCK_TEST_WITH_RETURN(dev, file_priv);
  767. i810_flush_queue(dev);
  768. return 0;
  769. }
  770. static int i810_dma_vertex(struct drm_device *dev, void *data,
  771. struct drm_file *file_priv)
  772. {
  773. struct drm_device_dma *dma = dev->dma;
  774. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  775. u32 *hw_status = dev_priv->hw_status_page;
  776. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  777. dev_priv->sarea_priv;
  778. drm_i810_vertex_t *vertex = data;
  779. LOCK_TEST_WITH_RETURN(dev, file_priv);
  780. DRM_DEBUG("idx %d used %d discard %d\n",
  781. vertex->idx, vertex->used, vertex->discard);
  782. if (vertex->idx < 0 || vertex->idx > dma->buf_count)
  783. return -EINVAL;
  784. i810_dma_dispatch_vertex(dev,
  785. dma->buflist[vertex->idx],
  786. vertex->discard, vertex->used);
  787. atomic_add(vertex->used, &dev->counts[_DRM_STAT_SECONDARY]);
  788. atomic_inc(&dev->counts[_DRM_STAT_DMA]);
  789. sarea_priv->last_enqueue = dev_priv->counter - 1;
  790. sarea_priv->last_dispatch = (int)hw_status[5];
  791. return 0;
  792. }
  793. static int i810_clear_bufs(struct drm_device *dev, void *data,
  794. struct drm_file *file_priv)
  795. {
  796. drm_i810_clear_t *clear = data;
  797. LOCK_TEST_WITH_RETURN(dev, file_priv);
  798. /* GH: Someone's doing nasty things... */
  799. if (!dev->dev_private)
  800. return -EINVAL;
  801. i810_dma_dispatch_clear(dev, clear->flags,
  802. clear->clear_color, clear->clear_depth);
  803. return 0;
  804. }
  805. static int i810_swap_bufs(struct drm_device *dev, void *data,
  806. struct drm_file *file_priv)
  807. {
  808. DRM_DEBUG("\n");
  809. LOCK_TEST_WITH_RETURN(dev, file_priv);
  810. i810_dma_dispatch_swap(dev);
  811. return 0;
  812. }
  813. static int i810_getage(struct drm_device *dev, void *data,
  814. struct drm_file *file_priv)
  815. {
  816. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  817. u32 *hw_status = dev_priv->hw_status_page;
  818. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  819. dev_priv->sarea_priv;
  820. sarea_priv->last_dispatch = (int)hw_status[5];
  821. return 0;
  822. }
  823. static int i810_getbuf(struct drm_device *dev, void *data,
  824. struct drm_file *file_priv)
  825. {
  826. int retcode = 0;
  827. drm_i810_dma_t *d = data;
  828. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  829. u32 *hw_status = dev_priv->hw_status_page;
  830. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  831. dev_priv->sarea_priv;
  832. LOCK_TEST_WITH_RETURN(dev, file_priv);
  833. d->granted = 0;
  834. retcode = i810_dma_get_buffer(dev, d, file_priv);
  835. DRM_DEBUG("i810_dma: %d returning %d, granted = %d\n",
  836. task_pid_nr(current), retcode, d->granted);
  837. sarea_priv->last_dispatch = (int)hw_status[5];
  838. return retcode;
  839. }
  840. static int i810_copybuf(struct drm_device *dev, void *data,
  841. struct drm_file *file_priv)
  842. {
  843. /* Never copy - 2.4.x doesn't need it */
  844. return 0;
  845. }
  846. static int i810_docopy(struct drm_device *dev, void *data,
  847. struct drm_file *file_priv)
  848. {
  849. /* Never copy - 2.4.x doesn't need it */
  850. return 0;
  851. }
  852. static void i810_dma_dispatch_mc(struct drm_device *dev, struct drm_buf *buf, int used,
  853. unsigned int last_render)
  854. {
  855. drm_i810_private_t *dev_priv = dev->dev_private;
  856. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  857. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  858. unsigned long address = (unsigned long)buf->bus_address;
  859. unsigned long start = address - dev->agp->base;
  860. int u;
  861. RING_LOCALS;
  862. i810_kernel_lost_context(dev);
  863. u = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_HARDWARE);
  864. if (u != I810_BUF_CLIENT)
  865. DRM_DEBUG("MC found buffer that isn't mine!\n");
  866. if (used > 4 * 1024)
  867. used = 0;
  868. sarea_priv->dirty = 0x7f;
  869. DRM_DEBUG("addr 0x%lx, used 0x%x\n", address, used);
  870. dev_priv->counter++;
  871. DRM_DEBUG("dispatch counter : %ld\n", dev_priv->counter);
  872. DRM_DEBUG("start : %lx\n", start);
  873. DRM_DEBUG("used : %d\n", used);
  874. DRM_DEBUG("start + used - 4 : %ld\n", start + used - 4);
  875. if (buf_priv->currently_mapped == I810_BUF_MAPPED) {
  876. if (used & 4) {
  877. *(u32 *) ((char *) buf_priv->virtual + used) = 0;
  878. used += 4;
  879. }
  880. i810_unmap_buffer(buf);
  881. }
  882. BEGIN_LP_RING(4);
  883. OUT_RING(CMD_OP_BATCH_BUFFER);
  884. OUT_RING(start | BB1_PROTECTED);
  885. OUT_RING(start + used - 4);
  886. OUT_RING(0);
  887. ADVANCE_LP_RING();
  888. BEGIN_LP_RING(8);
  889. OUT_RING(CMD_STORE_DWORD_IDX);
  890. OUT_RING(buf_priv->my_use_idx);
  891. OUT_RING(I810_BUF_FREE);
  892. OUT_RING(0);
  893. OUT_RING(CMD_STORE_DWORD_IDX);
  894. OUT_RING(16);
  895. OUT_RING(last_render);
  896. OUT_RING(0);
  897. ADVANCE_LP_RING();
  898. }
  899. static int i810_dma_mc(struct drm_device *dev, void *data,
  900. struct drm_file *file_priv)
  901. {
  902. struct drm_device_dma *dma = dev->dma;
  903. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  904. u32 *hw_status = dev_priv->hw_status_page;
  905. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  906. dev_priv->sarea_priv;
  907. drm_i810_mc_t *mc = data;
  908. LOCK_TEST_WITH_RETURN(dev, file_priv);
  909. if (mc->idx >= dma->buf_count || mc->idx < 0)
  910. return -EINVAL;
  911. i810_dma_dispatch_mc(dev, dma->buflist[mc->idx], mc->used,
  912. mc->last_render);
  913. atomic_add(mc->used, &dev->counts[_DRM_STAT_SECONDARY]);
  914. atomic_inc(&dev->counts[_DRM_STAT_DMA]);
  915. sarea_priv->last_enqueue = dev_priv->counter - 1;
  916. sarea_priv->last_dispatch = (int)hw_status[5];
  917. return 0;
  918. }
  919. static int i810_rstatus(struct drm_device *dev, void *data,
  920. struct drm_file *file_priv)
  921. {
  922. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  923. return (int)(((u32 *) (dev_priv->hw_status_page))[4]);
  924. }
  925. static int i810_ov0_info(struct drm_device *dev, void *data,
  926. struct drm_file *file_priv)
  927. {
  928. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  929. drm_i810_overlay_t *ov = data;
  930. ov->offset = dev_priv->overlay_offset;
  931. ov->physical = dev_priv->overlay_physical;
  932. return 0;
  933. }
  934. static int i810_fstatus(struct drm_device *dev, void *data,
  935. struct drm_file *file_priv)
  936. {
  937. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  938. LOCK_TEST_WITH_RETURN(dev, file_priv);
  939. return I810_READ(0x30008);
  940. }
  941. static int i810_ov0_flip(struct drm_device *dev, void *data,
  942. struct drm_file *file_priv)
  943. {
  944. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  945. LOCK_TEST_WITH_RETURN(dev, file_priv);
  946. /* Tell the overlay to update */
  947. I810_WRITE(0x30000, dev_priv->overlay_physical | 0x80000000);
  948. return 0;
  949. }
  950. /* Not sure why this isn't set all the time:
  951. */
  952. static void i810_do_init_pageflip(struct drm_device *dev)
  953. {
  954. drm_i810_private_t *dev_priv = dev->dev_private;
  955. DRM_DEBUG("\n");
  956. dev_priv->page_flipping = 1;
  957. dev_priv->current_page = 0;
  958. dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
  959. }
  960. static int i810_do_cleanup_pageflip(struct drm_device *dev)
  961. {
  962. drm_i810_private_t *dev_priv = dev->dev_private;
  963. DRM_DEBUG("\n");
  964. if (dev_priv->current_page != 0)
  965. i810_dma_dispatch_flip(dev);
  966. dev_priv->page_flipping = 0;
  967. return 0;
  968. }
  969. static int i810_flip_bufs(struct drm_device *dev, void *data,
  970. struct drm_file *file_priv)
  971. {
  972. drm_i810_private_t *dev_priv = dev->dev_private;
  973. DRM_DEBUG("\n");
  974. LOCK_TEST_WITH_RETURN(dev, file_priv);
  975. if (!dev_priv->page_flipping)
  976. i810_do_init_pageflip(dev);
  977. i810_dma_dispatch_flip(dev);
  978. return 0;
  979. }
  980. int i810_driver_load(struct drm_device *dev, unsigned long flags)
  981. {
  982. /* i810 has 4 more counters */
  983. dev->counters += 4;
  984. dev->types[6] = _DRM_STAT_IRQ;
  985. dev->types[7] = _DRM_STAT_PRIMARY;
  986. dev->types[8] = _DRM_STAT_SECONDARY;
  987. dev->types[9] = _DRM_STAT_DMA;
  988. return 0;
  989. }
  990. void i810_driver_lastclose(struct drm_device *dev)
  991. {
  992. i810_dma_cleanup(dev);
  993. }
  994. void i810_driver_preclose(struct drm_device *dev, struct drm_file *file_priv)
  995. {
  996. if (dev->dev_private) {
  997. drm_i810_private_t *dev_priv = dev->dev_private;
  998. if (dev_priv->page_flipping)
  999. i810_do_cleanup_pageflip(dev);
  1000. }
  1001. }
  1002. void i810_driver_reclaim_buffers_locked(struct drm_device *dev,
  1003. struct drm_file *file_priv)
  1004. {
  1005. i810_reclaim_buffers(dev, file_priv);
  1006. }
  1007. int i810_driver_dma_quiescent(struct drm_device *dev)
  1008. {
  1009. i810_dma_quiescent(dev);
  1010. return 0;
  1011. }
  1012. struct drm_ioctl_desc i810_ioctls[] = {
  1013. DRM_IOCTL_DEF_DRV(I810_INIT, i810_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
  1014. DRM_IOCTL_DEF_DRV(I810_VERTEX, i810_dma_vertex, DRM_AUTH|DRM_UNLOCKED),
  1015. DRM_IOCTL_DEF_DRV(I810_CLEAR, i810_clear_bufs, DRM_AUTH|DRM_UNLOCKED),
  1016. DRM_IOCTL_DEF_DRV(I810_FLUSH, i810_flush_ioctl, DRM_AUTH|DRM_UNLOCKED),
  1017. DRM_IOCTL_DEF_DRV(I810_GETAGE, i810_getage, DRM_AUTH|DRM_UNLOCKED),
  1018. DRM_IOCTL_DEF_DRV(I810_GETBUF, i810_getbuf, DRM_AUTH|DRM_UNLOCKED),
  1019. DRM_IOCTL_DEF_DRV(I810_SWAP, i810_swap_bufs, DRM_AUTH|DRM_UNLOCKED),
  1020. DRM_IOCTL_DEF_DRV(I810_COPY, i810_copybuf, DRM_AUTH|DRM_UNLOCKED),
  1021. DRM_IOCTL_DEF_DRV(I810_DOCOPY, i810_docopy, DRM_AUTH|DRM_UNLOCKED),
  1022. DRM_IOCTL_DEF_DRV(I810_OV0INFO, i810_ov0_info, DRM_AUTH|DRM_UNLOCKED),
  1023. DRM_IOCTL_DEF_DRV(I810_FSTATUS, i810_fstatus, DRM_AUTH|DRM_UNLOCKED),
  1024. DRM_IOCTL_DEF_DRV(I810_OV0FLIP, i810_ov0_flip, DRM_AUTH|DRM_UNLOCKED),
  1025. DRM_IOCTL_DEF_DRV(I810_MC, i810_dma_mc, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
  1026. DRM_IOCTL_DEF_DRV(I810_RSTATUS, i810_rstatus, DRM_AUTH|DRM_UNLOCKED),
  1027. DRM_IOCTL_DEF_DRV(I810_FLIP, i810_flip_bufs, DRM_AUTH|DRM_UNLOCKED),
  1028. };
  1029. int i810_max_ioctl = DRM_ARRAY_SIZE(i810_ioctls);
  1030. /**
  1031. * Determine if the device really is AGP or not.
  1032. *
  1033. * All Intel graphics chipsets are treated as AGP, even if they are really
  1034. * PCI-e.
  1035. *
  1036. * \param dev The device to be tested.
  1037. *
  1038. * \returns
  1039. * A value of 1 is always retured to indictate every i810 is AGP.
  1040. */
  1041. int i810_driver_device_is_agp(struct drm_device *dev)
  1042. {
  1043. return 1;
  1044. }