sbc8560.c 6.3 KB

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  1. /*
  2. * Wind River SBC8560 setup and early boot code.
  3. *
  4. * Copyright 2007 Wind River Systems Inc.
  5. *
  6. * By Paul Gortmaker (see MAINTAINERS for contact information)
  7. *
  8. * Based largely on the MPC8560ADS support - Copyright 2005 Freescale Inc.
  9. *
  10. * This program is free software; you can redistribute it and/or modify it
  11. * under the terms of the GNU General Public License as published by the
  12. * Free Software Foundation; either version 2 of the License, or (at your
  13. * option) any later version.
  14. */
  15. #include <linux/stddef.h>
  16. #include <linux/kernel.h>
  17. #include <linux/pci.h>
  18. #include <linux/kdev_t.h>
  19. #include <linux/delay.h>
  20. #include <linux/seq_file.h>
  21. #include <linux/of_platform.h>
  22. #include <asm/system.h>
  23. #include <asm/time.h>
  24. #include <asm/machdep.h>
  25. #include <asm/pci-bridge.h>
  26. #include <asm/mpic.h>
  27. #include <mm/mmu_decl.h>
  28. #include <asm/udbg.h>
  29. #include <sysdev/fsl_soc.h>
  30. #include <sysdev/fsl_pci.h>
  31. #include "mpc85xx.h"
  32. #ifdef CONFIG_CPM2
  33. #include <asm/cpm2.h>
  34. #include <sysdev/cpm2_pic.h>
  35. #endif
  36. static void __init sbc8560_pic_init(void)
  37. {
  38. struct mpic *mpic = mpic_alloc(NULL, 0,
  39. MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
  40. 0, 256, " OpenPIC ");
  41. BUG_ON(mpic == NULL);
  42. mpic_init(mpic);
  43. mpc85xx_cpm2_pic_init();
  44. }
  45. /*
  46. * Setup the architecture
  47. */
  48. #ifdef CONFIG_CPM2
  49. struct cpm_pin {
  50. int port, pin, flags;
  51. };
  52. static const struct cpm_pin sbc8560_pins[] = {
  53. /* SCC1 */
  54. {3, 29, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  55. {3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
  56. {3, 31, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  57. /* SCC2 */
  58. {3, 26, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  59. {3, 27, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  60. {3, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  61. /* FCC2 */
  62. {1, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  63. {1, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  64. {1, 20, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  65. {1, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  66. {1, 22, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  67. {1, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  68. {1, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  69. {1, 25, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  70. {1, 26, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  71. {1, 27, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  72. {1, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  73. {1, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
  74. {1, 30, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  75. {1, 31, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  76. {2, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK14 */
  77. {2, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK13 */
  78. /* FCC3 */
  79. {1, 4, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  80. {1, 5, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  81. {1, 6, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  82. {1, 7, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  83. {1, 8, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  84. {1, 9, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  85. {1, 10, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  86. {1, 11, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  87. {1, 12, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  88. {1, 13, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  89. {1, 14, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  90. {1, 15, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  91. {1, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  92. {1, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  93. {2, 16, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* CLK16 */
  94. {2, 17, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* CLK15 */
  95. };
  96. static void __init init_ioports(void)
  97. {
  98. int i;
  99. for (i = 0; i < ARRAY_SIZE(sbc8560_pins); i++) {
  100. const struct cpm_pin *pin = &sbc8560_pins[i];
  101. cpm2_set_pin(pin->port, pin->pin, pin->flags);
  102. }
  103. cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_RX);
  104. cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_TX);
  105. cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_RX);
  106. cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_TX);
  107. cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK13, CPM_CLK_RX);
  108. cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK14, CPM_CLK_TX);
  109. cpm2_clk_setup(CPM_CLK_FCC3, CPM_CLK15, CPM_CLK_RX);
  110. cpm2_clk_setup(CPM_CLK_FCC3, CPM_CLK16, CPM_CLK_TX);
  111. }
  112. #endif
  113. static void __init sbc8560_setup_arch(void)
  114. {
  115. #ifdef CONFIG_PCI
  116. struct device_node *np;
  117. #endif
  118. if (ppc_md.progress)
  119. ppc_md.progress("sbc8560_setup_arch()", 0);
  120. #ifdef CONFIG_CPM2
  121. cpm2_reset();
  122. init_ioports();
  123. #endif
  124. #ifdef CONFIG_PCI
  125. for_each_compatible_node(np, "pci", "fsl,mpc8540-pci")
  126. fsl_add_bridge(np, 1);
  127. #endif
  128. }
  129. static void sbc8560_show_cpuinfo(struct seq_file *m)
  130. {
  131. uint pvid, svid, phid1;
  132. pvid = mfspr(SPRN_PVR);
  133. svid = mfspr(SPRN_SVR);
  134. seq_printf(m, "Vendor\t\t: Wind River\n");
  135. seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
  136. seq_printf(m, "SVR\t\t: 0x%x\n", svid);
  137. /* Display cpu Pll setting */
  138. phid1 = mfspr(SPRN_HID1);
  139. seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
  140. }
  141. machine_device_initcall(sbc8560, mpc85xx_common_publish_devices);
  142. /*
  143. * Called very early, device-tree isn't unflattened
  144. */
  145. static int __init sbc8560_probe(void)
  146. {
  147. unsigned long root = of_get_flat_dt_root();
  148. return of_flat_dt_is_compatible(root, "SBC8560");
  149. }
  150. #ifdef CONFIG_RTC_DRV_M48T59
  151. static int __init sbc8560_rtc_init(void)
  152. {
  153. struct device_node *np;
  154. struct resource res;
  155. struct platform_device *rtc_dev;
  156. np = of_find_compatible_node(NULL, NULL, "m48t59");
  157. if (np == NULL) {
  158. printk("No RTC in DTB. Has it been eaten by wild dogs?\n");
  159. return -ENODEV;
  160. }
  161. of_address_to_resource(np, 0, &res);
  162. of_node_put(np);
  163. printk("Found RTC (m48t59) at i/o 0x%x\n", res.start);
  164. rtc_dev = platform_device_register_simple("rtc-m48t59", 0, &res, 1);
  165. if (IS_ERR(rtc_dev)) {
  166. printk("Registering sbc8560 RTC device failed\n");
  167. return PTR_ERR(rtc_dev);
  168. }
  169. return 0;
  170. }
  171. arch_initcall(sbc8560_rtc_init);
  172. #endif /* M48T59 */
  173. static __u8 __iomem *brstcr;
  174. static int __init sbc8560_bdrstcr_init(void)
  175. {
  176. struct device_node *np;
  177. struct resource res;
  178. np = of_find_compatible_node(NULL, NULL, "wrs,sbc8560-brstcr");
  179. if (np == NULL) {
  180. printk(KERN_WARNING "sbc8560: No board specific RSTCR in DTB.\n");
  181. return -ENODEV;
  182. }
  183. of_address_to_resource(np, 0, &res);
  184. printk(KERN_INFO "sbc8560: Found BRSTCR at %pR\n", &res);
  185. brstcr = ioremap(res.start, resource_size(&res));
  186. if(!brstcr)
  187. printk(KERN_WARNING "sbc8560: ioremap of brstcr failed.\n");
  188. of_node_put(np);
  189. return 0;
  190. }
  191. arch_initcall(sbc8560_bdrstcr_init);
  192. void sbc8560_rstcr_restart(char * cmd)
  193. {
  194. local_irq_disable();
  195. if(brstcr)
  196. clrbits8(brstcr, 0x80);
  197. while(1);
  198. }
  199. define_machine(sbc8560) {
  200. .name = "SBC8560",
  201. .probe = sbc8560_probe,
  202. .setup_arch = sbc8560_setup_arch,
  203. .init_IRQ = sbc8560_pic_init,
  204. .show_cpuinfo = sbc8560_show_cpuinfo,
  205. .get_irq = mpic_get_irq,
  206. .restart = sbc8560_rstcr_restart,
  207. .calibrate_decr = generic_calibrate_decr,
  208. .progress = udbg_progress,
  209. };