p2041si-pre.dtsi 3.1 KB

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  1. /*
  2. * P2041 Silicon/SoC Device Tree Source (pre include)
  3. *
  4. * Copyright 2011 Freescale Semiconductor Inc.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * * Neither the name of Freescale Semiconductor nor the
  14. * names of its contributors may be used to endorse or promote products
  15. * derived from this software without specific prior written permission.
  16. *
  17. *
  18. * ALTERNATIVELY, this software may be distributed under the terms of the
  19. * GNU General Public License ("GPL") as published by the Free Software
  20. * Foundation, either version 2 of that License or (at your option) any
  21. * later version.
  22. *
  23. * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24. * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26. * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33. */
  34. /dts-v1/;
  35. / {
  36. compatible = "fsl,P2041";
  37. #address-cells = <2>;
  38. #size-cells = <2>;
  39. interrupt-parent = <&mpic>;
  40. aliases {
  41. ccsr = &soc;
  42. dcsr = &dcsr;
  43. serial0 = &serial0;
  44. serial1 = &serial1;
  45. serial2 = &serial2;
  46. serial3 = &serial3;
  47. pci0 = &pci0;
  48. pci1 = &pci1;
  49. pci2 = &pci2;
  50. usb0 = &usb0;
  51. usb1 = &usb1;
  52. dma0 = &dma0;
  53. dma1 = &dma1;
  54. sdhc = &sdhc;
  55. msi0 = &msi0;
  56. msi1 = &msi1;
  57. msi2 = &msi2;
  58. crypto = &crypto;
  59. sec_jr0 = &sec_jr0;
  60. sec_jr1 = &sec_jr1;
  61. sec_jr2 = &sec_jr2;
  62. sec_jr3 = &sec_jr3;
  63. rtic_a = &rtic_a;
  64. rtic_b = &rtic_b;
  65. rtic_c = &rtic_c;
  66. rtic_d = &rtic_d;
  67. sec_mon = &sec_mon;
  68. };
  69. cpus {
  70. #address-cells = <1>;
  71. #size-cells = <0>;
  72. cpu0: PowerPC,e500mc@0 {
  73. device_type = "cpu";
  74. reg = <0>;
  75. next-level-cache = <&L2_0>;
  76. L2_0: l2-cache {
  77. next-level-cache = <&cpc>;
  78. };
  79. };
  80. cpu1: PowerPC,e500mc@1 {
  81. device_type = "cpu";
  82. reg = <1>;
  83. next-level-cache = <&L2_1>;
  84. L2_1: l2-cache {
  85. next-level-cache = <&cpc>;
  86. };
  87. };
  88. cpu2: PowerPC,e500mc@2 {
  89. device_type = "cpu";
  90. reg = <2>;
  91. next-level-cache = <&L2_2>;
  92. L2_2: l2-cache {
  93. next-level-cache = <&cpc>;
  94. };
  95. };
  96. cpu3: PowerPC,e500mc@3 {
  97. device_type = "cpu";
  98. reg = <3>;
  99. next-level-cache = <&L2_3>;
  100. L2_3: l2-cache {
  101. next-level-cache = <&cpc>;
  102. };
  103. };
  104. };
  105. };