ar71xx_regs.h 9.6 KB

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  1. /*
  2. * Atheros AR71XX/AR724X/AR913X SoC register definitions
  3. *
  4. * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
  5. * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  6. *
  7. * Parts of this file are based on Atheros' 2.6.15 BSP
  8. *
  9. * This program is free software; you can redistribute it and/or modify it
  10. * under the terms of the GNU General Public License version 2 as published
  11. * by the Free Software Foundation.
  12. */
  13. #ifndef __ASM_MACH_AR71XX_REGS_H
  14. #define __ASM_MACH_AR71XX_REGS_H
  15. #include <linux/types.h>
  16. #include <linux/init.h>
  17. #include <linux/io.h>
  18. #include <linux/bitops.h>
  19. #define AR71XX_APB_BASE 0x18000000
  20. #define AR71XX_EHCI_BASE 0x1b000000
  21. #define AR71XX_EHCI_SIZE 0x1000
  22. #define AR71XX_OHCI_BASE 0x1c000000
  23. #define AR71XX_OHCI_SIZE 0x1000
  24. #define AR71XX_SPI_BASE 0x1f000000
  25. #define AR71XX_SPI_SIZE 0x01000000
  26. #define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000)
  27. #define AR71XX_DDR_CTRL_SIZE 0x100
  28. #define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)
  29. #define AR71XX_UART_SIZE 0x100
  30. #define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
  31. #define AR71XX_USB_CTRL_SIZE 0x100
  32. #define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000)
  33. #define AR71XX_GPIO_SIZE 0x100
  34. #define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
  35. #define AR71XX_PLL_SIZE 0x100
  36. #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
  37. #define AR71XX_RESET_SIZE 0x100
  38. #define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
  39. #define AR7240_USB_CTRL_SIZE 0x100
  40. #define AR7240_OHCI_BASE 0x1b000000
  41. #define AR7240_OHCI_SIZE 0x1000
  42. #define AR724X_EHCI_BASE 0x1b000000
  43. #define AR724X_EHCI_SIZE 0x1000
  44. #define AR913X_EHCI_BASE 0x1b000000
  45. #define AR913X_EHCI_SIZE 0x1000
  46. #define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
  47. #define AR913X_WMAC_SIZE 0x30000
  48. #define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
  49. #define AR933X_UART_SIZE 0x14
  50. #define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
  51. #define AR933X_WMAC_SIZE 0x20000
  52. #define AR933X_EHCI_BASE 0x1b000000
  53. #define AR933X_EHCI_SIZE 0x1000
  54. /*
  55. * DDR_CTRL block
  56. */
  57. #define AR71XX_DDR_REG_PCI_WIN0 0x7c
  58. #define AR71XX_DDR_REG_PCI_WIN1 0x80
  59. #define AR71XX_DDR_REG_PCI_WIN2 0x84
  60. #define AR71XX_DDR_REG_PCI_WIN3 0x88
  61. #define AR71XX_DDR_REG_PCI_WIN4 0x8c
  62. #define AR71XX_DDR_REG_PCI_WIN5 0x90
  63. #define AR71XX_DDR_REG_PCI_WIN6 0x94
  64. #define AR71XX_DDR_REG_PCI_WIN7 0x98
  65. #define AR71XX_DDR_REG_FLUSH_GE0 0x9c
  66. #define AR71XX_DDR_REG_FLUSH_GE1 0xa0
  67. #define AR71XX_DDR_REG_FLUSH_USB 0xa4
  68. #define AR71XX_DDR_REG_FLUSH_PCI 0xa8
  69. #define AR724X_DDR_REG_FLUSH_GE0 0x7c
  70. #define AR724X_DDR_REG_FLUSH_GE1 0x80
  71. #define AR724X_DDR_REG_FLUSH_USB 0x84
  72. #define AR724X_DDR_REG_FLUSH_PCIE 0x88
  73. #define AR913X_DDR_REG_FLUSH_GE0 0x7c
  74. #define AR913X_DDR_REG_FLUSH_GE1 0x80
  75. #define AR913X_DDR_REG_FLUSH_USB 0x84
  76. #define AR913X_DDR_REG_FLUSH_WMAC 0x88
  77. #define AR933X_DDR_REG_FLUSH_GE0 0x7c
  78. #define AR933X_DDR_REG_FLUSH_GE1 0x80
  79. #define AR933X_DDR_REG_FLUSH_USB 0x84
  80. #define AR933X_DDR_REG_FLUSH_WMAC 0x88
  81. /*
  82. * PLL block
  83. */
  84. #define AR71XX_PLL_REG_CPU_CONFIG 0x00
  85. #define AR71XX_PLL_REG_SEC_CONFIG 0x04
  86. #define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10
  87. #define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14
  88. #define AR71XX_PLL_DIV_SHIFT 3
  89. #define AR71XX_PLL_DIV_MASK 0x1f
  90. #define AR71XX_CPU_DIV_SHIFT 16
  91. #define AR71XX_CPU_DIV_MASK 0x3
  92. #define AR71XX_DDR_DIV_SHIFT 18
  93. #define AR71XX_DDR_DIV_MASK 0x3
  94. #define AR71XX_AHB_DIV_SHIFT 20
  95. #define AR71XX_AHB_DIV_MASK 0x7
  96. #define AR724X_PLL_REG_CPU_CONFIG 0x00
  97. #define AR724X_PLL_REG_PCIE_CONFIG 0x18
  98. #define AR724X_PLL_DIV_SHIFT 0
  99. #define AR724X_PLL_DIV_MASK 0x3ff
  100. #define AR724X_PLL_REF_DIV_SHIFT 10
  101. #define AR724X_PLL_REF_DIV_MASK 0xf
  102. #define AR724X_AHB_DIV_SHIFT 19
  103. #define AR724X_AHB_DIV_MASK 0x1
  104. #define AR724X_DDR_DIV_SHIFT 22
  105. #define AR724X_DDR_DIV_MASK 0x3
  106. #define AR913X_PLL_REG_CPU_CONFIG 0x00
  107. #define AR913X_PLL_REG_ETH_CONFIG 0x04
  108. #define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
  109. #define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18
  110. #define AR913X_PLL_DIV_SHIFT 0
  111. #define AR913X_PLL_DIV_MASK 0x3ff
  112. #define AR913X_DDR_DIV_SHIFT 22
  113. #define AR913X_DDR_DIV_MASK 0x3
  114. #define AR913X_AHB_DIV_SHIFT 19
  115. #define AR913X_AHB_DIV_MASK 0x1
  116. #define AR933X_PLL_CPU_CONFIG_REG 0x00
  117. #define AR933X_PLL_CLOCK_CTRL_REG 0x08
  118. #define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10
  119. #define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f
  120. #define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16
  121. #define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
  122. #define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23
  123. #define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
  124. #define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2)
  125. #define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5
  126. #define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3
  127. #define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10
  128. #define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3
  129. #define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15
  130. #define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7
  131. /*
  132. * USB_CONFIG block
  133. */
  134. #define AR71XX_USB_CTRL_REG_FLADJ 0x00
  135. #define AR71XX_USB_CTRL_REG_CONFIG 0x04
  136. /*
  137. * RESET block
  138. */
  139. #define AR71XX_RESET_REG_TIMER 0x00
  140. #define AR71XX_RESET_REG_TIMER_RELOAD 0x04
  141. #define AR71XX_RESET_REG_WDOG_CTRL 0x08
  142. #define AR71XX_RESET_REG_WDOG 0x0c
  143. #define AR71XX_RESET_REG_MISC_INT_STATUS 0x10
  144. #define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14
  145. #define AR71XX_RESET_REG_PCI_INT_STATUS 0x18
  146. #define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c
  147. #define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20
  148. #define AR71XX_RESET_REG_RESET_MODULE 0x24
  149. #define AR71XX_RESET_REG_PERFC_CTRL 0x2c
  150. #define AR71XX_RESET_REG_PERFC0 0x30
  151. #define AR71XX_RESET_REG_PERFC1 0x34
  152. #define AR71XX_RESET_REG_REV_ID 0x90
  153. #define AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18
  154. #define AR913X_RESET_REG_RESET_MODULE 0x1c
  155. #define AR913X_RESET_REG_PERF_CTRL 0x20
  156. #define AR913X_RESET_REG_PERFC0 0x24
  157. #define AR913X_RESET_REG_PERFC1 0x28
  158. #define AR724X_RESET_REG_RESET_MODULE 0x1c
  159. #define AR933X_RESET_REG_RESET_MODULE 0x1c
  160. #define AR933X_RESET_REG_BOOTSTRAP 0xac
  161. #define MISC_INT_ETHSW BIT(12)
  162. #define MISC_INT_TIMER4 BIT(10)
  163. #define MISC_INT_TIMER3 BIT(9)
  164. #define MISC_INT_TIMER2 BIT(8)
  165. #define MISC_INT_DMA BIT(7)
  166. #define MISC_INT_OHCI BIT(6)
  167. #define MISC_INT_PERFC BIT(5)
  168. #define MISC_INT_WDOG BIT(4)
  169. #define MISC_INT_UART BIT(3)
  170. #define MISC_INT_GPIO BIT(2)
  171. #define MISC_INT_ERROR BIT(1)
  172. #define MISC_INT_TIMER BIT(0)
  173. #define AR71XX_RESET_EXTERNAL BIT(28)
  174. #define AR71XX_RESET_FULL_CHIP BIT(24)
  175. #define AR71XX_RESET_CPU_NMI BIT(21)
  176. #define AR71XX_RESET_CPU_COLD BIT(20)
  177. #define AR71XX_RESET_DMA BIT(19)
  178. #define AR71XX_RESET_SLIC BIT(18)
  179. #define AR71XX_RESET_STEREO BIT(17)
  180. #define AR71XX_RESET_DDR BIT(16)
  181. #define AR71XX_RESET_GE1_MAC BIT(13)
  182. #define AR71XX_RESET_GE1_PHY BIT(12)
  183. #define AR71XX_RESET_USBSUS_OVERRIDE BIT(10)
  184. #define AR71XX_RESET_GE0_MAC BIT(9)
  185. #define AR71XX_RESET_GE0_PHY BIT(8)
  186. #define AR71XX_RESET_USB_OHCI_DLL BIT(6)
  187. #define AR71XX_RESET_USB_HOST BIT(5)
  188. #define AR71XX_RESET_USB_PHY BIT(4)
  189. #define AR71XX_RESET_PCI_BUS BIT(1)
  190. #define AR71XX_RESET_PCI_CORE BIT(0)
  191. #define AR7240_RESET_USB_HOST BIT(5)
  192. #define AR7240_RESET_OHCI_DLL BIT(3)
  193. #define AR724X_RESET_GE1_MDIO BIT(23)
  194. #define AR724X_RESET_GE0_MDIO BIT(22)
  195. #define AR724X_RESET_PCIE_PHY_SERIAL BIT(10)
  196. #define AR724X_RESET_PCIE_PHY BIT(7)
  197. #define AR724X_RESET_PCIE BIT(6)
  198. #define AR724X_RESET_USB_HOST BIT(5)
  199. #define AR724X_RESET_USB_PHY BIT(4)
  200. #define AR724X_RESET_USBSUS_OVERRIDE BIT(3)
  201. #define AR913X_RESET_AMBA2WMAC BIT(22)
  202. #define AR913X_RESET_USBSUS_OVERRIDE BIT(10)
  203. #define AR913X_RESET_USB_HOST BIT(5)
  204. #define AR913X_RESET_USB_PHY BIT(4)
  205. #define AR933X_RESET_WMAC BIT(11)
  206. #define AR933X_RESET_USB_HOST BIT(5)
  207. #define AR933X_RESET_USB_PHY BIT(4)
  208. #define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
  209. #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
  210. #define REV_ID_MAJOR_MASK 0xfff0
  211. #define REV_ID_MAJOR_AR71XX 0x00a0
  212. #define REV_ID_MAJOR_AR913X 0x00b0
  213. #define REV_ID_MAJOR_AR7240 0x00c0
  214. #define REV_ID_MAJOR_AR7241 0x0100
  215. #define REV_ID_MAJOR_AR7242 0x1100
  216. #define REV_ID_MAJOR_AR9330 0x0110
  217. #define REV_ID_MAJOR_AR9331 0x1110
  218. #define AR71XX_REV_ID_MINOR_MASK 0x3
  219. #define AR71XX_REV_ID_MINOR_AR7130 0x0
  220. #define AR71XX_REV_ID_MINOR_AR7141 0x1
  221. #define AR71XX_REV_ID_MINOR_AR7161 0x2
  222. #define AR71XX_REV_ID_REVISION_MASK 0x3
  223. #define AR71XX_REV_ID_REVISION_SHIFT 2
  224. #define AR913X_REV_ID_MINOR_MASK 0x3
  225. #define AR913X_REV_ID_MINOR_AR9130 0x0
  226. #define AR913X_REV_ID_MINOR_AR9132 0x1
  227. #define AR913X_REV_ID_REVISION_MASK 0x3
  228. #define AR913X_REV_ID_REVISION_SHIFT 2
  229. #define AR933X_REV_ID_REVISION_MASK 0x3
  230. #define AR724X_REV_ID_REVISION_MASK 0x3
  231. /*
  232. * SPI block
  233. */
  234. #define AR71XX_SPI_REG_FS 0x00 /* Function Select */
  235. #define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */
  236. #define AR71XX_SPI_REG_IOC 0x08 /* SPI I/O Control */
  237. #define AR71XX_SPI_REG_RDS 0x0c /* Read Data Shift */
  238. #define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */
  239. #define AR71XX_SPI_CTRL_RD BIT(6) /* Remap Disable */
  240. #define AR71XX_SPI_CTRL_DIV_MASK 0x3f
  241. #define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */
  242. #define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */
  243. #define AR71XX_SPI_IOC_CS(n) BIT(16 + (n))
  244. #define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0)
  245. #define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1)
  246. #define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2)
  247. #define AR71XX_SPI_IOC_CS_ALL (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | \
  248. AR71XX_SPI_IOC_CS2)
  249. /*
  250. * GPIO block
  251. */
  252. #define AR71XX_GPIO_REG_OE 0x00
  253. #define AR71XX_GPIO_REG_IN 0x04
  254. #define AR71XX_GPIO_REG_OUT 0x08
  255. #define AR71XX_GPIO_REG_SET 0x0c
  256. #define AR71XX_GPIO_REG_CLEAR 0x10
  257. #define AR71XX_GPIO_REG_INT_MODE 0x14
  258. #define AR71XX_GPIO_REG_INT_TYPE 0x18
  259. #define AR71XX_GPIO_REG_INT_POLARITY 0x1c
  260. #define AR71XX_GPIO_REG_INT_PENDING 0x20
  261. #define AR71XX_GPIO_REG_INT_ENABLE 0x24
  262. #define AR71XX_GPIO_REG_FUNC 0x28
  263. #define AR71XX_GPIO_COUNT 16
  264. #define AR724X_GPIO_COUNT 18
  265. #define AR913X_GPIO_COUNT 22
  266. #define AR933X_GPIO_COUNT 30
  267. #endif /* __ASM_MACH_AR71XX_REGS_H */