tll6527m.c 23 KB

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  1. /* File: arch/blackfin/mach-bf527/boards/tll6527m.c
  2. * Based on: arch/blackfin/mach-bf527/boards/ezkit.c
  3. * Author: Ashish Gupta
  4. *
  5. * Copyright: 2010 - The Learning Labs Inc.
  6. *
  7. * Licensed under the GPL-2 or later.
  8. */
  9. #include <linux/device.h>
  10. #include <linux/export.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/mtd/mtd.h>
  13. #include <linux/mtd/partitions.h>
  14. #include <linux/mtd/physmap.h>
  15. #include <linux/spi/spi.h>
  16. #include <linux/spi/flash.h>
  17. #include <linux/i2c.h>
  18. #include <linux/irq.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/usb/musb.h>
  21. #include <linux/leds.h>
  22. #include <linux/input.h>
  23. #include <asm/dma.h>
  24. #include <asm/bfin5xx_spi.h>
  25. #include <asm/reboot.h>
  26. #include <asm/nand.h>
  27. #include <asm/portmux.h>
  28. #include <asm/dpmc.h>
  29. #if defined(CONFIG_TOUCHSCREEN_AD7879) \
  30. || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
  31. #include <linux/spi/ad7879.h>
  32. #define LCD_BACKLIGHT_GPIO 0x40
  33. /* TLL6527M uses TLL7UIQ35 / ADI LCD EZ Extender. AD7879 AUX GPIO is used for
  34. * LCD Backlight Enable
  35. */
  36. #endif
  37. /*
  38. * Name the Board for the /proc/cpuinfo
  39. */
  40. const char bfin_board_name[] = "TLL6527M";
  41. /*
  42. * Driver needs to know address, irq and flag pin.
  43. */
  44. #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
  45. static struct resource musb_resources[] = {
  46. [0] = {
  47. .start = 0xffc03800,
  48. .end = 0xffc03cff,
  49. .flags = IORESOURCE_MEM,
  50. },
  51. [1] = { /* general IRQ */
  52. .start = IRQ_USB_INT0,
  53. .end = IRQ_USB_INT0,
  54. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  55. },
  56. [2] = { /* DMA IRQ */
  57. .start = IRQ_USB_DMA,
  58. .end = IRQ_USB_DMA,
  59. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  60. },
  61. };
  62. static struct musb_hdrc_config musb_config = {
  63. .multipoint = 0,
  64. .dyn_fifo = 0,
  65. .soft_con = 1,
  66. .dma = 1,
  67. .num_eps = 8,
  68. .dma_channels = 8,
  69. /*.gpio_vrsel = GPIO_PG13,*/
  70. /* Some custom boards need to be active low, just set it to "0"
  71. * if it is the case.
  72. */
  73. .gpio_vrsel_active = 1,
  74. };
  75. static struct musb_hdrc_platform_data musb_plat = {
  76. #if defined(CONFIG_USB_MUSB_OTG)
  77. .mode = MUSB_OTG,
  78. #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
  79. .mode = MUSB_HOST,
  80. #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
  81. .mode = MUSB_PERIPHERAL,
  82. #endif
  83. .config = &musb_config,
  84. };
  85. static u64 musb_dmamask = ~(u32)0;
  86. static struct platform_device musb_device = {
  87. .name = "musb-blackfin",
  88. .id = 0,
  89. .dev = {
  90. .dma_mask = &musb_dmamask,
  91. .coherent_dma_mask = 0xffffffff,
  92. .platform_data = &musb_plat,
  93. },
  94. .num_resources = ARRAY_SIZE(musb_resources),
  95. .resource = musb_resources,
  96. };
  97. #endif
  98. #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
  99. #include <asm/bfin-lq035q1.h>
  100. static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
  101. .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
  102. .ppi_mode = USE_RGB565_16_BIT_PPI,
  103. .use_bl = 1,
  104. .gpio_bl = LCD_BACKLIGHT_GPIO,
  105. };
  106. static struct resource bfin_lq035q1_resources[] = {
  107. {
  108. .start = IRQ_PPI_ERROR,
  109. .end = IRQ_PPI_ERROR,
  110. .flags = IORESOURCE_IRQ,
  111. },
  112. };
  113. static struct platform_device bfin_lq035q1_device = {
  114. .name = "bfin-lq035q1",
  115. .id = -1,
  116. .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
  117. .resource = bfin_lq035q1_resources,
  118. .dev = {
  119. .platform_data = &bfin_lq035q1_data,
  120. },
  121. };
  122. #endif
  123. #if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
  124. static struct mtd_partition tll6527m_partitions[] = {
  125. {
  126. .name = "bootloader(nor)",
  127. .size = 0xA0000,
  128. .offset = 0,
  129. }, {
  130. .name = "linux kernel(nor)",
  131. .size = 0xD00000,
  132. .offset = MTDPART_OFS_APPEND,
  133. }, {
  134. .name = "file system(nor)",
  135. .size = MTDPART_SIZ_FULL,
  136. .offset = MTDPART_OFS_APPEND,
  137. }
  138. };
  139. static struct physmap_flash_data tll6527m_flash_data = {
  140. .width = 2,
  141. .parts = tll6527m_partitions,
  142. .nr_parts = ARRAY_SIZE(tll6527m_partitions),
  143. };
  144. static unsigned tll6527m_flash_gpios[] = { GPIO_PG11, GPIO_PH11, GPIO_PH12 };
  145. static struct resource tll6527m_flash_resource[] = {
  146. {
  147. .name = "cfi_probe",
  148. .start = 0x20000000,
  149. .end = 0x201fffff,
  150. .flags = IORESOURCE_MEM,
  151. }, {
  152. .start = (unsigned long)tll6527m_flash_gpios,
  153. .end = ARRAY_SIZE(tll6527m_flash_gpios),
  154. .flags = IORESOURCE_IRQ,
  155. }
  156. };
  157. static struct platform_device tll6527m_flash_device = {
  158. .name = "gpio-addr-flash",
  159. .id = 0,
  160. .dev = {
  161. .platform_data = &tll6527m_flash_data,
  162. },
  163. .num_resources = ARRAY_SIZE(tll6527m_flash_resource),
  164. .resource = tll6527m_flash_resource,
  165. };
  166. #endif
  167. #if defined(CONFIG_GPIO_DECODER) || defined(CONFIG_GPIO_DECODER_MODULE)
  168. /* An SN74LVC138A 3:8 decoder chip has been used to generate 7 augmented
  169. * outputs used as SPI CS lines for all SPI SLAVE devices on TLL6527v1-0.
  170. * EXP_GPIO_SPISEL_BASE is the base number for the expanded outputs being
  171. * used as SPI CS lines, this should be > MAX_BLACKFIN_GPIOS
  172. */
  173. #include <linux/gpio-decoder.h>
  174. #define EXP_GPIO_SPISEL_BASE 0x64
  175. static unsigned gpio_addr_inputs[] = {
  176. GPIO_PG1, GPIO_PH9, GPIO_PH10
  177. };
  178. static struct gpio_decoder_platform_data spi_decoded_cs = {
  179. .base = EXP_GPIO_SPISEL_BASE,
  180. .input_addrs = gpio_addr_inputs,
  181. .nr_input_addrs = ARRAY_SIZE(gpio_addr_inputs),
  182. .default_output = 0,
  183. /* .default_output = (1 << ARRAY_SIZE(gpio_addr_inputs)) - 1 */
  184. };
  185. static struct platform_device spi_decoded_gpio = {
  186. .name = "gpio-decoder",
  187. .id = 0,
  188. .dev = {
  189. .platform_data = &spi_decoded_cs,
  190. },
  191. };
  192. #else
  193. #define EXP_GPIO_SPISEL_BASE 0x0
  194. #endif
  195. #if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE)
  196. #include <linux/input/adxl34x.h>
  197. static const struct adxl34x_platform_data adxl345_info = {
  198. .x_axis_offset = 0,
  199. .y_axis_offset = 0,
  200. .z_axis_offset = 0,
  201. .tap_threshold = 0x31,
  202. .tap_duration = 0x10,
  203. .tap_latency = 0x60,
  204. .tap_window = 0xF0,
  205. .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
  206. .act_axis_control = 0xFF,
  207. .activity_threshold = 5,
  208. .inactivity_threshold = 2,
  209. .inactivity_time = 2,
  210. .free_fall_threshold = 0x7,
  211. .free_fall_time = 0x20,
  212. .data_rate = 0x8,
  213. .data_range = ADXL_FULL_RES,
  214. .ev_type = EV_ABS,
  215. .ev_code_x = ABS_X, /* EV_REL */
  216. .ev_code_y = ABS_Y, /* EV_REL */
  217. .ev_code_z = ABS_Z, /* EV_REL */
  218. .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
  219. /* .ev_code_ff = KEY_F,*/ /* EV_KEY */
  220. .ev_code_act_inactivity = KEY_A, /* EV_KEY */
  221. .use_int2 = 1,
  222. .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
  223. .fifo_mode = ADXL_FIFO_STREAM,
  224. };
  225. #endif
  226. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  227. static struct platform_device rtc_device = {
  228. .name = "rtc-bfin",
  229. .id = -1,
  230. };
  231. #endif
  232. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  233. #include <linux/bfin_mac.h>
  234. static const unsigned short bfin_mac_peripherals[] = P_RMII0;
  235. static struct bfin_phydev_platform_data bfin_phydev_data[] = {
  236. {
  237. .addr = 1,
  238. .irq = IRQ_MAC_PHYINT,
  239. },
  240. };
  241. static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
  242. .phydev_number = 1,
  243. .phydev_data = bfin_phydev_data,
  244. .phy_mode = PHY_INTERFACE_MODE_RMII,
  245. .mac_peripherals = bfin_mac_peripherals,
  246. };
  247. static struct platform_device bfin_mii_bus = {
  248. .name = "bfin_mii_bus",
  249. .dev = {
  250. .platform_data = &bfin_mii_bus_data,
  251. }
  252. };
  253. static struct platform_device bfin_mac_device = {
  254. .name = "bfin_mac",
  255. .dev = {
  256. .platform_data = &bfin_mii_bus,
  257. }
  258. };
  259. #endif
  260. #if defined(CONFIG_MTD_M25P80) \
  261. || defined(CONFIG_MTD_M25P80_MODULE)
  262. static struct mtd_partition bfin_spi_flash_partitions[] = {
  263. {
  264. .name = "bootloader(spi)",
  265. .size = 0x00040000,
  266. .offset = 0,
  267. .mask_flags = MTD_CAP_ROM
  268. }, {
  269. .name = "linux kernel(spi)",
  270. .size = MTDPART_SIZ_FULL,
  271. .offset = MTDPART_OFS_APPEND,
  272. }
  273. };
  274. static struct flash_platform_data bfin_spi_flash_data = {
  275. .name = "m25p80",
  276. .parts = bfin_spi_flash_partitions,
  277. .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
  278. .type = "m25p16",
  279. };
  280. /* SPI flash chip (m25p64) */
  281. static struct bfin5xx_spi_chip spi_flash_chip_info = {
  282. .enable_dma = 0, /* use dma transfer with this chip*/
  283. };
  284. #endif
  285. #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
  286. static struct bfin5xx_spi_chip mmc_spi_chip_info = {
  287. .enable_dma = 0,
  288. };
  289. #endif
  290. #if defined(CONFIG_TOUCHSCREEN_AD7879) \
  291. || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
  292. static const struct ad7879_platform_data bfin_ad7879_ts_info = {
  293. .model = 7879, /* Model = AD7879 */
  294. .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
  295. .pressure_max = 10000,
  296. .pressure_min = 0,
  297. .first_conversion_delay = 3,
  298. /* wait 512us before do a first conversion */
  299. .acquisition_time = 1, /* 4us acquisition time per sample */
  300. .median = 2, /* do 8 measurements */
  301. .averaging = 1,
  302. /* take the average of 4 middle samples */
  303. .pen_down_acc_interval = 255, /* 9.4 ms */
  304. .gpio_export = 1, /* configure AUX as GPIO output*/
  305. .gpio_base = LCD_BACKLIGHT_GPIO,
  306. };
  307. #endif
  308. #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
  309. static struct platform_device bfin_i2s = {
  310. .name = "bfin-i2s",
  311. .id = CONFIG_SND_BF5XX_SPORT_NUM,
  312. /* TODO: add platform data here */
  313. };
  314. #endif
  315. #if defined(CONFIG_GPIO_MCP23S08) || defined(CONFIG_GPIO_MCP23S08_MODULE)
  316. #include <linux/spi/mcp23s08.h>
  317. static const struct mcp23s08_platform_data bfin_mcp23s08_sys_gpio_info = {
  318. .chip[0].is_present = true,
  319. .base = 0x30,
  320. };
  321. static const struct mcp23s08_platform_data bfin_mcp23s08_usr_gpio_info = {
  322. .chip[2].is_present = true,
  323. .base = 0x38,
  324. };
  325. #endif
  326. static struct spi_board_info bfin_spi_board_info[] __initdata = {
  327. #if defined(CONFIG_MTD_M25P80) \
  328. || defined(CONFIG_MTD_M25P80_MODULE)
  329. {
  330. /* the modalias must be the same as spi device driver name */
  331. .modalias = "m25p80", /* Name of spi_driver for this device */
  332. .max_speed_hz = 25000000,
  333. /* max spi clock (SCK) speed in HZ */
  334. .bus_num = 0, /* Framework bus number */
  335. .chip_select = EXP_GPIO_SPISEL_BASE + 0x04 + MAX_CTRL_CS,
  336. /* Can be connected to TLL6527M GPIO connector */
  337. /* Either SPI_ADC or M25P80 FLASH can be installed at a time */
  338. .platform_data = &bfin_spi_flash_data,
  339. .controller_data = &spi_flash_chip_info,
  340. .mode = SPI_MODE_3,
  341. },
  342. #endif
  343. #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
  344. {
  345. .modalias = "mmc_spi",
  346. /*
  347. * TLL6527M V1.0 does not support SD Card at SPI Clock > 10 MHz due to
  348. * SPI buffer limitations
  349. */
  350. .max_speed_hz = 10000000,
  351. /* max spi clock (SCK) speed in HZ */
  352. .bus_num = 0,
  353. .chip_select = EXP_GPIO_SPISEL_BASE + 0x05 + MAX_CTRL_CS,
  354. .controller_data = &mmc_spi_chip_info,
  355. .mode = SPI_MODE_0,
  356. },
  357. #endif
  358. #if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) \
  359. || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
  360. {
  361. .modalias = "ad7879",
  362. .platform_data = &bfin_ad7879_ts_info,
  363. .irq = IRQ_PH14,
  364. .max_speed_hz = 5000000,
  365. /* max spi clock (SCK) speed in HZ */
  366. .bus_num = 0,
  367. .chip_select = EXP_GPIO_SPISEL_BASE + 0x07 + MAX_CTRL_CS,
  368. .mode = SPI_CPHA | SPI_CPOL,
  369. },
  370. #endif
  371. #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
  372. {
  373. .modalias = "spidev",
  374. .max_speed_hz = 10000000,
  375. /* TLL6527Mv1-0 supports max spi clock (SCK) speed = 10 MHz */
  376. .bus_num = 0,
  377. .chip_select = EXP_GPIO_SPISEL_BASE + 0x03 + MAX_CTRL_CS,
  378. .mode = SPI_CPHA | SPI_CPOL,
  379. },
  380. #endif
  381. #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
  382. {
  383. .modalias = "bfin-lq035q1-spi",
  384. .max_speed_hz = 20000000,
  385. .bus_num = 0,
  386. .chip_select = EXP_GPIO_SPISEL_BASE + 0x06 + MAX_CTRL_CS,
  387. .mode = SPI_CPHA | SPI_CPOL,
  388. },
  389. #endif
  390. #if defined(CONFIG_GPIO_MCP23S08) || defined(CONFIG_GPIO_MCP23S08_MODULE)
  391. {
  392. .modalias = "mcp23s08",
  393. .platform_data = &bfin_mcp23s08_sys_gpio_info,
  394. .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
  395. .bus_num = 0,
  396. .chip_select = EXP_GPIO_SPISEL_BASE + 0x01 + MAX_CTRL_CS,
  397. .mode = SPI_CPHA | SPI_CPOL,
  398. },
  399. {
  400. .modalias = "mcp23s08",
  401. .platform_data = &bfin_mcp23s08_usr_gpio_info,
  402. .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
  403. .bus_num = 0,
  404. .chip_select = EXP_GPIO_SPISEL_BASE + 0x02 + MAX_CTRL_CS,
  405. .mode = SPI_CPHA | SPI_CPOL,
  406. },
  407. #endif
  408. };
  409. #if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
  410. /* SPI controller data */
  411. static struct bfin5xx_spi_master bfin_spi0_info = {
  412. .num_chipselect = EXP_GPIO_SPISEL_BASE + 8 + MAX_CTRL_CS,
  413. /* EXP_GPIO_SPISEL_BASE will be > MAX_BLACKFIN_GPIOS */
  414. .enable_dma = 1, /* master has the ability to do dma transfer */
  415. .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
  416. };
  417. /* SPI (0) */
  418. static struct resource bfin_spi0_resource[] = {
  419. [0] = {
  420. .start = SPI0_REGBASE,
  421. .end = SPI0_REGBASE + 0xFF,
  422. .flags = IORESOURCE_MEM,
  423. },
  424. [1] = {
  425. .start = CH_SPI,
  426. .end = CH_SPI,
  427. .flags = IORESOURCE_DMA,
  428. },
  429. [2] = {
  430. .start = IRQ_SPI,
  431. .end = IRQ_SPI,
  432. .flags = IORESOURCE_IRQ,
  433. },
  434. };
  435. static struct platform_device bfin_spi0_device = {
  436. .name = "bfin-spi",
  437. .id = 0, /* Bus number */
  438. .num_resources = ARRAY_SIZE(bfin_spi0_resource),
  439. .resource = bfin_spi0_resource,
  440. .dev = {
  441. .platform_data = &bfin_spi0_info, /* Passed to driver */
  442. },
  443. };
  444. #endif /* spi master and devices */
  445. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  446. #ifdef CONFIG_SERIAL_BFIN_UART0
  447. static struct resource bfin_uart0_resources[] = {
  448. {
  449. .start = UART0_THR,
  450. .end = UART0_GCTL+2,
  451. .flags = IORESOURCE_MEM,
  452. },
  453. {
  454. .start = IRQ_UART0_TX,
  455. .end = IRQ_UART0_TX,
  456. .flags = IORESOURCE_IRQ,
  457. },
  458. {
  459. .start = IRQ_UART0_RX,
  460. .end = IRQ_UART0_RX,
  461. .flags = IORESOURCE_IRQ,
  462. },
  463. {
  464. .start = IRQ_UART0_ERROR,
  465. .end = IRQ_UART0_ERROR,
  466. .flags = IORESOURCE_IRQ,
  467. },
  468. {
  469. .start = CH_UART0_TX,
  470. .end = CH_UART0_TX,
  471. .flags = IORESOURCE_DMA,
  472. },
  473. {
  474. .start = CH_UART0_RX,
  475. .end = CH_UART0_RX,
  476. .flags = IORESOURCE_DMA,
  477. },
  478. };
  479. static unsigned short bfin_uart0_peripherals[] = {
  480. P_UART0_TX, P_UART0_RX, 0
  481. };
  482. static struct platform_device bfin_uart0_device = {
  483. .name = "bfin-uart",
  484. .id = 0,
  485. .num_resources = ARRAY_SIZE(bfin_uart0_resources),
  486. .resource = bfin_uart0_resources,
  487. .dev = {
  488. .platform_data = &bfin_uart0_peripherals,
  489. /* Passed to driver */
  490. },
  491. };
  492. #endif
  493. #ifdef CONFIG_SERIAL_BFIN_UART1
  494. static struct resource bfin_uart1_resources[] = {
  495. {
  496. .start = UART1_THR,
  497. .end = UART1_GCTL+2,
  498. .flags = IORESOURCE_MEM,
  499. },
  500. {
  501. .start = IRQ_UART1_TX,
  502. .end = IRQ_UART1_TX,
  503. .flags = IORESOURCE_IRQ,
  504. },
  505. {
  506. .start = IRQ_UART1_RX,
  507. .end = IRQ_UART1_RX,
  508. .flags = IORESOURCE_IRQ,
  509. },
  510. {
  511. .start = IRQ_UART1_ERROR,
  512. .end = IRQ_UART1_ERROR,
  513. .flags = IORESOURCE_IRQ,
  514. },
  515. {
  516. .start = CH_UART1_TX,
  517. .end = CH_UART1_TX,
  518. .flags = IORESOURCE_DMA,
  519. },
  520. {
  521. .start = CH_UART1_RX,
  522. .end = CH_UART1_RX,
  523. .flags = IORESOURCE_DMA,
  524. },
  525. #ifdef CONFIG_BFIN_UART1_CTSRTS
  526. { /* CTS pin */
  527. .start = GPIO_PF9,
  528. .end = GPIO_PF9,
  529. .flags = IORESOURCE_IO,
  530. },
  531. { /* RTS pin */
  532. .start = GPIO_PF10,
  533. .end = GPIO_PF10,
  534. .flags = IORESOURCE_IO,
  535. },
  536. #endif
  537. };
  538. static unsigned short bfin_uart1_peripherals[] = {
  539. P_UART1_TX, P_UART1_RX, 0
  540. };
  541. static struct platform_device bfin_uart1_device = {
  542. .name = "bfin-uart",
  543. .id = 1,
  544. .num_resources = ARRAY_SIZE(bfin_uart1_resources),
  545. .resource = bfin_uart1_resources,
  546. .dev = {
  547. .platform_data = &bfin_uart1_peripherals,
  548. /* Passed to driver */
  549. },
  550. };
  551. #endif
  552. #endif
  553. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  554. #ifdef CONFIG_BFIN_SIR0
  555. static struct resource bfin_sir0_resources[] = {
  556. {
  557. .start = 0xFFC00400,
  558. .end = 0xFFC004FF,
  559. .flags = IORESOURCE_MEM,
  560. },
  561. {
  562. .start = IRQ_UART0_RX,
  563. .end = IRQ_UART0_RX+1,
  564. .flags = IORESOURCE_IRQ,
  565. },
  566. {
  567. .start = CH_UART0_RX,
  568. .end = CH_UART0_RX+1,
  569. .flags = IORESOURCE_DMA,
  570. },
  571. };
  572. static struct platform_device bfin_sir0_device = {
  573. .name = "bfin_sir",
  574. .id = 0,
  575. .num_resources = ARRAY_SIZE(bfin_sir0_resources),
  576. .resource = bfin_sir0_resources,
  577. };
  578. #endif
  579. #ifdef CONFIG_BFIN_SIR1
  580. static struct resource bfin_sir1_resources[] = {
  581. {
  582. .start = 0xFFC02000,
  583. .end = 0xFFC020FF,
  584. .flags = IORESOURCE_MEM,
  585. },
  586. {
  587. .start = IRQ_UART1_RX,
  588. .end = IRQ_UART1_RX+1,
  589. .flags = IORESOURCE_IRQ,
  590. },
  591. {
  592. .start = CH_UART1_RX,
  593. .end = CH_UART1_RX+1,
  594. .flags = IORESOURCE_DMA,
  595. },
  596. };
  597. static struct platform_device bfin_sir1_device = {
  598. .name = "bfin_sir",
  599. .id = 1,
  600. .num_resources = ARRAY_SIZE(bfin_sir1_resources),
  601. .resource = bfin_sir1_resources,
  602. };
  603. #endif
  604. #endif
  605. #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
  606. static struct resource bfin_twi0_resource[] = {
  607. [0] = {
  608. .start = TWI0_REGBASE,
  609. .end = TWI0_REGBASE,
  610. .flags = IORESOURCE_MEM,
  611. },
  612. [1] = {
  613. .start = IRQ_TWI,
  614. .end = IRQ_TWI,
  615. .flags = IORESOURCE_IRQ,
  616. },
  617. };
  618. static struct platform_device i2c_bfin_twi_device = {
  619. .name = "i2c-bfin-twi",
  620. .id = 0,
  621. .num_resources = ARRAY_SIZE(bfin_twi0_resource),
  622. .resource = bfin_twi0_resource,
  623. };
  624. #endif
  625. static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
  626. #if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
  627. {
  628. I2C_BOARD_INFO("pcf8574_lcd", 0x22),
  629. },
  630. #endif
  631. #if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
  632. {
  633. I2C_BOARD_INFO("bfin-adv7393", 0x2B),
  634. },
  635. #endif
  636. #if defined(CONFIG_TOUCHSCREEN_AD7879_I2C) \
  637. || defined(CONFIG_TOUCHSCREEN_AD7879_I2C_MODULE)
  638. {
  639. I2C_BOARD_INFO("ad7879", 0x2C),
  640. .irq = IRQ_PH14,
  641. .platform_data = (void *)&bfin_ad7879_ts_info,
  642. },
  643. #endif
  644. #if defined(CONFIG_SND_SOC_SSM2602) || defined(CONFIG_SND_SOC_SSM2602_MODULE)
  645. {
  646. I2C_BOARD_INFO("ssm2602", 0x1b),
  647. },
  648. #endif
  649. {
  650. I2C_BOARD_INFO("adm1192", 0x2e),
  651. },
  652. {
  653. I2C_BOARD_INFO("ltc3576", 0x09),
  654. },
  655. #if defined(CONFIG_INPUT_ADXL34X_I2C) \
  656. || defined(CONFIG_INPUT_ADXL34X_I2C_MODULE)
  657. {
  658. I2C_BOARD_INFO("adxl34x", 0x53),
  659. .irq = IRQ_PH13,
  660. .platform_data = (void *)&adxl345_info,
  661. },
  662. #endif
  663. };
  664. #if defined(CONFIG_SERIAL_BFIN_SPORT) \
  665. || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  666. #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
  667. static struct resource bfin_sport0_uart_resources[] = {
  668. {
  669. .start = SPORT0_TCR1,
  670. .end = SPORT0_MRCS3+4,
  671. .flags = IORESOURCE_MEM,
  672. },
  673. {
  674. .start = IRQ_SPORT0_RX,
  675. .end = IRQ_SPORT0_RX+1,
  676. .flags = IORESOURCE_IRQ,
  677. },
  678. {
  679. .start = IRQ_SPORT0_ERROR,
  680. .end = IRQ_SPORT0_ERROR,
  681. .flags = IORESOURCE_IRQ,
  682. },
  683. };
  684. static unsigned short bfin_sport0_peripherals[] = {
  685. P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
  686. P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
  687. };
  688. static struct platform_device bfin_sport0_uart_device = {
  689. .name = "bfin-sport-uart",
  690. .id = 0,
  691. .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
  692. .resource = bfin_sport0_uart_resources,
  693. .dev = {
  694. .platform_data = &bfin_sport0_peripherals,
  695. /* Passed to driver */
  696. },
  697. };
  698. #endif
  699. #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
  700. static struct resource bfin_sport1_uart_resources[] = {
  701. {
  702. .start = SPORT1_TCR1,
  703. .end = SPORT1_MRCS3+4,
  704. .flags = IORESOURCE_MEM,
  705. },
  706. {
  707. .start = IRQ_SPORT1_RX,
  708. .end = IRQ_SPORT1_RX+1,
  709. .flags = IORESOURCE_IRQ,
  710. },
  711. {
  712. .start = IRQ_SPORT1_ERROR,
  713. .end = IRQ_SPORT1_ERROR,
  714. .flags = IORESOURCE_IRQ,
  715. },
  716. };
  717. static unsigned short bfin_sport1_peripherals[] = {
  718. P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
  719. P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
  720. };
  721. static struct platform_device bfin_sport1_uart_device = {
  722. .name = "bfin-sport-uart",
  723. .id = 1,
  724. .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
  725. .resource = bfin_sport1_uart_resources,
  726. .dev = {
  727. .platform_data = &bfin_sport1_peripherals,
  728. /* Passed to driver */
  729. },
  730. };
  731. #endif
  732. #endif
  733. static const unsigned int cclk_vlev_datasheet[] = {
  734. VRPAIR(VLEV_100, 400000000),
  735. VRPAIR(VLEV_105, 426000000),
  736. VRPAIR(VLEV_110, 500000000),
  737. VRPAIR(VLEV_115, 533000000),
  738. VRPAIR(VLEV_120, 600000000),
  739. };
  740. static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
  741. .tuple_tab = cclk_vlev_datasheet,
  742. .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
  743. .vr_settling_time = 25 /* us */,
  744. };
  745. static struct platform_device bfin_dpmc = {
  746. .name = "bfin dpmc",
  747. .dev = {
  748. .platform_data = &bfin_dmpc_vreg_data,
  749. },
  750. };
  751. static struct platform_device *tll6527m_devices[] __initdata = {
  752. &bfin_dpmc,
  753. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  754. &rtc_device,
  755. #endif
  756. #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
  757. &musb_device,
  758. #endif
  759. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  760. &bfin_mii_bus,
  761. &bfin_mac_device,
  762. #endif
  763. #if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
  764. &bfin_spi0_device,
  765. #endif
  766. #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
  767. &bfin_lq035q1_device,
  768. #endif
  769. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  770. #ifdef CONFIG_SERIAL_BFIN_UART0
  771. &bfin_uart0_device,
  772. #endif
  773. #ifdef CONFIG_SERIAL_BFIN_UART1
  774. &bfin_uart1_device,
  775. #endif
  776. #endif
  777. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  778. #ifdef CONFIG_BFIN_SIR0
  779. &bfin_sir0_device,
  780. #endif
  781. #ifdef CONFIG_BFIN_SIR1
  782. &bfin_sir1_device,
  783. #endif
  784. #endif
  785. #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
  786. &i2c_bfin_twi_device,
  787. #endif
  788. #if defined(CONFIG_SERIAL_BFIN_SPORT) \
  789. || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  790. #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
  791. &bfin_sport0_uart_device,
  792. #endif
  793. #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
  794. &bfin_sport1_uart_device,
  795. #endif
  796. #endif
  797. #if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
  798. &tll6527m_flash_device,
  799. #endif
  800. #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
  801. &bfin_i2s,
  802. #endif
  803. #if defined(CONFIG_GPIO_DECODER) || defined(CONFIG_GPIO_DECODER_MODULE)
  804. &spi_decoded_gpio,
  805. #endif
  806. };
  807. static int __init tll6527m_init(void)
  808. {
  809. printk(KERN_INFO "%s(): registering device resources\n", __func__);
  810. i2c_register_board_info(0, bfin_i2c_board_info,
  811. ARRAY_SIZE(bfin_i2c_board_info));
  812. platform_add_devices(tll6527m_devices, ARRAY_SIZE(tll6527m_devices));
  813. spi_register_board_info(bfin_spi_board_info,
  814. ARRAY_SIZE(bfin_spi_board_info));
  815. return 0;
  816. }
  817. arch_initcall(tll6527m_init);
  818. static struct platform_device *tll6527m_early_devices[] __initdata = {
  819. #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
  820. #ifdef CONFIG_SERIAL_BFIN_UART0
  821. &bfin_uart0_device,
  822. #endif
  823. #ifdef CONFIG_SERIAL_BFIN_UART1
  824. &bfin_uart1_device,
  825. #endif
  826. #endif
  827. #if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
  828. #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
  829. &bfin_sport0_uart_device,
  830. #endif
  831. #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
  832. &bfin_sport1_uart_device,
  833. #endif
  834. #endif
  835. };
  836. void __init native_machine_early_platform_add_devices(void)
  837. {
  838. printk(KERN_INFO "register early platform devices\n");
  839. early_platform_add_devices(tll6527m_early_devices,
  840. ARRAY_SIZE(tll6527m_early_devices));
  841. }
  842. void native_machine_restart(char *cmd)
  843. {
  844. /* workaround reboot hang when booting from SPI */
  845. if ((bfin_read_SYSCR() & 0x7) == 0x3)
  846. bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
  847. }
  848. void bfin_get_ether_addr(char *addr)
  849. {
  850. /* the MAC is stored in OTP memory page 0xDF */
  851. u32 ret;
  852. u64 otp_mac;
  853. u32 (*otp_read)(u32 page, u32 flags,
  854. u64 *page_content) = (void *)0xEF00001A;
  855. ret = otp_read(0xDF, 0x00, &otp_mac);
  856. if (!(ret & 0x1)) {
  857. char *otp_mac_p = (char *)&otp_mac;
  858. for (ret = 0; ret < 6; ++ret)
  859. addr[ret] = otp_mac_p[5 - ret];
  860. }
  861. }
  862. EXPORT_SYMBOL(bfin_get_ether_addr);