adc.c 12 KB

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  1. /* arch/arm/plat-samsung/adc.c
  2. *
  3. * Copyright (c) 2008 Simtec Electronics
  4. * http://armlinux.simtec.co.uk/
  5. * Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org>
  6. *
  7. * Samsung ADC device core
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/sched.h>
  17. #include <linux/list.h>
  18. #include <linux/slab.h>
  19. #include <linux/err.h>
  20. #include <linux/clk.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/io.h>
  23. #include <linux/regulator/consumer.h>
  24. #include <plat/regs-adc.h>
  25. #include <plat/adc.h>
  26. /* This driver is designed to control the usage of the ADC block between
  27. * the touchscreen and any other drivers that may need to use it, such as
  28. * the hwmon driver.
  29. *
  30. * Priority will be given to the touchscreen driver, but as this itself is
  31. * rate limited it should not starve other requests which are processed in
  32. * order that they are received.
  33. *
  34. * Each user registers to get a client block which uniquely identifies it
  35. * and stores information such as the necessary functions to callback when
  36. * action is required.
  37. */
  38. enum s3c_cpu_type {
  39. TYPE_ADCV1, /* S3C24XX */
  40. TYPE_ADCV11, /* S3C2443 */
  41. TYPE_ADCV12, /* S3C2416, S3C2450 */
  42. TYPE_ADCV2, /* S3C64XX, S5P64X0, S5PC100 */
  43. TYPE_ADCV3, /* S5PV210, S5PC110, EXYNOS4210 */
  44. };
  45. struct s3c_adc_client {
  46. struct platform_device *pdev;
  47. struct list_head pend;
  48. wait_queue_head_t *wait;
  49. unsigned int nr_samples;
  50. int result;
  51. unsigned char is_ts;
  52. unsigned char channel;
  53. void (*select_cb)(struct s3c_adc_client *c, unsigned selected);
  54. void (*convert_cb)(struct s3c_adc_client *c,
  55. unsigned val1, unsigned val2,
  56. unsigned *samples_left);
  57. };
  58. struct adc_device {
  59. struct platform_device *pdev;
  60. struct platform_device *owner;
  61. struct clk *clk;
  62. struct s3c_adc_client *cur;
  63. struct s3c_adc_client *ts_pend;
  64. void __iomem *regs;
  65. spinlock_t lock;
  66. unsigned int prescale;
  67. int irq;
  68. struct regulator *vdd;
  69. };
  70. static struct adc_device *adc_dev;
  71. static LIST_HEAD(adc_pending); /* protected by adc_device.lock */
  72. #define adc_dbg(_adc, msg...) dev_dbg(&(_adc)->pdev->dev, msg)
  73. static inline void s3c_adc_convert(struct adc_device *adc)
  74. {
  75. unsigned con = readl(adc->regs + S3C2410_ADCCON);
  76. con |= S3C2410_ADCCON_ENABLE_START;
  77. writel(con, adc->regs + S3C2410_ADCCON);
  78. }
  79. static inline void s3c_adc_select(struct adc_device *adc,
  80. struct s3c_adc_client *client)
  81. {
  82. unsigned con = readl(adc->regs + S3C2410_ADCCON);
  83. enum s3c_cpu_type cpu = platform_get_device_id(adc->pdev)->driver_data;
  84. client->select_cb(client, 1);
  85. if (cpu == TYPE_ADCV1 || cpu == TYPE_ADCV2)
  86. con &= ~S3C2410_ADCCON_MUXMASK;
  87. con &= ~S3C2410_ADCCON_STDBM;
  88. con &= ~S3C2410_ADCCON_STARTMASK;
  89. if (!client->is_ts) {
  90. if (cpu == TYPE_ADCV3)
  91. writel(client->channel & 0xf, adc->regs + S5P_ADCMUX);
  92. else if (cpu == TYPE_ADCV11 || cpu == TYPE_ADCV12)
  93. writel(client->channel & 0xf,
  94. adc->regs + S3C2443_ADCMUX);
  95. else
  96. con |= S3C2410_ADCCON_SELMUX(client->channel);
  97. }
  98. writel(con, adc->regs + S3C2410_ADCCON);
  99. }
  100. static void s3c_adc_dbgshow(struct adc_device *adc)
  101. {
  102. adc_dbg(adc, "CON=%08x, TSC=%08x, DLY=%08x\n",
  103. readl(adc->regs + S3C2410_ADCCON),
  104. readl(adc->regs + S3C2410_ADCTSC),
  105. readl(adc->regs + S3C2410_ADCDLY));
  106. }
  107. static void s3c_adc_try(struct adc_device *adc)
  108. {
  109. struct s3c_adc_client *next = adc->ts_pend;
  110. if (!next && !list_empty(&adc_pending)) {
  111. next = list_first_entry(&adc_pending,
  112. struct s3c_adc_client, pend);
  113. list_del(&next->pend);
  114. } else
  115. adc->ts_pend = NULL;
  116. if (next) {
  117. adc_dbg(adc, "new client is %p\n", next);
  118. adc->cur = next;
  119. s3c_adc_select(adc, next);
  120. s3c_adc_convert(adc);
  121. s3c_adc_dbgshow(adc);
  122. }
  123. }
  124. int s3c_adc_start(struct s3c_adc_client *client,
  125. unsigned int channel, unsigned int nr_samples)
  126. {
  127. struct adc_device *adc = adc_dev;
  128. unsigned long flags;
  129. if (!adc) {
  130. printk(KERN_ERR "%s: failed to find adc\n", __func__);
  131. return -EINVAL;
  132. }
  133. if (client->is_ts && adc->ts_pend)
  134. return -EAGAIN;
  135. spin_lock_irqsave(&adc->lock, flags);
  136. client->channel = channel;
  137. client->nr_samples = nr_samples;
  138. if (client->is_ts)
  139. adc->ts_pend = client;
  140. else
  141. list_add_tail(&client->pend, &adc_pending);
  142. if (!adc->cur)
  143. s3c_adc_try(adc);
  144. spin_unlock_irqrestore(&adc->lock, flags);
  145. return 0;
  146. }
  147. EXPORT_SYMBOL_GPL(s3c_adc_start);
  148. static void s3c_convert_done(struct s3c_adc_client *client,
  149. unsigned v, unsigned u, unsigned *left)
  150. {
  151. client->result = v;
  152. wake_up(client->wait);
  153. }
  154. int s3c_adc_read(struct s3c_adc_client *client, unsigned int ch)
  155. {
  156. DECLARE_WAIT_QUEUE_HEAD_ONSTACK(wake);
  157. int ret;
  158. client->convert_cb = s3c_convert_done;
  159. client->wait = &wake;
  160. client->result = -1;
  161. ret = s3c_adc_start(client, ch, 1);
  162. if (ret < 0)
  163. goto err;
  164. ret = wait_event_timeout(wake, client->result >= 0, HZ / 2);
  165. if (client->result < 0) {
  166. ret = -ETIMEDOUT;
  167. goto err;
  168. }
  169. client->convert_cb = NULL;
  170. return client->result;
  171. err:
  172. return ret;
  173. }
  174. EXPORT_SYMBOL_GPL(s3c_adc_read);
  175. static void s3c_adc_default_select(struct s3c_adc_client *client,
  176. unsigned select)
  177. {
  178. }
  179. struct s3c_adc_client *s3c_adc_register(struct platform_device *pdev,
  180. void (*select)(struct s3c_adc_client *client,
  181. unsigned int selected),
  182. void (*conv)(struct s3c_adc_client *client,
  183. unsigned d0, unsigned d1,
  184. unsigned *samples_left),
  185. unsigned int is_ts)
  186. {
  187. struct s3c_adc_client *client;
  188. WARN_ON(!pdev);
  189. if (!select)
  190. select = s3c_adc_default_select;
  191. if (!pdev)
  192. return ERR_PTR(-EINVAL);
  193. client = kzalloc(sizeof(struct s3c_adc_client), GFP_KERNEL);
  194. if (!client) {
  195. dev_err(&pdev->dev, "no memory for adc client\n");
  196. return ERR_PTR(-ENOMEM);
  197. }
  198. client->pdev = pdev;
  199. client->is_ts = is_ts;
  200. client->select_cb = select;
  201. client->convert_cb = conv;
  202. return client;
  203. }
  204. EXPORT_SYMBOL_GPL(s3c_adc_register);
  205. void s3c_adc_release(struct s3c_adc_client *client)
  206. {
  207. unsigned long flags;
  208. spin_lock_irqsave(&adc_dev->lock, flags);
  209. /* We should really check that nothing is in progress. */
  210. if (adc_dev->cur == client)
  211. adc_dev->cur = NULL;
  212. if (adc_dev->ts_pend == client)
  213. adc_dev->ts_pend = NULL;
  214. else {
  215. struct list_head *p, *n;
  216. struct s3c_adc_client *tmp;
  217. list_for_each_safe(p, n, &adc_pending) {
  218. tmp = list_entry(p, struct s3c_adc_client, pend);
  219. if (tmp == client)
  220. list_del(&tmp->pend);
  221. }
  222. }
  223. if (adc_dev->cur == NULL)
  224. s3c_adc_try(adc_dev);
  225. spin_unlock_irqrestore(&adc_dev->lock, flags);
  226. kfree(client);
  227. }
  228. EXPORT_SYMBOL_GPL(s3c_adc_release);
  229. static irqreturn_t s3c_adc_irq(int irq, void *pw)
  230. {
  231. struct adc_device *adc = pw;
  232. struct s3c_adc_client *client = adc->cur;
  233. enum s3c_cpu_type cpu = platform_get_device_id(adc->pdev)->driver_data;
  234. unsigned data0, data1;
  235. if (!client) {
  236. dev_warn(&adc->pdev->dev, "%s: no adc pending\n", __func__);
  237. goto exit;
  238. }
  239. data0 = readl(adc->regs + S3C2410_ADCDAT0);
  240. data1 = readl(adc->regs + S3C2410_ADCDAT1);
  241. adc_dbg(adc, "read %d: 0x%04x, 0x%04x\n", client->nr_samples, data0, data1);
  242. client->nr_samples--;
  243. if (cpu == TYPE_ADCV1 || cpu == TYPE_ADCV11) {
  244. data0 &= 0x3ff;
  245. data1 &= 0x3ff;
  246. } else {
  247. /* S3C2416/S3C64XX/S5P ADC resolution is 12-bit */
  248. data0 &= 0xfff;
  249. data1 &= 0xfff;
  250. }
  251. if (client->convert_cb)
  252. (client->convert_cb)(client, data0, data1, &client->nr_samples);
  253. if (client->nr_samples > 0) {
  254. /* fire another conversion for this */
  255. client->select_cb(client, 1);
  256. s3c_adc_convert(adc);
  257. } else {
  258. spin_lock(&adc->lock);
  259. (client->select_cb)(client, 0);
  260. adc->cur = NULL;
  261. s3c_adc_try(adc);
  262. spin_unlock(&adc->lock);
  263. }
  264. exit:
  265. if (cpu == TYPE_ADCV2 || cpu == TYPE_ADCV3) {
  266. /* Clear ADC interrupt */
  267. writel(0, adc->regs + S3C64XX_ADCCLRINT);
  268. }
  269. return IRQ_HANDLED;
  270. }
  271. static int s3c_adc_probe(struct platform_device *pdev)
  272. {
  273. struct device *dev = &pdev->dev;
  274. struct adc_device *adc;
  275. struct resource *regs;
  276. enum s3c_cpu_type cpu = platform_get_device_id(pdev)->driver_data;
  277. int ret;
  278. unsigned tmp;
  279. adc = kzalloc(sizeof(struct adc_device), GFP_KERNEL);
  280. if (adc == NULL) {
  281. dev_err(dev, "failed to allocate adc_device\n");
  282. return -ENOMEM;
  283. }
  284. spin_lock_init(&adc->lock);
  285. adc->pdev = pdev;
  286. adc->prescale = S3C2410_ADCCON_PRSCVL(49);
  287. adc->vdd = regulator_get(dev, "vdd");
  288. if (IS_ERR(adc->vdd)) {
  289. dev_err(dev, "operating without regulator \"vdd\" .\n");
  290. ret = PTR_ERR(adc->vdd);
  291. goto err_alloc;
  292. }
  293. adc->irq = platform_get_irq(pdev, 1);
  294. if (adc->irq <= 0) {
  295. dev_err(dev, "failed to get adc irq\n");
  296. ret = -ENOENT;
  297. goto err_reg;
  298. }
  299. ret = request_irq(adc->irq, s3c_adc_irq, 0, dev_name(dev), adc);
  300. if (ret < 0) {
  301. dev_err(dev, "failed to attach adc irq\n");
  302. goto err_reg;
  303. }
  304. adc->clk = clk_get(dev, "adc");
  305. if (IS_ERR(adc->clk)) {
  306. dev_err(dev, "failed to get adc clock\n");
  307. ret = PTR_ERR(adc->clk);
  308. goto err_irq;
  309. }
  310. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  311. if (!regs) {
  312. dev_err(dev, "failed to find registers\n");
  313. ret = -ENXIO;
  314. goto err_clk;
  315. }
  316. adc->regs = ioremap(regs->start, resource_size(regs));
  317. if (!adc->regs) {
  318. dev_err(dev, "failed to map registers\n");
  319. ret = -ENXIO;
  320. goto err_clk;
  321. }
  322. ret = regulator_enable(adc->vdd);
  323. if (ret)
  324. goto err_ioremap;
  325. clk_enable(adc->clk);
  326. tmp = adc->prescale | S3C2410_ADCCON_PRSCEN;
  327. /* Enable 12-bit ADC resolution */
  328. if (cpu == TYPE_ADCV12)
  329. tmp |= S3C2416_ADCCON_RESSEL;
  330. if (cpu == TYPE_ADCV2 || cpu == TYPE_ADCV3)
  331. tmp |= S3C64XX_ADCCON_RESSEL;
  332. writel(tmp, adc->regs + S3C2410_ADCCON);
  333. dev_info(dev, "attached adc driver\n");
  334. platform_set_drvdata(pdev, adc);
  335. adc_dev = adc;
  336. return 0;
  337. err_ioremap:
  338. iounmap(adc->regs);
  339. err_clk:
  340. clk_put(adc->clk);
  341. err_irq:
  342. free_irq(adc->irq, adc);
  343. err_reg:
  344. regulator_put(adc->vdd);
  345. err_alloc:
  346. kfree(adc);
  347. return ret;
  348. }
  349. static int __devexit s3c_adc_remove(struct platform_device *pdev)
  350. {
  351. struct adc_device *adc = platform_get_drvdata(pdev);
  352. iounmap(adc->regs);
  353. free_irq(adc->irq, adc);
  354. clk_disable(adc->clk);
  355. regulator_disable(adc->vdd);
  356. regulator_put(adc->vdd);
  357. clk_put(adc->clk);
  358. kfree(adc);
  359. return 0;
  360. }
  361. #ifdef CONFIG_PM
  362. static int s3c_adc_suspend(struct device *dev)
  363. {
  364. struct platform_device *pdev = container_of(dev,
  365. struct platform_device, dev);
  366. struct adc_device *adc = platform_get_drvdata(pdev);
  367. unsigned long flags;
  368. u32 con;
  369. spin_lock_irqsave(&adc->lock, flags);
  370. con = readl(adc->regs + S3C2410_ADCCON);
  371. con |= S3C2410_ADCCON_STDBM;
  372. writel(con, adc->regs + S3C2410_ADCCON);
  373. disable_irq(adc->irq);
  374. spin_unlock_irqrestore(&adc->lock, flags);
  375. clk_disable(adc->clk);
  376. regulator_disable(adc->vdd);
  377. return 0;
  378. }
  379. static int s3c_adc_resume(struct device *dev)
  380. {
  381. struct platform_device *pdev = container_of(dev,
  382. struct platform_device, dev);
  383. struct adc_device *adc = platform_get_drvdata(pdev);
  384. enum s3c_cpu_type cpu = platform_get_device_id(pdev)->driver_data;
  385. int ret;
  386. unsigned long tmp;
  387. ret = regulator_enable(adc->vdd);
  388. if (ret)
  389. return ret;
  390. clk_enable(adc->clk);
  391. enable_irq(adc->irq);
  392. tmp = adc->prescale | S3C2410_ADCCON_PRSCEN;
  393. /* Enable 12-bit ADC resolution */
  394. if (cpu == TYPE_ADCV12)
  395. tmp |= S3C2416_ADCCON_RESSEL;
  396. if (cpu == TYPE_ADCV2 || cpu == TYPE_ADCV3)
  397. tmp |= S3C64XX_ADCCON_RESSEL;
  398. writel(tmp, adc->regs + S3C2410_ADCCON);
  399. return 0;
  400. }
  401. #else
  402. #define s3c_adc_suspend NULL
  403. #define s3c_adc_resume NULL
  404. #endif
  405. static struct platform_device_id s3c_adc_driver_ids[] = {
  406. {
  407. .name = "s3c24xx-adc",
  408. .driver_data = TYPE_ADCV1,
  409. }, {
  410. .name = "s3c2443-adc",
  411. .driver_data = TYPE_ADCV11,
  412. }, {
  413. .name = "s3c2416-adc",
  414. .driver_data = TYPE_ADCV12,
  415. }, {
  416. .name = "s3c64xx-adc",
  417. .driver_data = TYPE_ADCV2,
  418. }, {
  419. .name = "samsung-adc-v3",
  420. .driver_data = TYPE_ADCV3,
  421. },
  422. { }
  423. };
  424. MODULE_DEVICE_TABLE(platform, s3c_adc_driver_ids);
  425. static const struct dev_pm_ops adc_pm_ops = {
  426. .suspend = s3c_adc_suspend,
  427. .resume = s3c_adc_resume,
  428. };
  429. static struct platform_driver s3c_adc_driver = {
  430. .id_table = s3c_adc_driver_ids,
  431. .driver = {
  432. .name = "s3c-adc",
  433. .owner = THIS_MODULE,
  434. .pm = &adc_pm_ops,
  435. },
  436. .probe = s3c_adc_probe,
  437. .remove = __devexit_p(s3c_adc_remove),
  438. };
  439. static int __init adc_init(void)
  440. {
  441. int ret;
  442. ret = platform_driver_register(&s3c_adc_driver);
  443. if (ret)
  444. printk(KERN_ERR "%s: failed to add adc driver\n", __func__);
  445. return ret;
  446. }
  447. module_init(adc_init);