inst.h 9.1 KB

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  1. /******************************************************************************
  2. * arch/ia64/include/asm/xen/inst.h
  3. *
  4. * Copyright (c) 2008 Isaku Yamahata <yamahata at valinux co jp>
  5. * VA Linux Systems Japan K.K.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  20. *
  21. */
  22. #include <asm/xen/privop.h>
  23. #define DO_SAVE_MIN XEN_DO_SAVE_MIN
  24. #define MOV_FROM_IFA(reg) \
  25. movl reg = XSI_IFA; \
  26. ;; \
  27. ld8 reg = [reg]
  28. #define MOV_FROM_ITIR(reg) \
  29. movl reg = XSI_ITIR; \
  30. ;; \
  31. ld8 reg = [reg]
  32. #define MOV_FROM_ISR(reg) \
  33. movl reg = XSI_ISR; \
  34. ;; \
  35. ld8 reg = [reg]
  36. #define MOV_FROM_IHA(reg) \
  37. movl reg = XSI_IHA; \
  38. ;; \
  39. ld8 reg = [reg]
  40. #define MOV_FROM_IPSR(pred, reg) \
  41. (pred) movl reg = XSI_IPSR; \
  42. ;; \
  43. (pred) ld8 reg = [reg]
  44. #define MOV_FROM_IIM(reg) \
  45. movl reg = XSI_IIM; \
  46. ;; \
  47. ld8 reg = [reg]
  48. #define MOV_FROM_IIP(reg) \
  49. movl reg = XSI_IIP; \
  50. ;; \
  51. ld8 reg = [reg]
  52. .macro __MOV_FROM_IVR reg, clob
  53. .ifc "\reg", "r8"
  54. XEN_HYPER_GET_IVR
  55. .exitm
  56. .endif
  57. .ifc "\clob", "r8"
  58. XEN_HYPER_GET_IVR
  59. ;;
  60. mov \reg = r8
  61. .exitm
  62. .endif
  63. mov \clob = r8
  64. ;;
  65. XEN_HYPER_GET_IVR
  66. ;;
  67. mov \reg = r8
  68. ;;
  69. mov r8 = \clob
  70. .endm
  71. #define MOV_FROM_IVR(reg, clob) __MOV_FROM_IVR reg, clob
  72. .macro __MOV_FROM_PSR pred, reg, clob
  73. .ifc "\reg", "r8"
  74. (\pred) XEN_HYPER_GET_PSR;
  75. .exitm
  76. .endif
  77. .ifc "\clob", "r8"
  78. (\pred) XEN_HYPER_GET_PSR
  79. ;;
  80. (\pred) mov \reg = r8
  81. .exitm
  82. .endif
  83. (\pred) mov \clob = r8
  84. (\pred) XEN_HYPER_GET_PSR
  85. ;;
  86. (\pred) mov \reg = r8
  87. (\pred) mov r8 = \clob
  88. .endm
  89. #define MOV_FROM_PSR(pred, reg, clob) __MOV_FROM_PSR pred, reg, clob
  90. #define MOV_TO_IFA(reg, clob) \
  91. movl clob = XSI_IFA; \
  92. ;; \
  93. st8 [clob] = reg \
  94. #define MOV_TO_ITIR(pred, reg, clob) \
  95. (pred) movl clob = XSI_ITIR; \
  96. ;; \
  97. (pred) st8 [clob] = reg
  98. #define MOV_TO_IHA(pred, reg, clob) \
  99. (pred) movl clob = XSI_IHA; \
  100. ;; \
  101. (pred) st8 [clob] = reg
  102. #define MOV_TO_IPSR(pred, reg, clob) \
  103. (pred) movl clob = XSI_IPSR; \
  104. ;; \
  105. (pred) st8 [clob] = reg; \
  106. ;;
  107. #define MOV_TO_IFS(pred, reg, clob) \
  108. (pred) movl clob = XSI_IFS; \
  109. ;; \
  110. (pred) st8 [clob] = reg; \
  111. ;;
  112. #define MOV_TO_IIP(reg, clob) \
  113. movl clob = XSI_IIP; \
  114. ;; \
  115. st8 [clob] = reg
  116. .macro ____MOV_TO_KR kr, reg, clob0, clob1
  117. .ifc "\clob0", "r9"
  118. .error "clob0 \clob0 must not be r9"
  119. .endif
  120. .ifc "\clob1", "r8"
  121. .error "clob1 \clob1 must not be r8"
  122. .endif
  123. .ifnc "\reg", "r9"
  124. .ifnc "\clob1", "r9"
  125. mov \clob1 = r9
  126. .endif
  127. mov r9 = \reg
  128. .endif
  129. .ifnc "\clob0", "r8"
  130. mov \clob0 = r8
  131. .endif
  132. mov r8 = \kr
  133. ;;
  134. XEN_HYPER_SET_KR
  135. .ifnc "\reg", "r9"
  136. .ifnc "\clob1", "r9"
  137. mov r9 = \clob1
  138. .endif
  139. .endif
  140. .ifnc "\clob0", "r8"
  141. mov r8 = \clob0
  142. .endif
  143. .endm
  144. .macro __MOV_TO_KR kr, reg, clob0, clob1
  145. .ifc "\clob0", "r9"
  146. ____MOV_TO_KR \kr, \reg, \clob1, \clob0
  147. .exitm
  148. .endif
  149. .ifc "\clob1", "r8"
  150. ____MOV_TO_KR \kr, \reg, \clob1, \clob0
  151. .exitm
  152. .endif
  153. ____MOV_TO_KR \kr, \reg, \clob0, \clob1
  154. .endm
  155. #define MOV_TO_KR(kr, reg, clob0, clob1) \
  156. __MOV_TO_KR IA64_KR_ ## kr, reg, clob0, clob1
  157. .macro __ITC_I pred, reg, clob
  158. .ifc "\reg", "r8"
  159. (\pred) XEN_HYPER_ITC_I
  160. .exitm
  161. .endif
  162. .ifc "\clob", "r8"
  163. (\pred) mov r8 = \reg
  164. ;;
  165. (\pred) XEN_HYPER_ITC_I
  166. .exitm
  167. .endif
  168. (\pred) mov \clob = r8
  169. (\pred) mov r8 = \reg
  170. ;;
  171. (\pred) XEN_HYPER_ITC_I
  172. ;;
  173. (\pred) mov r8 = \clob
  174. ;;
  175. .endm
  176. #define ITC_I(pred, reg, clob) __ITC_I pred, reg, clob
  177. .macro __ITC_D pred, reg, clob
  178. .ifc "\reg", "r8"
  179. (\pred) XEN_HYPER_ITC_D
  180. ;;
  181. .exitm
  182. .endif
  183. .ifc "\clob", "r8"
  184. (\pred) mov r8 = \reg
  185. ;;
  186. (\pred) XEN_HYPER_ITC_D
  187. ;;
  188. .exitm
  189. .endif
  190. (\pred) mov \clob = r8
  191. (\pred) mov r8 = \reg
  192. ;;
  193. (\pred) XEN_HYPER_ITC_D
  194. ;;
  195. (\pred) mov r8 = \clob
  196. ;;
  197. .endm
  198. #define ITC_D(pred, reg, clob) __ITC_D pred, reg, clob
  199. .macro __ITC_I_AND_D pred_i, pred_d, reg, clob
  200. .ifc "\reg", "r8"
  201. (\pred_i)XEN_HYPER_ITC_I
  202. ;;
  203. (\pred_d)XEN_HYPER_ITC_D
  204. ;;
  205. .exitm
  206. .endif
  207. .ifc "\clob", "r8"
  208. mov r8 = \reg
  209. ;;
  210. (\pred_i)XEN_HYPER_ITC_I
  211. ;;
  212. (\pred_d)XEN_HYPER_ITC_D
  213. ;;
  214. .exitm
  215. .endif
  216. mov \clob = r8
  217. mov r8 = \reg
  218. ;;
  219. (\pred_i)XEN_HYPER_ITC_I
  220. ;;
  221. (\pred_d)XEN_HYPER_ITC_D
  222. ;;
  223. mov r8 = \clob
  224. ;;
  225. .endm
  226. #define ITC_I_AND_D(pred_i, pred_d, reg, clob) \
  227. __ITC_I_AND_D pred_i, pred_d, reg, clob
  228. .macro __THASH pred, reg0, reg1, clob
  229. .ifc "\reg0", "r8"
  230. (\pred) mov r8 = \reg1
  231. (\pred) XEN_HYPER_THASH
  232. .exitm
  233. .endc
  234. .ifc "\reg1", "r8"
  235. (\pred) XEN_HYPER_THASH
  236. ;;
  237. (\pred) mov \reg0 = r8
  238. ;;
  239. .exitm
  240. .endif
  241. .ifc "\clob", "r8"
  242. (\pred) mov r8 = \reg1
  243. (\pred) XEN_HYPER_THASH
  244. ;;
  245. (\pred) mov \reg0 = r8
  246. ;;
  247. .exitm
  248. .endif
  249. (\pred) mov \clob = r8
  250. (\pred) mov r8 = \reg1
  251. (\pred) XEN_HYPER_THASH
  252. ;;
  253. (\pred) mov \reg0 = r8
  254. (\pred) mov r8 = \clob
  255. ;;
  256. .endm
  257. #define THASH(pred, reg0, reg1, clob) __THASH pred, reg0, reg1, clob
  258. #define SSM_PSR_IC_AND_DEFAULT_BITS_AND_SRLZ_I(clob0, clob1) \
  259. mov clob0 = 1; \
  260. movl clob1 = XSI_PSR_IC; \
  261. ;; \
  262. st4 [clob1] = clob0 \
  263. ;;
  264. #define SSM_PSR_IC_AND_SRLZ_D(clob0, clob1) \
  265. ;; \
  266. srlz.d; \
  267. mov clob1 = 1; \
  268. movl clob0 = XSI_PSR_IC; \
  269. ;; \
  270. st4 [clob0] = clob1
  271. #define RSM_PSR_IC(clob) \
  272. movl clob = XSI_PSR_IC; \
  273. ;; \
  274. st4 [clob] = r0; \
  275. ;;
  276. /* pred will be clobbered */
  277. #define MASK_TO_PEND_OFS (-1)
  278. #define SSM_PSR_I(pred, pred_clob, clob) \
  279. (pred) movl clob = XSI_PSR_I_ADDR \
  280. ;; \
  281. (pred) ld8 clob = [clob] \
  282. ;; \
  283. /* if (pred) vpsr.i = 1 */ \
  284. /* if (pred) (vcpu->vcpu_info->evtchn_upcall_mask)=0 */ \
  285. (pred) st1 [clob] = r0, MASK_TO_PEND_OFS \
  286. ;; \
  287. /* if (vcpu->vcpu_info->evtchn_upcall_pending) */ \
  288. (pred) ld1 clob = [clob] \
  289. ;; \
  290. (pred) cmp.ne.unc pred_clob, p0 = clob, r0 \
  291. ;; \
  292. (pred_clob)XEN_HYPER_SSM_I /* do areal ssm psr.i */
  293. #define RSM_PSR_I(pred, clob0, clob1) \
  294. movl clob0 = XSI_PSR_I_ADDR; \
  295. mov clob1 = 1; \
  296. ;; \
  297. ld8 clob0 = [clob0]; \
  298. ;; \
  299. (pred) st1 [clob0] = clob1
  300. #define RSM_PSR_I_IC(clob0, clob1, clob2) \
  301. movl clob0 = XSI_PSR_I_ADDR; \
  302. movl clob1 = XSI_PSR_IC; \
  303. ;; \
  304. ld8 clob0 = [clob0]; \
  305. mov clob2 = 1; \
  306. ;; \
  307. /* note: clears both vpsr.i and vpsr.ic! */ \
  308. st1 [clob0] = clob2; \
  309. st4 [clob1] = r0; \
  310. ;;
  311. #define RSM_PSR_DT \
  312. XEN_HYPER_RSM_PSR_DT
  313. #define SSM_PSR_DT_AND_SRLZ_I \
  314. XEN_HYPER_SSM_PSR_DT
  315. #define BSW_0(clob0, clob1, clob2) \
  316. ;; \
  317. /* r16-r31 all now hold bank1 values */ \
  318. mov clob2 = ar.unat; \
  319. movl clob0 = XSI_BANK1_R16; \
  320. movl clob1 = XSI_BANK1_R16 + 8; \
  321. ;; \
  322. .mem.offset 0, 0; st8.spill [clob0] = r16, 16; \
  323. .mem.offset 8, 0; st8.spill [clob1] = r17, 16; \
  324. ;; \
  325. .mem.offset 0, 0; st8.spill [clob0] = r18, 16; \
  326. .mem.offset 8, 0; st8.spill [clob1] = r19, 16; \
  327. ;; \
  328. .mem.offset 0, 0; st8.spill [clob0] = r20, 16; \
  329. .mem.offset 8, 0; st8.spill [clob1] = r21, 16; \
  330. ;; \
  331. .mem.offset 0, 0; st8.spill [clob0] = r22, 16; \
  332. .mem.offset 8, 0; st8.spill [clob1] = r23, 16; \
  333. ;; \
  334. .mem.offset 0, 0; st8.spill [clob0] = r24, 16; \
  335. .mem.offset 8, 0; st8.spill [clob1] = r25, 16; \
  336. ;; \
  337. .mem.offset 0, 0; st8.spill [clob0] = r26, 16; \
  338. .mem.offset 8, 0; st8.spill [clob1] = r27, 16; \
  339. ;; \
  340. .mem.offset 0, 0; st8.spill [clob0] = r28, 16; \
  341. .mem.offset 8, 0; st8.spill [clob1] = r29, 16; \
  342. ;; \
  343. .mem.offset 0, 0; st8.spill [clob0] = r30, 16; \
  344. .mem.offset 8, 0; st8.spill [clob1] = r31, 16; \
  345. ;; \
  346. mov clob1 = ar.unat; \
  347. movl clob0 = XSI_B1NAT; \
  348. ;; \
  349. st8 [clob0] = clob1; \
  350. mov ar.unat = clob2; \
  351. movl clob0 = XSI_BANKNUM; \
  352. ;; \
  353. st4 [clob0] = r0
  354. /* FIXME: THIS CODE IS NOT NaT SAFE! */
  355. #define XEN_BSW_1(clob) \
  356. mov clob = ar.unat; \
  357. movl r30 = XSI_B1NAT; \
  358. ;; \
  359. ld8 r30 = [r30]; \
  360. mov r31 = 1; \
  361. ;; \
  362. mov ar.unat = r30; \
  363. movl r30 = XSI_BANKNUM; \
  364. ;; \
  365. st4 [r30] = r31; \
  366. movl r30 = XSI_BANK1_R16; \
  367. movl r31 = XSI_BANK1_R16+8; \
  368. ;; \
  369. ld8.fill r16 = [r30], 16; \
  370. ld8.fill r17 = [r31], 16; \
  371. ;; \
  372. ld8.fill r18 = [r30], 16; \
  373. ld8.fill r19 = [r31], 16; \
  374. ;; \
  375. ld8.fill r20 = [r30], 16; \
  376. ld8.fill r21 = [r31], 16; \
  377. ;; \
  378. ld8.fill r22 = [r30], 16; \
  379. ld8.fill r23 = [r31], 16; \
  380. ;; \
  381. ld8.fill r24 = [r30], 16; \
  382. ld8.fill r25 = [r31], 16; \
  383. ;; \
  384. ld8.fill r26 = [r30], 16; \
  385. ld8.fill r27 = [r31], 16; \
  386. ;; \
  387. ld8.fill r28 = [r30], 16; \
  388. ld8.fill r29 = [r31], 16; \
  389. ;; \
  390. ld8.fill r30 = [r30]; \
  391. ld8.fill r31 = [r31]; \
  392. ;; \
  393. mov ar.unat = clob
  394. #define BSW_1(clob0, clob1) XEN_BSW_1(clob1)
  395. #define COVER \
  396. XEN_HYPER_COVER
  397. #define RFI \
  398. XEN_HYPER_RFI; \
  399. dv_serialize_data