init.c 11 KB

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  1. /*
  2. * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc.
  3. * All rights reserved.
  4. * Authors: Carsten Langgaard <carstenl@mips.com>
  5. * Maciej W. Rozycki <macro@mips.com>
  6. *
  7. * This program is free software; you can distribute it and/or modify it
  8. * under the terms of the GNU General Public License (Version 2) as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  14. * for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along
  17. * with this program; if not, write to the Free Software Foundation, Inc.,
  18. * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  19. *
  20. * PROM library initialisation code.
  21. */
  22. #include <linux/init.h>
  23. #include <linux/string.h>
  24. #include <linux/kernel.h>
  25. #include <asm/bootinfo.h>
  26. #include <asm/gt64120.h>
  27. #include <asm/io.h>
  28. #include <asm/system.h>
  29. #include <asm/cacheflush.h>
  30. #include <asm/traps.h>
  31. #include <asm/mips-boards/prom.h>
  32. #include <asm/mips-boards/generic.h>
  33. #include <asm/mips-boards/bonito64.h>
  34. #include <asm/mips-boards/msc01_pci.h>
  35. #include <asm/mips-boards/malta.h>
  36. #ifdef CONFIG_KGDB
  37. extern int rs_kgdb_hook(int, int);
  38. extern int rs_putDebugChar(char);
  39. extern char rs_getDebugChar(void);
  40. extern int saa9730_kgdb_hook(int);
  41. extern int saa9730_putDebugChar(char);
  42. extern char saa9730_getDebugChar(void);
  43. #endif
  44. int prom_argc;
  45. int *_prom_argv, *_prom_envp;
  46. /*
  47. * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer.
  48. * This macro take care of sign extension, if running in 64-bit mode.
  49. */
  50. #define prom_envp(index) ((char *)(long)_prom_envp[(index)])
  51. int init_debug = 0;
  52. int mips_revision_corid;
  53. int mips_revision_sconid;
  54. /* Bonito64 system controller register base. */
  55. unsigned long _pcictrl_bonito;
  56. unsigned long _pcictrl_bonito_pcicfg;
  57. /* GT64120 system controller register base */
  58. unsigned long _pcictrl_gt64120;
  59. /* MIPS System controller register base */
  60. unsigned long _pcictrl_msc;
  61. char *prom_getenv(char *envname)
  62. {
  63. /*
  64. * Return a pointer to the given environment variable.
  65. * In 64-bit mode: we're using 64-bit pointers, but all pointers
  66. * in the PROM structures are only 32-bit, so we need some
  67. * workarounds, if we are running in 64-bit mode.
  68. */
  69. int i, index=0;
  70. i = strlen(envname);
  71. while (prom_envp(index)) {
  72. if(strncmp(envname, prom_envp(index), i) == 0) {
  73. return(prom_envp(index+1));
  74. }
  75. index += 2;
  76. }
  77. return NULL;
  78. }
  79. static inline unsigned char str2hexnum(unsigned char c)
  80. {
  81. if (c >= '0' && c <= '9')
  82. return c - '0';
  83. if (c >= 'a' && c <= 'f')
  84. return c - 'a' + 10;
  85. return 0; /* foo */
  86. }
  87. static inline void str2eaddr(unsigned char *ea, unsigned char *str)
  88. {
  89. int i;
  90. for (i = 0; i < 6; i++) {
  91. unsigned char num;
  92. if((*str == '.') || (*str == ':'))
  93. str++;
  94. num = str2hexnum(*str++) << 4;
  95. num |= (str2hexnum(*str++));
  96. ea[i] = num;
  97. }
  98. }
  99. int get_ethernet_addr(char *ethernet_addr)
  100. {
  101. char *ethaddr_str;
  102. ethaddr_str = prom_getenv("ethaddr");
  103. if (!ethaddr_str) {
  104. printk("ethaddr not set in boot prom\n");
  105. return -1;
  106. }
  107. str2eaddr(ethernet_addr, ethaddr_str);
  108. if (init_debug > 1) {
  109. int i;
  110. printk("get_ethernet_addr: ");
  111. for (i=0; i<5; i++)
  112. printk("%02x:", (unsigned char)*(ethernet_addr+i));
  113. printk("%02x\n", *(ethernet_addr+i));
  114. }
  115. return 0;
  116. }
  117. #ifdef CONFIG_SERIAL_8250_CONSOLE
  118. static void __init console_config(void)
  119. {
  120. char console_string[40];
  121. int baud = 0;
  122. char parity = '\0', bits = '\0', flow = '\0';
  123. char *s;
  124. if ((strstr(prom_getcmdline(), "console=")) == NULL) {
  125. s = prom_getenv("modetty0");
  126. if (s) {
  127. while (*s >= '0' && *s <= '9')
  128. baud = baud*10 + *s++ - '0';
  129. if (*s == ',') s++;
  130. if (*s) parity = *s++;
  131. if (*s == ',') s++;
  132. if (*s) bits = *s++;
  133. if (*s == ',') s++;
  134. if (*s == 'h') flow = 'r';
  135. }
  136. if (baud == 0)
  137. baud = 38400;
  138. if (parity != 'n' && parity != 'o' && parity != 'e')
  139. parity = 'n';
  140. if (bits != '7' && bits != '8')
  141. bits = '8';
  142. if (flow == '\0')
  143. flow = 'r';
  144. sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, parity, bits, flow);
  145. strcat(prom_getcmdline(), console_string);
  146. pr_info("Config serial console:%s\n", console_string);
  147. }
  148. }
  149. #endif
  150. #ifdef CONFIG_KGDB
  151. void __init kgdb_config(void)
  152. {
  153. extern int (*generic_putDebugChar)(char);
  154. extern char (*generic_getDebugChar)(void);
  155. char *argptr;
  156. int line, speed;
  157. argptr = prom_getcmdline();
  158. if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) {
  159. argptr += strlen("kgdb=ttyS");
  160. if (*argptr != '0' && *argptr != '1')
  161. printk("KGDB: Unknown serial line /dev/ttyS%c, "
  162. "falling back to /dev/ttyS1\n", *argptr);
  163. line = *argptr == '0' ? 0 : 1;
  164. printk("KGDB: Using serial line /dev/ttyS%d for session\n", line);
  165. speed = 0;
  166. if (*++argptr == ',')
  167. {
  168. int c;
  169. while ((c = *++argptr) && ('0' <= c && c <= '9'))
  170. speed = speed * 10 + c - '0';
  171. }
  172. {
  173. speed = rs_kgdb_hook(line, speed);
  174. generic_putDebugChar = rs_putDebugChar;
  175. generic_getDebugChar = rs_getDebugChar;
  176. }
  177. pr_info("KGDB: Using serial line /dev/ttyS%d at %d for "
  178. "session, please connect your debugger\n",
  179. line ? 1 : 0, speed);
  180. {
  181. char *s;
  182. for (s = "Please connect GDB to this port\r\n"; *s; )
  183. generic_putDebugChar(*s++);
  184. }
  185. /* Breakpoint is invoked after interrupts are initialised */
  186. }
  187. }
  188. #endif
  189. static void __init mips_nmi_setup(void)
  190. {
  191. void *base;
  192. extern char except_vec_nmi;
  193. base = cpu_has_veic ?
  194. (void *)(CAC_BASE + 0xa80) :
  195. (void *)(CAC_BASE + 0x380);
  196. memcpy(base, &except_vec_nmi, 0x80);
  197. flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
  198. }
  199. static void __init mips_ejtag_setup(void)
  200. {
  201. void *base;
  202. extern char except_vec_ejtag_debug;
  203. base = cpu_has_veic ?
  204. (void *)(CAC_BASE + 0xa00) :
  205. (void *)(CAC_BASE + 0x300);
  206. memcpy(base, &except_vec_ejtag_debug, 0x80);
  207. flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
  208. }
  209. extern struct plat_smp_ops msmtc_smp_ops;
  210. void __init prom_init(void)
  211. {
  212. prom_argc = fw_arg0;
  213. _prom_argv = (int *) fw_arg1;
  214. _prom_envp = (int *) fw_arg2;
  215. mips_display_message("LINUX");
  216. #ifdef CONFIG_MIPS_SEAD
  217. set_io_port_base(KSEG1);
  218. #else
  219. /*
  220. * early setup of _pcictrl_bonito so that we can determine
  221. * the system controller on a CORE_EMUL board
  222. */
  223. _pcictrl_bonito = (unsigned long)ioremap(BONITO_REG_BASE, BONITO_REG_SIZE);
  224. mips_revision_corid = MIPS_REVISION_CORID;
  225. if (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL) {
  226. if (BONITO_PCIDID == 0x0001df53 ||
  227. BONITO_PCIDID == 0x0003df53)
  228. mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_BON;
  229. else
  230. mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_MSC;
  231. }
  232. mips_revision_sconid = MIPS_REVISION_SCONID;
  233. if (mips_revision_sconid == MIPS_REVISION_SCON_OTHER) {
  234. switch (mips_revision_corid) {
  235. case MIPS_REVISION_CORID_QED_RM5261:
  236. case MIPS_REVISION_CORID_CORE_LV:
  237. case MIPS_REVISION_CORID_CORE_FPGA:
  238. case MIPS_REVISION_CORID_CORE_FPGAR2:
  239. mips_revision_sconid = MIPS_REVISION_SCON_GT64120;
  240. break;
  241. case MIPS_REVISION_CORID_CORE_EMUL_BON:
  242. case MIPS_REVISION_CORID_BONITO64:
  243. case MIPS_REVISION_CORID_CORE_20K:
  244. mips_revision_sconid = MIPS_REVISION_SCON_BONITO;
  245. break;
  246. case MIPS_REVISION_CORID_CORE_MSC:
  247. case MIPS_REVISION_CORID_CORE_FPGA2:
  248. case MIPS_REVISION_CORID_CORE_24K:
  249. /*
  250. * SOCit/ROCit support is essentially identical
  251. * but make an attempt to distinguish them
  252. */
  253. mips_revision_sconid = MIPS_REVISION_SCON_SOCIT;
  254. break;
  255. case MIPS_REVISION_CORID_CORE_FPGA3:
  256. case MIPS_REVISION_CORID_CORE_FPGA4:
  257. case MIPS_REVISION_CORID_CORE_FPGA5:
  258. case MIPS_REVISION_CORID_CORE_EMUL_MSC:
  259. default:
  260. /* See above */
  261. mips_revision_sconid = MIPS_REVISION_SCON_ROCIT;
  262. break;
  263. }
  264. }
  265. switch (mips_revision_sconid) {
  266. u32 start, map, mask, data;
  267. case MIPS_REVISION_SCON_GT64120:
  268. /*
  269. * Setup the North bridge to do Master byte-lane swapping
  270. * when running in bigendian.
  271. */
  272. _pcictrl_gt64120 = (unsigned long)ioremap(MIPS_GT_BASE, 0x2000);
  273. #ifdef CONFIG_CPU_LITTLE_ENDIAN
  274. GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT |
  275. GT_PCI0_CMD_SBYTESWAP_BIT);
  276. #else
  277. GT_WRITE(GT_PCI0_CMD_OFS, 0);
  278. #endif
  279. /* Fix up PCI I/O mapping if necessary (for Atlas). */
  280. start = GT_READ(GT_PCI0IOLD_OFS);
  281. map = GT_READ(GT_PCI0IOREMAP_OFS);
  282. if ((start & map) != 0) {
  283. map &= ~start;
  284. GT_WRITE(GT_PCI0IOREMAP_OFS, map);
  285. }
  286. set_io_port_base(MALTA_GT_PORT_BASE);
  287. break;
  288. case MIPS_REVISION_SCON_BONITO:
  289. _pcictrl_bonito_pcicfg = (unsigned long)ioremap(BONITO_PCICFG_BASE, BONITO_PCICFG_SIZE);
  290. /*
  291. * Disable Bonito IOBC.
  292. */
  293. BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
  294. ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
  295. BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
  296. /*
  297. * Setup the North bridge to do Master byte-lane swapping
  298. * when running in bigendian.
  299. */
  300. #ifdef CONFIG_CPU_LITTLE_ENDIAN
  301. BONITO_BONGENCFG = BONITO_BONGENCFG &
  302. ~(BONITO_BONGENCFG_MSTRBYTESWAP |
  303. BONITO_BONGENCFG_BYTESWAP);
  304. #else
  305. BONITO_BONGENCFG = BONITO_BONGENCFG |
  306. BONITO_BONGENCFG_MSTRBYTESWAP |
  307. BONITO_BONGENCFG_BYTESWAP;
  308. #endif
  309. set_io_port_base(MALTA_BONITO_PORT_BASE);
  310. break;
  311. case MIPS_REVISION_SCON_SOCIT:
  312. case MIPS_REVISION_SCON_ROCIT:
  313. _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000);
  314. mips_pci_controller:
  315. mb();
  316. MSC_READ(MSC01_PCI_CFG, data);
  317. MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT);
  318. wmb();
  319. /* Fix up lane swapping. */
  320. #ifdef CONFIG_CPU_LITTLE_ENDIAN
  321. MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP);
  322. #else
  323. MSC_WRITE(MSC01_PCI_SWAP,
  324. MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_IO_SHF |
  325. MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF |
  326. MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF);
  327. #endif
  328. /* Fix up target memory mapping. */
  329. MSC_READ(MSC01_PCI_BAR0, mask);
  330. MSC_WRITE(MSC01_PCI_P2SCMSKL, mask & MSC01_PCI_BAR0_SIZE_MSK);
  331. /* Don't handle target retries indefinitely. */
  332. if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) ==
  333. MSC01_PCI_CFG_MAXRTRY_MSK)
  334. data = (data & ~(MSC01_PCI_CFG_MAXRTRY_MSK <<
  335. MSC01_PCI_CFG_MAXRTRY_SHF)) |
  336. ((MSC01_PCI_CFG_MAXRTRY_MSK - 1) <<
  337. MSC01_PCI_CFG_MAXRTRY_SHF);
  338. wmb();
  339. MSC_WRITE(MSC01_PCI_CFG, data);
  340. mb();
  341. set_io_port_base(MALTA_MSC_PORT_BASE);
  342. break;
  343. case MIPS_REVISION_SCON_SOCITSC:
  344. case MIPS_REVISION_SCON_SOCITSCP:
  345. _pcictrl_msc = (unsigned long)ioremap(MIPS_SOCITSC_PCI_REG_BASE, 0x2000);
  346. goto mips_pci_controller;
  347. default:
  348. /* Unknown system controller */
  349. mips_display_message("SC Error");
  350. while (1); /* We die here... */
  351. }
  352. #endif
  353. board_nmi_handler_setup = mips_nmi_setup;
  354. board_ejtag_handler_setup = mips_ejtag_setup;
  355. pr_info("\nLINUX started...\n");
  356. prom_init_cmdline();
  357. prom_meminit();
  358. #ifdef CONFIG_SERIAL_8250_CONSOLE
  359. console_config();
  360. #endif
  361. #ifdef CONFIG_MIPS_CMP
  362. register_smp_ops(&cmp_smp_ops);
  363. #endif
  364. #ifdef CONFIG_MIPS_MT_SMP
  365. register_smp_ops(&vsmp_smp_ops);
  366. #endif
  367. #ifdef CONFIG_MIPS_MT_SMTC
  368. register_smp_ops(&msmtc_smp_ops);
  369. #endif
  370. }