imx53.dtsi 8.7 KB

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  1. /*
  2. * Copyright 2011 Freescale Semiconductor, Inc.
  3. * Copyright 2011 Linaro Ltd.
  4. *
  5. * The code contained herein is licensed under the GNU General Public
  6. * License. You may obtain a copy of the GNU General Public License
  7. * Version 2 or later at the following locations:
  8. *
  9. * http://www.opensource.org/licenses/gpl-license.html
  10. * http://www.gnu.org/copyleft/gpl.html
  11. */
  12. /include/ "skeleton.dtsi"
  13. / {
  14. aliases {
  15. serial0 = &uart1;
  16. serial1 = &uart2;
  17. serial2 = &uart3;
  18. serial3 = &uart4;
  19. serial4 = &uart5;
  20. gpio0 = &gpio1;
  21. gpio1 = &gpio2;
  22. gpio2 = &gpio3;
  23. gpio3 = &gpio4;
  24. gpio4 = &gpio5;
  25. gpio5 = &gpio6;
  26. gpio6 = &gpio7;
  27. };
  28. tzic: tz-interrupt-controller@0fffc000 {
  29. compatible = "fsl,imx53-tzic", "fsl,tzic";
  30. interrupt-controller;
  31. #interrupt-cells = <1>;
  32. reg = <0x0fffc000 0x4000>;
  33. };
  34. clocks {
  35. #address-cells = <1>;
  36. #size-cells = <0>;
  37. ckil {
  38. compatible = "fsl,imx-ckil", "fixed-clock";
  39. clock-frequency = <32768>;
  40. };
  41. ckih1 {
  42. compatible = "fsl,imx-ckih1", "fixed-clock";
  43. clock-frequency = <22579200>;
  44. };
  45. ckih2 {
  46. compatible = "fsl,imx-ckih2", "fixed-clock";
  47. clock-frequency = <0>;
  48. };
  49. osc {
  50. compatible = "fsl,imx-osc", "fixed-clock";
  51. clock-frequency = <24000000>;
  52. };
  53. };
  54. soc {
  55. #address-cells = <1>;
  56. #size-cells = <1>;
  57. compatible = "simple-bus";
  58. interrupt-parent = <&tzic>;
  59. ranges;
  60. aips@50000000 { /* AIPS1 */
  61. compatible = "fsl,aips-bus", "simple-bus";
  62. #address-cells = <1>;
  63. #size-cells = <1>;
  64. reg = <0x50000000 0x10000000>;
  65. ranges;
  66. spba@50000000 {
  67. compatible = "fsl,spba-bus", "simple-bus";
  68. #address-cells = <1>;
  69. #size-cells = <1>;
  70. reg = <0x50000000 0x40000>;
  71. ranges;
  72. esdhc@50004000 { /* ESDHC1 */
  73. compatible = "fsl,imx53-esdhc";
  74. reg = <0x50004000 0x4000>;
  75. interrupts = <1>;
  76. status = "disabled";
  77. };
  78. esdhc@50008000 { /* ESDHC2 */
  79. compatible = "fsl,imx53-esdhc";
  80. reg = <0x50008000 0x4000>;
  81. interrupts = <2>;
  82. status = "disabled";
  83. };
  84. uart3: serial@5000c000 {
  85. compatible = "fsl,imx53-uart", "fsl,imx21-uart";
  86. reg = <0x5000c000 0x4000>;
  87. interrupts = <33>;
  88. status = "disabled";
  89. };
  90. ecspi@50010000 { /* ECSPI1 */
  91. #address-cells = <1>;
  92. #size-cells = <0>;
  93. compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
  94. reg = <0x50010000 0x4000>;
  95. interrupts = <36>;
  96. status = "disabled";
  97. };
  98. ssi2: ssi@50014000 {
  99. compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
  100. reg = <0x50014000 0x4000>;
  101. interrupts = <30>;
  102. fsl,fifo-depth = <15>;
  103. fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
  104. status = "disabled";
  105. };
  106. esdhc@50020000 { /* ESDHC3 */
  107. compatible = "fsl,imx53-esdhc";
  108. reg = <0x50020000 0x4000>;
  109. interrupts = <3>;
  110. status = "disabled";
  111. };
  112. esdhc@50024000 { /* ESDHC4 */
  113. compatible = "fsl,imx53-esdhc";
  114. reg = <0x50024000 0x4000>;
  115. interrupts = <4>;
  116. status = "disabled";
  117. };
  118. };
  119. usb@53f80000 {
  120. compatible = "fsl,imx53-usb", "fsl,imx27-usb";
  121. reg = <0x53f80000 0x0200>;
  122. interrupts = <18>;
  123. status = "disabled";
  124. };
  125. usb@53f80200 {
  126. compatible = "fsl,imx53-usb", "fsl,imx27-usb";
  127. reg = <0x53f80200 0x0200>;
  128. interrupts = <14>;
  129. status = "disabled";
  130. };
  131. usb@53f80400 {
  132. compatible = "fsl,imx53-usb", "fsl,imx27-usb";
  133. reg = <0x53f80400 0x0200>;
  134. interrupts = <16>;
  135. status = "disabled";
  136. };
  137. usb@53f80600 {
  138. compatible = "fsl,imx53-usb", "fsl,imx27-usb";
  139. reg = <0x53f80600 0x0200>;
  140. interrupts = <17>;
  141. status = "disabled";
  142. };
  143. gpio1: gpio@53f84000 {
  144. compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
  145. reg = <0x53f84000 0x4000>;
  146. interrupts = <50 51>;
  147. gpio-controller;
  148. #gpio-cells = <2>;
  149. interrupt-controller;
  150. #interrupt-cells = <2>;
  151. };
  152. gpio2: gpio@53f88000 {
  153. compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
  154. reg = <0x53f88000 0x4000>;
  155. interrupts = <52 53>;
  156. gpio-controller;
  157. #gpio-cells = <2>;
  158. interrupt-controller;
  159. #interrupt-cells = <2>;
  160. };
  161. gpio3: gpio@53f8c000 {
  162. compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
  163. reg = <0x53f8c000 0x4000>;
  164. interrupts = <54 55>;
  165. gpio-controller;
  166. #gpio-cells = <2>;
  167. interrupt-controller;
  168. #interrupt-cells = <2>;
  169. };
  170. gpio4: gpio@53f90000 {
  171. compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
  172. reg = <0x53f90000 0x4000>;
  173. interrupts = <56 57>;
  174. gpio-controller;
  175. #gpio-cells = <2>;
  176. interrupt-controller;
  177. #interrupt-cells = <2>;
  178. };
  179. wdog@53f98000 { /* WDOG1 */
  180. compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
  181. reg = <0x53f98000 0x4000>;
  182. interrupts = <58>;
  183. };
  184. wdog@53f9c000 { /* WDOG2 */
  185. compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
  186. reg = <0x53f9c000 0x4000>;
  187. interrupts = <59>;
  188. status = "disabled";
  189. };
  190. uart1: serial@53fbc000 {
  191. compatible = "fsl,imx53-uart", "fsl,imx21-uart";
  192. reg = <0x53fbc000 0x4000>;
  193. interrupts = <31>;
  194. status = "disabled";
  195. };
  196. uart2: serial@53fc0000 {
  197. compatible = "fsl,imx53-uart", "fsl,imx21-uart";
  198. reg = <0x53fc0000 0x4000>;
  199. interrupts = <32>;
  200. status = "disabled";
  201. };
  202. can1: can@53fc8000 {
  203. compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
  204. reg = <0x53fc8000 0x4000>;
  205. interrupts = <82>;
  206. status = "disabled";
  207. };
  208. can2: can@53fcc000 {
  209. compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
  210. reg = <0x53fcc000 0x4000>;
  211. interrupts = <83>;
  212. status = "disabled";
  213. };
  214. gpio5: gpio@53fdc000 {
  215. compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
  216. reg = <0x53fdc000 0x4000>;
  217. interrupts = <103 104>;
  218. gpio-controller;
  219. #gpio-cells = <2>;
  220. interrupt-controller;
  221. #interrupt-cells = <2>;
  222. };
  223. gpio6: gpio@53fe0000 {
  224. compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
  225. reg = <0x53fe0000 0x4000>;
  226. interrupts = <105 106>;
  227. gpio-controller;
  228. #gpio-cells = <2>;
  229. interrupt-controller;
  230. #interrupt-cells = <2>;
  231. };
  232. gpio7: gpio@53fe4000 {
  233. compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
  234. reg = <0x53fe4000 0x4000>;
  235. interrupts = <107 108>;
  236. gpio-controller;
  237. #gpio-cells = <2>;
  238. interrupt-controller;
  239. #interrupt-cells = <2>;
  240. };
  241. i2c@53fec000 { /* I2C3 */
  242. #address-cells = <1>;
  243. #size-cells = <0>;
  244. compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
  245. reg = <0x53fec000 0x4000>;
  246. interrupts = <64>;
  247. status = "disabled";
  248. };
  249. uart4: serial@53ff0000 {
  250. compatible = "fsl,imx53-uart", "fsl,imx21-uart";
  251. reg = <0x53ff0000 0x4000>;
  252. interrupts = <13>;
  253. status = "disabled";
  254. };
  255. };
  256. aips@60000000 { /* AIPS2 */
  257. compatible = "fsl,aips-bus", "simple-bus";
  258. #address-cells = <1>;
  259. #size-cells = <1>;
  260. reg = <0x60000000 0x10000000>;
  261. ranges;
  262. uart5: serial@63f90000 {
  263. compatible = "fsl,imx53-uart", "fsl,imx21-uart";
  264. reg = <0x63f90000 0x4000>;
  265. interrupts = <86>;
  266. status = "disabled";
  267. };
  268. ecspi@63fac000 { /* ECSPI2 */
  269. #address-cells = <1>;
  270. #size-cells = <0>;
  271. compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
  272. reg = <0x63fac000 0x4000>;
  273. interrupts = <37>;
  274. status = "disabled";
  275. };
  276. sdma@63fb0000 {
  277. compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
  278. reg = <0x63fb0000 0x4000>;
  279. interrupts = <6>;
  280. fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
  281. };
  282. cspi@63fc0000 {
  283. #address-cells = <1>;
  284. #size-cells = <0>;
  285. compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
  286. reg = <0x63fc0000 0x4000>;
  287. interrupts = <38>;
  288. status = "disabled";
  289. };
  290. i2c@63fc4000 { /* I2C2 */
  291. #address-cells = <1>;
  292. #size-cells = <0>;
  293. compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
  294. reg = <0x63fc4000 0x4000>;
  295. interrupts = <63>;
  296. status = "disabled";
  297. };
  298. i2c@63fc8000 { /* I2C1 */
  299. #address-cells = <1>;
  300. #size-cells = <0>;
  301. compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
  302. reg = <0x63fc8000 0x4000>;
  303. interrupts = <62>;
  304. status = "disabled";
  305. };
  306. ssi1: ssi@63fcc000 {
  307. compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
  308. reg = <0x63fcc000 0x4000>;
  309. interrupts = <29>;
  310. fsl,fifo-depth = <15>;
  311. fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
  312. status = "disabled";
  313. };
  314. audmux@63fd0000 {
  315. compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
  316. reg = <0x63fd0000 0x4000>;
  317. status = "disabled";
  318. };
  319. ssi3: ssi@63fe8000 {
  320. compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
  321. reg = <0x63fe8000 0x4000>;
  322. interrupts = <96>;
  323. fsl,fifo-depth = <15>;
  324. fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
  325. status = "disabled";
  326. };
  327. ethernet@63fec000 {
  328. compatible = "fsl,imx53-fec", "fsl,imx25-fec";
  329. reg = <0x63fec000 0x4000>;
  330. interrupts = <87>;
  331. status = "disabled";
  332. };
  333. };
  334. };
  335. };