intel_crt.c 20 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741
  1. /*
  2. * Copyright © 2006-2007 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. */
  26. #include <linux/dmi.h>
  27. #include <linux/i2c.h>
  28. #include <linux/slab.h>
  29. #include "drmP.h"
  30. #include "drm.h"
  31. #include "drm_crtc.h"
  32. #include "drm_crtc_helper.h"
  33. #include "drm_edid.h"
  34. #include "intel_drv.h"
  35. #include "i915_drm.h"
  36. #include "i915_drv.h"
  37. /* Here's the desired hotplug mode */
  38. #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \
  39. ADPA_CRT_HOTPLUG_WARMUP_10MS | \
  40. ADPA_CRT_HOTPLUG_SAMPLE_4S | \
  41. ADPA_CRT_HOTPLUG_VOLTAGE_50 | \
  42. ADPA_CRT_HOTPLUG_VOLREF_325MV | \
  43. ADPA_CRT_HOTPLUG_ENABLE)
  44. struct intel_crt {
  45. struct intel_encoder base;
  46. bool force_hotplug_required;
  47. u32 adpa_reg;
  48. };
  49. static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
  50. {
  51. return container_of(intel_attached_encoder(connector),
  52. struct intel_crt, base);
  53. }
  54. static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
  55. {
  56. return container_of(encoder, struct intel_crt, base);
  57. }
  58. static void intel_disable_crt(struct intel_encoder *encoder)
  59. {
  60. struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
  61. struct intel_crt *crt = intel_encoder_to_crt(encoder);
  62. u32 temp;
  63. temp = I915_READ(crt->adpa_reg);
  64. temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
  65. temp &= ~ADPA_DAC_ENABLE;
  66. I915_WRITE(crt->adpa_reg, temp);
  67. }
  68. static void intel_enable_crt(struct intel_encoder *encoder)
  69. {
  70. struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
  71. struct intel_crt *crt = intel_encoder_to_crt(encoder);
  72. u32 temp;
  73. temp = I915_READ(crt->adpa_reg);
  74. temp |= ADPA_DAC_ENABLE;
  75. I915_WRITE(crt->adpa_reg, temp);
  76. }
  77. static void pch_crt_dpms(struct drm_encoder *encoder, int mode)
  78. {
  79. struct drm_device *dev = encoder->dev;
  80. struct drm_i915_private *dev_priv = dev->dev_private;
  81. u32 temp;
  82. temp = I915_READ(PCH_ADPA);
  83. temp &= ~ADPA_DAC_ENABLE;
  84. switch (mode) {
  85. case DRM_MODE_DPMS_ON:
  86. temp |= ADPA_DAC_ENABLE;
  87. break;
  88. case DRM_MODE_DPMS_STANDBY:
  89. case DRM_MODE_DPMS_SUSPEND:
  90. case DRM_MODE_DPMS_OFF:
  91. /* Just leave port enable cleared */
  92. break;
  93. }
  94. I915_WRITE(PCH_ADPA, temp);
  95. }
  96. static void gmch_crt_dpms(struct drm_encoder *encoder, int mode)
  97. {
  98. struct drm_device *dev = encoder->dev;
  99. struct drm_i915_private *dev_priv = dev->dev_private;
  100. u32 temp;
  101. temp = I915_READ(ADPA);
  102. temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
  103. temp &= ~ADPA_DAC_ENABLE;
  104. if (IS_VALLEYVIEW(dev) && mode != DRM_MODE_DPMS_ON)
  105. mode = DRM_MODE_DPMS_OFF;
  106. switch (mode) {
  107. case DRM_MODE_DPMS_ON:
  108. temp |= ADPA_DAC_ENABLE;
  109. break;
  110. case DRM_MODE_DPMS_STANDBY:
  111. temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
  112. break;
  113. case DRM_MODE_DPMS_SUSPEND:
  114. temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
  115. break;
  116. case DRM_MODE_DPMS_OFF:
  117. temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
  118. break;
  119. }
  120. I915_WRITE(ADPA, temp);
  121. }
  122. static int intel_crt_mode_valid(struct drm_connector *connector,
  123. struct drm_display_mode *mode)
  124. {
  125. struct drm_device *dev = connector->dev;
  126. int max_clock = 0;
  127. if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  128. return MODE_NO_DBLESCAN;
  129. if (mode->clock < 25000)
  130. return MODE_CLOCK_LOW;
  131. if (IS_GEN2(dev))
  132. max_clock = 350000;
  133. else
  134. max_clock = 400000;
  135. if (mode->clock > max_clock)
  136. return MODE_CLOCK_HIGH;
  137. return MODE_OK;
  138. }
  139. static bool intel_crt_mode_fixup(struct drm_encoder *encoder,
  140. const struct drm_display_mode *mode,
  141. struct drm_display_mode *adjusted_mode)
  142. {
  143. return true;
  144. }
  145. static void intel_crt_mode_set(struct drm_encoder *encoder,
  146. struct drm_display_mode *mode,
  147. struct drm_display_mode *adjusted_mode)
  148. {
  149. struct drm_device *dev = encoder->dev;
  150. struct drm_crtc *crtc = encoder->crtc;
  151. struct intel_crt *crt =
  152. intel_encoder_to_crt(to_intel_encoder(encoder));
  153. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  154. struct drm_i915_private *dev_priv = dev->dev_private;
  155. int dpll_md_reg;
  156. u32 adpa, dpll_md;
  157. dpll_md_reg = DPLL_MD(intel_crtc->pipe);
  158. /*
  159. * Disable separate mode multiplier used when cloning SDVO to CRT
  160. * XXX this needs to be adjusted when we really are cloning
  161. */
  162. if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
  163. dpll_md = I915_READ(dpll_md_reg);
  164. I915_WRITE(dpll_md_reg,
  165. dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK);
  166. }
  167. adpa = ADPA_HOTPLUG_BITS;
  168. if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  169. adpa |= ADPA_HSYNC_ACTIVE_HIGH;
  170. if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  171. adpa |= ADPA_VSYNC_ACTIVE_HIGH;
  172. /* For CPT allow 3 pipe config, for others just use A or B */
  173. if (HAS_PCH_CPT(dev))
  174. adpa |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
  175. else if (intel_crtc->pipe == 0)
  176. adpa |= ADPA_PIPE_A_SELECT;
  177. else
  178. adpa |= ADPA_PIPE_B_SELECT;
  179. if (!HAS_PCH_SPLIT(dev))
  180. I915_WRITE(BCLRPAT(intel_crtc->pipe), 0);
  181. I915_WRITE(crt->adpa_reg, adpa);
  182. }
  183. static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
  184. {
  185. struct drm_device *dev = connector->dev;
  186. struct intel_crt *crt = intel_attached_crt(connector);
  187. struct drm_i915_private *dev_priv = dev->dev_private;
  188. u32 adpa;
  189. bool ret;
  190. /* The first time through, trigger an explicit detection cycle */
  191. if (crt->force_hotplug_required) {
  192. bool turn_off_dac = HAS_PCH_SPLIT(dev);
  193. u32 save_adpa;
  194. crt->force_hotplug_required = 0;
  195. save_adpa = adpa = I915_READ(PCH_ADPA);
  196. DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
  197. adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
  198. if (turn_off_dac)
  199. adpa &= ~ADPA_DAC_ENABLE;
  200. I915_WRITE(PCH_ADPA, adpa);
  201. if (wait_for((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
  202. 1000))
  203. DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
  204. if (turn_off_dac) {
  205. I915_WRITE(PCH_ADPA, save_adpa);
  206. POSTING_READ(PCH_ADPA);
  207. }
  208. }
  209. /* Check the status to see if both blue and green are on now */
  210. adpa = I915_READ(PCH_ADPA);
  211. if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
  212. ret = true;
  213. else
  214. ret = false;
  215. DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
  216. return ret;
  217. }
  218. static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
  219. {
  220. struct drm_device *dev = connector->dev;
  221. struct drm_i915_private *dev_priv = dev->dev_private;
  222. u32 adpa;
  223. bool ret;
  224. u32 save_adpa;
  225. save_adpa = adpa = I915_READ(ADPA);
  226. DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
  227. adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
  228. I915_WRITE(ADPA, adpa);
  229. if (wait_for((I915_READ(ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
  230. 1000)) {
  231. DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
  232. I915_WRITE(ADPA, save_adpa);
  233. }
  234. /* Check the status to see if both blue and green are on now */
  235. adpa = I915_READ(ADPA);
  236. if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
  237. ret = true;
  238. else
  239. ret = false;
  240. DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
  241. /* FIXME: debug force function and remove */
  242. ret = true;
  243. return ret;
  244. }
  245. /**
  246. * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
  247. *
  248. * Not for i915G/i915GM
  249. *
  250. * \return true if CRT is connected.
  251. * \return false if CRT is disconnected.
  252. */
  253. static bool intel_crt_detect_hotplug(struct drm_connector *connector)
  254. {
  255. struct drm_device *dev = connector->dev;
  256. struct drm_i915_private *dev_priv = dev->dev_private;
  257. u32 hotplug_en, orig, stat;
  258. bool ret = false;
  259. int i, tries = 0;
  260. if (HAS_PCH_SPLIT(dev))
  261. return intel_ironlake_crt_detect_hotplug(connector);
  262. if (IS_VALLEYVIEW(dev))
  263. return valleyview_crt_detect_hotplug(connector);
  264. /*
  265. * On 4 series desktop, CRT detect sequence need to be done twice
  266. * to get a reliable result.
  267. */
  268. if (IS_G4X(dev) && !IS_GM45(dev))
  269. tries = 2;
  270. else
  271. tries = 1;
  272. hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN);
  273. hotplug_en |= CRT_HOTPLUG_FORCE_DETECT;
  274. for (i = 0; i < tries ; i++) {
  275. /* turn on the FORCE_DETECT */
  276. I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
  277. /* wait for FORCE_DETECT to go off */
  278. if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
  279. CRT_HOTPLUG_FORCE_DETECT) == 0,
  280. 1000))
  281. DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
  282. }
  283. stat = I915_READ(PORT_HOTPLUG_STAT);
  284. if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
  285. ret = true;
  286. /* clear the interrupt we just generated, if any */
  287. I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
  288. /* and put the bits back */
  289. I915_WRITE(PORT_HOTPLUG_EN, orig);
  290. return ret;
  291. }
  292. static bool intel_crt_detect_ddc(struct drm_connector *connector)
  293. {
  294. struct intel_crt *crt = intel_attached_crt(connector);
  295. struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private;
  296. struct edid *edid;
  297. struct i2c_adapter *i2c;
  298. BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
  299. i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->crt_ddc_pin);
  300. edid = drm_get_edid(connector, i2c);
  301. if (edid) {
  302. bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
  303. /*
  304. * This may be a DVI-I connector with a shared DDC
  305. * link between analog and digital outputs, so we
  306. * have to check the EDID input spec of the attached device.
  307. */
  308. if (!is_digital) {
  309. DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
  310. return true;
  311. }
  312. DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
  313. } else {
  314. DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n");
  315. }
  316. kfree(edid);
  317. return false;
  318. }
  319. static enum drm_connector_status
  320. intel_crt_load_detect(struct intel_crt *crt)
  321. {
  322. struct drm_device *dev = crt->base.base.dev;
  323. struct drm_i915_private *dev_priv = dev->dev_private;
  324. uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe;
  325. uint32_t save_bclrpat;
  326. uint32_t save_vtotal;
  327. uint32_t vtotal, vactive;
  328. uint32_t vsample;
  329. uint32_t vblank, vblank_start, vblank_end;
  330. uint32_t dsl;
  331. uint32_t bclrpat_reg;
  332. uint32_t vtotal_reg;
  333. uint32_t vblank_reg;
  334. uint32_t vsync_reg;
  335. uint32_t pipeconf_reg;
  336. uint32_t pipe_dsl_reg;
  337. uint8_t st00;
  338. enum drm_connector_status status;
  339. DRM_DEBUG_KMS("starting load-detect on CRT\n");
  340. bclrpat_reg = BCLRPAT(pipe);
  341. vtotal_reg = VTOTAL(pipe);
  342. vblank_reg = VBLANK(pipe);
  343. vsync_reg = VSYNC(pipe);
  344. pipeconf_reg = PIPECONF(pipe);
  345. pipe_dsl_reg = PIPEDSL(pipe);
  346. save_bclrpat = I915_READ(bclrpat_reg);
  347. save_vtotal = I915_READ(vtotal_reg);
  348. vblank = I915_READ(vblank_reg);
  349. vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
  350. vactive = (save_vtotal & 0x7ff) + 1;
  351. vblank_start = (vblank & 0xfff) + 1;
  352. vblank_end = ((vblank >> 16) & 0xfff) + 1;
  353. /* Set the border color to purple. */
  354. I915_WRITE(bclrpat_reg, 0x500050);
  355. if (!IS_GEN2(dev)) {
  356. uint32_t pipeconf = I915_READ(pipeconf_reg);
  357. I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
  358. POSTING_READ(pipeconf_reg);
  359. /* Wait for next Vblank to substitue
  360. * border color for Color info */
  361. intel_wait_for_vblank(dev, pipe);
  362. st00 = I915_READ8(VGA_MSR_WRITE);
  363. status = ((st00 & (1 << 4)) != 0) ?
  364. connector_status_connected :
  365. connector_status_disconnected;
  366. I915_WRITE(pipeconf_reg, pipeconf);
  367. } else {
  368. bool restore_vblank = false;
  369. int count, detect;
  370. /*
  371. * If there isn't any border, add some.
  372. * Yes, this will flicker
  373. */
  374. if (vblank_start <= vactive && vblank_end >= vtotal) {
  375. uint32_t vsync = I915_READ(vsync_reg);
  376. uint32_t vsync_start = (vsync & 0xffff) + 1;
  377. vblank_start = vsync_start;
  378. I915_WRITE(vblank_reg,
  379. (vblank_start - 1) |
  380. ((vblank_end - 1) << 16));
  381. restore_vblank = true;
  382. }
  383. /* sample in the vertical border, selecting the larger one */
  384. if (vblank_start - vactive >= vtotal - vblank_end)
  385. vsample = (vblank_start + vactive) >> 1;
  386. else
  387. vsample = (vtotal + vblank_end) >> 1;
  388. /*
  389. * Wait for the border to be displayed
  390. */
  391. while (I915_READ(pipe_dsl_reg) >= vactive)
  392. ;
  393. while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
  394. ;
  395. /*
  396. * Watch ST00 for an entire scanline
  397. */
  398. detect = 0;
  399. count = 0;
  400. do {
  401. count++;
  402. /* Read the ST00 VGA status register */
  403. st00 = I915_READ8(VGA_MSR_WRITE);
  404. if (st00 & (1 << 4))
  405. detect++;
  406. } while ((I915_READ(pipe_dsl_reg) == dsl));
  407. /* restore vblank if necessary */
  408. if (restore_vblank)
  409. I915_WRITE(vblank_reg, vblank);
  410. /*
  411. * If more than 3/4 of the scanline detected a monitor,
  412. * then it is assumed to be present. This works even on i830,
  413. * where there isn't any way to force the border color across
  414. * the screen
  415. */
  416. status = detect * 4 > count * 3 ?
  417. connector_status_connected :
  418. connector_status_disconnected;
  419. }
  420. /* Restore previous settings */
  421. I915_WRITE(bclrpat_reg, save_bclrpat);
  422. return status;
  423. }
  424. static enum drm_connector_status
  425. intel_crt_detect(struct drm_connector *connector, bool force)
  426. {
  427. struct drm_device *dev = connector->dev;
  428. struct intel_crt *crt = intel_attached_crt(connector);
  429. enum drm_connector_status status;
  430. struct intel_load_detect_pipe tmp;
  431. if (I915_HAS_HOTPLUG(dev)) {
  432. /* We can not rely on the HPD pin always being correctly wired
  433. * up, for example many KVM do not pass it through, and so
  434. * only trust an assertion that the monitor is connected.
  435. */
  436. if (intel_crt_detect_hotplug(connector)) {
  437. DRM_DEBUG_KMS("CRT detected via hotplug\n");
  438. return connector_status_connected;
  439. } else
  440. DRM_DEBUG_KMS("CRT not detected via hotplug\n");
  441. }
  442. if (intel_crt_detect_ddc(connector))
  443. return connector_status_connected;
  444. /* Load detection is broken on HPD capable machines. Whoever wants a
  445. * broken monitor (without edid) to work behind a broken kvm (that fails
  446. * to have the right resistors for HP detection) needs to fix this up.
  447. * For now just bail out. */
  448. if (I915_HAS_HOTPLUG(dev))
  449. return connector_status_disconnected;
  450. if (!force)
  451. return connector->status;
  452. /* for pre-945g platforms use load detect */
  453. if (intel_get_load_detect_pipe(connector, NULL, &tmp)) {
  454. if (intel_crt_detect_ddc(connector))
  455. status = connector_status_connected;
  456. else
  457. status = intel_crt_load_detect(crt);
  458. intel_release_load_detect_pipe(connector, &tmp);
  459. } else
  460. status = connector_status_unknown;
  461. return status;
  462. }
  463. static void intel_crt_destroy(struct drm_connector *connector)
  464. {
  465. drm_sysfs_connector_remove(connector);
  466. drm_connector_cleanup(connector);
  467. kfree(connector);
  468. }
  469. static int intel_crt_get_modes(struct drm_connector *connector)
  470. {
  471. struct drm_device *dev = connector->dev;
  472. struct drm_i915_private *dev_priv = dev->dev_private;
  473. int ret;
  474. struct i2c_adapter *i2c;
  475. i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->crt_ddc_pin);
  476. ret = intel_ddc_get_modes(connector, i2c);
  477. if (ret || !IS_G4X(dev))
  478. return ret;
  479. /* Try to probe digital port for output in DVI-I -> VGA mode. */
  480. i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB);
  481. return intel_ddc_get_modes(connector, i2c);
  482. }
  483. static int intel_crt_set_property(struct drm_connector *connector,
  484. struct drm_property *property,
  485. uint64_t value)
  486. {
  487. return 0;
  488. }
  489. static void intel_crt_reset(struct drm_connector *connector)
  490. {
  491. struct drm_device *dev = connector->dev;
  492. struct intel_crt *crt = intel_attached_crt(connector);
  493. if (HAS_PCH_SPLIT(dev))
  494. crt->force_hotplug_required = 1;
  495. }
  496. /*
  497. * Routines for controlling stuff on the analog port
  498. */
  499. static const struct drm_encoder_helper_funcs pch_encoder_funcs = {
  500. .mode_fixup = intel_crt_mode_fixup,
  501. .prepare = intel_encoder_noop,
  502. .commit = intel_encoder_noop,
  503. .mode_set = intel_crt_mode_set,
  504. .dpms = pch_crt_dpms,
  505. .disable = intel_encoder_disable,
  506. };
  507. static const struct drm_encoder_helper_funcs gmch_encoder_funcs = {
  508. .mode_fixup = intel_crt_mode_fixup,
  509. .prepare = intel_encoder_noop,
  510. .commit = intel_encoder_noop,
  511. .mode_set = intel_crt_mode_set,
  512. .dpms = gmch_crt_dpms,
  513. .disable = intel_encoder_disable,
  514. };
  515. static const struct drm_connector_funcs intel_crt_connector_funcs = {
  516. .reset = intel_crt_reset,
  517. .dpms = drm_helper_connector_dpms,
  518. .detect = intel_crt_detect,
  519. .fill_modes = drm_helper_probe_single_connector_modes,
  520. .destroy = intel_crt_destroy,
  521. .set_property = intel_crt_set_property,
  522. };
  523. static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
  524. .mode_valid = intel_crt_mode_valid,
  525. .get_modes = intel_crt_get_modes,
  526. .best_encoder = intel_best_encoder,
  527. };
  528. static const struct drm_encoder_funcs intel_crt_enc_funcs = {
  529. .destroy = intel_encoder_destroy,
  530. };
  531. static int __init intel_no_crt_dmi_callback(const struct dmi_system_id *id)
  532. {
  533. DRM_INFO("Skipping CRT initialization for %s\n", id->ident);
  534. return 1;
  535. }
  536. static const struct dmi_system_id intel_no_crt[] = {
  537. {
  538. .callback = intel_no_crt_dmi_callback,
  539. .ident = "ACER ZGB",
  540. .matches = {
  541. DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
  542. DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
  543. },
  544. },
  545. { }
  546. };
  547. void intel_crt_init(struct drm_device *dev)
  548. {
  549. struct drm_connector *connector;
  550. struct intel_crt *crt;
  551. struct intel_connector *intel_connector;
  552. struct drm_i915_private *dev_priv = dev->dev_private;
  553. const struct drm_encoder_helper_funcs *encoder_helper_funcs;
  554. /* Skip machines without VGA that falsely report hotplug events */
  555. if (dmi_check_system(intel_no_crt))
  556. return;
  557. crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
  558. if (!crt)
  559. return;
  560. intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
  561. if (!intel_connector) {
  562. kfree(crt);
  563. return;
  564. }
  565. connector = &intel_connector->base;
  566. drm_connector_init(dev, &intel_connector->base,
  567. &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
  568. drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs,
  569. DRM_MODE_ENCODER_DAC);
  570. intel_connector_attach_encoder(intel_connector, &crt->base);
  571. crt->base.type = INTEL_OUTPUT_ANALOG;
  572. crt->base.cloneable = true;
  573. if (IS_HASWELL(dev))
  574. crt->base.crtc_mask = (1 << 0);
  575. else
  576. crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
  577. if (IS_GEN2(dev))
  578. connector->interlace_allowed = 0;
  579. else
  580. connector->interlace_allowed = 1;
  581. connector->doublescan_allowed = 0;
  582. if (HAS_PCH_SPLIT(dev))
  583. encoder_helper_funcs = &pch_encoder_funcs;
  584. else
  585. encoder_helper_funcs = &gmch_encoder_funcs;
  586. if (HAS_PCH_SPLIT(dev))
  587. crt->adpa_reg = PCH_ADPA;
  588. else if (IS_VALLEYVIEW(dev))
  589. crt->adpa_reg = VLV_ADPA;
  590. else
  591. crt->adpa_reg = ADPA;
  592. crt->base.disable = intel_disable_crt;
  593. crt->base.enable = intel_enable_crt;
  594. drm_encoder_helper_add(&crt->base.base, encoder_helper_funcs);
  595. drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
  596. drm_sysfs_connector_add(connector);
  597. if (I915_HAS_HOTPLUG(dev))
  598. connector->polled = DRM_CONNECTOR_POLL_HPD;
  599. else
  600. connector->polled = DRM_CONNECTOR_POLL_CONNECT;
  601. /*
  602. * Configure the automatic hotplug detection stuff
  603. */
  604. crt->force_hotplug_required = 0;
  605. if (HAS_PCH_SPLIT(dev)) {
  606. u32 adpa;
  607. adpa = I915_READ(PCH_ADPA);
  608. adpa &= ~ADPA_CRT_HOTPLUG_MASK;
  609. adpa |= ADPA_HOTPLUG_BITS;
  610. I915_WRITE(PCH_ADPA, adpa);
  611. POSTING_READ(PCH_ADPA);
  612. DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa);
  613. crt->force_hotplug_required = 1;
  614. }
  615. dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS;
  616. }