main.c 51 KB

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  1. /*
  2. * Copyright (c) 2008-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/nl80211.h>
  17. #include <linux/delay.h>
  18. #include "ath9k.h"
  19. #include "btcoex.h"
  20. static u8 parse_mpdudensity(u8 mpdudensity)
  21. {
  22. /*
  23. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  24. * 0 for no restriction
  25. * 1 for 1/4 us
  26. * 2 for 1/2 us
  27. * 3 for 1 us
  28. * 4 for 2 us
  29. * 5 for 4 us
  30. * 6 for 8 us
  31. * 7 for 16 us
  32. */
  33. switch (mpdudensity) {
  34. case 0:
  35. return 0;
  36. case 1:
  37. case 2:
  38. case 3:
  39. /* Our lower layer calculations limit our precision to
  40. 1 microsecond */
  41. return 1;
  42. case 4:
  43. return 2;
  44. case 5:
  45. return 4;
  46. case 6:
  47. return 8;
  48. case 7:
  49. return 16;
  50. default:
  51. return 0;
  52. }
  53. }
  54. static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
  55. {
  56. bool pending = false;
  57. spin_lock_bh(&txq->axq_lock);
  58. if (txq->axq_depth || !list_empty(&txq->axq_acq))
  59. pending = true;
  60. spin_unlock_bh(&txq->axq_lock);
  61. return pending;
  62. }
  63. static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
  64. {
  65. unsigned long flags;
  66. bool ret;
  67. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  68. ret = ath9k_hw_setpower(sc->sc_ah, mode);
  69. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  70. return ret;
  71. }
  72. void ath9k_ps_wakeup(struct ath_softc *sc)
  73. {
  74. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  75. unsigned long flags;
  76. enum ath9k_power_mode power_mode;
  77. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  78. if (++sc->ps_usecount != 1)
  79. goto unlock;
  80. power_mode = sc->sc_ah->power_mode;
  81. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  82. /*
  83. * While the hardware is asleep, the cycle counters contain no
  84. * useful data. Better clear them now so that they don't mess up
  85. * survey data results.
  86. */
  87. if (power_mode != ATH9K_PM_AWAKE) {
  88. spin_lock(&common->cc_lock);
  89. ath_hw_cycle_counters_update(common);
  90. memset(&common->cc_survey, 0, sizeof(common->cc_survey));
  91. memset(&common->cc_ani, 0, sizeof(common->cc_ani));
  92. spin_unlock(&common->cc_lock);
  93. }
  94. unlock:
  95. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  96. }
  97. void ath9k_ps_restore(struct ath_softc *sc)
  98. {
  99. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  100. enum ath9k_power_mode mode;
  101. unsigned long flags;
  102. bool reset;
  103. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  104. if (--sc->ps_usecount != 0)
  105. goto unlock;
  106. if (sc->ps_idle) {
  107. ath9k_hw_setrxabort(sc->sc_ah, 1);
  108. ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
  109. mode = ATH9K_PM_FULL_SLEEP;
  110. } else if (sc->ps_enabled &&
  111. !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
  112. PS_WAIT_FOR_CAB |
  113. PS_WAIT_FOR_PSPOLL_DATA |
  114. PS_WAIT_FOR_TX_ACK))) {
  115. mode = ATH9K_PM_NETWORK_SLEEP;
  116. } else {
  117. goto unlock;
  118. }
  119. spin_lock(&common->cc_lock);
  120. ath_hw_cycle_counters_update(common);
  121. spin_unlock(&common->cc_lock);
  122. ath9k_hw_setpower(sc->sc_ah, mode);
  123. unlock:
  124. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  125. }
  126. static void __ath_cancel_work(struct ath_softc *sc)
  127. {
  128. cancel_work_sync(&sc->paprd_work);
  129. cancel_work_sync(&sc->hw_check_work);
  130. cancel_delayed_work_sync(&sc->tx_complete_work);
  131. cancel_delayed_work_sync(&sc->hw_pll_work);
  132. #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
  133. cancel_work_sync(&sc->mci_work);
  134. #endif
  135. }
  136. static void ath_cancel_work(struct ath_softc *sc)
  137. {
  138. __ath_cancel_work(sc);
  139. cancel_work_sync(&sc->hw_reset_work);
  140. }
  141. static void ath_restart_work(struct ath_softc *sc)
  142. {
  143. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  144. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  145. if (AR_SREV_9485(sc->sc_ah) || AR_SREV_9340(sc->sc_ah))
  146. ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
  147. msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
  148. ath_start_rx_poll(sc, 3);
  149. if (!common->disable_ani)
  150. ath_start_ani(common);
  151. }
  152. static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush)
  153. {
  154. struct ath_hw *ah = sc->sc_ah;
  155. struct ath_common *common = ath9k_hw_common(ah);
  156. bool ret = true;
  157. ieee80211_stop_queues(sc->hw);
  158. sc->hw_busy_count = 0;
  159. del_timer_sync(&common->ani.timer);
  160. del_timer_sync(&sc->rx_poll_timer);
  161. ath9k_debug_samp_bb_mac(sc);
  162. ath9k_hw_disable_interrupts(ah);
  163. if (!ath_stoprecv(sc))
  164. ret = false;
  165. if (!ath_drain_all_txq(sc, retry_tx))
  166. ret = false;
  167. if (!flush) {
  168. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  169. ath_rx_tasklet(sc, 1, true);
  170. ath_rx_tasklet(sc, 1, false);
  171. } else {
  172. ath_flushrecv(sc);
  173. }
  174. return ret;
  175. }
  176. static bool ath_complete_reset(struct ath_softc *sc, bool start)
  177. {
  178. struct ath_hw *ah = sc->sc_ah;
  179. struct ath_common *common = ath9k_hw_common(ah);
  180. unsigned long flags;
  181. if (ath_startrecv(sc) != 0) {
  182. ath_err(common, "Unable to restart recv logic\n");
  183. return false;
  184. }
  185. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  186. sc->config.txpowlimit, &sc->curtxpow);
  187. clear_bit(SC_OP_HW_RESET, &sc->sc_flags);
  188. ath9k_hw_set_interrupts(ah);
  189. ath9k_hw_enable_interrupts(ah);
  190. if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) {
  191. if (!test_bit(SC_OP_BEACONS, &sc->sc_flags))
  192. goto work;
  193. ath_set_beacon(sc);
  194. if (ah->opmode == NL80211_IFTYPE_STATION &&
  195. test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  196. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  197. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  198. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  199. }
  200. work:
  201. ath_restart_work(sc);
  202. }
  203. if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3)
  204. ath_ant_comb_update(sc);
  205. ieee80211_wake_queues(sc->hw);
  206. return true;
  207. }
  208. static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan,
  209. bool retry_tx)
  210. {
  211. struct ath_hw *ah = sc->sc_ah;
  212. struct ath_common *common = ath9k_hw_common(ah);
  213. struct ath9k_hw_cal_data *caldata = NULL;
  214. bool fastcc = true;
  215. bool flush = false;
  216. int r;
  217. __ath_cancel_work(sc);
  218. spin_lock_bh(&sc->sc_pcu_lock);
  219. if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) {
  220. fastcc = false;
  221. caldata = &sc->caldata;
  222. }
  223. if (!hchan) {
  224. fastcc = false;
  225. flush = true;
  226. hchan = ah->curchan;
  227. }
  228. if (!ath_prepare_reset(sc, retry_tx, flush))
  229. fastcc = false;
  230. ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
  231. hchan->channel, IS_CHAN_HT40(hchan), fastcc);
  232. r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
  233. if (r) {
  234. ath_err(common,
  235. "Unable to reset channel, reset status %d\n", r);
  236. goto out;
  237. }
  238. if (!ath_complete_reset(sc, true))
  239. r = -EIO;
  240. out:
  241. spin_unlock_bh(&sc->sc_pcu_lock);
  242. return r;
  243. }
  244. /*
  245. * Set/change channels. If the channel is really being changed, it's done
  246. * by reseting the chip. To accomplish this we must first cleanup any pending
  247. * DMA, then restart stuff.
  248. */
  249. static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
  250. struct ath9k_channel *hchan)
  251. {
  252. int r;
  253. if (test_bit(SC_OP_INVALID, &sc->sc_flags))
  254. return -EIO;
  255. r = ath_reset_internal(sc, hchan, false);
  256. return r;
  257. }
  258. static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
  259. struct ieee80211_vif *vif)
  260. {
  261. struct ath_node *an;
  262. an = (struct ath_node *)sta->drv_priv;
  263. #ifdef CONFIG_ATH9K_DEBUGFS
  264. spin_lock(&sc->nodes_lock);
  265. list_add(&an->list, &sc->nodes);
  266. spin_unlock(&sc->nodes_lock);
  267. #endif
  268. an->sta = sta;
  269. an->vif = vif;
  270. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
  271. ath_tx_node_init(sc, an);
  272. an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
  273. sta->ht_cap.ampdu_factor);
  274. an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
  275. }
  276. }
  277. static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
  278. {
  279. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  280. #ifdef CONFIG_ATH9K_DEBUGFS
  281. spin_lock(&sc->nodes_lock);
  282. list_del(&an->list);
  283. spin_unlock(&sc->nodes_lock);
  284. an->sta = NULL;
  285. #endif
  286. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  287. ath_tx_node_cleanup(sc, an);
  288. }
  289. void ath9k_tasklet(unsigned long data)
  290. {
  291. struct ath_softc *sc = (struct ath_softc *)data;
  292. struct ath_hw *ah = sc->sc_ah;
  293. struct ath_common *common = ath9k_hw_common(ah);
  294. unsigned long flags;
  295. u32 status = sc->intrstatus;
  296. u32 rxmask;
  297. ath9k_ps_wakeup(sc);
  298. spin_lock(&sc->sc_pcu_lock);
  299. if ((status & ATH9K_INT_FATAL) ||
  300. (status & ATH9K_INT_BB_WATCHDOG)) {
  301. #ifdef CONFIG_ATH9K_DEBUGFS
  302. enum ath_reset_type type;
  303. if (status & ATH9K_INT_FATAL)
  304. type = RESET_TYPE_FATAL_INT;
  305. else
  306. type = RESET_TYPE_BB_WATCHDOG;
  307. RESET_STAT_INC(sc, type);
  308. #endif
  309. set_bit(SC_OP_HW_RESET, &sc->sc_flags);
  310. ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
  311. goto out;
  312. }
  313. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  314. if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
  315. /*
  316. * TSF sync does not look correct; remain awake to sync with
  317. * the next Beacon.
  318. */
  319. ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
  320. sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
  321. }
  322. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  323. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  324. rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
  325. ATH9K_INT_RXORN);
  326. else
  327. rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  328. if (status & rxmask) {
  329. /* Check for high priority Rx first */
  330. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  331. (status & ATH9K_INT_RXHP))
  332. ath_rx_tasklet(sc, 0, true);
  333. ath_rx_tasklet(sc, 0, false);
  334. }
  335. if (status & ATH9K_INT_TX) {
  336. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  337. ath_tx_edma_tasklet(sc);
  338. else
  339. ath_tx_tasklet(sc);
  340. }
  341. ath9k_btcoex_handle_interrupt(sc, status);
  342. out:
  343. /* re-enable hardware interrupt */
  344. ath9k_hw_enable_interrupts(ah);
  345. spin_unlock(&sc->sc_pcu_lock);
  346. ath9k_ps_restore(sc);
  347. }
  348. irqreturn_t ath_isr(int irq, void *dev)
  349. {
  350. #define SCHED_INTR ( \
  351. ATH9K_INT_FATAL | \
  352. ATH9K_INT_BB_WATCHDOG | \
  353. ATH9K_INT_RXORN | \
  354. ATH9K_INT_RXEOL | \
  355. ATH9K_INT_RX | \
  356. ATH9K_INT_RXLP | \
  357. ATH9K_INT_RXHP | \
  358. ATH9K_INT_TX | \
  359. ATH9K_INT_BMISS | \
  360. ATH9K_INT_CST | \
  361. ATH9K_INT_TSFOOR | \
  362. ATH9K_INT_GENTIMER | \
  363. ATH9K_INT_MCI)
  364. struct ath_softc *sc = dev;
  365. struct ath_hw *ah = sc->sc_ah;
  366. struct ath_common *common = ath9k_hw_common(ah);
  367. enum ath9k_int status;
  368. bool sched = false;
  369. /*
  370. * The hardware is not ready/present, don't
  371. * touch anything. Note this can happen early
  372. * on if the IRQ is shared.
  373. */
  374. if (test_bit(SC_OP_INVALID, &sc->sc_flags))
  375. return IRQ_NONE;
  376. /* shared irq, not for us */
  377. if (!ath9k_hw_intrpend(ah))
  378. return IRQ_NONE;
  379. if(test_bit(SC_OP_HW_RESET, &sc->sc_flags))
  380. return IRQ_HANDLED;
  381. /*
  382. * Figure out the reason(s) for the interrupt. Note
  383. * that the hal returns a pseudo-ISR that may include
  384. * bits we haven't explicitly enabled so we mask the
  385. * value to insure we only process bits we requested.
  386. */
  387. ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
  388. status &= ah->imask; /* discard unasked-for bits */
  389. /*
  390. * If there are no status bits set, then this interrupt was not
  391. * for me (should have been caught above).
  392. */
  393. if (!status)
  394. return IRQ_NONE;
  395. /* Cache the status */
  396. sc->intrstatus = status;
  397. if (status & SCHED_INTR)
  398. sched = true;
  399. /*
  400. * If a FATAL or RXORN interrupt is received, we have to reset the
  401. * chip immediately.
  402. */
  403. if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
  404. !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
  405. goto chip_reset;
  406. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  407. (status & ATH9K_INT_BB_WATCHDOG)) {
  408. spin_lock(&common->cc_lock);
  409. ath_hw_cycle_counters_update(common);
  410. ar9003_hw_bb_watchdog_dbg_info(ah);
  411. spin_unlock(&common->cc_lock);
  412. goto chip_reset;
  413. }
  414. if (status & ATH9K_INT_SWBA)
  415. tasklet_schedule(&sc->bcon_tasklet);
  416. if (status & ATH9K_INT_TXURN)
  417. ath9k_hw_updatetxtriglevel(ah, true);
  418. if (status & ATH9K_INT_RXEOL) {
  419. ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  420. ath9k_hw_set_interrupts(ah);
  421. }
  422. if (status & ATH9K_INT_MIB) {
  423. /*
  424. * Disable interrupts until we service the MIB
  425. * interrupt; otherwise it will continue to
  426. * fire.
  427. */
  428. ath9k_hw_disable_interrupts(ah);
  429. /*
  430. * Let the hal handle the event. We assume
  431. * it will clear whatever condition caused
  432. * the interrupt.
  433. */
  434. spin_lock(&common->cc_lock);
  435. ath9k_hw_proc_mib_event(ah);
  436. spin_unlock(&common->cc_lock);
  437. ath9k_hw_enable_interrupts(ah);
  438. }
  439. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  440. if (status & ATH9K_INT_TIM_TIMER) {
  441. if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
  442. goto chip_reset;
  443. /* Clear RxAbort bit so that we can
  444. * receive frames */
  445. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  446. spin_lock(&sc->sc_pm_lock);
  447. ath9k_hw_setrxabort(sc->sc_ah, 0);
  448. sc->ps_flags |= PS_WAIT_FOR_BEACON;
  449. spin_unlock(&sc->sc_pm_lock);
  450. }
  451. chip_reset:
  452. ath_debug_stat_interrupt(sc, status);
  453. if (sched) {
  454. /* turn off every interrupt */
  455. ath9k_hw_disable_interrupts(ah);
  456. tasklet_schedule(&sc->intr_tq);
  457. }
  458. return IRQ_HANDLED;
  459. #undef SCHED_INTR
  460. }
  461. static int ath_reset(struct ath_softc *sc, bool retry_tx)
  462. {
  463. int r;
  464. ath9k_ps_wakeup(sc);
  465. r = ath_reset_internal(sc, NULL, retry_tx);
  466. if (retry_tx) {
  467. int i;
  468. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  469. if (ATH_TXQ_SETUP(sc, i)) {
  470. spin_lock_bh(&sc->tx.txq[i].axq_lock);
  471. ath_txq_schedule(sc, &sc->tx.txq[i]);
  472. spin_unlock_bh(&sc->tx.txq[i].axq_lock);
  473. }
  474. }
  475. }
  476. ath9k_ps_restore(sc);
  477. return r;
  478. }
  479. void ath_reset_work(struct work_struct *work)
  480. {
  481. struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
  482. ath_reset(sc, true);
  483. }
  484. /**********************/
  485. /* mac80211 callbacks */
  486. /**********************/
  487. static int ath9k_start(struct ieee80211_hw *hw)
  488. {
  489. struct ath_softc *sc = hw->priv;
  490. struct ath_hw *ah = sc->sc_ah;
  491. struct ath_common *common = ath9k_hw_common(ah);
  492. struct ieee80211_channel *curchan = hw->conf.channel;
  493. struct ath9k_channel *init_channel;
  494. int r;
  495. ath_dbg(common, CONFIG,
  496. "Starting driver with initial channel: %d MHz\n",
  497. curchan->center_freq);
  498. ath9k_ps_wakeup(sc);
  499. mutex_lock(&sc->mutex);
  500. init_channel = ath9k_cmn_get_curchannel(hw, ah);
  501. /* Reset SERDES registers */
  502. ath9k_hw_configpcipowersave(ah, false);
  503. /*
  504. * The basic interface to setting the hardware in a good
  505. * state is ``reset''. On return the hardware is known to
  506. * be powered up and with interrupts disabled. This must
  507. * be followed by initialization of the appropriate bits
  508. * and then setup of the interrupt mask.
  509. */
  510. spin_lock_bh(&sc->sc_pcu_lock);
  511. atomic_set(&ah->intr_ref_cnt, -1);
  512. r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
  513. if (r) {
  514. ath_err(common,
  515. "Unable to reset hardware; reset status %d (freq %u MHz)\n",
  516. r, curchan->center_freq);
  517. spin_unlock_bh(&sc->sc_pcu_lock);
  518. goto mutex_unlock;
  519. }
  520. /* Setup our intr mask. */
  521. ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
  522. ATH9K_INT_RXORN | ATH9K_INT_FATAL |
  523. ATH9K_INT_GLOBAL;
  524. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  525. ah->imask |= ATH9K_INT_RXHP |
  526. ATH9K_INT_RXLP |
  527. ATH9K_INT_BB_WATCHDOG;
  528. else
  529. ah->imask |= ATH9K_INT_RX;
  530. ah->imask |= ATH9K_INT_GTT;
  531. if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  532. ah->imask |= ATH9K_INT_CST;
  533. ath_mci_enable(sc);
  534. clear_bit(SC_OP_INVALID, &sc->sc_flags);
  535. sc->sc_ah->is_monitoring = false;
  536. if (!ath_complete_reset(sc, false)) {
  537. r = -EIO;
  538. spin_unlock_bh(&sc->sc_pcu_lock);
  539. goto mutex_unlock;
  540. }
  541. if (ah->led_pin >= 0) {
  542. ath9k_hw_cfg_output(ah, ah->led_pin,
  543. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  544. ath9k_hw_set_gpio(ah, ah->led_pin, 0);
  545. }
  546. /*
  547. * Reset key cache to sane defaults (all entries cleared) instead of
  548. * semi-random values after suspend/resume.
  549. */
  550. ath9k_cmn_init_crypto(sc->sc_ah);
  551. spin_unlock_bh(&sc->sc_pcu_lock);
  552. ath9k_start_btcoex(sc);
  553. if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
  554. common->bus_ops->extn_synch_en(common);
  555. mutex_unlock:
  556. mutex_unlock(&sc->mutex);
  557. ath9k_ps_restore(sc);
  558. return r;
  559. }
  560. static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  561. {
  562. struct ath_softc *sc = hw->priv;
  563. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  564. struct ath_tx_control txctl;
  565. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  566. unsigned long flags;
  567. if (sc->ps_enabled) {
  568. /*
  569. * mac80211 does not set PM field for normal data frames, so we
  570. * need to update that based on the current PS mode.
  571. */
  572. if (ieee80211_is_data(hdr->frame_control) &&
  573. !ieee80211_is_nullfunc(hdr->frame_control) &&
  574. !ieee80211_has_pm(hdr->frame_control)) {
  575. ath_dbg(common, PS,
  576. "Add PM=1 for a TX frame while in PS mode\n");
  577. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
  578. }
  579. }
  580. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
  581. /*
  582. * We are using PS-Poll and mac80211 can request TX while in
  583. * power save mode. Need to wake up hardware for the TX to be
  584. * completed and if needed, also for RX of buffered frames.
  585. */
  586. ath9k_ps_wakeup(sc);
  587. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  588. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  589. ath9k_hw_setrxabort(sc->sc_ah, 0);
  590. if (ieee80211_is_pspoll(hdr->frame_control)) {
  591. ath_dbg(common, PS,
  592. "Sending PS-Poll to pick a buffered frame\n");
  593. sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
  594. } else {
  595. ath_dbg(common, PS, "Wake up to complete TX\n");
  596. sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
  597. }
  598. /*
  599. * The actual restore operation will happen only after
  600. * the ps_flags bit is cleared. We are just dropping
  601. * the ps_usecount here.
  602. */
  603. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  604. ath9k_ps_restore(sc);
  605. }
  606. /*
  607. * Cannot tx while the hardware is in full sleep, it first needs a full
  608. * chip reset to recover from that
  609. */
  610. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
  611. ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
  612. goto exit;
  613. }
  614. memset(&txctl, 0, sizeof(struct ath_tx_control));
  615. txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
  616. ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
  617. if (ath_tx_start(hw, skb, &txctl) != 0) {
  618. ath_dbg(common, XMIT, "TX failed\n");
  619. TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
  620. goto exit;
  621. }
  622. return;
  623. exit:
  624. dev_kfree_skb_any(skb);
  625. }
  626. static void ath9k_stop(struct ieee80211_hw *hw)
  627. {
  628. struct ath_softc *sc = hw->priv;
  629. struct ath_hw *ah = sc->sc_ah;
  630. struct ath_common *common = ath9k_hw_common(ah);
  631. bool prev_idle;
  632. mutex_lock(&sc->mutex);
  633. ath_cancel_work(sc);
  634. del_timer_sync(&sc->rx_poll_timer);
  635. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  636. ath_dbg(common, ANY, "Device not present\n");
  637. mutex_unlock(&sc->mutex);
  638. return;
  639. }
  640. /* Ensure HW is awake when we try to shut it down. */
  641. ath9k_ps_wakeup(sc);
  642. ath9k_stop_btcoex(sc);
  643. spin_lock_bh(&sc->sc_pcu_lock);
  644. /* prevent tasklets to enable interrupts once we disable them */
  645. ah->imask &= ~ATH9K_INT_GLOBAL;
  646. /* make sure h/w will not generate any interrupt
  647. * before setting the invalid flag. */
  648. ath9k_hw_disable_interrupts(ah);
  649. spin_unlock_bh(&sc->sc_pcu_lock);
  650. /* we can now sync irq and kill any running tasklets, since we already
  651. * disabled interrupts and not holding a spin lock */
  652. synchronize_irq(sc->irq);
  653. tasklet_kill(&sc->intr_tq);
  654. tasklet_kill(&sc->bcon_tasklet);
  655. prev_idle = sc->ps_idle;
  656. sc->ps_idle = true;
  657. spin_lock_bh(&sc->sc_pcu_lock);
  658. if (ah->led_pin >= 0) {
  659. ath9k_hw_set_gpio(ah, ah->led_pin, 1);
  660. ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
  661. }
  662. ath_prepare_reset(sc, false, true);
  663. if (sc->rx.frag) {
  664. dev_kfree_skb_any(sc->rx.frag);
  665. sc->rx.frag = NULL;
  666. }
  667. if (!ah->curchan)
  668. ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
  669. ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
  670. ath9k_hw_phy_disable(ah);
  671. ath9k_hw_configpcipowersave(ah, true);
  672. spin_unlock_bh(&sc->sc_pcu_lock);
  673. ath9k_ps_restore(sc);
  674. set_bit(SC_OP_INVALID, &sc->sc_flags);
  675. sc->ps_idle = prev_idle;
  676. mutex_unlock(&sc->mutex);
  677. ath_dbg(common, CONFIG, "Driver halt\n");
  678. }
  679. bool ath9k_uses_beacons(int type)
  680. {
  681. switch (type) {
  682. case NL80211_IFTYPE_AP:
  683. case NL80211_IFTYPE_ADHOC:
  684. case NL80211_IFTYPE_MESH_POINT:
  685. return true;
  686. default:
  687. return false;
  688. }
  689. }
  690. static void ath9k_reclaim_beacon(struct ath_softc *sc,
  691. struct ieee80211_vif *vif)
  692. {
  693. struct ath_vif *avp = (void *)vif->drv_priv;
  694. ath9k_set_beaconing_status(sc, false);
  695. ath_beacon_return(sc, avp);
  696. ath9k_set_beaconing_status(sc, true);
  697. }
  698. static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  699. {
  700. struct ath9k_vif_iter_data *iter_data = data;
  701. int i;
  702. if (iter_data->hw_macaddr)
  703. for (i = 0; i < ETH_ALEN; i++)
  704. iter_data->mask[i] &=
  705. ~(iter_data->hw_macaddr[i] ^ mac[i]);
  706. switch (vif->type) {
  707. case NL80211_IFTYPE_AP:
  708. iter_data->naps++;
  709. break;
  710. case NL80211_IFTYPE_STATION:
  711. iter_data->nstations++;
  712. break;
  713. case NL80211_IFTYPE_ADHOC:
  714. iter_data->nadhocs++;
  715. break;
  716. case NL80211_IFTYPE_MESH_POINT:
  717. iter_data->nmeshes++;
  718. break;
  719. case NL80211_IFTYPE_WDS:
  720. iter_data->nwds++;
  721. break;
  722. default:
  723. break;
  724. }
  725. }
  726. /* Called with sc->mutex held. */
  727. void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
  728. struct ieee80211_vif *vif,
  729. struct ath9k_vif_iter_data *iter_data)
  730. {
  731. struct ath_softc *sc = hw->priv;
  732. struct ath_hw *ah = sc->sc_ah;
  733. struct ath_common *common = ath9k_hw_common(ah);
  734. /*
  735. * Use the hardware MAC address as reference, the hardware uses it
  736. * together with the BSSID mask when matching addresses.
  737. */
  738. memset(iter_data, 0, sizeof(*iter_data));
  739. iter_data->hw_macaddr = common->macaddr;
  740. memset(&iter_data->mask, 0xff, ETH_ALEN);
  741. if (vif)
  742. ath9k_vif_iter(iter_data, vif->addr, vif);
  743. /* Get list of all active MAC addresses */
  744. ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
  745. iter_data);
  746. }
  747. /* Called with sc->mutex held. */
  748. static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
  749. struct ieee80211_vif *vif)
  750. {
  751. struct ath_softc *sc = hw->priv;
  752. struct ath_hw *ah = sc->sc_ah;
  753. struct ath_common *common = ath9k_hw_common(ah);
  754. struct ath9k_vif_iter_data iter_data;
  755. ath9k_calculate_iter_data(hw, vif, &iter_data);
  756. /* Set BSSID mask. */
  757. memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
  758. ath_hw_setbssidmask(common);
  759. /* Set op-mode & TSF */
  760. if (iter_data.naps > 0) {
  761. ath9k_hw_set_tsfadjust(ah, 1);
  762. set_bit(SC_OP_TSF_RESET, &sc->sc_flags);
  763. ah->opmode = NL80211_IFTYPE_AP;
  764. } else {
  765. ath9k_hw_set_tsfadjust(ah, 0);
  766. clear_bit(SC_OP_TSF_RESET, &sc->sc_flags);
  767. if (iter_data.nmeshes)
  768. ah->opmode = NL80211_IFTYPE_MESH_POINT;
  769. else if (iter_data.nwds)
  770. ah->opmode = NL80211_IFTYPE_AP;
  771. else if (iter_data.nadhocs)
  772. ah->opmode = NL80211_IFTYPE_ADHOC;
  773. else
  774. ah->opmode = NL80211_IFTYPE_STATION;
  775. }
  776. /*
  777. * Enable MIB interrupts when there are hardware phy counters.
  778. */
  779. if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) {
  780. if (ah->config.enable_ani)
  781. ah->imask |= ATH9K_INT_MIB;
  782. ah->imask |= ATH9K_INT_TSFOOR;
  783. } else {
  784. ah->imask &= ~ATH9K_INT_MIB;
  785. ah->imask &= ~ATH9K_INT_TSFOOR;
  786. }
  787. ath9k_hw_set_interrupts(ah);
  788. /* Set up ANI */
  789. if (iter_data.naps > 0) {
  790. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  791. if (!common->disable_ani) {
  792. set_bit(SC_OP_ANI_RUN, &sc->sc_flags);
  793. ath_start_ani(common);
  794. }
  795. } else {
  796. clear_bit(SC_OP_ANI_RUN, &sc->sc_flags);
  797. del_timer_sync(&common->ani.timer);
  798. }
  799. }
  800. /* Called with sc->mutex held, vif counts set up properly. */
  801. static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw,
  802. struct ieee80211_vif *vif)
  803. {
  804. struct ath_softc *sc = hw->priv;
  805. ath9k_calculate_summary_state(hw, vif);
  806. if (ath9k_uses_beacons(vif->type)) {
  807. /* Reserve a beacon slot for the vif */
  808. ath9k_set_beaconing_status(sc, false);
  809. ath_beacon_alloc(sc, vif);
  810. ath9k_set_beaconing_status(sc, true);
  811. }
  812. }
  813. static int ath9k_add_interface(struct ieee80211_hw *hw,
  814. struct ieee80211_vif *vif)
  815. {
  816. struct ath_softc *sc = hw->priv;
  817. struct ath_hw *ah = sc->sc_ah;
  818. struct ath_common *common = ath9k_hw_common(ah);
  819. int ret = 0;
  820. ath9k_ps_wakeup(sc);
  821. mutex_lock(&sc->mutex);
  822. switch (vif->type) {
  823. case NL80211_IFTYPE_STATION:
  824. case NL80211_IFTYPE_WDS:
  825. case NL80211_IFTYPE_ADHOC:
  826. case NL80211_IFTYPE_AP:
  827. case NL80211_IFTYPE_MESH_POINT:
  828. break;
  829. default:
  830. ath_err(common, "Interface type %d not yet supported\n",
  831. vif->type);
  832. ret = -EOPNOTSUPP;
  833. goto out;
  834. }
  835. if (ath9k_uses_beacons(vif->type)) {
  836. if (sc->nbcnvifs >= ATH_BCBUF) {
  837. ath_err(common, "Not enough beacon buffers when adding"
  838. " new interface of type: %i\n",
  839. vif->type);
  840. ret = -ENOBUFS;
  841. goto out;
  842. }
  843. }
  844. ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
  845. sc->nvifs++;
  846. ath9k_do_vif_add_setup(hw, vif);
  847. out:
  848. mutex_unlock(&sc->mutex);
  849. ath9k_ps_restore(sc);
  850. return ret;
  851. }
  852. static int ath9k_change_interface(struct ieee80211_hw *hw,
  853. struct ieee80211_vif *vif,
  854. enum nl80211_iftype new_type,
  855. bool p2p)
  856. {
  857. struct ath_softc *sc = hw->priv;
  858. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  859. int ret = 0;
  860. ath_dbg(common, CONFIG, "Change Interface\n");
  861. mutex_lock(&sc->mutex);
  862. ath9k_ps_wakeup(sc);
  863. if (ath9k_uses_beacons(new_type) &&
  864. !ath9k_uses_beacons(vif->type)) {
  865. if (sc->nbcnvifs >= ATH_BCBUF) {
  866. ath_err(common, "No beacon slot available\n");
  867. ret = -ENOBUFS;
  868. goto out;
  869. }
  870. }
  871. /* Clean up old vif stuff */
  872. if (ath9k_uses_beacons(vif->type))
  873. ath9k_reclaim_beacon(sc, vif);
  874. /* Add new settings */
  875. vif->type = new_type;
  876. vif->p2p = p2p;
  877. ath9k_do_vif_add_setup(hw, vif);
  878. out:
  879. ath9k_ps_restore(sc);
  880. mutex_unlock(&sc->mutex);
  881. return ret;
  882. }
  883. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  884. struct ieee80211_vif *vif)
  885. {
  886. struct ath_softc *sc = hw->priv;
  887. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  888. ath_dbg(common, CONFIG, "Detach Interface\n");
  889. ath9k_ps_wakeup(sc);
  890. mutex_lock(&sc->mutex);
  891. sc->nvifs--;
  892. /* Reclaim beacon resources */
  893. if (ath9k_uses_beacons(vif->type))
  894. ath9k_reclaim_beacon(sc, vif);
  895. ath9k_calculate_summary_state(hw, NULL);
  896. mutex_unlock(&sc->mutex);
  897. ath9k_ps_restore(sc);
  898. }
  899. static void ath9k_enable_ps(struct ath_softc *sc)
  900. {
  901. struct ath_hw *ah = sc->sc_ah;
  902. struct ath_common *common = ath9k_hw_common(ah);
  903. sc->ps_enabled = true;
  904. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  905. if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
  906. ah->imask |= ATH9K_INT_TIM_TIMER;
  907. ath9k_hw_set_interrupts(ah);
  908. }
  909. ath9k_hw_setrxabort(ah, 1);
  910. }
  911. ath_dbg(common, PS, "PowerSave enabled\n");
  912. }
  913. static void ath9k_disable_ps(struct ath_softc *sc)
  914. {
  915. struct ath_hw *ah = sc->sc_ah;
  916. struct ath_common *common = ath9k_hw_common(ah);
  917. sc->ps_enabled = false;
  918. ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
  919. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  920. ath9k_hw_setrxabort(ah, 0);
  921. sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
  922. PS_WAIT_FOR_CAB |
  923. PS_WAIT_FOR_PSPOLL_DATA |
  924. PS_WAIT_FOR_TX_ACK);
  925. if (ah->imask & ATH9K_INT_TIM_TIMER) {
  926. ah->imask &= ~ATH9K_INT_TIM_TIMER;
  927. ath9k_hw_set_interrupts(ah);
  928. }
  929. }
  930. ath_dbg(common, PS, "PowerSave disabled\n");
  931. }
  932. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  933. {
  934. struct ath_softc *sc = hw->priv;
  935. struct ath_hw *ah = sc->sc_ah;
  936. struct ath_common *common = ath9k_hw_common(ah);
  937. struct ieee80211_conf *conf = &hw->conf;
  938. bool reset_channel = false;
  939. ath9k_ps_wakeup(sc);
  940. mutex_lock(&sc->mutex);
  941. if (changed & IEEE80211_CONF_CHANGE_IDLE) {
  942. sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
  943. if (sc->ps_idle)
  944. ath_cancel_work(sc);
  945. else
  946. /*
  947. * The chip needs a reset to properly wake up from
  948. * full sleep
  949. */
  950. reset_channel = ah->chip_fullsleep;
  951. }
  952. /*
  953. * We just prepare to enable PS. We have to wait until our AP has
  954. * ACK'd our null data frame to disable RX otherwise we'll ignore
  955. * those ACKs and end up retransmitting the same null data frames.
  956. * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
  957. */
  958. if (changed & IEEE80211_CONF_CHANGE_PS) {
  959. unsigned long flags;
  960. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  961. if (conf->flags & IEEE80211_CONF_PS)
  962. ath9k_enable_ps(sc);
  963. else
  964. ath9k_disable_ps(sc);
  965. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  966. }
  967. if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
  968. if (conf->flags & IEEE80211_CONF_MONITOR) {
  969. ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
  970. sc->sc_ah->is_monitoring = true;
  971. } else {
  972. ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
  973. sc->sc_ah->is_monitoring = false;
  974. }
  975. }
  976. if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) {
  977. struct ieee80211_channel *curchan = hw->conf.channel;
  978. int pos = curchan->hw_value;
  979. int old_pos = -1;
  980. unsigned long flags;
  981. if (ah->curchan)
  982. old_pos = ah->curchan - &ah->channels[0];
  983. ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n",
  984. curchan->center_freq, conf->channel_type);
  985. /* update survey stats for the old channel before switching */
  986. spin_lock_irqsave(&common->cc_lock, flags);
  987. ath_update_survey_stats(sc);
  988. spin_unlock_irqrestore(&common->cc_lock, flags);
  989. /*
  990. * Preserve the current channel values, before updating
  991. * the same channel
  992. */
  993. if (ah->curchan && (old_pos == pos))
  994. ath9k_hw_getnf(ah, ah->curchan);
  995. ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
  996. curchan, conf->channel_type);
  997. /*
  998. * If the operating channel changes, change the survey in-use flags
  999. * along with it.
  1000. * Reset the survey data for the new channel, unless we're switching
  1001. * back to the operating channel from an off-channel operation.
  1002. */
  1003. if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
  1004. sc->cur_survey != &sc->survey[pos]) {
  1005. if (sc->cur_survey)
  1006. sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
  1007. sc->cur_survey = &sc->survey[pos];
  1008. memset(sc->cur_survey, 0, sizeof(struct survey_info));
  1009. sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
  1010. } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
  1011. memset(&sc->survey[pos], 0, sizeof(struct survey_info));
  1012. }
  1013. if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
  1014. ath_err(common, "Unable to set channel\n");
  1015. mutex_unlock(&sc->mutex);
  1016. ath9k_ps_restore(sc);
  1017. return -EINVAL;
  1018. }
  1019. /*
  1020. * The most recent snapshot of channel->noisefloor for the old
  1021. * channel is only available after the hardware reset. Copy it to
  1022. * the survey stats now.
  1023. */
  1024. if (old_pos >= 0)
  1025. ath_update_survey_nf(sc, old_pos);
  1026. }
  1027. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  1028. ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
  1029. sc->config.txpowlimit = 2 * conf->power_level;
  1030. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  1031. sc->config.txpowlimit, &sc->curtxpow);
  1032. }
  1033. mutex_unlock(&sc->mutex);
  1034. ath9k_ps_restore(sc);
  1035. return 0;
  1036. }
  1037. #define SUPPORTED_FILTERS \
  1038. (FIF_PROMISC_IN_BSS | \
  1039. FIF_ALLMULTI | \
  1040. FIF_CONTROL | \
  1041. FIF_PSPOLL | \
  1042. FIF_OTHER_BSS | \
  1043. FIF_BCN_PRBRESP_PROMISC | \
  1044. FIF_PROBE_REQ | \
  1045. FIF_FCSFAIL)
  1046. /* FIXME: sc->sc_full_reset ? */
  1047. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  1048. unsigned int changed_flags,
  1049. unsigned int *total_flags,
  1050. u64 multicast)
  1051. {
  1052. struct ath_softc *sc = hw->priv;
  1053. u32 rfilt;
  1054. changed_flags &= SUPPORTED_FILTERS;
  1055. *total_flags &= SUPPORTED_FILTERS;
  1056. sc->rx.rxfilter = *total_flags;
  1057. ath9k_ps_wakeup(sc);
  1058. rfilt = ath_calcrxfilter(sc);
  1059. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1060. ath9k_ps_restore(sc);
  1061. ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
  1062. rfilt);
  1063. }
  1064. static int ath9k_sta_add(struct ieee80211_hw *hw,
  1065. struct ieee80211_vif *vif,
  1066. struct ieee80211_sta *sta)
  1067. {
  1068. struct ath_softc *sc = hw->priv;
  1069. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1070. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1071. struct ieee80211_key_conf ps_key = { };
  1072. ath_node_attach(sc, sta, vif);
  1073. if (vif->type != NL80211_IFTYPE_AP &&
  1074. vif->type != NL80211_IFTYPE_AP_VLAN)
  1075. return 0;
  1076. an->ps_key = ath_key_config(common, vif, sta, &ps_key);
  1077. return 0;
  1078. }
  1079. static void ath9k_del_ps_key(struct ath_softc *sc,
  1080. struct ieee80211_vif *vif,
  1081. struct ieee80211_sta *sta)
  1082. {
  1083. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1084. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1085. struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
  1086. if (!an->ps_key)
  1087. return;
  1088. ath_key_delete(common, &ps_key);
  1089. }
  1090. static int ath9k_sta_remove(struct ieee80211_hw *hw,
  1091. struct ieee80211_vif *vif,
  1092. struct ieee80211_sta *sta)
  1093. {
  1094. struct ath_softc *sc = hw->priv;
  1095. ath9k_del_ps_key(sc, vif, sta);
  1096. ath_node_detach(sc, sta);
  1097. return 0;
  1098. }
  1099. static void ath9k_sta_notify(struct ieee80211_hw *hw,
  1100. struct ieee80211_vif *vif,
  1101. enum sta_notify_cmd cmd,
  1102. struct ieee80211_sta *sta)
  1103. {
  1104. struct ath_softc *sc = hw->priv;
  1105. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1106. if (!sta->ht_cap.ht_supported)
  1107. return;
  1108. switch (cmd) {
  1109. case STA_NOTIFY_SLEEP:
  1110. an->sleeping = true;
  1111. ath_tx_aggr_sleep(sta, sc, an);
  1112. break;
  1113. case STA_NOTIFY_AWAKE:
  1114. an->sleeping = false;
  1115. ath_tx_aggr_wakeup(sc, an);
  1116. break;
  1117. }
  1118. }
  1119. static int ath9k_conf_tx(struct ieee80211_hw *hw,
  1120. struct ieee80211_vif *vif, u16 queue,
  1121. const struct ieee80211_tx_queue_params *params)
  1122. {
  1123. struct ath_softc *sc = hw->priv;
  1124. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1125. struct ath_txq *txq;
  1126. struct ath9k_tx_queue_info qi;
  1127. int ret = 0;
  1128. if (queue >= WME_NUM_AC)
  1129. return 0;
  1130. txq = sc->tx.txq_map[queue];
  1131. ath9k_ps_wakeup(sc);
  1132. mutex_lock(&sc->mutex);
  1133. memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
  1134. qi.tqi_aifs = params->aifs;
  1135. qi.tqi_cwmin = params->cw_min;
  1136. qi.tqi_cwmax = params->cw_max;
  1137. qi.tqi_burstTime = params->txop;
  1138. ath_dbg(common, CONFIG,
  1139. "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1140. queue, txq->axq_qnum, params->aifs, params->cw_min,
  1141. params->cw_max, params->txop);
  1142. ret = ath_txq_update(sc, txq->axq_qnum, &qi);
  1143. if (ret)
  1144. ath_err(common, "TXQ Update failed\n");
  1145. if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
  1146. if (queue == WME_AC_BE && !ret)
  1147. ath_beaconq_config(sc);
  1148. mutex_unlock(&sc->mutex);
  1149. ath9k_ps_restore(sc);
  1150. return ret;
  1151. }
  1152. static int ath9k_set_key(struct ieee80211_hw *hw,
  1153. enum set_key_cmd cmd,
  1154. struct ieee80211_vif *vif,
  1155. struct ieee80211_sta *sta,
  1156. struct ieee80211_key_conf *key)
  1157. {
  1158. struct ath_softc *sc = hw->priv;
  1159. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1160. int ret = 0;
  1161. if (ath9k_modparam_nohwcrypt)
  1162. return -ENOSPC;
  1163. if ((vif->type == NL80211_IFTYPE_ADHOC ||
  1164. vif->type == NL80211_IFTYPE_MESH_POINT) &&
  1165. (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
  1166. key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
  1167. !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
  1168. /*
  1169. * For now, disable hw crypto for the RSN IBSS group keys. This
  1170. * could be optimized in the future to use a modified key cache
  1171. * design to support per-STA RX GTK, but until that gets
  1172. * implemented, use of software crypto for group addressed
  1173. * frames is a acceptable to allow RSN IBSS to be used.
  1174. */
  1175. return -EOPNOTSUPP;
  1176. }
  1177. mutex_lock(&sc->mutex);
  1178. ath9k_ps_wakeup(sc);
  1179. ath_dbg(common, CONFIG, "Set HW Key\n");
  1180. switch (cmd) {
  1181. case SET_KEY:
  1182. if (sta)
  1183. ath9k_del_ps_key(sc, vif, sta);
  1184. ret = ath_key_config(common, vif, sta, key);
  1185. if (ret >= 0) {
  1186. key->hw_key_idx = ret;
  1187. /* push IV and Michael MIC generation to stack */
  1188. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1189. if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
  1190. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1191. if (sc->sc_ah->sw_mgmt_crypto &&
  1192. key->cipher == WLAN_CIPHER_SUITE_CCMP)
  1193. key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
  1194. ret = 0;
  1195. }
  1196. break;
  1197. case DISABLE_KEY:
  1198. ath_key_delete(common, key);
  1199. break;
  1200. default:
  1201. ret = -EINVAL;
  1202. }
  1203. ath9k_ps_restore(sc);
  1204. mutex_unlock(&sc->mutex);
  1205. return ret;
  1206. }
  1207. static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  1208. {
  1209. struct ath_softc *sc = data;
  1210. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1211. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1212. struct ath_vif *avp = (void *)vif->drv_priv;
  1213. unsigned long flags;
  1214. /*
  1215. * Skip iteration if primary station vif's bss info
  1216. * was not changed
  1217. */
  1218. if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags))
  1219. return;
  1220. if (bss_conf->assoc) {
  1221. set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
  1222. avp->primary_sta_vif = true;
  1223. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1224. common->curaid = bss_conf->aid;
  1225. ath9k_hw_write_associd(sc->sc_ah);
  1226. ath_dbg(common, CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
  1227. bss_conf->aid, common->curbssid);
  1228. ath_beacon_config(sc, vif);
  1229. /*
  1230. * Request a re-configuration of Beacon related timers
  1231. * on the receipt of the first Beacon frame (i.e.,
  1232. * after time sync with the AP).
  1233. */
  1234. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  1235. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  1236. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  1237. /* Reset rssi stats */
  1238. sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
  1239. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  1240. ath_start_rx_poll(sc, 3);
  1241. if (!common->disable_ani) {
  1242. set_bit(SC_OP_ANI_RUN, &sc->sc_flags);
  1243. ath_start_ani(common);
  1244. }
  1245. }
  1246. }
  1247. static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif)
  1248. {
  1249. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1250. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1251. struct ath_vif *avp = (void *)vif->drv_priv;
  1252. if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
  1253. return;
  1254. /* Reconfigure bss info */
  1255. if (avp->primary_sta_vif && !bss_conf->assoc) {
  1256. ath_dbg(common, CONFIG, "Bss Info DISASSOC %d, bssid %pM\n",
  1257. common->curaid, common->curbssid);
  1258. clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
  1259. clear_bit(SC_OP_BEACONS, &sc->sc_flags);
  1260. avp->primary_sta_vif = false;
  1261. memset(common->curbssid, 0, ETH_ALEN);
  1262. common->curaid = 0;
  1263. }
  1264. ieee80211_iterate_active_interfaces_atomic(
  1265. sc->hw, ath9k_bss_iter, sc);
  1266. /*
  1267. * None of station vifs are associated.
  1268. * Clear bssid & aid
  1269. */
  1270. if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  1271. ath9k_hw_write_associd(sc->sc_ah);
  1272. clear_bit(SC_OP_ANI_RUN, &sc->sc_flags);
  1273. del_timer_sync(&common->ani.timer);
  1274. del_timer_sync(&sc->rx_poll_timer);
  1275. memset(&sc->caldata, 0, sizeof(sc->caldata));
  1276. }
  1277. }
  1278. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1279. struct ieee80211_vif *vif,
  1280. struct ieee80211_bss_conf *bss_conf,
  1281. u32 changed)
  1282. {
  1283. struct ath_softc *sc = hw->priv;
  1284. struct ath_hw *ah = sc->sc_ah;
  1285. struct ath_common *common = ath9k_hw_common(ah);
  1286. struct ath_vif *avp = (void *)vif->drv_priv;
  1287. int slottime;
  1288. ath9k_ps_wakeup(sc);
  1289. mutex_lock(&sc->mutex);
  1290. if (changed & BSS_CHANGED_ASSOC) {
  1291. ath9k_config_bss(sc, vif);
  1292. ath_dbg(common, CONFIG, "BSSID: %pM aid: 0x%x\n",
  1293. common->curbssid, common->curaid);
  1294. }
  1295. if (changed & BSS_CHANGED_IBSS) {
  1296. /* There can be only one vif available */
  1297. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1298. common->curaid = bss_conf->aid;
  1299. ath9k_hw_write_associd(sc->sc_ah);
  1300. if (bss_conf->ibss_joined) {
  1301. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  1302. if (!common->disable_ani) {
  1303. set_bit(SC_OP_ANI_RUN, &sc->sc_flags);
  1304. ath_start_ani(common);
  1305. }
  1306. } else {
  1307. clear_bit(SC_OP_ANI_RUN, &sc->sc_flags);
  1308. del_timer_sync(&common->ani.timer);
  1309. del_timer_sync(&sc->rx_poll_timer);
  1310. }
  1311. }
  1312. /*
  1313. * In case of AP mode, the HW TSF has to be reset
  1314. * when the beacon interval changes.
  1315. */
  1316. if ((changed & BSS_CHANGED_BEACON_INT) &&
  1317. (vif->type == NL80211_IFTYPE_AP))
  1318. set_bit(SC_OP_TSF_RESET, &sc->sc_flags);
  1319. /* Configure beaconing (AP, IBSS, MESH) */
  1320. if (ath9k_uses_beacons(vif->type) &&
  1321. ((changed & BSS_CHANGED_BEACON) ||
  1322. (changed & BSS_CHANGED_BEACON_ENABLED) ||
  1323. (changed & BSS_CHANGED_BEACON_INT))) {
  1324. ath9k_set_beaconing_status(sc, false);
  1325. if (bss_conf->enable_beacon)
  1326. ath_beacon_alloc(sc, vif);
  1327. else
  1328. avp->is_bslot_active = false;
  1329. ath_beacon_config(sc, vif);
  1330. ath9k_set_beaconing_status(sc, true);
  1331. }
  1332. if (changed & BSS_CHANGED_ERP_SLOT) {
  1333. if (bss_conf->use_short_slot)
  1334. slottime = 9;
  1335. else
  1336. slottime = 20;
  1337. if (vif->type == NL80211_IFTYPE_AP) {
  1338. /*
  1339. * Defer update, so that connected stations can adjust
  1340. * their settings at the same time.
  1341. * See beacon.c for more details
  1342. */
  1343. sc->beacon.slottime = slottime;
  1344. sc->beacon.updateslot = UPDATE;
  1345. } else {
  1346. ah->slottime = slottime;
  1347. ath9k_hw_init_global_settings(ah);
  1348. }
  1349. }
  1350. mutex_unlock(&sc->mutex);
  1351. ath9k_ps_restore(sc);
  1352. }
  1353. static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1354. {
  1355. struct ath_softc *sc = hw->priv;
  1356. u64 tsf;
  1357. mutex_lock(&sc->mutex);
  1358. ath9k_ps_wakeup(sc);
  1359. tsf = ath9k_hw_gettsf64(sc->sc_ah);
  1360. ath9k_ps_restore(sc);
  1361. mutex_unlock(&sc->mutex);
  1362. return tsf;
  1363. }
  1364. static void ath9k_set_tsf(struct ieee80211_hw *hw,
  1365. struct ieee80211_vif *vif,
  1366. u64 tsf)
  1367. {
  1368. struct ath_softc *sc = hw->priv;
  1369. mutex_lock(&sc->mutex);
  1370. ath9k_ps_wakeup(sc);
  1371. ath9k_hw_settsf64(sc->sc_ah, tsf);
  1372. ath9k_ps_restore(sc);
  1373. mutex_unlock(&sc->mutex);
  1374. }
  1375. static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1376. {
  1377. struct ath_softc *sc = hw->priv;
  1378. mutex_lock(&sc->mutex);
  1379. ath9k_ps_wakeup(sc);
  1380. ath9k_hw_reset_tsf(sc->sc_ah);
  1381. ath9k_ps_restore(sc);
  1382. mutex_unlock(&sc->mutex);
  1383. }
  1384. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1385. struct ieee80211_vif *vif,
  1386. enum ieee80211_ampdu_mlme_action action,
  1387. struct ieee80211_sta *sta,
  1388. u16 tid, u16 *ssn, u8 buf_size)
  1389. {
  1390. struct ath_softc *sc = hw->priv;
  1391. int ret = 0;
  1392. local_bh_disable();
  1393. switch (action) {
  1394. case IEEE80211_AMPDU_RX_START:
  1395. break;
  1396. case IEEE80211_AMPDU_RX_STOP:
  1397. break;
  1398. case IEEE80211_AMPDU_TX_START:
  1399. ath9k_ps_wakeup(sc);
  1400. ret = ath_tx_aggr_start(sc, sta, tid, ssn);
  1401. if (!ret)
  1402. ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1403. ath9k_ps_restore(sc);
  1404. break;
  1405. case IEEE80211_AMPDU_TX_STOP:
  1406. ath9k_ps_wakeup(sc);
  1407. ath_tx_aggr_stop(sc, sta, tid);
  1408. ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1409. ath9k_ps_restore(sc);
  1410. break;
  1411. case IEEE80211_AMPDU_TX_OPERATIONAL:
  1412. ath9k_ps_wakeup(sc);
  1413. ath_tx_aggr_resume(sc, sta, tid);
  1414. ath9k_ps_restore(sc);
  1415. break;
  1416. default:
  1417. ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
  1418. }
  1419. local_bh_enable();
  1420. return ret;
  1421. }
  1422. static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
  1423. struct survey_info *survey)
  1424. {
  1425. struct ath_softc *sc = hw->priv;
  1426. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1427. struct ieee80211_supported_band *sband;
  1428. struct ieee80211_channel *chan;
  1429. unsigned long flags;
  1430. int pos;
  1431. spin_lock_irqsave(&common->cc_lock, flags);
  1432. if (idx == 0)
  1433. ath_update_survey_stats(sc);
  1434. sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
  1435. if (sband && idx >= sband->n_channels) {
  1436. idx -= sband->n_channels;
  1437. sband = NULL;
  1438. }
  1439. if (!sband)
  1440. sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
  1441. if (!sband || idx >= sband->n_channels) {
  1442. spin_unlock_irqrestore(&common->cc_lock, flags);
  1443. return -ENOENT;
  1444. }
  1445. chan = &sband->channels[idx];
  1446. pos = chan->hw_value;
  1447. memcpy(survey, &sc->survey[pos], sizeof(*survey));
  1448. survey->channel = chan;
  1449. spin_unlock_irqrestore(&common->cc_lock, flags);
  1450. return 0;
  1451. }
  1452. static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
  1453. {
  1454. struct ath_softc *sc = hw->priv;
  1455. struct ath_hw *ah = sc->sc_ah;
  1456. mutex_lock(&sc->mutex);
  1457. ah->coverage_class = coverage_class;
  1458. ath9k_ps_wakeup(sc);
  1459. ath9k_hw_init_global_settings(ah);
  1460. ath9k_ps_restore(sc);
  1461. mutex_unlock(&sc->mutex);
  1462. }
  1463. static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
  1464. {
  1465. struct ath_softc *sc = hw->priv;
  1466. struct ath_hw *ah = sc->sc_ah;
  1467. struct ath_common *common = ath9k_hw_common(ah);
  1468. int timeout = 200; /* ms */
  1469. int i, j;
  1470. bool drain_txq;
  1471. mutex_lock(&sc->mutex);
  1472. cancel_delayed_work_sync(&sc->tx_complete_work);
  1473. if (ah->ah_flags & AH_UNPLUGGED) {
  1474. ath_dbg(common, ANY, "Device has been unplugged!\n");
  1475. mutex_unlock(&sc->mutex);
  1476. return;
  1477. }
  1478. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  1479. ath_dbg(common, ANY, "Device not present\n");
  1480. mutex_unlock(&sc->mutex);
  1481. return;
  1482. }
  1483. for (j = 0; j < timeout; j++) {
  1484. bool npend = false;
  1485. if (j)
  1486. usleep_range(1000, 2000);
  1487. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1488. if (!ATH_TXQ_SETUP(sc, i))
  1489. continue;
  1490. npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
  1491. if (npend)
  1492. break;
  1493. }
  1494. if (!npend)
  1495. break;
  1496. }
  1497. if (drop) {
  1498. ath9k_ps_wakeup(sc);
  1499. spin_lock_bh(&sc->sc_pcu_lock);
  1500. drain_txq = ath_drain_all_txq(sc, false);
  1501. spin_unlock_bh(&sc->sc_pcu_lock);
  1502. if (!drain_txq)
  1503. ath_reset(sc, false);
  1504. ath9k_ps_restore(sc);
  1505. ieee80211_wake_queues(hw);
  1506. }
  1507. ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
  1508. mutex_unlock(&sc->mutex);
  1509. }
  1510. static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
  1511. {
  1512. struct ath_softc *sc = hw->priv;
  1513. int i;
  1514. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1515. if (!ATH_TXQ_SETUP(sc, i))
  1516. continue;
  1517. if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
  1518. return true;
  1519. }
  1520. return false;
  1521. }
  1522. static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
  1523. {
  1524. struct ath_softc *sc = hw->priv;
  1525. struct ath_hw *ah = sc->sc_ah;
  1526. struct ieee80211_vif *vif;
  1527. struct ath_vif *avp;
  1528. struct ath_buf *bf;
  1529. struct ath_tx_status ts;
  1530. bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
  1531. int status;
  1532. vif = sc->beacon.bslot[0];
  1533. if (!vif)
  1534. return 0;
  1535. avp = (void *)vif->drv_priv;
  1536. if (!avp->is_bslot_active)
  1537. return 0;
  1538. if (!sc->beacon.tx_processed && !edma) {
  1539. tasklet_disable(&sc->bcon_tasklet);
  1540. bf = avp->av_bcbuf;
  1541. if (!bf || !bf->bf_mpdu)
  1542. goto skip;
  1543. status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
  1544. if (status == -EINPROGRESS)
  1545. goto skip;
  1546. sc->beacon.tx_processed = true;
  1547. sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
  1548. skip:
  1549. tasklet_enable(&sc->bcon_tasklet);
  1550. }
  1551. return sc->beacon.tx_last;
  1552. }
  1553. static int ath9k_get_stats(struct ieee80211_hw *hw,
  1554. struct ieee80211_low_level_stats *stats)
  1555. {
  1556. struct ath_softc *sc = hw->priv;
  1557. struct ath_hw *ah = sc->sc_ah;
  1558. struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
  1559. stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
  1560. stats->dot11RTSFailureCount = mib_stats->rts_bad;
  1561. stats->dot11FCSErrorCount = mib_stats->fcs_bad;
  1562. stats->dot11RTSSuccessCount = mib_stats->rts_good;
  1563. return 0;
  1564. }
  1565. static u32 fill_chainmask(u32 cap, u32 new)
  1566. {
  1567. u32 filled = 0;
  1568. int i;
  1569. for (i = 0; cap && new; i++, cap >>= 1) {
  1570. if (!(cap & BIT(0)))
  1571. continue;
  1572. if (new & BIT(0))
  1573. filled |= BIT(i);
  1574. new >>= 1;
  1575. }
  1576. return filled;
  1577. }
  1578. static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
  1579. {
  1580. struct ath_softc *sc = hw->priv;
  1581. struct ath_hw *ah = sc->sc_ah;
  1582. if (!rx_ant || !tx_ant)
  1583. return -EINVAL;
  1584. sc->ant_rx = rx_ant;
  1585. sc->ant_tx = tx_ant;
  1586. if (ah->caps.rx_chainmask == 1)
  1587. return 0;
  1588. /* AR9100 runs into calibration issues if not all rx chains are enabled */
  1589. if (AR_SREV_9100(ah))
  1590. ah->rxchainmask = 0x7;
  1591. else
  1592. ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
  1593. ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
  1594. ath9k_reload_chainmask_settings(sc);
  1595. return 0;
  1596. }
  1597. static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
  1598. {
  1599. struct ath_softc *sc = hw->priv;
  1600. *tx_ant = sc->ant_tx;
  1601. *rx_ant = sc->ant_rx;
  1602. return 0;
  1603. }
  1604. #ifdef CONFIG_ATH9K_DEBUGFS
  1605. /* Ethtool support for get-stats */
  1606. #define AMKSTR(nm) #nm "_BE", #nm "_BK", #nm "_VI", #nm "_VO"
  1607. static const char ath9k_gstrings_stats[][ETH_GSTRING_LEN] = {
  1608. "tx_pkts_nic",
  1609. "tx_bytes_nic",
  1610. "rx_pkts_nic",
  1611. "rx_bytes_nic",
  1612. AMKSTR(d_tx_pkts),
  1613. AMKSTR(d_tx_bytes),
  1614. AMKSTR(d_tx_mpdus_queued),
  1615. AMKSTR(d_tx_mpdus_completed),
  1616. AMKSTR(d_tx_mpdu_xretries),
  1617. AMKSTR(d_tx_aggregates),
  1618. AMKSTR(d_tx_ampdus_queued_hw),
  1619. AMKSTR(d_tx_ampdus_queued_sw),
  1620. AMKSTR(d_tx_ampdus_completed),
  1621. AMKSTR(d_tx_ampdu_retries),
  1622. AMKSTR(d_tx_ampdu_xretries),
  1623. AMKSTR(d_tx_fifo_underrun),
  1624. AMKSTR(d_tx_op_exceeded),
  1625. AMKSTR(d_tx_timer_expiry),
  1626. AMKSTR(d_tx_desc_cfg_err),
  1627. AMKSTR(d_tx_data_underrun),
  1628. AMKSTR(d_tx_delim_underrun),
  1629. "d_rx_decrypt_crc_err",
  1630. "d_rx_phy_err",
  1631. "d_rx_mic_err",
  1632. "d_rx_pre_delim_crc_err",
  1633. "d_rx_post_delim_crc_err",
  1634. "d_rx_decrypt_busy_err",
  1635. "d_rx_phyerr_radar",
  1636. "d_rx_phyerr_ofdm_timing",
  1637. "d_rx_phyerr_cck_timing",
  1638. };
  1639. #define ATH9K_SSTATS_LEN ARRAY_SIZE(ath9k_gstrings_stats)
  1640. static void ath9k_get_et_strings(struct ieee80211_hw *hw,
  1641. struct ieee80211_vif *vif,
  1642. u32 sset, u8 *data)
  1643. {
  1644. if (sset == ETH_SS_STATS)
  1645. memcpy(data, *ath9k_gstrings_stats,
  1646. sizeof(ath9k_gstrings_stats));
  1647. }
  1648. static int ath9k_get_et_sset_count(struct ieee80211_hw *hw,
  1649. struct ieee80211_vif *vif, int sset)
  1650. {
  1651. if (sset == ETH_SS_STATS)
  1652. return ATH9K_SSTATS_LEN;
  1653. return 0;
  1654. }
  1655. #define PR_QNUM(_n) (sc->tx.txq_map[_n]->axq_qnum)
  1656. #define AWDATA(elem) \
  1657. do { \
  1658. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].elem; \
  1659. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].elem; \
  1660. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].elem; \
  1661. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].elem; \
  1662. } while (0)
  1663. #define AWDATA_RX(elem) \
  1664. do { \
  1665. data[i++] = sc->debug.stats.rxstats.elem; \
  1666. } while (0)
  1667. static void ath9k_get_et_stats(struct ieee80211_hw *hw,
  1668. struct ieee80211_vif *vif,
  1669. struct ethtool_stats *stats, u64 *data)
  1670. {
  1671. struct ath_softc *sc = hw->priv;
  1672. int i = 0;
  1673. data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_pkts_all +
  1674. sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_pkts_all +
  1675. sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_pkts_all +
  1676. sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_pkts_all);
  1677. data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_bytes_all +
  1678. sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_bytes_all +
  1679. sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_bytes_all +
  1680. sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_bytes_all);
  1681. AWDATA_RX(rx_pkts_all);
  1682. AWDATA_RX(rx_bytes_all);
  1683. AWDATA(tx_pkts_all);
  1684. AWDATA(tx_bytes_all);
  1685. AWDATA(queued);
  1686. AWDATA(completed);
  1687. AWDATA(xretries);
  1688. AWDATA(a_aggr);
  1689. AWDATA(a_queued_hw);
  1690. AWDATA(a_queued_sw);
  1691. AWDATA(a_completed);
  1692. AWDATA(a_retries);
  1693. AWDATA(a_xretries);
  1694. AWDATA(fifo_underrun);
  1695. AWDATA(xtxop);
  1696. AWDATA(timer_exp);
  1697. AWDATA(desc_cfg_err);
  1698. AWDATA(data_underrun);
  1699. AWDATA(delim_underrun);
  1700. AWDATA_RX(decrypt_crc_err);
  1701. AWDATA_RX(phy_err);
  1702. AWDATA_RX(mic_err);
  1703. AWDATA_RX(pre_delim_crc_err);
  1704. AWDATA_RX(post_delim_crc_err);
  1705. AWDATA_RX(decrypt_busy_err);
  1706. AWDATA_RX(phy_err_stats[ATH9K_PHYERR_RADAR]);
  1707. AWDATA_RX(phy_err_stats[ATH9K_PHYERR_OFDM_TIMING]);
  1708. AWDATA_RX(phy_err_stats[ATH9K_PHYERR_CCK_TIMING]);
  1709. WARN_ON(i != ATH9K_SSTATS_LEN);
  1710. }
  1711. /* End of ethtool get-stats functions */
  1712. #endif
  1713. struct ieee80211_ops ath9k_ops = {
  1714. .tx = ath9k_tx,
  1715. .start = ath9k_start,
  1716. .stop = ath9k_stop,
  1717. .add_interface = ath9k_add_interface,
  1718. .change_interface = ath9k_change_interface,
  1719. .remove_interface = ath9k_remove_interface,
  1720. .config = ath9k_config,
  1721. .configure_filter = ath9k_configure_filter,
  1722. .sta_add = ath9k_sta_add,
  1723. .sta_remove = ath9k_sta_remove,
  1724. .sta_notify = ath9k_sta_notify,
  1725. .conf_tx = ath9k_conf_tx,
  1726. .bss_info_changed = ath9k_bss_info_changed,
  1727. .set_key = ath9k_set_key,
  1728. .get_tsf = ath9k_get_tsf,
  1729. .set_tsf = ath9k_set_tsf,
  1730. .reset_tsf = ath9k_reset_tsf,
  1731. .ampdu_action = ath9k_ampdu_action,
  1732. .get_survey = ath9k_get_survey,
  1733. .rfkill_poll = ath9k_rfkill_poll_state,
  1734. .set_coverage_class = ath9k_set_coverage_class,
  1735. .flush = ath9k_flush,
  1736. .tx_frames_pending = ath9k_tx_frames_pending,
  1737. .tx_last_beacon = ath9k_tx_last_beacon,
  1738. .get_stats = ath9k_get_stats,
  1739. .set_antenna = ath9k_set_antenna,
  1740. .get_antenna = ath9k_get_antenna,
  1741. #ifdef CONFIG_ATH9K_DEBUGFS
  1742. .get_et_sset_count = ath9k_get_et_sset_count,
  1743. .get_et_stats = ath9k_get_et_stats,
  1744. .get_et_strings = ath9k_get_et_strings,
  1745. #endif
  1746. };