sun4m_smp.c 6.2 KB

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  1. /*
  2. * sun4m SMP support.
  3. *
  4. * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
  5. */
  6. #include <linux/clockchips.h>
  7. #include <linux/interrupt.h>
  8. #include <linux/profile.h>
  9. #include <linux/delay.h>
  10. #include <linux/sched.h>
  11. #include <linux/cpu.h>
  12. #include <asm/cacheflush.h>
  13. #include <asm/switch_to.h>
  14. #include <asm/tlbflush.h>
  15. #include <asm/timer.h>
  16. #include <asm/oplib.h>
  17. #include "irq.h"
  18. #include "kernel.h"
  19. #define IRQ_IPI_SINGLE 12
  20. #define IRQ_IPI_MASK 13
  21. #define IRQ_IPI_RESCHED 14
  22. #define IRQ_CROSS_CALL 15
  23. static inline unsigned long
  24. swap_ulong(volatile unsigned long *ptr, unsigned long val)
  25. {
  26. __asm__ __volatile__("swap [%1], %0\n\t" :
  27. "=&r" (val), "=&r" (ptr) :
  28. "0" (val), "1" (ptr));
  29. return val;
  30. }
  31. void __cpuinit smp4m_callin(void)
  32. {
  33. int cpuid = hard_smp_processor_id();
  34. local_ops->cache_all();
  35. local_ops->tlb_all();
  36. notify_cpu_starting(cpuid);
  37. register_percpu_ce(cpuid);
  38. calibrate_delay();
  39. smp_store_cpu_info(cpuid);
  40. local_ops->cache_all();
  41. local_ops->tlb_all();
  42. /*
  43. * Unblock the master CPU _only_ when the scheduler state
  44. * of all secondary CPUs will be up-to-date, so after
  45. * the SMP initialization the master will be just allowed
  46. * to call the scheduler code.
  47. */
  48. /* Allow master to continue. */
  49. swap_ulong(&cpu_callin_map[cpuid], 1);
  50. /* XXX: What's up with all the flushes? */
  51. local_ops->cache_all();
  52. local_ops->tlb_all();
  53. /* Fix idle thread fields. */
  54. __asm__ __volatile__("ld [%0], %%g6\n\t"
  55. : : "r" (&current_set[cpuid])
  56. : "memory" /* paranoid */);
  57. /* Attach to the address space of init_task. */
  58. atomic_inc(&init_mm.mm_count);
  59. current->active_mm = &init_mm;
  60. while (!cpumask_test_cpu(cpuid, &smp_commenced_mask))
  61. mb();
  62. local_irq_enable();
  63. set_cpu_online(cpuid, true);
  64. }
  65. /*
  66. * Cycle through the processors asking the PROM to start each one.
  67. */
  68. void __init smp4m_boot_cpus(void)
  69. {
  70. sun4m_unmask_profile_irq();
  71. local_ops->cache_all();
  72. }
  73. int __cpuinit smp4m_boot_one_cpu(int i)
  74. {
  75. unsigned long *entry = &sun4m_cpu_startup;
  76. struct task_struct *p;
  77. int timeout;
  78. int cpu_node;
  79. cpu_find_by_mid(i, &cpu_node);
  80. /* Cook up an idler for this guy. */
  81. p = fork_idle(i);
  82. current_set[i] = task_thread_info(p);
  83. /* See trampoline.S for details... */
  84. entry += ((i - 1) * 3);
  85. /*
  86. * Initialize the contexts table
  87. * Since the call to prom_startcpu() trashes the structure,
  88. * we need to re-initialize it for each cpu
  89. */
  90. smp_penguin_ctable.which_io = 0;
  91. smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys;
  92. smp_penguin_ctable.reg_size = 0;
  93. /* whirrr, whirrr, whirrrrrrrrr... */
  94. printk(KERN_INFO "Starting CPU %d at %p\n", i, entry);
  95. local_ops->cache_all();
  96. prom_startcpu(cpu_node, &smp_penguin_ctable, 0, (char *)entry);
  97. /* wheee... it's going... */
  98. for (timeout = 0; timeout < 10000; timeout++) {
  99. if (cpu_callin_map[i])
  100. break;
  101. udelay(200);
  102. }
  103. if (!(cpu_callin_map[i])) {
  104. printk(KERN_ERR "Processor %d is stuck.\n", i);
  105. return -ENODEV;
  106. }
  107. local_ops->cache_all();
  108. return 0;
  109. }
  110. void __init smp4m_smp_done(void)
  111. {
  112. int i, first;
  113. int *prev;
  114. /* setup cpu list for irq rotation */
  115. first = 0;
  116. prev = &first;
  117. for_each_online_cpu(i) {
  118. *prev = i;
  119. prev = &cpu_data(i).next;
  120. }
  121. *prev = first;
  122. local_ops->cache_all();
  123. /* Ok, they are spinning and ready to go. */
  124. }
  125. static void sun4m_send_ipi(int cpu, int level)
  126. {
  127. sbus_writel(SUN4M_SOFT_INT(level), &sun4m_irq_percpu[cpu]->set);
  128. }
  129. static void sun4m_ipi_resched(int cpu)
  130. {
  131. sun4m_send_ipi(cpu, IRQ_IPI_RESCHED);
  132. }
  133. static void sun4m_ipi_single(int cpu)
  134. {
  135. sun4m_send_ipi(cpu, IRQ_IPI_SINGLE);
  136. }
  137. static void sun4m_ipi_mask_one(int cpu)
  138. {
  139. sun4m_send_ipi(cpu, IRQ_IPI_MASK);
  140. }
  141. static struct smp_funcall {
  142. smpfunc_t func;
  143. unsigned long arg1;
  144. unsigned long arg2;
  145. unsigned long arg3;
  146. unsigned long arg4;
  147. unsigned long arg5;
  148. unsigned long processors_in[SUN4M_NCPUS]; /* Set when ipi entered. */
  149. unsigned long processors_out[SUN4M_NCPUS]; /* Set when ipi exited. */
  150. } ccall_info;
  151. static DEFINE_SPINLOCK(cross_call_lock);
  152. /* Cross calls must be serialized, at least currently. */
  153. static void sun4m_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1,
  154. unsigned long arg2, unsigned long arg3,
  155. unsigned long arg4)
  156. {
  157. register int ncpus = SUN4M_NCPUS;
  158. unsigned long flags;
  159. spin_lock_irqsave(&cross_call_lock, flags);
  160. /* Init function glue. */
  161. ccall_info.func = func;
  162. ccall_info.arg1 = arg1;
  163. ccall_info.arg2 = arg2;
  164. ccall_info.arg3 = arg3;
  165. ccall_info.arg4 = arg4;
  166. ccall_info.arg5 = 0;
  167. /* Init receive/complete mapping, plus fire the IPI's off. */
  168. {
  169. register int i;
  170. cpumask_clear_cpu(smp_processor_id(), &mask);
  171. cpumask_and(&mask, cpu_online_mask, &mask);
  172. for (i = 0; i < ncpus; i++) {
  173. if (cpumask_test_cpu(i, &mask)) {
  174. ccall_info.processors_in[i] = 0;
  175. ccall_info.processors_out[i] = 0;
  176. sun4m_send_ipi(i, IRQ_CROSS_CALL);
  177. } else {
  178. ccall_info.processors_in[i] = 1;
  179. ccall_info.processors_out[i] = 1;
  180. }
  181. }
  182. }
  183. {
  184. register int i;
  185. i = 0;
  186. do {
  187. if (!cpumask_test_cpu(i, &mask))
  188. continue;
  189. while (!ccall_info.processors_in[i])
  190. barrier();
  191. } while (++i < ncpus);
  192. i = 0;
  193. do {
  194. if (!cpumask_test_cpu(i, &mask))
  195. continue;
  196. while (!ccall_info.processors_out[i])
  197. barrier();
  198. } while (++i < ncpus);
  199. }
  200. spin_unlock_irqrestore(&cross_call_lock, flags);
  201. }
  202. /* Running cross calls. */
  203. void smp4m_cross_call_irq(void)
  204. {
  205. int i = smp_processor_id();
  206. ccall_info.processors_in[i] = 1;
  207. ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3,
  208. ccall_info.arg4, ccall_info.arg5);
  209. ccall_info.processors_out[i] = 1;
  210. }
  211. void smp4m_percpu_timer_interrupt(struct pt_regs *regs)
  212. {
  213. struct pt_regs *old_regs;
  214. struct clock_event_device *ce;
  215. int cpu = smp_processor_id();
  216. old_regs = set_irq_regs(regs);
  217. ce = &per_cpu(sparc32_clockevent, cpu);
  218. if (ce->mode & CLOCK_EVT_MODE_PERIODIC)
  219. sun4m_clear_profile_irq(cpu);
  220. else
  221. sparc_config.load_profile_irq(cpu, 0); /* Is this needless? */
  222. irq_enter();
  223. ce->event_handler(ce);
  224. irq_exit();
  225. set_irq_regs(old_regs);
  226. }
  227. static const struct sparc32_ipi_ops sun4m_ipi_ops = {
  228. .cross_call = sun4m_cross_call,
  229. .resched = sun4m_ipi_resched,
  230. .single = sun4m_ipi_single,
  231. .mask_one = sun4m_ipi_mask_one,
  232. };
  233. void __init sun4m_init_smp(void)
  234. {
  235. sparc32_ipi_ops = &sun4m_ipi_ops;
  236. }