pinctrl.c 9.2 KB

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  1. /*
  2. * SuperH Pin Function Controller pinmux support.
  3. *
  4. * Copyright (C) 2012 Paul Mundt
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License. See the file "COPYING" in the main directory of this archive
  8. * for more details.
  9. */
  10. #define DRV_NAME "sh-pfc"
  11. #define pr_fmt(fmt) KBUILD_MODNAME " pinctrl: " fmt
  12. #include <linux/device.h>
  13. #include <linux/err.h>
  14. #include <linux/init.h>
  15. #include <linux/module.h>
  16. #include <linux/pinctrl/consumer.h>
  17. #include <linux/pinctrl/pinconf.h>
  18. #include <linux/pinctrl/pinconf-generic.h>
  19. #include <linux/pinctrl/pinctrl.h>
  20. #include <linux/pinctrl/pinmux.h>
  21. #include <linux/slab.h>
  22. #include <linux/spinlock.h>
  23. #include "core.h"
  24. struct sh_pfc_pinctrl {
  25. struct pinctrl_dev *pctl;
  26. struct pinctrl_desc pctl_desc;
  27. struct pinctrl_gpio_range range;
  28. struct sh_pfc *pfc;
  29. struct pinmux_gpio **functions;
  30. unsigned int nr_functions;
  31. struct pinctrl_pin_desc *pads;
  32. unsigned int nr_pads;
  33. };
  34. static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev)
  35. {
  36. struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
  37. return pmx->nr_pads;
  38. }
  39. static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev,
  40. unsigned selector)
  41. {
  42. struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
  43. return pmx->pads[selector].name;
  44. }
  45. static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
  46. const unsigned **pins, unsigned *num_pins)
  47. {
  48. struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
  49. *pins = &pmx->pads[group].number;
  50. *num_pins = 1;
  51. return 0;
  52. }
  53. static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
  54. unsigned offset)
  55. {
  56. seq_printf(s, "%s", DRV_NAME);
  57. }
  58. static const struct pinctrl_ops sh_pfc_pinctrl_ops = {
  59. .get_groups_count = sh_pfc_get_groups_count,
  60. .get_group_name = sh_pfc_get_group_name,
  61. .get_group_pins = sh_pfc_get_group_pins,
  62. .pin_dbg_show = sh_pfc_pin_dbg_show,
  63. };
  64. static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev)
  65. {
  66. struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
  67. return pmx->nr_functions;
  68. }
  69. static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev,
  70. unsigned selector)
  71. {
  72. struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
  73. return pmx->functions[selector]->name;
  74. }
  75. static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev, unsigned func,
  76. const char * const **groups,
  77. unsigned * const num_groups)
  78. {
  79. struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
  80. *groups = &pmx->functions[func]->name;
  81. *num_groups = 1;
  82. return 0;
  83. }
  84. static int sh_pfc_noop_enable(struct pinctrl_dev *pctldev, unsigned func,
  85. unsigned group)
  86. {
  87. return 0;
  88. }
  89. static void sh_pfc_noop_disable(struct pinctrl_dev *pctldev, unsigned func,
  90. unsigned group)
  91. {
  92. }
  93. static int sh_pfc_reconfig_pin(struct sh_pfc *pfc, unsigned offset,
  94. int new_type)
  95. {
  96. unsigned long flags;
  97. int pinmux_type;
  98. int ret = -EINVAL;
  99. spin_lock_irqsave(&pfc->lock, flags);
  100. pinmux_type = pfc->info->gpios[offset].flags & PINMUX_FLAG_TYPE;
  101. /*
  102. * See if the present config needs to first be de-configured.
  103. */
  104. switch (pinmux_type) {
  105. case PINMUX_TYPE_GPIO:
  106. break;
  107. case PINMUX_TYPE_OUTPUT:
  108. case PINMUX_TYPE_INPUT:
  109. case PINMUX_TYPE_INPUT_PULLUP:
  110. case PINMUX_TYPE_INPUT_PULLDOWN:
  111. sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE);
  112. break;
  113. default:
  114. goto err;
  115. }
  116. /*
  117. * Dry run
  118. */
  119. if (sh_pfc_config_gpio(pfc, offset, new_type,
  120. GPIO_CFG_DRYRUN) != 0)
  121. goto err;
  122. /*
  123. * Request
  124. */
  125. if (sh_pfc_config_gpio(pfc, offset, new_type,
  126. GPIO_CFG_REQ) != 0)
  127. goto err;
  128. pfc->info->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
  129. pfc->info->gpios[offset].flags |= new_type;
  130. ret = 0;
  131. err:
  132. spin_unlock_irqrestore(&pfc->lock, flags);
  133. return ret;
  134. }
  135. static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
  136. struct pinctrl_gpio_range *range,
  137. unsigned offset)
  138. {
  139. struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
  140. struct sh_pfc *pfc = pmx->pfc;
  141. unsigned long flags;
  142. int ret, pinmux_type;
  143. spin_lock_irqsave(&pfc->lock, flags);
  144. pinmux_type = pfc->info->gpios[offset].flags & PINMUX_FLAG_TYPE;
  145. switch (pinmux_type) {
  146. case PINMUX_TYPE_GPIO:
  147. case PINMUX_TYPE_INPUT:
  148. case PINMUX_TYPE_OUTPUT:
  149. break;
  150. case PINMUX_TYPE_FUNCTION:
  151. default:
  152. pr_err("Unsupported mux type (%d), bailing...\n", pinmux_type);
  153. ret = -ENOTSUPP;
  154. goto err;
  155. }
  156. ret = 0;
  157. err:
  158. spin_unlock_irqrestore(&pfc->lock, flags);
  159. return ret;
  160. }
  161. static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
  162. struct pinctrl_gpio_range *range,
  163. unsigned offset)
  164. {
  165. struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
  166. struct sh_pfc *pfc = pmx->pfc;
  167. unsigned long flags;
  168. int pinmux_type;
  169. spin_lock_irqsave(&pfc->lock, flags);
  170. pinmux_type = pfc->info->gpios[offset].flags & PINMUX_FLAG_TYPE;
  171. sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE);
  172. spin_unlock_irqrestore(&pfc->lock, flags);
  173. }
  174. static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
  175. struct pinctrl_gpio_range *range,
  176. unsigned offset, bool input)
  177. {
  178. struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
  179. int type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT;
  180. return sh_pfc_reconfig_pin(pmx->pfc, offset, type);
  181. }
  182. static const struct pinmux_ops sh_pfc_pinmux_ops = {
  183. .get_functions_count = sh_pfc_get_functions_count,
  184. .get_function_name = sh_pfc_get_function_name,
  185. .get_function_groups = sh_pfc_get_function_groups,
  186. .enable = sh_pfc_noop_enable,
  187. .disable = sh_pfc_noop_disable,
  188. .gpio_request_enable = sh_pfc_gpio_request_enable,
  189. .gpio_disable_free = sh_pfc_gpio_disable_free,
  190. .gpio_set_direction = sh_pfc_gpio_set_direction,
  191. };
  192. static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
  193. unsigned long *config)
  194. {
  195. struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
  196. struct sh_pfc *pfc = pmx->pfc;
  197. *config = pfc->info->gpios[pin].flags & PINMUX_FLAG_TYPE;
  198. return 0;
  199. }
  200. static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
  201. unsigned long config)
  202. {
  203. struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
  204. /* Validate the new type */
  205. if (config >= PINMUX_FLAG_TYPE)
  206. return -EINVAL;
  207. return sh_pfc_reconfig_pin(pmx->pfc, pin, config);
  208. }
  209. static void sh_pfc_pinconf_dbg_show(struct pinctrl_dev *pctldev,
  210. struct seq_file *s, unsigned pin)
  211. {
  212. const char *pinmux_type_str[] = {
  213. [PINMUX_TYPE_NONE] = "none",
  214. [PINMUX_TYPE_FUNCTION] = "function",
  215. [PINMUX_TYPE_GPIO] = "gpio",
  216. [PINMUX_TYPE_OUTPUT] = "output",
  217. [PINMUX_TYPE_INPUT] = "input",
  218. [PINMUX_TYPE_INPUT_PULLUP] = "input bias pull up",
  219. [PINMUX_TYPE_INPUT_PULLDOWN] = "input bias pull down",
  220. };
  221. unsigned long config;
  222. int rc;
  223. rc = sh_pfc_pinconf_get(pctldev, pin, &config);
  224. if (unlikely(rc != 0))
  225. return;
  226. seq_printf(s, " %s", pinmux_type_str[config]);
  227. }
  228. static const struct pinconf_ops sh_pfc_pinconf_ops = {
  229. .pin_config_get = sh_pfc_pinconf_get,
  230. .pin_config_set = sh_pfc_pinconf_set,
  231. .pin_config_dbg_show = sh_pfc_pinconf_dbg_show,
  232. };
  233. /* pinmux ranges -> pinctrl pin descs */
  234. static int sh_pfc_map_gpios(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
  235. {
  236. int i;
  237. pmx->nr_pads = pfc->info->nr_gpios;
  238. pmx->pads = devm_kzalloc(pfc->dev, sizeof(*pmx->pads) * pmx->nr_pads,
  239. GFP_KERNEL);
  240. if (unlikely(!pmx->pads)) {
  241. pmx->nr_pads = 0;
  242. return -ENOMEM;
  243. }
  244. for (i = 0; i < pmx->nr_pads; i++) {
  245. struct pinctrl_pin_desc *pin = pmx->pads + i;
  246. struct pinmux_gpio *gpio = pfc->info->gpios + i;
  247. pin->number = i;
  248. pin->name = gpio->name;
  249. /* XXX */
  250. if (unlikely(!gpio->enum_id))
  251. continue;
  252. if ((gpio->flags & PINMUX_FLAG_TYPE) == PINMUX_TYPE_FUNCTION)
  253. pmx->nr_functions++;
  254. }
  255. return 0;
  256. }
  257. static int sh_pfc_map_functions(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
  258. {
  259. int i, fn;
  260. pmx->functions = devm_kzalloc(pfc->dev, pmx->nr_functions *
  261. sizeof(*pmx->functions), GFP_KERNEL);
  262. if (unlikely(!pmx->functions))
  263. return -ENOMEM;
  264. for (i = fn = 0; i < pmx->nr_pads; i++) {
  265. struct pinmux_gpio *gpio = pfc->info->gpios + i;
  266. if ((gpio->flags & PINMUX_FLAG_TYPE) == PINMUX_TYPE_FUNCTION)
  267. pmx->functions[fn++] = gpio;
  268. }
  269. return 0;
  270. }
  271. int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
  272. {
  273. struct sh_pfc_pinctrl *pmx;
  274. int ret;
  275. pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL);
  276. if (unlikely(!pmx))
  277. return -ENOMEM;
  278. pmx->pfc = pfc;
  279. pfc->pinctrl = pmx;
  280. ret = sh_pfc_map_gpios(pfc, pmx);
  281. if (unlikely(ret != 0))
  282. return ret;
  283. ret = sh_pfc_map_functions(pfc, pmx);
  284. if (unlikely(ret != 0))
  285. return ret;
  286. pmx->pctl_desc.name = DRV_NAME;
  287. pmx->pctl_desc.owner = THIS_MODULE;
  288. pmx->pctl_desc.pctlops = &sh_pfc_pinctrl_ops;
  289. pmx->pctl_desc.pmxops = &sh_pfc_pinmux_ops;
  290. pmx->pctl_desc.confops = &sh_pfc_pinconf_ops;
  291. pmx->pctl_desc.pins = pmx->pads;
  292. pmx->pctl_desc.npins = pmx->nr_pads;
  293. pmx->pctl = pinctrl_register(&pmx->pctl_desc, pfc->dev, pmx);
  294. if (IS_ERR(pmx->pctl))
  295. return PTR_ERR(pmx->pctl);
  296. pmx->range.name = DRV_NAME,
  297. pmx->range.id = 0;
  298. pmx->range.npins = pfc->info->nr_pins;
  299. pmx->range.base = 0;
  300. pmx->range.pin_base = 0;
  301. pinctrl_add_gpio_range(pmx->pctl, &pmx->range);
  302. return 0;
  303. }
  304. int sh_pfc_unregister_pinctrl(struct sh_pfc *pfc)
  305. {
  306. struct sh_pfc_pinctrl *pmx = pfc->pinctrl;
  307. pinctrl_unregister(pmx->pctl);
  308. pfc->pinctrl = NULL;
  309. return 0;
  310. }