ql4_mbx.c 35 KB

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  1. /*
  2. * QLogic iSCSI HBA Driver
  3. * Copyright (c) 2003-2006 QLogic Corporation
  4. *
  5. * See LICENSE.qla4xxx for copyright and licensing details.
  6. */
  7. #include "ql4_def.h"
  8. #include "ql4_glbl.h"
  9. #include "ql4_dbg.h"
  10. #include "ql4_inline.h"
  11. /**
  12. * qla4xxx_mailbox_command - issues mailbox commands
  13. * @ha: Pointer to host adapter structure.
  14. * @inCount: number of mailbox registers to load.
  15. * @outCount: number of mailbox registers to return.
  16. * @mbx_cmd: data pointer for mailbox in registers.
  17. * @mbx_sts: data pointer for mailbox out registers.
  18. *
  19. * This routine isssue mailbox commands and waits for completion.
  20. * If outCount is 0, this routine completes successfully WITHOUT waiting
  21. * for the mailbox command to complete.
  22. **/
  23. int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount,
  24. uint8_t outCount, uint32_t *mbx_cmd,
  25. uint32_t *mbx_sts)
  26. {
  27. int status = QLA_ERROR;
  28. uint8_t i;
  29. u_long wait_count;
  30. uint32_t intr_status;
  31. unsigned long flags = 0;
  32. /* Make sure that pointers are valid */
  33. if (!mbx_cmd || !mbx_sts) {
  34. DEBUG2(printk("scsi%ld: %s: Invalid mbx_cmd or mbx_sts "
  35. "pointer\n", ha->host_no, __func__));
  36. return status;
  37. }
  38. if (is_qla8022(ha) &&
  39. test_bit(AF_FW_RECOVERY, &ha->flags)) {
  40. DEBUG2(ql4_printk(KERN_WARNING, ha, "scsi%ld: %s: prematurely "
  41. "completing mbx cmd as firmware recovery detected\n",
  42. ha->host_no, __func__));
  43. return status;
  44. }
  45. /* Mailbox code active */
  46. wait_count = MBOX_TOV * 100;
  47. while (wait_count--) {
  48. mutex_lock(&ha->mbox_sem);
  49. if (!test_bit(AF_MBOX_COMMAND, &ha->flags)) {
  50. set_bit(AF_MBOX_COMMAND, &ha->flags);
  51. mutex_unlock(&ha->mbox_sem);
  52. break;
  53. }
  54. mutex_unlock(&ha->mbox_sem);
  55. if (!wait_count) {
  56. DEBUG2(printk("scsi%ld: %s: mbox_sem failed\n",
  57. ha->host_no, __func__));
  58. return status;
  59. }
  60. msleep(10);
  61. }
  62. /* To prevent overwriting mailbox registers for a command that has
  63. * not yet been serviced, check to see if an active command
  64. * (AEN, IOCB, etc.) is interrupting, then service it.
  65. * -----------------------------------------------------------------
  66. */
  67. spin_lock_irqsave(&ha->hardware_lock, flags);
  68. if (is_qla8022(ha)) {
  69. intr_status = readl(&ha->qla4_8xxx_reg->host_int);
  70. if (intr_status & ISRX_82XX_RISC_INT) {
  71. /* Service existing interrupt */
  72. DEBUG2(printk("scsi%ld: %s: "
  73. "servicing existing interrupt\n",
  74. ha->host_no, __func__));
  75. intr_status = readl(&ha->qla4_8xxx_reg->host_status);
  76. ha->isp_ops->interrupt_service_routine(ha, intr_status);
  77. clear_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
  78. if (test_bit(AF_INTERRUPTS_ON, &ha->flags) &&
  79. test_bit(AF_INTx_ENABLED, &ha->flags))
  80. qla4_8xxx_wr_32(ha,
  81. ha->nx_legacy_intr.tgt_mask_reg,
  82. 0xfbff);
  83. }
  84. } else {
  85. intr_status = readl(&ha->reg->ctrl_status);
  86. if (intr_status & CSR_SCSI_PROCESSOR_INTR) {
  87. /* Service existing interrupt */
  88. ha->isp_ops->interrupt_service_routine(ha, intr_status);
  89. clear_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
  90. }
  91. }
  92. ha->mbox_status_count = outCount;
  93. for (i = 0; i < outCount; i++)
  94. ha->mbox_status[i] = 0;
  95. if (is_qla8022(ha)) {
  96. /* Load all mailbox registers, except mailbox 0. */
  97. DEBUG5(
  98. printk("scsi%ld: %s: Cmd ", ha->host_no, __func__);
  99. for (i = 0; i < inCount; i++)
  100. printk("mb%d=%04x ", i, mbx_cmd[i]);
  101. printk("\n"));
  102. for (i = 1; i < inCount; i++)
  103. writel(mbx_cmd[i], &ha->qla4_8xxx_reg->mailbox_in[i]);
  104. writel(mbx_cmd[0], &ha->qla4_8xxx_reg->mailbox_in[0]);
  105. readl(&ha->qla4_8xxx_reg->mailbox_in[0]);
  106. writel(HINT_MBX_INT_PENDING, &ha->qla4_8xxx_reg->hint);
  107. } else {
  108. /* Load all mailbox registers, except mailbox 0. */
  109. for (i = 1; i < inCount; i++)
  110. writel(mbx_cmd[i], &ha->reg->mailbox[i]);
  111. /* Wakeup firmware */
  112. writel(mbx_cmd[0], &ha->reg->mailbox[0]);
  113. readl(&ha->reg->mailbox[0]);
  114. writel(set_rmask(CSR_INTR_RISC), &ha->reg->ctrl_status);
  115. readl(&ha->reg->ctrl_status);
  116. }
  117. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  118. /* Wait for completion */
  119. /*
  120. * If we don't want status, don't wait for the mailbox command to
  121. * complete. For example, MBOX_CMD_RESET_FW doesn't return status,
  122. * you must poll the inbound Interrupt Mask for completion.
  123. */
  124. if (outCount == 0) {
  125. status = QLA_SUCCESS;
  126. goto mbox_exit;
  127. }
  128. /*
  129. * Wait for completion: Poll or completion queue
  130. */
  131. if (test_bit(AF_IRQ_ATTACHED, &ha->flags) &&
  132. test_bit(AF_INTERRUPTS_ON, &ha->flags) &&
  133. test_bit(AF_ONLINE, &ha->flags) &&
  134. !test_bit(AF_HBA_GOING_AWAY, &ha->flags)) {
  135. /* Do not poll for completion. Use completion queue */
  136. set_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
  137. wait_for_completion_timeout(&ha->mbx_intr_comp, MBOX_TOV * HZ);
  138. clear_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
  139. } else {
  140. /* Poll for command to complete */
  141. wait_count = jiffies + MBOX_TOV * HZ;
  142. while (test_bit(AF_MBOX_COMMAND_DONE, &ha->flags) == 0) {
  143. if (time_after_eq(jiffies, wait_count))
  144. break;
  145. /*
  146. * Service the interrupt.
  147. * The ISR will save the mailbox status registers
  148. * to a temporary storage location in the adapter
  149. * structure.
  150. */
  151. spin_lock_irqsave(&ha->hardware_lock, flags);
  152. if (is_qla8022(ha)) {
  153. intr_status =
  154. readl(&ha->qla4_8xxx_reg->host_int);
  155. if (intr_status & ISRX_82XX_RISC_INT) {
  156. ha->mbox_status_count = outCount;
  157. intr_status =
  158. readl(&ha->qla4_8xxx_reg->host_status);
  159. ha->isp_ops->interrupt_service_routine(
  160. ha, intr_status);
  161. if (test_bit(AF_INTERRUPTS_ON,
  162. &ha->flags) &&
  163. test_bit(AF_INTx_ENABLED,
  164. &ha->flags))
  165. qla4_8xxx_wr_32(ha,
  166. ha->nx_legacy_intr.tgt_mask_reg,
  167. 0xfbff);
  168. }
  169. } else {
  170. intr_status = readl(&ha->reg->ctrl_status);
  171. if (intr_status & INTR_PENDING) {
  172. /*
  173. * Service the interrupt.
  174. * The ISR will save the mailbox status
  175. * registers to a temporary storage
  176. * location in the adapter structure.
  177. */
  178. ha->mbox_status_count = outCount;
  179. ha->isp_ops->interrupt_service_routine(
  180. ha, intr_status);
  181. }
  182. }
  183. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  184. msleep(10);
  185. }
  186. }
  187. /* Check for mailbox timeout. */
  188. if (!test_bit(AF_MBOX_COMMAND_DONE, &ha->flags)) {
  189. if (is_qla8022(ha) &&
  190. test_bit(AF_FW_RECOVERY, &ha->flags)) {
  191. DEBUG2(ql4_printk(KERN_INFO, ha,
  192. "scsi%ld: %s: prematurely completing mbx cmd as "
  193. "firmware recovery detected\n",
  194. ha->host_no, __func__));
  195. goto mbox_exit;
  196. }
  197. DEBUG2(printk("scsi%ld: Mailbox Cmd 0x%08X timed out ...,"
  198. " Scheduling Adapter Reset\n", ha->host_no,
  199. mbx_cmd[0]));
  200. ha->mailbox_timeout_count++;
  201. mbx_sts[0] = (-1);
  202. set_bit(DPC_RESET_HA, &ha->dpc_flags);
  203. goto mbox_exit;
  204. }
  205. /*
  206. * Copy the mailbox out registers to the caller's mailbox in/out
  207. * structure.
  208. */
  209. spin_lock_irqsave(&ha->hardware_lock, flags);
  210. for (i = 0; i < outCount; i++)
  211. mbx_sts[i] = ha->mbox_status[i];
  212. /* Set return status and error flags (if applicable). */
  213. switch (ha->mbox_status[0]) {
  214. case MBOX_STS_COMMAND_COMPLETE:
  215. status = QLA_SUCCESS;
  216. break;
  217. case MBOX_STS_INTERMEDIATE_COMPLETION:
  218. status = QLA_SUCCESS;
  219. break;
  220. case MBOX_STS_BUSY:
  221. DEBUG2( printk("scsi%ld: %s: Cmd = %08X, ISP BUSY\n",
  222. ha->host_no, __func__, mbx_cmd[0]));
  223. ha->mailbox_timeout_count++;
  224. break;
  225. default:
  226. DEBUG2(printk("scsi%ld: %s: **** FAILED, cmd = %08X, "
  227. "sts = %08X ****\n", ha->host_no, __func__,
  228. mbx_cmd[0], mbx_sts[0]));
  229. break;
  230. }
  231. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  232. mbox_exit:
  233. mutex_lock(&ha->mbox_sem);
  234. clear_bit(AF_MBOX_COMMAND, &ha->flags);
  235. mutex_unlock(&ha->mbox_sem);
  236. clear_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
  237. return status;
  238. }
  239. void qla4xxx_mailbox_premature_completion(struct scsi_qla_host *ha)
  240. {
  241. set_bit(AF_FW_RECOVERY, &ha->flags);
  242. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: set FW RECOVERY!\n",
  243. ha->host_no, __func__);
  244. if (test_bit(AF_MBOX_COMMAND, &ha->flags)) {
  245. if (test_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags)) {
  246. complete(&ha->mbx_intr_comp);
  247. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw "
  248. "recovery, doing premature completion of "
  249. "mbx cmd\n", ha->host_no, __func__);
  250. } else {
  251. set_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
  252. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw "
  253. "recovery, doing premature completion of "
  254. "polling mbx cmd\n", ha->host_no, __func__);
  255. }
  256. }
  257. }
  258. static uint8_t
  259. qla4xxx_set_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  260. uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
  261. {
  262. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  263. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  264. mbox_cmd[0] = MBOX_CMD_INITIALIZE_FIRMWARE;
  265. mbox_cmd[1] = 0;
  266. mbox_cmd[2] = LSDW(init_fw_cb_dma);
  267. mbox_cmd[3] = MSDW(init_fw_cb_dma);
  268. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  269. mbox_cmd[5] = (IFCB_VER_MAX << 8) | IFCB_VER_MIN;
  270. if (qla4xxx_mailbox_command(ha, 6, 6, mbox_cmd, mbox_sts) !=
  271. QLA_SUCCESS) {
  272. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
  273. "MBOX_CMD_INITIALIZE_FIRMWARE"
  274. " failed w/ status %04X\n",
  275. ha->host_no, __func__, mbox_sts[0]));
  276. return QLA_ERROR;
  277. }
  278. return QLA_SUCCESS;
  279. }
  280. static uint8_t
  281. qla4xxx_get_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  282. uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
  283. {
  284. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  285. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  286. mbox_cmd[0] = MBOX_CMD_GET_INIT_FW_CTRL_BLOCK;
  287. mbox_cmd[2] = LSDW(init_fw_cb_dma);
  288. mbox_cmd[3] = MSDW(init_fw_cb_dma);
  289. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  290. if (qla4xxx_mailbox_command(ha, 5, 5, mbox_cmd, mbox_sts) !=
  291. QLA_SUCCESS) {
  292. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
  293. "MBOX_CMD_GET_INIT_FW_CTRL_BLOCK"
  294. " failed w/ status %04X\n",
  295. ha->host_no, __func__, mbox_sts[0]));
  296. return QLA_ERROR;
  297. }
  298. return QLA_SUCCESS;
  299. }
  300. static void
  301. qla4xxx_update_local_ip(struct scsi_qla_host *ha,
  302. struct addr_ctrl_blk *init_fw_cb)
  303. {
  304. /* Save IPv4 Address Info */
  305. memcpy(ha->ip_address, init_fw_cb->ipv4_addr,
  306. min(sizeof(ha->ip_address), sizeof(init_fw_cb->ipv4_addr)));
  307. memcpy(ha->subnet_mask, init_fw_cb->ipv4_subnet,
  308. min(sizeof(ha->subnet_mask), sizeof(init_fw_cb->ipv4_subnet)));
  309. memcpy(ha->gateway, init_fw_cb->ipv4_gw_addr,
  310. min(sizeof(ha->gateway), sizeof(init_fw_cb->ipv4_gw_addr)));
  311. if (is_ipv6_enabled(ha)) {
  312. /* Save IPv6 Address */
  313. ha->ipv6_link_local_state = init_fw_cb->ipv6_lnk_lcl_addr_state;
  314. ha->ipv6_addr0_state = init_fw_cb->ipv6_addr0_state;
  315. ha->ipv6_addr1_state = init_fw_cb->ipv6_addr1_state;
  316. ha->ipv6_default_router_state = init_fw_cb->ipv6_dflt_rtr_state;
  317. ha->ipv6_link_local_addr.in6_u.u6_addr8[0] = 0xFE;
  318. ha->ipv6_link_local_addr.in6_u.u6_addr8[1] = 0x80;
  319. memcpy(&ha->ipv6_link_local_addr.in6_u.u6_addr8[8],
  320. init_fw_cb->ipv6_if_id,
  321. min(sizeof(ha->ipv6_link_local_addr)/2,
  322. sizeof(init_fw_cb->ipv6_if_id)));
  323. memcpy(&ha->ipv6_addr0, init_fw_cb->ipv6_addr0,
  324. min(sizeof(ha->ipv6_addr0),
  325. sizeof(init_fw_cb->ipv6_addr0)));
  326. memcpy(&ha->ipv6_addr1, init_fw_cb->ipv6_addr1,
  327. min(sizeof(ha->ipv6_addr1),
  328. sizeof(init_fw_cb->ipv6_addr1)));
  329. memcpy(&ha->ipv6_default_router_addr,
  330. init_fw_cb->ipv6_dflt_rtr_addr,
  331. min(sizeof(ha->ipv6_default_router_addr),
  332. sizeof(init_fw_cb->ipv6_dflt_rtr_addr)));
  333. }
  334. }
  335. static uint8_t
  336. qla4xxx_update_local_ifcb(struct scsi_qla_host *ha,
  337. uint32_t *mbox_cmd,
  338. uint32_t *mbox_sts,
  339. struct addr_ctrl_blk *init_fw_cb,
  340. dma_addr_t init_fw_cb_dma)
  341. {
  342. if (qla4xxx_get_ifcb(ha, mbox_cmd, mbox_sts, init_fw_cb_dma)
  343. != QLA_SUCCESS) {
  344. DEBUG2(printk(KERN_WARNING
  345. "scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
  346. ha->host_no, __func__));
  347. return QLA_ERROR;
  348. }
  349. DEBUG2(qla4xxx_dump_buffer(init_fw_cb, sizeof(struct addr_ctrl_blk)));
  350. /* Save some info in adapter structure. */
  351. ha->acb_version = init_fw_cb->acb_version;
  352. ha->firmware_options = le16_to_cpu(init_fw_cb->fw_options);
  353. ha->tcp_options = le16_to_cpu(init_fw_cb->ipv4_tcp_opts);
  354. ha->ipv4_options = le16_to_cpu(init_fw_cb->ipv4_ip_opts);
  355. ha->ipv4_addr_state = le16_to_cpu(init_fw_cb->ipv4_addr_state);
  356. ha->heartbeat_interval = init_fw_cb->hb_interval;
  357. memcpy(ha->name_string, init_fw_cb->iscsi_name,
  358. min(sizeof(ha->name_string),
  359. sizeof(init_fw_cb->iscsi_name)));
  360. /*memcpy(ha->alias, init_fw_cb->Alias,
  361. min(sizeof(ha->alias), sizeof(init_fw_cb->Alias)));*/
  362. /* Save Command Line Paramater info */
  363. ha->discovery_wait = ql4xdiscoverywait;
  364. if (ha->acb_version == ACB_SUPPORTED) {
  365. ha->ipv6_options = init_fw_cb->ipv6_opts;
  366. ha->ipv6_addl_options = init_fw_cb->ipv6_addtl_opts;
  367. }
  368. qla4xxx_update_local_ip(ha, init_fw_cb);
  369. return QLA_SUCCESS;
  370. }
  371. /**
  372. * qla4xxx_initialize_fw_cb - initializes firmware control block.
  373. * @ha: Pointer to host adapter structure.
  374. **/
  375. int qla4xxx_initialize_fw_cb(struct scsi_qla_host * ha)
  376. {
  377. struct addr_ctrl_blk *init_fw_cb;
  378. dma_addr_t init_fw_cb_dma;
  379. uint32_t mbox_cmd[MBOX_REG_COUNT];
  380. uint32_t mbox_sts[MBOX_REG_COUNT];
  381. int status = QLA_ERROR;
  382. init_fw_cb = dma_alloc_coherent(&ha->pdev->dev,
  383. sizeof(struct addr_ctrl_blk),
  384. &init_fw_cb_dma, GFP_KERNEL);
  385. if (init_fw_cb == NULL) {
  386. DEBUG2(printk("scsi%ld: %s: Unable to alloc init_cb\n",
  387. ha->host_no, __func__));
  388. goto exit_init_fw_cb_no_free;
  389. }
  390. memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk));
  391. /* Get Initialize Firmware Control Block. */
  392. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  393. memset(&mbox_sts, 0, sizeof(mbox_sts));
  394. if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
  395. QLA_SUCCESS) {
  396. dma_free_coherent(&ha->pdev->dev,
  397. sizeof(struct addr_ctrl_blk),
  398. init_fw_cb, init_fw_cb_dma);
  399. goto exit_init_fw_cb;
  400. }
  401. /* Initialize request and response queues. */
  402. qla4xxx_init_rings(ha);
  403. /* Fill in the request and response queue information. */
  404. init_fw_cb->rqq_consumer_idx = cpu_to_le16(ha->request_out);
  405. init_fw_cb->compq_producer_idx = cpu_to_le16(ha->response_in);
  406. init_fw_cb->rqq_len = __constant_cpu_to_le16(REQUEST_QUEUE_DEPTH);
  407. init_fw_cb->compq_len = __constant_cpu_to_le16(RESPONSE_QUEUE_DEPTH);
  408. init_fw_cb->rqq_addr_lo = cpu_to_le32(LSDW(ha->request_dma));
  409. init_fw_cb->rqq_addr_hi = cpu_to_le32(MSDW(ha->request_dma));
  410. init_fw_cb->compq_addr_lo = cpu_to_le32(LSDW(ha->response_dma));
  411. init_fw_cb->compq_addr_hi = cpu_to_le32(MSDW(ha->response_dma));
  412. init_fw_cb->shdwreg_addr_lo = cpu_to_le32(LSDW(ha->shadow_regs_dma));
  413. init_fw_cb->shdwreg_addr_hi = cpu_to_le32(MSDW(ha->shadow_regs_dma));
  414. /* Set up required options. */
  415. init_fw_cb->fw_options |=
  416. __constant_cpu_to_le16(FWOPT_SESSION_MODE |
  417. FWOPT_INITIATOR_MODE);
  418. init_fw_cb->fw_options &= __constant_cpu_to_le16(~FWOPT_TARGET_MODE);
  419. if (qla4xxx_set_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma)
  420. != QLA_SUCCESS) {
  421. DEBUG2(printk(KERN_WARNING
  422. "scsi%ld: %s: Failed to set init_fw_ctrl_blk\n",
  423. ha->host_no, __func__));
  424. goto exit_init_fw_cb;
  425. }
  426. if (qla4xxx_update_local_ifcb(ha, &mbox_cmd[0], &mbox_sts[0],
  427. init_fw_cb, init_fw_cb_dma) != QLA_SUCCESS) {
  428. DEBUG2(printk("scsi%ld: %s: Failed to update local ifcb\n",
  429. ha->host_no, __func__));
  430. goto exit_init_fw_cb;
  431. }
  432. status = QLA_SUCCESS;
  433. exit_init_fw_cb:
  434. dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
  435. init_fw_cb, init_fw_cb_dma);
  436. exit_init_fw_cb_no_free:
  437. return status;
  438. }
  439. /**
  440. * qla4xxx_get_dhcp_ip_address - gets HBA ip address via DHCP
  441. * @ha: Pointer to host adapter structure.
  442. **/
  443. int qla4xxx_get_dhcp_ip_address(struct scsi_qla_host * ha)
  444. {
  445. struct addr_ctrl_blk *init_fw_cb;
  446. dma_addr_t init_fw_cb_dma;
  447. uint32_t mbox_cmd[MBOX_REG_COUNT];
  448. uint32_t mbox_sts[MBOX_REG_COUNT];
  449. init_fw_cb = dma_alloc_coherent(&ha->pdev->dev,
  450. sizeof(struct addr_ctrl_blk),
  451. &init_fw_cb_dma, GFP_KERNEL);
  452. if (init_fw_cb == NULL) {
  453. printk("scsi%ld: %s: Unable to alloc init_cb\n", ha->host_no,
  454. __func__);
  455. return QLA_ERROR;
  456. }
  457. /* Get Initialize Firmware Control Block. */
  458. memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk));
  459. if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
  460. QLA_SUCCESS) {
  461. DEBUG2(printk("scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
  462. ha->host_no, __func__));
  463. dma_free_coherent(&ha->pdev->dev,
  464. sizeof(struct addr_ctrl_blk),
  465. init_fw_cb, init_fw_cb_dma);
  466. return QLA_ERROR;
  467. }
  468. /* Save IP Address. */
  469. qla4xxx_update_local_ip(ha, init_fw_cb);
  470. dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
  471. init_fw_cb, init_fw_cb_dma);
  472. return QLA_SUCCESS;
  473. }
  474. /**
  475. * qla4xxx_get_firmware_state - gets firmware state of HBA
  476. * @ha: Pointer to host adapter structure.
  477. **/
  478. int qla4xxx_get_firmware_state(struct scsi_qla_host * ha)
  479. {
  480. uint32_t mbox_cmd[MBOX_REG_COUNT];
  481. uint32_t mbox_sts[MBOX_REG_COUNT];
  482. /* Get firmware version */
  483. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  484. memset(&mbox_sts, 0, sizeof(mbox_sts));
  485. mbox_cmd[0] = MBOX_CMD_GET_FW_STATE;
  486. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 4, &mbox_cmd[0], &mbox_sts[0]) !=
  487. QLA_SUCCESS) {
  488. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATE failed w/ "
  489. "status %04X\n", ha->host_no, __func__,
  490. mbox_sts[0]));
  491. return QLA_ERROR;
  492. }
  493. ha->firmware_state = mbox_sts[1];
  494. ha->board_id = mbox_sts[2];
  495. ha->addl_fw_state = mbox_sts[3];
  496. DEBUG2(printk("scsi%ld: %s firmware_state=0x%x\n",
  497. ha->host_no, __func__, ha->firmware_state);)
  498. return QLA_SUCCESS;
  499. }
  500. /**
  501. * qla4xxx_get_firmware_status - retrieves firmware status
  502. * @ha: Pointer to host adapter structure.
  503. **/
  504. int qla4xxx_get_firmware_status(struct scsi_qla_host * ha)
  505. {
  506. uint32_t mbox_cmd[MBOX_REG_COUNT];
  507. uint32_t mbox_sts[MBOX_REG_COUNT];
  508. /* Get firmware version */
  509. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  510. memset(&mbox_sts, 0, sizeof(mbox_sts));
  511. mbox_cmd[0] = MBOX_CMD_GET_FW_STATUS;
  512. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0], &mbox_sts[0]) !=
  513. QLA_SUCCESS) {
  514. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATUS failed w/ "
  515. "status %04X\n", ha->host_no, __func__,
  516. mbox_sts[0]));
  517. return QLA_ERROR;
  518. }
  519. ql4_printk(KERN_INFO, ha, "%ld firmare IOCBs available (%d).\n",
  520. ha->host_no, mbox_cmd[2]);
  521. return QLA_SUCCESS;
  522. }
  523. /**
  524. * qla4xxx_get_fwddb_entry - retrieves firmware ddb entry
  525. * @ha: Pointer to host adapter structure.
  526. * @fw_ddb_index: Firmware's device database index
  527. * @fw_ddb_entry: Pointer to firmware's device database entry structure
  528. * @num_valid_ddb_entries: Pointer to number of valid ddb entries
  529. * @next_ddb_index: Pointer to next valid device database index
  530. * @fw_ddb_device_state: Pointer to device state
  531. **/
  532. int qla4xxx_get_fwddb_entry(struct scsi_qla_host *ha,
  533. uint16_t fw_ddb_index,
  534. struct dev_db_entry *fw_ddb_entry,
  535. dma_addr_t fw_ddb_entry_dma,
  536. uint32_t *num_valid_ddb_entries,
  537. uint32_t *next_ddb_index,
  538. uint32_t *fw_ddb_device_state,
  539. uint32_t *conn_err_detail,
  540. uint16_t *tcp_source_port_num,
  541. uint16_t *connection_id)
  542. {
  543. int status = QLA_ERROR;
  544. uint16_t options;
  545. uint32_t mbox_cmd[MBOX_REG_COUNT];
  546. uint32_t mbox_sts[MBOX_REG_COUNT];
  547. /* Make sure the device index is valid */
  548. if (fw_ddb_index >= MAX_DDB_ENTRIES) {
  549. DEBUG2(printk("scsi%ld: %s: ddb [%d] out of range.\n",
  550. ha->host_no, __func__, fw_ddb_index));
  551. goto exit_get_fwddb;
  552. }
  553. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  554. memset(&mbox_sts, 0, sizeof(mbox_sts));
  555. mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY;
  556. mbox_cmd[1] = (uint32_t) fw_ddb_index;
  557. mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
  558. mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
  559. mbox_cmd[4] = sizeof(struct dev_db_entry);
  560. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 7, &mbox_cmd[0], &mbox_sts[0]) ==
  561. QLA_ERROR) {
  562. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_DATABASE_ENTRY failed"
  563. " with status 0x%04X\n", ha->host_no, __func__,
  564. mbox_sts[0]));
  565. goto exit_get_fwddb;
  566. }
  567. if (fw_ddb_index != mbox_sts[1]) {
  568. DEBUG2(printk("scsi%ld: %s: ddb mismatch [%d] != [%d].\n",
  569. ha->host_no, __func__, fw_ddb_index,
  570. mbox_sts[1]));
  571. goto exit_get_fwddb;
  572. }
  573. if (fw_ddb_entry) {
  574. options = le16_to_cpu(fw_ddb_entry->options);
  575. if (options & DDB_OPT_IPV6_DEVICE) {
  576. ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
  577. "Next %d State %04x ConnErr %08x %pI6 "
  578. ":%04d \"%s\"\n", __func__, fw_ddb_index,
  579. mbox_sts[0], mbox_sts[2], mbox_sts[3],
  580. mbox_sts[4], mbox_sts[5],
  581. fw_ddb_entry->ip_addr,
  582. le16_to_cpu(fw_ddb_entry->port),
  583. fw_ddb_entry->iscsi_name);
  584. } else {
  585. ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
  586. "Next %d State %04x ConnErr %08x %pI4 "
  587. ":%04d \"%s\"\n", __func__, fw_ddb_index,
  588. mbox_sts[0], mbox_sts[2], mbox_sts[3],
  589. mbox_sts[4], mbox_sts[5],
  590. fw_ddb_entry->ip_addr,
  591. le16_to_cpu(fw_ddb_entry->port),
  592. fw_ddb_entry->iscsi_name);
  593. }
  594. }
  595. if (num_valid_ddb_entries)
  596. *num_valid_ddb_entries = mbox_sts[2];
  597. if (next_ddb_index)
  598. *next_ddb_index = mbox_sts[3];
  599. if (fw_ddb_device_state)
  600. *fw_ddb_device_state = mbox_sts[4];
  601. /*
  602. * RA: This mailbox has been changed to pass connection error and
  603. * details. Its true for ISP4010 as per Version E - Not sure when it
  604. * was changed. Get the time2wait from the fw_dd_entry field :
  605. * default_time2wait which we call it as minTime2Wait DEV_DB_ENTRY
  606. * struct.
  607. */
  608. if (conn_err_detail)
  609. *conn_err_detail = mbox_sts[5];
  610. if (tcp_source_port_num)
  611. *tcp_source_port_num = (uint16_t) (mbox_sts[6] >> 16);
  612. if (connection_id)
  613. *connection_id = (uint16_t) mbox_sts[6] & 0x00FF;
  614. status = QLA_SUCCESS;
  615. exit_get_fwddb:
  616. return status;
  617. }
  618. /**
  619. * qla4xxx_set_fwddb_entry - sets a ddb entry.
  620. * @ha: Pointer to host adapter structure.
  621. * @fw_ddb_index: Firmware's device database index
  622. * @fw_ddb_entry: Pointer to firmware's ddb entry structure, or NULL.
  623. *
  624. * This routine initializes or updates the adapter's device database
  625. * entry for the specified device. It also triggers a login for the
  626. * specified device. Therefore, it may also be used as a secondary
  627. * login routine when a NULL pointer is specified for the fw_ddb_entry.
  628. **/
  629. int qla4xxx_set_ddb_entry(struct scsi_qla_host * ha, uint16_t fw_ddb_index,
  630. dma_addr_t fw_ddb_entry_dma)
  631. {
  632. uint32_t mbox_cmd[MBOX_REG_COUNT];
  633. uint32_t mbox_sts[MBOX_REG_COUNT];
  634. int status;
  635. /* Do not wait for completion. The firmware will send us an
  636. * ASTS_DATABASE_CHANGED (0x8014) to notify us of the login status.
  637. */
  638. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  639. memset(&mbox_sts, 0, sizeof(mbox_sts));
  640. mbox_cmd[0] = MBOX_CMD_SET_DATABASE_ENTRY;
  641. mbox_cmd[1] = (uint32_t) fw_ddb_index;
  642. mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
  643. mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
  644. mbox_cmd[4] = sizeof(struct dev_db_entry);
  645. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
  646. &mbox_sts[0]);
  647. DEBUG2(printk("scsi%ld: %s: status=%d mbx0=0x%x mbx4=0x%x\n",
  648. ha->host_no, __func__, status, mbox_sts[0], mbox_sts[4]);)
  649. return status;
  650. }
  651. /**
  652. * qla4xxx_get_crash_record - retrieves crash record.
  653. * @ha: Pointer to host adapter structure.
  654. *
  655. * This routine retrieves a crash record from the QLA4010 after an 8002h aen.
  656. **/
  657. void qla4xxx_get_crash_record(struct scsi_qla_host * ha)
  658. {
  659. uint32_t mbox_cmd[MBOX_REG_COUNT];
  660. uint32_t mbox_sts[MBOX_REG_COUNT];
  661. struct crash_record *crash_record = NULL;
  662. dma_addr_t crash_record_dma = 0;
  663. uint32_t crash_record_size = 0;
  664. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  665. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  666. /* Get size of crash record. */
  667. mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
  668. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  669. QLA_SUCCESS) {
  670. DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve size!\n",
  671. ha->host_no, __func__));
  672. goto exit_get_crash_record;
  673. }
  674. crash_record_size = mbox_sts[4];
  675. if (crash_record_size == 0) {
  676. DEBUG2(printk("scsi%ld: %s: ERROR: Crash record size is 0!\n",
  677. ha->host_no, __func__));
  678. goto exit_get_crash_record;
  679. }
  680. /* Alloc Memory for Crash Record. */
  681. crash_record = dma_alloc_coherent(&ha->pdev->dev, crash_record_size,
  682. &crash_record_dma, GFP_KERNEL);
  683. if (crash_record == NULL)
  684. goto exit_get_crash_record;
  685. /* Get Crash Record. */
  686. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  687. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  688. mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
  689. mbox_cmd[2] = LSDW(crash_record_dma);
  690. mbox_cmd[3] = MSDW(crash_record_dma);
  691. mbox_cmd[4] = crash_record_size;
  692. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  693. QLA_SUCCESS)
  694. goto exit_get_crash_record;
  695. /* Dump Crash Record. */
  696. exit_get_crash_record:
  697. if (crash_record)
  698. dma_free_coherent(&ha->pdev->dev, crash_record_size,
  699. crash_record, crash_record_dma);
  700. }
  701. /**
  702. * qla4xxx_get_conn_event_log - retrieves connection event log
  703. * @ha: Pointer to host adapter structure.
  704. **/
  705. void qla4xxx_get_conn_event_log(struct scsi_qla_host * ha)
  706. {
  707. uint32_t mbox_cmd[MBOX_REG_COUNT];
  708. uint32_t mbox_sts[MBOX_REG_COUNT];
  709. struct conn_event_log_entry *event_log = NULL;
  710. dma_addr_t event_log_dma = 0;
  711. uint32_t event_log_size = 0;
  712. uint32_t num_valid_entries;
  713. uint32_t oldest_entry = 0;
  714. uint32_t max_event_log_entries;
  715. uint8_t i;
  716. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  717. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  718. /* Get size of crash record. */
  719. mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
  720. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  721. QLA_SUCCESS)
  722. goto exit_get_event_log;
  723. event_log_size = mbox_sts[4];
  724. if (event_log_size == 0)
  725. goto exit_get_event_log;
  726. /* Alloc Memory for Crash Record. */
  727. event_log = dma_alloc_coherent(&ha->pdev->dev, event_log_size,
  728. &event_log_dma, GFP_KERNEL);
  729. if (event_log == NULL)
  730. goto exit_get_event_log;
  731. /* Get Crash Record. */
  732. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  733. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  734. mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
  735. mbox_cmd[2] = LSDW(event_log_dma);
  736. mbox_cmd[3] = MSDW(event_log_dma);
  737. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  738. QLA_SUCCESS) {
  739. DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve event "
  740. "log!\n", ha->host_no, __func__));
  741. goto exit_get_event_log;
  742. }
  743. /* Dump Event Log. */
  744. num_valid_entries = mbox_sts[1];
  745. max_event_log_entries = event_log_size /
  746. sizeof(struct conn_event_log_entry);
  747. if (num_valid_entries > max_event_log_entries)
  748. oldest_entry = num_valid_entries % max_event_log_entries;
  749. DEBUG3(printk("scsi%ld: Connection Event Log Dump (%d entries):\n",
  750. ha->host_no, num_valid_entries));
  751. if (ql4xextended_error_logging == 3) {
  752. if (oldest_entry == 0) {
  753. /* Circular Buffer has not wrapped around */
  754. for (i=0; i < num_valid_entries; i++) {
  755. qla4xxx_dump_buffer((uint8_t *)event_log+
  756. (i*sizeof(*event_log)),
  757. sizeof(*event_log));
  758. }
  759. }
  760. else {
  761. /* Circular Buffer has wrapped around -
  762. * display accordingly*/
  763. for (i=oldest_entry; i < max_event_log_entries; i++) {
  764. qla4xxx_dump_buffer((uint8_t *)event_log+
  765. (i*sizeof(*event_log)),
  766. sizeof(*event_log));
  767. }
  768. for (i=0; i < oldest_entry; i++) {
  769. qla4xxx_dump_buffer((uint8_t *)event_log+
  770. (i*sizeof(*event_log)),
  771. sizeof(*event_log));
  772. }
  773. }
  774. }
  775. exit_get_event_log:
  776. if (event_log)
  777. dma_free_coherent(&ha->pdev->dev, event_log_size, event_log,
  778. event_log_dma);
  779. }
  780. /**
  781. * qla4xxx_abort_task - issues Abort Task
  782. * @ha: Pointer to host adapter structure.
  783. * @srb: Pointer to srb entry
  784. *
  785. * This routine performs a LUN RESET on the specified target/lun.
  786. * The caller must ensure that the ddb_entry and lun_entry pointers
  787. * are valid before calling this routine.
  788. **/
  789. int qla4xxx_abort_task(struct scsi_qla_host *ha, struct srb *srb)
  790. {
  791. uint32_t mbox_cmd[MBOX_REG_COUNT];
  792. uint32_t mbox_sts[MBOX_REG_COUNT];
  793. struct scsi_cmnd *cmd = srb->cmd;
  794. int status = QLA_SUCCESS;
  795. unsigned long flags = 0;
  796. uint32_t index;
  797. /*
  798. * Send abort task command to ISP, so that the ISP will return
  799. * request with ABORT status
  800. */
  801. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  802. memset(&mbox_sts, 0, sizeof(mbox_sts));
  803. spin_lock_irqsave(&ha->hardware_lock, flags);
  804. index = (unsigned long)(unsigned char *)cmd->host_scribble;
  805. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  806. /* Firmware already posted completion on response queue */
  807. if (index == MAX_SRBS)
  808. return status;
  809. mbox_cmd[0] = MBOX_CMD_ABORT_TASK;
  810. mbox_cmd[1] = srb->fw_ddb_index;
  811. mbox_cmd[2] = index;
  812. /* Immediate Command Enable */
  813. mbox_cmd[5] = 0x01;
  814. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
  815. &mbox_sts[0]);
  816. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE) {
  817. status = QLA_ERROR;
  818. DEBUG2(printk(KERN_WARNING "scsi%ld:%d:%d: abort task FAILED: "
  819. "mbx0=%04X, mb1=%04X, mb2=%04X, mb3=%04X, mb4=%04X\n",
  820. ha->host_no, cmd->device->id, cmd->device->lun, mbox_sts[0],
  821. mbox_sts[1], mbox_sts[2], mbox_sts[3], mbox_sts[4]));
  822. }
  823. return status;
  824. }
  825. /**
  826. * qla4xxx_reset_lun - issues LUN Reset
  827. * @ha: Pointer to host adapter structure.
  828. * @ddb_entry: Pointer to device database entry
  829. * @lun: lun number
  830. *
  831. * This routine performs a LUN RESET on the specified target/lun.
  832. * The caller must ensure that the ddb_entry and lun_entry pointers
  833. * are valid before calling this routine.
  834. **/
  835. int qla4xxx_reset_lun(struct scsi_qla_host * ha, struct ddb_entry * ddb_entry,
  836. int lun)
  837. {
  838. uint32_t mbox_cmd[MBOX_REG_COUNT];
  839. uint32_t mbox_sts[MBOX_REG_COUNT];
  840. int status = QLA_SUCCESS;
  841. DEBUG2(printk("scsi%ld:%d:%d: lun reset issued\n", ha->host_no,
  842. ddb_entry->fw_ddb_index, lun));
  843. /*
  844. * Send lun reset command to ISP, so that the ISP will return all
  845. * outstanding requests with RESET status
  846. */
  847. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  848. memset(&mbox_sts, 0, sizeof(mbox_sts));
  849. mbox_cmd[0] = MBOX_CMD_LUN_RESET;
  850. mbox_cmd[1] = ddb_entry->fw_ddb_index;
  851. mbox_cmd[2] = lun << 8;
  852. mbox_cmd[5] = 0x01; /* Immediate Command Enable */
  853. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]);
  854. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
  855. mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
  856. status = QLA_ERROR;
  857. return status;
  858. }
  859. /**
  860. * qla4xxx_reset_target - issues target Reset
  861. * @ha: Pointer to host adapter structure.
  862. * @db_entry: Pointer to device database entry
  863. * @un_entry: Pointer to lun entry structure
  864. *
  865. * This routine performs a TARGET RESET on the specified target.
  866. * The caller must ensure that the ddb_entry pointers
  867. * are valid before calling this routine.
  868. **/
  869. int qla4xxx_reset_target(struct scsi_qla_host *ha,
  870. struct ddb_entry *ddb_entry)
  871. {
  872. uint32_t mbox_cmd[MBOX_REG_COUNT];
  873. uint32_t mbox_sts[MBOX_REG_COUNT];
  874. int status = QLA_SUCCESS;
  875. DEBUG2(printk("scsi%ld:%d: target reset issued\n", ha->host_no,
  876. ddb_entry->fw_ddb_index));
  877. /*
  878. * Send target reset command to ISP, so that the ISP will return all
  879. * outstanding requests with RESET status
  880. */
  881. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  882. memset(&mbox_sts, 0, sizeof(mbox_sts));
  883. mbox_cmd[0] = MBOX_CMD_TARGET_WARM_RESET;
  884. mbox_cmd[1] = ddb_entry->fw_ddb_index;
  885. mbox_cmd[5] = 0x01; /* Immediate Command Enable */
  886. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
  887. &mbox_sts[0]);
  888. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
  889. mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
  890. status = QLA_ERROR;
  891. return status;
  892. }
  893. int qla4xxx_get_flash(struct scsi_qla_host * ha, dma_addr_t dma_addr,
  894. uint32_t offset, uint32_t len)
  895. {
  896. uint32_t mbox_cmd[MBOX_REG_COUNT];
  897. uint32_t mbox_sts[MBOX_REG_COUNT];
  898. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  899. memset(&mbox_sts, 0, sizeof(mbox_sts));
  900. mbox_cmd[0] = MBOX_CMD_READ_FLASH;
  901. mbox_cmd[1] = LSDW(dma_addr);
  902. mbox_cmd[2] = MSDW(dma_addr);
  903. mbox_cmd[3] = offset;
  904. mbox_cmd[4] = len;
  905. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0], &mbox_sts[0]) !=
  906. QLA_SUCCESS) {
  907. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_READ_FLASH, failed w/ "
  908. "status %04X %04X, offset %08x, len %08x\n", ha->host_no,
  909. __func__, mbox_sts[0], mbox_sts[1], offset, len));
  910. return QLA_ERROR;
  911. }
  912. return QLA_SUCCESS;
  913. }
  914. /**
  915. * qla4xxx_get_fw_version - gets firmware version
  916. * @ha: Pointer to host adapter structure.
  917. *
  918. * Retrieves the firmware version on HBA. In QLA4010, mailboxes 2 & 3 may
  919. * hold an address for data. Make sure that we write 0 to those mailboxes,
  920. * if unused.
  921. **/
  922. int qla4xxx_get_fw_version(struct scsi_qla_host * ha)
  923. {
  924. uint32_t mbox_cmd[MBOX_REG_COUNT];
  925. uint32_t mbox_sts[MBOX_REG_COUNT];
  926. /* Get firmware version. */
  927. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  928. memset(&mbox_sts, 0, sizeof(mbox_sts));
  929. mbox_cmd[0] = MBOX_CMD_ABOUT_FW;
  930. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  931. QLA_SUCCESS) {
  932. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_ABOUT_FW failed w/ "
  933. "status %04X\n", ha->host_no, __func__, mbox_sts[0]));
  934. return QLA_ERROR;
  935. }
  936. /* Save firmware version information. */
  937. ha->firmware_version[0] = mbox_sts[1];
  938. ha->firmware_version[1] = mbox_sts[2];
  939. ha->patch_number = mbox_sts[3];
  940. ha->build_number = mbox_sts[4];
  941. return QLA_SUCCESS;
  942. }
  943. static int qla4xxx_get_default_ddb(struct scsi_qla_host *ha,
  944. dma_addr_t dma_addr)
  945. {
  946. uint32_t mbox_cmd[MBOX_REG_COUNT];
  947. uint32_t mbox_sts[MBOX_REG_COUNT];
  948. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  949. memset(&mbox_sts, 0, sizeof(mbox_sts));
  950. mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS;
  951. mbox_cmd[2] = LSDW(dma_addr);
  952. mbox_cmd[3] = MSDW(dma_addr);
  953. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]) !=
  954. QLA_SUCCESS) {
  955. DEBUG2(printk("scsi%ld: %s: failed status %04X\n",
  956. ha->host_no, __func__, mbox_sts[0]));
  957. return QLA_ERROR;
  958. }
  959. return QLA_SUCCESS;
  960. }
  961. static int qla4xxx_req_ddb_entry(struct scsi_qla_host *ha, uint32_t *ddb_index)
  962. {
  963. uint32_t mbox_cmd[MBOX_REG_COUNT];
  964. uint32_t mbox_sts[MBOX_REG_COUNT];
  965. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  966. memset(&mbox_sts, 0, sizeof(mbox_sts));
  967. mbox_cmd[0] = MBOX_CMD_REQUEST_DATABASE_ENTRY;
  968. mbox_cmd[1] = MAX_PRST_DEV_DB_ENTRIES;
  969. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0], &mbox_sts[0]) !=
  970. QLA_SUCCESS) {
  971. if (mbox_sts[0] == MBOX_STS_COMMAND_ERROR) {
  972. *ddb_index = mbox_sts[2];
  973. } else {
  974. DEBUG2(printk("scsi%ld: %s: failed status %04X\n",
  975. ha->host_no, __func__, mbox_sts[0]));
  976. return QLA_ERROR;
  977. }
  978. } else {
  979. *ddb_index = MAX_PRST_DEV_DB_ENTRIES;
  980. }
  981. return QLA_SUCCESS;
  982. }
  983. int qla4xxx_send_tgts(struct scsi_qla_host *ha, char *ip, uint16_t port)
  984. {
  985. struct dev_db_entry *fw_ddb_entry;
  986. dma_addr_t fw_ddb_entry_dma;
  987. uint32_t ddb_index;
  988. int ret_val = QLA_SUCCESS;
  989. fw_ddb_entry = dma_alloc_coherent(&ha->pdev->dev,
  990. sizeof(*fw_ddb_entry),
  991. &fw_ddb_entry_dma, GFP_KERNEL);
  992. if (!fw_ddb_entry) {
  993. DEBUG2(printk("scsi%ld: %s: Unable to allocate dma buffer.\n",
  994. ha->host_no, __func__));
  995. ret_val = QLA_ERROR;
  996. goto exit_send_tgts_no_free;
  997. }
  998. ret_val = qla4xxx_get_default_ddb(ha, fw_ddb_entry_dma);
  999. if (ret_val != QLA_SUCCESS)
  1000. goto exit_send_tgts;
  1001. ret_val = qla4xxx_req_ddb_entry(ha, &ddb_index);
  1002. if (ret_val != QLA_SUCCESS)
  1003. goto exit_send_tgts;
  1004. memset(fw_ddb_entry->iscsi_alias, 0,
  1005. sizeof(fw_ddb_entry->iscsi_alias));
  1006. memset(fw_ddb_entry->iscsi_name, 0,
  1007. sizeof(fw_ddb_entry->iscsi_name));
  1008. memset(fw_ddb_entry->ip_addr, 0, sizeof(fw_ddb_entry->ip_addr));
  1009. memset(fw_ddb_entry->tgt_addr, 0,
  1010. sizeof(fw_ddb_entry->tgt_addr));
  1011. fw_ddb_entry->options = (DDB_OPT_DISC_SESSION | DDB_OPT_TARGET);
  1012. fw_ddb_entry->port = cpu_to_le16(ntohs(port));
  1013. fw_ddb_entry->ip_addr[0] = *ip;
  1014. fw_ddb_entry->ip_addr[1] = *(ip + 1);
  1015. fw_ddb_entry->ip_addr[2] = *(ip + 2);
  1016. fw_ddb_entry->ip_addr[3] = *(ip + 3);
  1017. ret_val = qla4xxx_set_ddb_entry(ha, ddb_index, fw_ddb_entry_dma);
  1018. exit_send_tgts:
  1019. dma_free_coherent(&ha->pdev->dev, sizeof(*fw_ddb_entry),
  1020. fw_ddb_entry, fw_ddb_entry_dma);
  1021. exit_send_tgts_no_free:
  1022. return ret_val;
  1023. }