irq.c 7.8 KB

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  1. /*
  2. * linux/arch/i386/kernel/irq.c
  3. *
  4. * Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
  5. *
  6. * This file contains the lowest level x86-specific interrupt
  7. * entry, irq-stacks and irq statistics code. All the remaining
  8. * irq logic is done by the generic kernel/irq/ code and
  9. * by the x86-specific irq controller code. (e.g. i8259.c and
  10. * io_apic.c.)
  11. */
  12. #include <asm/uaccess.h>
  13. #include <linux/module.h>
  14. #include <linux/seq_file.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/kernel_stat.h>
  17. #include <linux/notifier.h>
  18. #include <linux/cpu.h>
  19. #include <linux/delay.h>
  20. DEFINE_PER_CPU(irq_cpustat_t, irq_stat) ____cacheline_internodealigned_in_smp;
  21. EXPORT_PER_CPU_SYMBOL(irq_stat);
  22. #ifndef CONFIG_X86_LOCAL_APIC
  23. /*
  24. * 'what should we do if we get a hw irq event on an illegal vector'.
  25. * each architecture has to answer this themselves.
  26. */
  27. void ack_bad_irq(unsigned int irq)
  28. {
  29. printk("unexpected IRQ trap at vector %02x\n", irq);
  30. }
  31. #endif
  32. #ifdef CONFIG_4KSTACKS
  33. /*
  34. * per-CPU IRQ handling contexts (thread information and stack)
  35. */
  36. union irq_ctx {
  37. struct thread_info tinfo;
  38. u32 stack[THREAD_SIZE/sizeof(u32)];
  39. };
  40. static union irq_ctx *hardirq_ctx[NR_CPUS] __read_mostly;
  41. static union irq_ctx *softirq_ctx[NR_CPUS] __read_mostly;
  42. #endif
  43. /*
  44. * do_IRQ handles all normal device IRQ's (the special
  45. * SMP cross-CPU interrupts have their own specific
  46. * handlers).
  47. */
  48. fastcall unsigned int do_IRQ(struct pt_regs *regs)
  49. {
  50. /* high bit used in ret_from_ code */
  51. int irq = ~regs->orig_eax;
  52. #ifdef CONFIG_4KSTACKS
  53. union irq_ctx *curctx, *irqctx;
  54. u32 *isp;
  55. #endif
  56. if (unlikely((unsigned)irq >= NR_IRQS)) {
  57. printk(KERN_EMERG "%s: cannot handle IRQ %d\n",
  58. __FUNCTION__, irq);
  59. BUG();
  60. }
  61. irq_enter();
  62. #ifdef CONFIG_DEBUG_STACKOVERFLOW
  63. /* Debugging check for stack overflow: is there less than 1KB free? */
  64. {
  65. long esp;
  66. __asm__ __volatile__("andl %%esp,%0" :
  67. "=r" (esp) : "0" (THREAD_SIZE - 1));
  68. if (unlikely(esp < (sizeof(struct thread_info) + STACK_WARN))) {
  69. printk("do_IRQ: stack overflow: %ld\n",
  70. esp - sizeof(struct thread_info));
  71. dump_stack();
  72. }
  73. }
  74. #endif
  75. #ifdef CONFIG_4KSTACKS
  76. curctx = (union irq_ctx *) current_thread_info();
  77. irqctx = hardirq_ctx[smp_processor_id()];
  78. /*
  79. * this is where we switch to the IRQ stack. However, if we are
  80. * already using the IRQ stack (because we interrupted a hardirq
  81. * handler) we can't do that and just have to keep using the
  82. * current stack (which is the irq stack already after all)
  83. */
  84. if (curctx != irqctx) {
  85. int arg1, arg2, ebx;
  86. /* build the stack frame on the IRQ stack */
  87. isp = (u32*) ((char*)irqctx + sizeof(*irqctx));
  88. irqctx->tinfo.task = curctx->tinfo.task;
  89. irqctx->tinfo.previous_esp = current_stack_pointer;
  90. /*
  91. * Copy the softirq bits in preempt_count so that the
  92. * softirq checks work in the hardirq context.
  93. */
  94. irqctx->tinfo.preempt_count =
  95. (irqctx->tinfo.preempt_count & ~SOFTIRQ_MASK) |
  96. (curctx->tinfo.preempt_count & SOFTIRQ_MASK);
  97. asm volatile(
  98. " xchgl %%ebx,%%esp \n"
  99. " call __do_IRQ \n"
  100. " movl %%ebx,%%esp \n"
  101. : "=a" (arg1), "=d" (arg2), "=b" (ebx)
  102. : "0" (irq), "1" (regs), "2" (isp)
  103. : "memory", "cc", "ecx"
  104. );
  105. } else
  106. #endif
  107. __do_IRQ(irq, regs);
  108. irq_exit();
  109. return 1;
  110. }
  111. #ifdef CONFIG_4KSTACKS
  112. /*
  113. * These should really be __section__(".bss.page_aligned") as well, but
  114. * gcc's 3.0 and earlier don't handle that correctly.
  115. */
  116. static char softirq_stack[NR_CPUS * THREAD_SIZE]
  117. __attribute__((__aligned__(THREAD_SIZE)));
  118. static char hardirq_stack[NR_CPUS * THREAD_SIZE]
  119. __attribute__((__aligned__(THREAD_SIZE)));
  120. /*
  121. * allocate per-cpu stacks for hardirq and for softirq processing
  122. */
  123. void irq_ctx_init(int cpu)
  124. {
  125. union irq_ctx *irqctx;
  126. if (hardirq_ctx[cpu])
  127. return;
  128. irqctx = (union irq_ctx*) &hardirq_stack[cpu*THREAD_SIZE];
  129. irqctx->tinfo.task = NULL;
  130. irqctx->tinfo.exec_domain = NULL;
  131. irqctx->tinfo.cpu = cpu;
  132. irqctx->tinfo.preempt_count = HARDIRQ_OFFSET;
  133. irqctx->tinfo.addr_limit = MAKE_MM_SEG(0);
  134. hardirq_ctx[cpu] = irqctx;
  135. irqctx = (union irq_ctx*) &softirq_stack[cpu*THREAD_SIZE];
  136. irqctx->tinfo.task = NULL;
  137. irqctx->tinfo.exec_domain = NULL;
  138. irqctx->tinfo.cpu = cpu;
  139. irqctx->tinfo.preempt_count = 0;
  140. irqctx->tinfo.addr_limit = MAKE_MM_SEG(0);
  141. softirq_ctx[cpu] = irqctx;
  142. printk("CPU %u irqstacks, hard=%p soft=%p\n",
  143. cpu,hardirq_ctx[cpu],softirq_ctx[cpu]);
  144. }
  145. void irq_ctx_exit(int cpu)
  146. {
  147. hardirq_ctx[cpu] = NULL;
  148. }
  149. extern asmlinkage void __do_softirq(void);
  150. asmlinkage void do_softirq(void)
  151. {
  152. unsigned long flags;
  153. struct thread_info *curctx;
  154. union irq_ctx *irqctx;
  155. u32 *isp;
  156. if (in_interrupt())
  157. return;
  158. local_irq_save(flags);
  159. if (local_softirq_pending()) {
  160. curctx = current_thread_info();
  161. irqctx = softirq_ctx[smp_processor_id()];
  162. irqctx->tinfo.task = curctx->task;
  163. irqctx->tinfo.previous_esp = current_stack_pointer;
  164. /* build the stack frame on the softirq stack */
  165. isp = (u32*) ((char*)irqctx + sizeof(*irqctx));
  166. asm volatile(
  167. " xchgl %%ebx,%%esp \n"
  168. " call __do_softirq \n"
  169. " movl %%ebx,%%esp \n"
  170. : "=b"(isp)
  171. : "0"(isp)
  172. : "memory", "cc", "edx", "ecx", "eax"
  173. );
  174. /*
  175. * Shouldnt happen, we returned above if in_interrupt():
  176. */
  177. WARN_ON_ONCE(softirq_count());
  178. }
  179. local_irq_restore(flags);
  180. }
  181. EXPORT_SYMBOL(do_softirq);
  182. #endif
  183. /*
  184. * Interrupt statistics:
  185. */
  186. atomic_t irq_err_count;
  187. /*
  188. * /proc/interrupts printing:
  189. */
  190. int show_interrupts(struct seq_file *p, void *v)
  191. {
  192. int i = *(loff_t *) v, j;
  193. struct irqaction * action;
  194. unsigned long flags;
  195. if (i == 0) {
  196. seq_printf(p, " ");
  197. for_each_online_cpu(j)
  198. seq_printf(p, "CPU%-8d",j);
  199. seq_putc(p, '\n');
  200. }
  201. if (i < NR_IRQS) {
  202. spin_lock_irqsave(&irq_desc[i].lock, flags);
  203. action = irq_desc[i].action;
  204. if (!action)
  205. goto skip;
  206. seq_printf(p, "%3d: ",i);
  207. #ifndef CONFIG_SMP
  208. seq_printf(p, "%10u ", kstat_irqs(i));
  209. #else
  210. for_each_online_cpu(j)
  211. seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
  212. #endif
  213. seq_printf(p, " %14s", irq_desc[i].chip->typename);
  214. seq_printf(p, " %s", action->name);
  215. for (action=action->next; action; action = action->next)
  216. seq_printf(p, ", %s", action->name);
  217. seq_putc(p, '\n');
  218. skip:
  219. spin_unlock_irqrestore(&irq_desc[i].lock, flags);
  220. } else if (i == NR_IRQS) {
  221. seq_printf(p, "NMI: ");
  222. for_each_online_cpu(j)
  223. seq_printf(p, "%10u ", nmi_count(j));
  224. seq_putc(p, '\n');
  225. #ifdef CONFIG_X86_LOCAL_APIC
  226. seq_printf(p, "LOC: ");
  227. for_each_online_cpu(j)
  228. seq_printf(p, "%10u ",
  229. per_cpu(irq_stat,j).apic_timer_irqs);
  230. seq_putc(p, '\n');
  231. #endif
  232. seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
  233. #if defined(CONFIG_X86_IO_APIC)
  234. seq_printf(p, "MIS: %10u\n", atomic_read(&irq_mis_count));
  235. #endif
  236. }
  237. return 0;
  238. }
  239. #ifdef CONFIG_HOTPLUG_CPU
  240. #include <mach_apic.h>
  241. void fixup_irqs(cpumask_t map)
  242. {
  243. unsigned int irq;
  244. static int warned;
  245. for (irq = 0; irq < NR_IRQS; irq++) {
  246. cpumask_t mask;
  247. if (irq == 2)
  248. continue;
  249. cpus_and(mask, irq_desc[irq].affinity, map);
  250. if (any_online_cpu(mask) == NR_CPUS) {
  251. printk("Breaking affinity for irq %i\n", irq);
  252. mask = map;
  253. }
  254. if (irq_desc[irq].chip->set_affinity)
  255. irq_desc[irq].chip->set_affinity(irq, mask);
  256. else if (irq_desc[irq].action && !(warned++))
  257. printk("Cannot set affinity for irq %i\n", irq);
  258. }
  259. #if 0
  260. barrier();
  261. /* Ingo Molnar says: "after the IO-APIC masks have been redirected
  262. [note the nop - the interrupt-enable boundary on x86 is two
  263. instructions from sti] - to flush out pending hardirqs and
  264. IPIs. After this point nothing is supposed to reach this CPU." */
  265. __asm__ __volatile__("sti; nop; cli");
  266. barrier();
  267. #else
  268. /* That doesn't seem sufficient. Give it 1ms. */
  269. local_irq_enable();
  270. mdelay(1);
  271. local_irq_disable();
  272. #endif
  273. }
  274. #endif