pxa-ssp.c 22 KB

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  1. #define DEBUG
  2. /*
  3. * pxa-ssp.c -- ALSA Soc Audio Layer
  4. *
  5. * Copyright 2005,2008 Wolfson Microelectronics PLC.
  6. * Author: Liam Girdwood
  7. * Mark Brown <broonie@opensource.wolfsonmicro.com>
  8. *
  9. * This program is free software; you can redistribute it and/or modify it
  10. * under the terms of the GNU General Public License as published by the
  11. * Free Software Foundation; either version 2 of the License, or (at your
  12. * option) any later version.
  13. *
  14. * TODO:
  15. * o Test network mode for > 16bit sample size
  16. */
  17. #include <linux/init.h>
  18. #include <linux/module.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/clk.h>
  21. #include <linux/io.h>
  22. #include <asm/irq.h>
  23. #include <sound/core.h>
  24. #include <sound/pcm.h>
  25. #include <sound/initval.h>
  26. #include <sound/pcm_params.h>
  27. #include <sound/soc.h>
  28. #include <sound/pxa2xx-lib.h>
  29. #include <mach/hardware.h>
  30. #include <mach/pxa-regs.h>
  31. #include <mach/regs-ssp.h>
  32. #include <mach/audio.h>
  33. #include <mach/ssp.h>
  34. #include "pxa2xx-pcm.h"
  35. #include "pxa-ssp.h"
  36. /*
  37. * SSP audio private data
  38. */
  39. struct ssp_priv {
  40. struct ssp_dev dev;
  41. unsigned int sysclk;
  42. int dai_fmt;
  43. #ifdef CONFIG_PM
  44. struct ssp_state state;
  45. #endif
  46. };
  47. #define PXA2xx_SSP1_BASE 0x41000000
  48. #define PXA27x_SSP2_BASE 0x41700000
  49. #define PXA27x_SSP3_BASE 0x41900000
  50. #define PXA3xx_SSP4_BASE 0x41a00000
  51. static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_mono_out = {
  52. .name = "SSP1 PCM Mono out",
  53. .dev_addr = PXA2xx_SSP1_BASE + SSDR,
  54. .drcmr = &DRCMR(14),
  55. .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
  56. DCMD_BURST16 | DCMD_WIDTH2,
  57. };
  58. static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_mono_in = {
  59. .name = "SSP1 PCM Mono in",
  60. .dev_addr = PXA2xx_SSP1_BASE + SSDR,
  61. .drcmr = &DRCMR(13),
  62. .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
  63. DCMD_BURST16 | DCMD_WIDTH2,
  64. };
  65. static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_stereo_out = {
  66. .name = "SSP1 PCM Stereo out",
  67. .dev_addr = PXA2xx_SSP1_BASE + SSDR,
  68. .drcmr = &DRCMR(14),
  69. .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
  70. DCMD_BURST16 | DCMD_WIDTH4,
  71. };
  72. static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_stereo_in = {
  73. .name = "SSP1 PCM Stereo in",
  74. .dev_addr = PXA2xx_SSP1_BASE + SSDR,
  75. .drcmr = &DRCMR(13),
  76. .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
  77. DCMD_BURST16 | DCMD_WIDTH4,
  78. };
  79. static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_mono_out = {
  80. .name = "SSP2 PCM Mono out",
  81. .dev_addr = PXA27x_SSP2_BASE + SSDR,
  82. .drcmr = &DRCMR(16),
  83. .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
  84. DCMD_BURST16 | DCMD_WIDTH2,
  85. };
  86. static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_mono_in = {
  87. .name = "SSP2 PCM Mono in",
  88. .dev_addr = PXA27x_SSP2_BASE + SSDR,
  89. .drcmr = &DRCMR(15),
  90. .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
  91. DCMD_BURST16 | DCMD_WIDTH2,
  92. };
  93. static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_stereo_out = {
  94. .name = "SSP2 PCM Stereo out",
  95. .dev_addr = PXA27x_SSP2_BASE + SSDR,
  96. .drcmr = &DRCMR(16),
  97. .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
  98. DCMD_BURST16 | DCMD_WIDTH4,
  99. };
  100. static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_stereo_in = {
  101. .name = "SSP2 PCM Stereo in",
  102. .dev_addr = PXA27x_SSP2_BASE + SSDR,
  103. .drcmr = &DRCMR(15),
  104. .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
  105. DCMD_BURST16 | DCMD_WIDTH4,
  106. };
  107. static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_mono_out = {
  108. .name = "SSP3 PCM Mono out",
  109. .dev_addr = PXA27x_SSP3_BASE + SSDR,
  110. .drcmr = &DRCMR(67),
  111. .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
  112. DCMD_BURST16 | DCMD_WIDTH2,
  113. };
  114. static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_mono_in = {
  115. .name = "SSP3 PCM Mono in",
  116. .dev_addr = PXA27x_SSP3_BASE + SSDR,
  117. .drcmr = &DRCMR(66),
  118. .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
  119. DCMD_BURST16 | DCMD_WIDTH2,
  120. };
  121. static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_stereo_out = {
  122. .name = "SSP3 PCM Stereo out",
  123. .dev_addr = PXA27x_SSP3_BASE + SSDR,
  124. .drcmr = &DRCMR(67),
  125. .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
  126. DCMD_BURST16 | DCMD_WIDTH4,
  127. };
  128. static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_stereo_in = {
  129. .name = "SSP3 PCM Stereo in",
  130. .dev_addr = PXA27x_SSP3_BASE + SSDR,
  131. .drcmr = &DRCMR(66),
  132. .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
  133. DCMD_BURST16 | DCMD_WIDTH4,
  134. };
  135. static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_mono_out = {
  136. .name = "SSP4 PCM Mono out",
  137. .dev_addr = PXA3xx_SSP4_BASE + SSDR,
  138. .drcmr = &DRCMR(67),
  139. .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
  140. DCMD_BURST16 | DCMD_WIDTH2,
  141. };
  142. static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_mono_in = {
  143. .name = "SSP4 PCM Mono in",
  144. .dev_addr = PXA3xx_SSP4_BASE + SSDR,
  145. .drcmr = &DRCMR(66),
  146. .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
  147. DCMD_BURST16 | DCMD_WIDTH2,
  148. };
  149. static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_stereo_out = {
  150. .name = "SSP4 PCM Stereo out",
  151. .dev_addr = PXA3xx_SSP4_BASE + SSDR,
  152. .drcmr = &DRCMR(67),
  153. .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
  154. DCMD_BURST16 | DCMD_WIDTH4,
  155. };
  156. static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_stereo_in = {
  157. .name = "SSP4 PCM Stereo in",
  158. .dev_addr = PXA3xx_SSP4_BASE + SSDR,
  159. .drcmr = &DRCMR(66),
  160. .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
  161. DCMD_BURST16 | DCMD_WIDTH4,
  162. };
  163. static void dump_registers(struct ssp_device *ssp)
  164. {
  165. dev_dbg(&ssp->pdev->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n",
  166. ssp_read_reg(ssp, SSCR0), ssp_read_reg(ssp, SSCR1),
  167. ssp_read_reg(ssp, SSTO));
  168. dev_dbg(&ssp->pdev->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n",
  169. ssp_read_reg(ssp, SSPSP), ssp_read_reg(ssp, SSSR),
  170. ssp_read_reg(ssp, SSACD));
  171. }
  172. static struct pxa2xx_pcm_dma_params *ssp_dma_params[4][4] = {
  173. {
  174. &pxa_ssp1_pcm_mono_out, &pxa_ssp1_pcm_mono_in,
  175. &pxa_ssp1_pcm_stereo_out, &pxa_ssp1_pcm_stereo_in,
  176. },
  177. {
  178. &pxa_ssp2_pcm_mono_out, &pxa_ssp2_pcm_mono_in,
  179. &pxa_ssp2_pcm_stereo_out, &pxa_ssp2_pcm_stereo_in,
  180. },
  181. {
  182. &pxa_ssp3_pcm_mono_out, &pxa_ssp3_pcm_mono_in,
  183. &pxa_ssp3_pcm_stereo_out, &pxa_ssp3_pcm_stereo_in,
  184. },
  185. {
  186. &pxa_ssp4_pcm_mono_out, &pxa_ssp4_pcm_mono_in,
  187. &pxa_ssp4_pcm_stereo_out, &pxa_ssp4_pcm_stereo_in,
  188. },
  189. };
  190. static int pxa_ssp_startup(struct snd_pcm_substream *substream,
  191. struct snd_soc_dai *dai)
  192. {
  193. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  194. struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
  195. struct ssp_priv *priv = cpu_dai->private_data;
  196. int ret = 0;
  197. if (!cpu_dai->active) {
  198. priv->dev.port = cpu_dai->id + 1;
  199. priv->dev.irq = NO_IRQ;
  200. clk_enable(priv->dev.ssp->clk);
  201. ssp_disable(&priv->dev);
  202. }
  203. return ret;
  204. }
  205. static void pxa_ssp_shutdown(struct snd_pcm_substream *substream,
  206. struct snd_soc_dai *dai)
  207. {
  208. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  209. struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
  210. struct ssp_priv *priv = cpu_dai->private_data;
  211. if (!cpu_dai->active) {
  212. ssp_disable(&priv->dev);
  213. clk_disable(priv->dev.ssp->clk);
  214. }
  215. }
  216. #ifdef CONFIG_PM
  217. static int pxa_ssp_suspend(struct snd_soc_dai *cpu_dai)
  218. {
  219. struct ssp_priv *priv = cpu_dai->private_data;
  220. if (!cpu_dai->active)
  221. return 0;
  222. ssp_save_state(&priv->dev, &priv->state);
  223. clk_disable(priv->dev.ssp->clk);
  224. return 0;
  225. }
  226. static int pxa_ssp_resume(struct snd_soc_dai *cpu_dai)
  227. {
  228. struct ssp_priv *priv = cpu_dai->private_data;
  229. if (!cpu_dai->active)
  230. return 0;
  231. clk_enable(priv->dev.ssp->clk);
  232. ssp_restore_state(&priv->dev, &priv->state);
  233. ssp_enable(&priv->dev);
  234. return 0;
  235. }
  236. #else
  237. #define pxa_ssp_suspend NULL
  238. #define pxa_ssp_resume NULL
  239. #endif
  240. /**
  241. * ssp_set_clkdiv - set SSP clock divider
  242. * @div: serial clock rate divider
  243. */
  244. static void ssp_set_scr(struct ssp_dev *dev, u32 div)
  245. {
  246. struct ssp_device *ssp = dev->ssp;
  247. u32 sscr0 = ssp_read_reg(dev->ssp, SSCR0) & ~SSCR0_SCR;
  248. ssp_write_reg(ssp, SSCR0, (sscr0 | SSCR0_SerClkDiv(div)));
  249. }
  250. /*
  251. * Set the SSP ports SYSCLK.
  252. */
  253. static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
  254. int clk_id, unsigned int freq, int dir)
  255. {
  256. struct ssp_priv *priv = cpu_dai->private_data;
  257. struct ssp_device *ssp = priv->dev.ssp;
  258. int val;
  259. u32 sscr0 = ssp_read_reg(ssp, SSCR0) &
  260. ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
  261. dev_dbg(&ssp->pdev->dev,
  262. "pxa_ssp_set_dai_sysclk id: %d, clk_id %d, freq %d\n",
  263. cpu_dai->id, clk_id, freq);
  264. switch (clk_id) {
  265. case PXA_SSP_CLK_NET_PLL:
  266. sscr0 |= SSCR0_MOD;
  267. break;
  268. case PXA_SSP_CLK_PLL:
  269. /* Internal PLL is fixed */
  270. if (cpu_is_pxa25x())
  271. priv->sysclk = 1843200;
  272. else
  273. priv->sysclk = 13000000;
  274. break;
  275. case PXA_SSP_CLK_EXT:
  276. priv->sysclk = freq;
  277. sscr0 |= SSCR0_ECS;
  278. break;
  279. case PXA_SSP_CLK_NET:
  280. priv->sysclk = freq;
  281. sscr0 |= SSCR0_NCS | SSCR0_MOD;
  282. break;
  283. case PXA_SSP_CLK_AUDIO:
  284. priv->sysclk = 0;
  285. ssp_set_scr(&priv->dev, 1);
  286. sscr0 |= SSCR0_ACS;
  287. break;
  288. default:
  289. return -ENODEV;
  290. }
  291. /* The SSP clock must be disabled when changing SSP clock mode
  292. * on PXA2xx. On PXA3xx it must be enabled when doing so. */
  293. if (!cpu_is_pxa3xx())
  294. clk_disable(priv->dev.ssp->clk);
  295. val = ssp_read_reg(ssp, SSCR0) | sscr0;
  296. ssp_write_reg(ssp, SSCR0, val);
  297. if (!cpu_is_pxa3xx())
  298. clk_enable(priv->dev.ssp->clk);
  299. return 0;
  300. }
  301. /*
  302. * Set the SSP clock dividers.
  303. */
  304. static int pxa_ssp_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
  305. int div_id, int div)
  306. {
  307. struct ssp_priv *priv = cpu_dai->private_data;
  308. struct ssp_device *ssp = priv->dev.ssp;
  309. int val;
  310. switch (div_id) {
  311. case PXA_SSP_AUDIO_DIV_ACDS:
  312. val = (ssp_read_reg(ssp, SSACD) & ~0x7) | SSACD_ACDS(div);
  313. ssp_write_reg(ssp, SSACD, val);
  314. break;
  315. case PXA_SSP_AUDIO_DIV_SCDB:
  316. val = ssp_read_reg(ssp, SSACD);
  317. val &= ~SSACD_SCDB;
  318. #if defined(CONFIG_PXA3xx)
  319. if (cpu_is_pxa3xx())
  320. val &= ~SSACD_SCDX8;
  321. #endif
  322. switch (div) {
  323. case PXA_SSP_CLK_SCDB_1:
  324. val |= SSACD_SCDB;
  325. break;
  326. case PXA_SSP_CLK_SCDB_4:
  327. break;
  328. #if defined(CONFIG_PXA3xx)
  329. case PXA_SSP_CLK_SCDB_8:
  330. if (cpu_is_pxa3xx())
  331. val |= SSACD_SCDX8;
  332. else
  333. return -EINVAL;
  334. break;
  335. #endif
  336. default:
  337. return -EINVAL;
  338. }
  339. ssp_write_reg(ssp, SSACD, val);
  340. break;
  341. case PXA_SSP_DIV_SCR:
  342. ssp_set_scr(&priv->dev, div);
  343. break;
  344. default:
  345. return -ENODEV;
  346. }
  347. return 0;
  348. }
  349. /*
  350. * Configure the PLL frequency pxa27x and (afaik - pxa320 only)
  351. */
  352. static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai,
  353. int pll_id, unsigned int freq_in, unsigned int freq_out)
  354. {
  355. struct ssp_priv *priv = cpu_dai->private_data;
  356. struct ssp_device *ssp = priv->dev.ssp;
  357. u32 ssacd = ssp_read_reg(ssp, SSACD) & ~0x70;
  358. #if defined(CONFIG_PXA3xx)
  359. if (cpu_is_pxa3xx())
  360. ssp_write_reg(ssp, SSACDD, 0);
  361. #endif
  362. switch (freq_out) {
  363. case 5622000:
  364. break;
  365. case 11345000:
  366. ssacd |= (0x1 << 4);
  367. break;
  368. case 12235000:
  369. ssacd |= (0x2 << 4);
  370. break;
  371. case 14857000:
  372. ssacd |= (0x3 << 4);
  373. break;
  374. case 32842000:
  375. ssacd |= (0x4 << 4);
  376. break;
  377. case 48000000:
  378. ssacd |= (0x5 << 4);
  379. break;
  380. case 0:
  381. /* Disable */
  382. break;
  383. default:
  384. #ifdef CONFIG_PXA3xx
  385. /* PXA3xx has a clock ditherer which can be used to generate
  386. * a wider range of frequencies - calculate a value for it.
  387. */
  388. if (cpu_is_pxa3xx()) {
  389. u32 val;
  390. u64 tmp = 19968;
  391. tmp *= 1000000;
  392. do_div(tmp, freq_out);
  393. val = tmp;
  394. val = (val << 16) | 64;;
  395. ssp_write_reg(ssp, SSACDD, val);
  396. ssacd |= (0x6 << 4);
  397. dev_dbg(&ssp->pdev->dev,
  398. "Using SSACDD %x to supply %dHz\n",
  399. val, freq_out);
  400. break;
  401. }
  402. #endif
  403. return -EINVAL;
  404. }
  405. ssp_write_reg(ssp, SSACD, ssacd);
  406. return 0;
  407. }
  408. /*
  409. * Set the active slots in TDM/Network mode
  410. */
  411. static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
  412. unsigned int mask, int slots)
  413. {
  414. struct ssp_priv *priv = cpu_dai->private_data;
  415. struct ssp_device *ssp = priv->dev.ssp;
  416. u32 sscr0;
  417. sscr0 = ssp_read_reg(ssp, SSCR0) & ~SSCR0_SlotsPerFrm(7);
  418. /* set number of active slots */
  419. sscr0 |= SSCR0_SlotsPerFrm(slots);
  420. ssp_write_reg(ssp, SSCR0, sscr0);
  421. /* set active slot mask */
  422. ssp_write_reg(ssp, SSTSA, mask);
  423. ssp_write_reg(ssp, SSRSA, mask);
  424. return 0;
  425. }
  426. /*
  427. * Tristate the SSP DAI lines
  428. */
  429. static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai,
  430. int tristate)
  431. {
  432. struct ssp_priv *priv = cpu_dai->private_data;
  433. struct ssp_device *ssp = priv->dev.ssp;
  434. u32 sscr1;
  435. sscr1 = ssp_read_reg(ssp, SSCR1);
  436. if (tristate)
  437. sscr1 &= ~SSCR1_TTE;
  438. else
  439. sscr1 |= SSCR1_TTE;
  440. ssp_write_reg(ssp, SSCR1, sscr1);
  441. return 0;
  442. }
  443. /*
  444. * Set up the SSP DAI format.
  445. * The SSP Port must be inactive before calling this function as the
  446. * physical interface format is changed.
  447. */
  448. static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
  449. unsigned int fmt)
  450. {
  451. struct ssp_priv *priv = cpu_dai->private_data;
  452. struct ssp_device *ssp = priv->dev.ssp;
  453. u32 sscr0;
  454. u32 sscr1;
  455. u32 sspsp;
  456. /* reset port settings */
  457. sscr0 = ssp_read_reg(ssp, SSCR0) &
  458. (SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
  459. sscr1 = SSCR1_RxTresh(8) | SSCR1_TxTresh(7);
  460. sspsp = 0;
  461. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  462. case SND_SOC_DAIFMT_CBM_CFM:
  463. sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR;
  464. break;
  465. case SND_SOC_DAIFMT_CBM_CFS:
  466. sscr1 |= SSCR1_SCLKDIR;
  467. break;
  468. case SND_SOC_DAIFMT_CBS_CFS:
  469. break;
  470. default:
  471. return -EINVAL;
  472. }
  473. ssp_write_reg(ssp, SSCR0, sscr0);
  474. ssp_write_reg(ssp, SSCR1, sscr1);
  475. ssp_write_reg(ssp, SSPSP, sspsp);
  476. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  477. case SND_SOC_DAIFMT_I2S:
  478. sscr0 |= SSCR0_MOD | SSCR0_PSP;
  479. sscr1 |= SSCR1_RWOT | SSCR1_TRAIL;
  480. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  481. case SND_SOC_DAIFMT_NB_NF:
  482. sspsp |= SSPSP_FSRT;
  483. break;
  484. case SND_SOC_DAIFMT_NB_IF:
  485. sspsp |= SSPSP_SFRMP | SSPSP_FSRT;
  486. break;
  487. case SND_SOC_DAIFMT_IB_IF:
  488. sspsp |= SSPSP_SFRMP;
  489. break;
  490. default:
  491. return -EINVAL;
  492. }
  493. break;
  494. case SND_SOC_DAIFMT_DSP_A:
  495. sspsp |= SSPSP_FSRT;
  496. case SND_SOC_DAIFMT_DSP_B:
  497. sscr0 |= SSCR0_MOD | SSCR0_PSP;
  498. sscr1 |= SSCR1_TRAIL | SSCR1_RWOT;
  499. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  500. case SND_SOC_DAIFMT_NB_NF:
  501. sspsp |= SSPSP_SFRMP;
  502. break;
  503. case SND_SOC_DAIFMT_IB_IF:
  504. break;
  505. default:
  506. return -EINVAL;
  507. }
  508. break;
  509. default:
  510. return -EINVAL;
  511. }
  512. ssp_write_reg(ssp, SSCR0, sscr0);
  513. ssp_write_reg(ssp, SSCR1, sscr1);
  514. ssp_write_reg(ssp, SSPSP, sspsp);
  515. dump_registers(ssp);
  516. /* Since we are configuring the timings for the format by hand
  517. * we have to defer some things until hw_params() where we
  518. * know parameters like the sample size.
  519. */
  520. priv->dai_fmt = fmt;
  521. return 0;
  522. }
  523. /*
  524. * Set the SSP audio DMA parameters and sample size.
  525. * Can be called multiple times by oss emulation.
  526. */
  527. static int pxa_ssp_hw_params(struct snd_pcm_substream *substream,
  528. struct snd_pcm_hw_params *params,
  529. struct snd_soc_dai *dai)
  530. {
  531. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  532. struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
  533. struct ssp_priv *priv = cpu_dai->private_data;
  534. struct ssp_device *ssp = priv->dev.ssp;
  535. int dma = 0, chn = params_channels(params);
  536. u32 sscr0;
  537. u32 sspsp;
  538. int width = snd_pcm_format_physical_width(params_format(params));
  539. /* select correct DMA params */
  540. if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
  541. dma = 1; /* capture DMA offset is 1,3 */
  542. if (chn == 2)
  543. dma += 2; /* stereo DMA offset is 2, mono is 0 */
  544. cpu_dai->dma_data = ssp_dma_params[cpu_dai->id][dma];
  545. dev_dbg(&ssp->pdev->dev, "pxa_ssp_hw_params: dma %d\n", dma);
  546. /* we can only change the settings if the port is not in use */
  547. if (ssp_read_reg(ssp, SSCR0) & SSCR0_SSE)
  548. return 0;
  549. /* clear selected SSP bits */
  550. sscr0 = ssp_read_reg(ssp, SSCR0) & ~(SSCR0_DSS | SSCR0_EDSS);
  551. ssp_write_reg(ssp, SSCR0, sscr0);
  552. /* bit size */
  553. sscr0 = ssp_read_reg(ssp, SSCR0);
  554. switch (params_format(params)) {
  555. case SNDRV_PCM_FORMAT_S16_LE:
  556. #ifdef CONFIG_PXA3xx
  557. if (cpu_is_pxa3xx())
  558. sscr0 |= SSCR0_FPCKE;
  559. #endif
  560. sscr0 |= SSCR0_DataSize(16);
  561. /* use network mode (2 slots) for 16 bit stereo */
  562. break;
  563. case SNDRV_PCM_FORMAT_S24_LE:
  564. sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(8));
  565. /* we must be in network mode (2 slots) for 24 bit stereo */
  566. break;
  567. case SNDRV_PCM_FORMAT_S32_LE:
  568. sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(16));
  569. /* we must be in network mode (2 slots) for 32 bit stereo */
  570. break;
  571. }
  572. ssp_write_reg(ssp, SSCR0, sscr0);
  573. switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  574. case SND_SOC_DAIFMT_I2S:
  575. /* Cleared when the DAI format is set */
  576. sspsp = ssp_read_reg(ssp, SSPSP) | SSPSP_SFRMWDTH(width);
  577. ssp_write_reg(ssp, SSPSP, sspsp);
  578. break;
  579. default:
  580. break;
  581. }
  582. /* We always use a network mode so we always require TDM slots
  583. * - complain loudly and fail if they've not been set up yet.
  584. */
  585. if (!(ssp_read_reg(ssp, SSTSA) & 0xf)) {
  586. dev_err(&ssp->pdev->dev, "No TDM timeslot configured\n");
  587. return -EINVAL;
  588. }
  589. dump_registers(ssp);
  590. return 0;
  591. }
  592. static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd,
  593. struct snd_soc_dai *dai)
  594. {
  595. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  596. struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
  597. int ret = 0;
  598. struct ssp_priv *priv = cpu_dai->private_data;
  599. struct ssp_device *ssp = priv->dev.ssp;
  600. int val;
  601. switch (cmd) {
  602. case SNDRV_PCM_TRIGGER_RESUME:
  603. ssp_enable(&priv->dev);
  604. break;
  605. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  606. val = ssp_read_reg(ssp, SSCR1);
  607. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  608. val |= SSCR1_TSRE;
  609. else
  610. val |= SSCR1_RSRE;
  611. ssp_write_reg(ssp, SSCR1, val);
  612. val = ssp_read_reg(ssp, SSSR);
  613. ssp_write_reg(ssp, SSSR, val);
  614. break;
  615. case SNDRV_PCM_TRIGGER_START:
  616. val = ssp_read_reg(ssp, SSCR1);
  617. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  618. val |= SSCR1_TSRE;
  619. else
  620. val |= SSCR1_RSRE;
  621. ssp_write_reg(ssp, SSCR1, val);
  622. ssp_enable(&priv->dev);
  623. break;
  624. case SNDRV_PCM_TRIGGER_STOP:
  625. val = ssp_read_reg(ssp, SSCR1);
  626. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  627. val &= ~SSCR1_TSRE;
  628. else
  629. val &= ~SSCR1_RSRE;
  630. ssp_write_reg(ssp, SSCR1, val);
  631. break;
  632. case SNDRV_PCM_TRIGGER_SUSPEND:
  633. ssp_disable(&priv->dev);
  634. break;
  635. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  636. val = ssp_read_reg(ssp, SSCR1);
  637. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  638. val &= ~SSCR1_TSRE;
  639. else
  640. val &= ~SSCR1_RSRE;
  641. ssp_write_reg(ssp, SSCR1, val);
  642. break;
  643. default:
  644. ret = -EINVAL;
  645. }
  646. dump_registers(ssp);
  647. return ret;
  648. }
  649. static int pxa_ssp_probe(struct platform_device *pdev,
  650. struct snd_soc_dai *dai)
  651. {
  652. struct ssp_priv *priv;
  653. int ret;
  654. priv = kzalloc(sizeof(struct ssp_priv), GFP_KERNEL);
  655. if (!priv)
  656. return -ENOMEM;
  657. priv->dev.ssp = ssp_request(dai->id + 1, "SoC audio");
  658. if (priv->dev.ssp == NULL) {
  659. ret = -ENODEV;
  660. goto err_priv;
  661. }
  662. dai->private_data = priv;
  663. return 0;
  664. err_priv:
  665. kfree(priv);
  666. return ret;
  667. }
  668. static void pxa_ssp_remove(struct platform_device *pdev,
  669. struct snd_soc_dai *dai)
  670. {
  671. struct ssp_priv *priv = dai->private_data;
  672. ssp_free(priv->dev.ssp);
  673. }
  674. #define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
  675. SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
  676. SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \
  677. SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
  678. #define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  679. SNDRV_PCM_FMTBIT_S24_LE | \
  680. SNDRV_PCM_FMTBIT_S32_LE)
  681. struct snd_soc_dai pxa_ssp_dai[] = {
  682. {
  683. .name = "pxa2xx-ssp1",
  684. .id = 0,
  685. .probe = pxa_ssp_probe,
  686. .remove = pxa_ssp_remove,
  687. .suspend = pxa_ssp_suspend,
  688. .resume = pxa_ssp_resume,
  689. .playback = {
  690. .channels_min = 1,
  691. .channels_max = 2,
  692. .rates = PXA_SSP_RATES,
  693. .formats = PXA_SSP_FORMATS,
  694. },
  695. .capture = {
  696. .channels_min = 1,
  697. .channels_max = 2,
  698. .rates = PXA_SSP_RATES,
  699. .formats = PXA_SSP_FORMATS,
  700. },
  701. .ops = {
  702. .startup = pxa_ssp_startup,
  703. .shutdown = pxa_ssp_shutdown,
  704. .trigger = pxa_ssp_trigger,
  705. .hw_params = pxa_ssp_hw_params,
  706. .set_sysclk = pxa_ssp_set_dai_sysclk,
  707. .set_clkdiv = pxa_ssp_set_dai_clkdiv,
  708. .set_pll = pxa_ssp_set_dai_pll,
  709. .set_fmt = pxa_ssp_set_dai_fmt,
  710. .set_tdm_slot = pxa_ssp_set_dai_tdm_slot,
  711. .set_tristate = pxa_ssp_set_dai_tristate,
  712. },
  713. },
  714. { .name = "pxa2xx-ssp2",
  715. .id = 1,
  716. .probe = pxa_ssp_probe,
  717. .remove = pxa_ssp_remove,
  718. .suspend = pxa_ssp_suspend,
  719. .resume = pxa_ssp_resume,
  720. .playback = {
  721. .channels_min = 1,
  722. .channels_max = 2,
  723. .rates = PXA_SSP_RATES,
  724. .formats = PXA_SSP_FORMATS,
  725. },
  726. .capture = {
  727. .channels_min = 1,
  728. .channels_max = 2,
  729. .rates = PXA_SSP_RATES,
  730. .formats = PXA_SSP_FORMATS,
  731. },
  732. .ops = {
  733. .startup = pxa_ssp_startup,
  734. .shutdown = pxa_ssp_shutdown,
  735. .trigger = pxa_ssp_trigger,
  736. .hw_params = pxa_ssp_hw_params,
  737. .set_sysclk = pxa_ssp_set_dai_sysclk,
  738. .set_clkdiv = pxa_ssp_set_dai_clkdiv,
  739. .set_pll = pxa_ssp_set_dai_pll,
  740. .set_fmt = pxa_ssp_set_dai_fmt,
  741. .set_tdm_slot = pxa_ssp_set_dai_tdm_slot,
  742. .set_tristate = pxa_ssp_set_dai_tristate,
  743. },
  744. },
  745. {
  746. .name = "pxa2xx-ssp3",
  747. .id = 2,
  748. .probe = pxa_ssp_probe,
  749. .remove = pxa_ssp_remove,
  750. .suspend = pxa_ssp_suspend,
  751. .resume = pxa_ssp_resume,
  752. .playback = {
  753. .channels_min = 1,
  754. .channels_max = 2,
  755. .rates = PXA_SSP_RATES,
  756. .formats = PXA_SSP_FORMATS,
  757. },
  758. .capture = {
  759. .channels_min = 1,
  760. .channels_max = 2,
  761. .rates = PXA_SSP_RATES,
  762. .formats = PXA_SSP_FORMATS,
  763. },
  764. .ops = {
  765. .startup = pxa_ssp_startup,
  766. .shutdown = pxa_ssp_shutdown,
  767. .trigger = pxa_ssp_trigger,
  768. .hw_params = pxa_ssp_hw_params,
  769. .set_sysclk = pxa_ssp_set_dai_sysclk,
  770. .set_clkdiv = pxa_ssp_set_dai_clkdiv,
  771. .set_pll = pxa_ssp_set_dai_pll,
  772. .set_fmt = pxa_ssp_set_dai_fmt,
  773. .set_tdm_slot = pxa_ssp_set_dai_tdm_slot,
  774. .set_tristate = pxa_ssp_set_dai_tristate,
  775. },
  776. },
  777. {
  778. .name = "pxa2xx-ssp4",
  779. .id = 3,
  780. .probe = pxa_ssp_probe,
  781. .remove = pxa_ssp_remove,
  782. .suspend = pxa_ssp_suspend,
  783. .resume = pxa_ssp_resume,
  784. .playback = {
  785. .channels_min = 1,
  786. .channels_max = 2,
  787. .rates = PXA_SSP_RATES,
  788. .formats = PXA_SSP_FORMATS,
  789. },
  790. .capture = {
  791. .channels_min = 1,
  792. .channels_max = 2,
  793. .rates = PXA_SSP_RATES,
  794. .formats = PXA_SSP_FORMATS,
  795. },
  796. .ops = {
  797. .startup = pxa_ssp_startup,
  798. .shutdown = pxa_ssp_shutdown,
  799. .trigger = pxa_ssp_trigger,
  800. .hw_params = pxa_ssp_hw_params,
  801. .set_sysclk = pxa_ssp_set_dai_sysclk,
  802. .set_clkdiv = pxa_ssp_set_dai_clkdiv,
  803. .set_pll = pxa_ssp_set_dai_pll,
  804. .set_fmt = pxa_ssp_set_dai_fmt,
  805. .set_tdm_slot = pxa_ssp_set_dai_tdm_slot,
  806. .set_tristate = pxa_ssp_set_dai_tristate,
  807. },
  808. },
  809. };
  810. EXPORT_SYMBOL_GPL(pxa_ssp_dai);
  811. static int __init pxa_ssp_init(void)
  812. {
  813. return snd_soc_register_dais(pxa_ssp_dai, ARRAY_SIZE(pxa_ssp_dai));
  814. }
  815. module_init(pxa_ssp_init);
  816. static void __exit pxa_ssp_exit(void)
  817. {
  818. snd_soc_unregister_dais(pxa_ssp_dai, ARRAY_SIZE(pxa_ssp_dai));
  819. }
  820. module_exit(pxa_ssp_exit);
  821. /* Module information */
  822. MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
  823. MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface");
  824. MODULE_LICENSE("GPL");