omap_hwmod_3xxx_data.c 32 KB

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  1. /*
  2. * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
  3. *
  4. * Copyright (C) 2009-2010 Nokia Corporation
  5. * Paul Walmsley
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. * The data in this file should be completely autogeneratable from
  12. * the TI hardware database or other technical documentation.
  13. *
  14. * XXX these should be marked initdata for multi-OMAP kernels
  15. */
  16. #include <plat/omap_hwmod.h>
  17. #include <mach/irqs.h>
  18. #include <plat/cpu.h>
  19. #include <plat/dma.h>
  20. #include <plat/serial.h>
  21. #include <plat/l4_3xxx.h>
  22. #include <plat/i2c.h>
  23. #include <plat/gpio.h>
  24. #include "omap_hwmod_common_data.h"
  25. #include "prm-regbits-34xx.h"
  26. #include "cm-regbits-34xx.h"
  27. /*
  28. * OMAP3xxx hardware module integration data
  29. *
  30. * ALl of the data in this section should be autogeneratable from the
  31. * TI hardware database or other technical documentation. Data that
  32. * is driver-specific or driver-kernel integration-specific belongs
  33. * elsewhere.
  34. */
  35. static struct omap_hwmod omap3xxx_mpu_hwmod;
  36. static struct omap_hwmod omap3xxx_iva_hwmod;
  37. static struct omap_hwmod omap3xxx_l3_main_hwmod;
  38. static struct omap_hwmod omap3xxx_l4_core_hwmod;
  39. static struct omap_hwmod omap3xxx_l4_per_hwmod;
  40. static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
  41. static struct omap_hwmod omap3xxx_i2c1_hwmod;
  42. static struct omap_hwmod omap3xxx_i2c2_hwmod;
  43. static struct omap_hwmod omap3xxx_i2c3_hwmod;
  44. static struct omap_hwmod omap3xxx_gpio1_hwmod;
  45. static struct omap_hwmod omap3xxx_gpio2_hwmod;
  46. static struct omap_hwmod omap3xxx_gpio3_hwmod;
  47. static struct omap_hwmod omap3xxx_gpio4_hwmod;
  48. static struct omap_hwmod omap3xxx_gpio5_hwmod;
  49. static struct omap_hwmod omap3xxx_gpio6_hwmod;
  50. static struct omap_hwmod omap3xxx_dma_system_hwmod;
  51. /* L3 -> L4_CORE interface */
  52. static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
  53. .master = &omap3xxx_l3_main_hwmod,
  54. .slave = &omap3xxx_l4_core_hwmod,
  55. .user = OCP_USER_MPU | OCP_USER_SDMA,
  56. };
  57. /* L3 -> L4_PER interface */
  58. static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
  59. .master = &omap3xxx_l3_main_hwmod,
  60. .slave = &omap3xxx_l4_per_hwmod,
  61. .user = OCP_USER_MPU | OCP_USER_SDMA,
  62. };
  63. /* MPU -> L3 interface */
  64. static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
  65. .master = &omap3xxx_mpu_hwmod,
  66. .slave = &omap3xxx_l3_main_hwmod,
  67. .user = OCP_USER_MPU,
  68. };
  69. /* Slave interfaces on the L3 interconnect */
  70. static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
  71. &omap3xxx_mpu__l3_main,
  72. };
  73. /* Master interfaces on the L3 interconnect */
  74. static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
  75. &omap3xxx_l3_main__l4_core,
  76. &omap3xxx_l3_main__l4_per,
  77. };
  78. /* L3 */
  79. static struct omap_hwmod omap3xxx_l3_main_hwmod = {
  80. .name = "l3_main",
  81. .class = &l3_hwmod_class,
  82. .masters = omap3xxx_l3_main_masters,
  83. .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters),
  84. .slaves = omap3xxx_l3_main_slaves,
  85. .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_main_slaves),
  86. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  87. .flags = HWMOD_NO_IDLEST,
  88. };
  89. static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
  90. static struct omap_hwmod omap3xxx_uart1_hwmod;
  91. static struct omap_hwmod omap3xxx_uart2_hwmod;
  92. static struct omap_hwmod omap3xxx_uart3_hwmod;
  93. static struct omap_hwmod omap3xxx_uart4_hwmod;
  94. /* L4_CORE -> L4_WKUP interface */
  95. static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
  96. .master = &omap3xxx_l4_core_hwmod,
  97. .slave = &omap3xxx_l4_wkup_hwmod,
  98. .user = OCP_USER_MPU | OCP_USER_SDMA,
  99. };
  100. /* L4 CORE -> UART1 interface */
  101. static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
  102. {
  103. .pa_start = OMAP3_UART1_BASE,
  104. .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
  105. .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
  106. },
  107. };
  108. static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
  109. .master = &omap3xxx_l4_core_hwmod,
  110. .slave = &omap3xxx_uart1_hwmod,
  111. .clk = "uart1_ick",
  112. .addr = omap3xxx_uart1_addr_space,
  113. .addr_cnt = ARRAY_SIZE(omap3xxx_uart1_addr_space),
  114. .user = OCP_USER_MPU | OCP_USER_SDMA,
  115. };
  116. /* L4 CORE -> UART2 interface */
  117. static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
  118. {
  119. .pa_start = OMAP3_UART2_BASE,
  120. .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
  121. .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
  122. },
  123. };
  124. static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
  125. .master = &omap3xxx_l4_core_hwmod,
  126. .slave = &omap3xxx_uart2_hwmod,
  127. .clk = "uart2_ick",
  128. .addr = omap3xxx_uart2_addr_space,
  129. .addr_cnt = ARRAY_SIZE(omap3xxx_uart2_addr_space),
  130. .user = OCP_USER_MPU | OCP_USER_SDMA,
  131. };
  132. /* L4 PER -> UART3 interface */
  133. static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
  134. {
  135. .pa_start = OMAP3_UART3_BASE,
  136. .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
  137. .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
  138. },
  139. };
  140. static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
  141. .master = &omap3xxx_l4_per_hwmod,
  142. .slave = &omap3xxx_uart3_hwmod,
  143. .clk = "uart3_ick",
  144. .addr = omap3xxx_uart3_addr_space,
  145. .addr_cnt = ARRAY_SIZE(omap3xxx_uart3_addr_space),
  146. .user = OCP_USER_MPU | OCP_USER_SDMA,
  147. };
  148. /* L4 PER -> UART4 interface */
  149. static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
  150. {
  151. .pa_start = OMAP3_UART4_BASE,
  152. .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
  153. .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
  154. },
  155. };
  156. static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
  157. .master = &omap3xxx_l4_per_hwmod,
  158. .slave = &omap3xxx_uart4_hwmod,
  159. .clk = "uart4_ick",
  160. .addr = omap3xxx_uart4_addr_space,
  161. .addr_cnt = ARRAY_SIZE(omap3xxx_uart4_addr_space),
  162. .user = OCP_USER_MPU | OCP_USER_SDMA,
  163. };
  164. /* I2C IP block address space length (in bytes) */
  165. #define OMAP2_I2C_AS_LEN 128
  166. /* L4 CORE -> I2C1 interface */
  167. static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space[] = {
  168. {
  169. .pa_start = 0x48070000,
  170. .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
  171. .flags = ADDR_TYPE_RT,
  172. },
  173. };
  174. static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
  175. .master = &omap3xxx_l4_core_hwmod,
  176. .slave = &omap3xxx_i2c1_hwmod,
  177. .clk = "i2c1_ick",
  178. .addr = omap3xxx_i2c1_addr_space,
  179. .addr_cnt = ARRAY_SIZE(omap3xxx_i2c1_addr_space),
  180. .fw = {
  181. .omap2 = {
  182. .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
  183. .l4_prot_group = 7,
  184. .flags = OMAP_FIREWALL_L4,
  185. }
  186. },
  187. .user = OCP_USER_MPU | OCP_USER_SDMA,
  188. };
  189. /* L4 CORE -> I2C2 interface */
  190. static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space[] = {
  191. {
  192. .pa_start = 0x48072000,
  193. .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
  194. .flags = ADDR_TYPE_RT,
  195. },
  196. };
  197. static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
  198. .master = &omap3xxx_l4_core_hwmod,
  199. .slave = &omap3xxx_i2c2_hwmod,
  200. .clk = "i2c2_ick",
  201. .addr = omap3xxx_i2c2_addr_space,
  202. .addr_cnt = ARRAY_SIZE(omap3xxx_i2c2_addr_space),
  203. .fw = {
  204. .omap2 = {
  205. .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
  206. .l4_prot_group = 7,
  207. .flags = OMAP_FIREWALL_L4,
  208. }
  209. },
  210. .user = OCP_USER_MPU | OCP_USER_SDMA,
  211. };
  212. /* L4 CORE -> I2C3 interface */
  213. static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
  214. {
  215. .pa_start = 0x48060000,
  216. .pa_end = 0x48060000 + OMAP2_I2C_AS_LEN - 1,
  217. .flags = ADDR_TYPE_RT,
  218. },
  219. };
  220. static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
  221. .master = &omap3xxx_l4_core_hwmod,
  222. .slave = &omap3xxx_i2c3_hwmod,
  223. .clk = "i2c3_ick",
  224. .addr = omap3xxx_i2c3_addr_space,
  225. .addr_cnt = ARRAY_SIZE(omap3xxx_i2c3_addr_space),
  226. .fw = {
  227. .omap2 = {
  228. .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
  229. .l4_prot_group = 7,
  230. .flags = OMAP_FIREWALL_L4,
  231. }
  232. },
  233. .user = OCP_USER_MPU | OCP_USER_SDMA,
  234. };
  235. /* Slave interfaces on the L4_CORE interconnect */
  236. static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
  237. &omap3xxx_l3_main__l4_core,
  238. };
  239. /* Master interfaces on the L4_CORE interconnect */
  240. static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = {
  241. &omap3xxx_l4_core__l4_wkup,
  242. &omap3_l4_core__uart1,
  243. &omap3_l4_core__uart2,
  244. &omap3_l4_core__i2c1,
  245. &omap3_l4_core__i2c2,
  246. &omap3_l4_core__i2c3,
  247. };
  248. /* L4 CORE */
  249. static struct omap_hwmod omap3xxx_l4_core_hwmod = {
  250. .name = "l4_core",
  251. .class = &l4_hwmod_class,
  252. .masters = omap3xxx_l4_core_masters,
  253. .masters_cnt = ARRAY_SIZE(omap3xxx_l4_core_masters),
  254. .slaves = omap3xxx_l4_core_slaves,
  255. .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves),
  256. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  257. .flags = HWMOD_NO_IDLEST,
  258. };
  259. /* Slave interfaces on the L4_PER interconnect */
  260. static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
  261. &omap3xxx_l3_main__l4_per,
  262. };
  263. /* Master interfaces on the L4_PER interconnect */
  264. static struct omap_hwmod_ocp_if *omap3xxx_l4_per_masters[] = {
  265. &omap3_l4_per__uart3,
  266. &omap3_l4_per__uart4,
  267. };
  268. /* L4 PER */
  269. static struct omap_hwmod omap3xxx_l4_per_hwmod = {
  270. .name = "l4_per",
  271. .class = &l4_hwmod_class,
  272. .masters = omap3xxx_l4_per_masters,
  273. .masters_cnt = ARRAY_SIZE(omap3xxx_l4_per_masters),
  274. .slaves = omap3xxx_l4_per_slaves,
  275. .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves),
  276. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  277. .flags = HWMOD_NO_IDLEST,
  278. };
  279. /* Slave interfaces on the L4_WKUP interconnect */
  280. static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
  281. &omap3xxx_l4_core__l4_wkup,
  282. };
  283. /* Master interfaces on the L4_WKUP interconnect */
  284. static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_masters[] = {
  285. };
  286. /* L4 WKUP */
  287. static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
  288. .name = "l4_wkup",
  289. .class = &l4_hwmod_class,
  290. .masters = omap3xxx_l4_wkup_masters,
  291. .masters_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_masters),
  292. .slaves = omap3xxx_l4_wkup_slaves,
  293. .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
  294. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  295. .flags = HWMOD_NO_IDLEST,
  296. };
  297. /* Master interfaces on the MPU device */
  298. static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
  299. &omap3xxx_mpu__l3_main,
  300. };
  301. /* MPU */
  302. static struct omap_hwmod omap3xxx_mpu_hwmod = {
  303. .name = "mpu",
  304. .class = &mpu_hwmod_class,
  305. .main_clk = "arm_fck",
  306. .masters = omap3xxx_mpu_masters,
  307. .masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters),
  308. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  309. };
  310. /*
  311. * IVA2_2 interface data
  312. */
  313. /* IVA2 <- L3 interface */
  314. static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
  315. .master = &omap3xxx_l3_main_hwmod,
  316. .slave = &omap3xxx_iva_hwmod,
  317. .clk = "iva2_ck",
  318. .user = OCP_USER_MPU | OCP_USER_SDMA,
  319. };
  320. static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
  321. &omap3xxx_l3__iva,
  322. };
  323. /*
  324. * IVA2 (IVA2)
  325. */
  326. static struct omap_hwmod omap3xxx_iva_hwmod = {
  327. .name = "iva",
  328. .class = &iva_hwmod_class,
  329. .masters = omap3xxx_iva_masters,
  330. .masters_cnt = ARRAY_SIZE(omap3xxx_iva_masters),
  331. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
  332. };
  333. /* l4_wkup -> wd_timer2 */
  334. static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
  335. {
  336. .pa_start = 0x48314000,
  337. .pa_end = 0x4831407f,
  338. .flags = ADDR_TYPE_RT
  339. },
  340. };
  341. static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
  342. .master = &omap3xxx_l4_wkup_hwmod,
  343. .slave = &omap3xxx_wd_timer2_hwmod,
  344. .clk = "wdt2_ick",
  345. .addr = omap3xxx_wd_timer2_addrs,
  346. .addr_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_addrs),
  347. .user = OCP_USER_MPU | OCP_USER_SDMA,
  348. };
  349. /*
  350. * 'wd_timer' class
  351. * 32-bit watchdog upward counter that generates a pulse on the reset pin on
  352. * overflow condition
  353. */
  354. static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
  355. .rev_offs = 0x0000,
  356. .sysc_offs = 0x0010,
  357. .syss_offs = 0x0014,
  358. .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
  359. SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
  360. SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY),
  361. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  362. .sysc_fields = &omap_hwmod_sysc_type1,
  363. };
  364. /* I2C common */
  365. static struct omap_hwmod_class_sysconfig i2c_sysc = {
  366. .rev_offs = 0x00,
  367. .sysc_offs = 0x20,
  368. .syss_offs = 0x10,
  369. .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
  370. SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
  371. SYSC_HAS_AUTOIDLE),
  372. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  373. .sysc_fields = &omap_hwmod_sysc_type1,
  374. };
  375. static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
  376. .name = "wd_timer",
  377. .sysc = &omap3xxx_wd_timer_sysc,
  378. };
  379. /* wd_timer2 */
  380. static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
  381. &omap3xxx_l4_wkup__wd_timer2,
  382. };
  383. static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
  384. .name = "wd_timer2",
  385. .class = &omap3xxx_wd_timer_hwmod_class,
  386. .main_clk = "wdt2_fck",
  387. .prcm = {
  388. .omap2 = {
  389. .prcm_reg_id = 1,
  390. .module_bit = OMAP3430_EN_WDT2_SHIFT,
  391. .module_offs = WKUP_MOD,
  392. .idlest_reg_id = 1,
  393. .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
  394. },
  395. },
  396. .slaves = omap3xxx_wd_timer2_slaves,
  397. .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
  398. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  399. };
  400. /* UART common */
  401. static struct omap_hwmod_class_sysconfig uart_sysc = {
  402. .rev_offs = 0x50,
  403. .sysc_offs = 0x54,
  404. .syss_offs = 0x58,
  405. .sysc_flags = (SYSC_HAS_SIDLEMODE |
  406. SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
  407. SYSC_HAS_AUTOIDLE),
  408. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  409. .sysc_fields = &omap_hwmod_sysc_type1,
  410. };
  411. static struct omap_hwmod_class uart_class = {
  412. .name = "uart",
  413. .sysc = &uart_sysc,
  414. };
  415. /* UART1 */
  416. static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
  417. { .irq = INT_24XX_UART1_IRQ, },
  418. };
  419. static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
  420. { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
  421. { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
  422. };
  423. static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
  424. &omap3_l4_core__uart1,
  425. };
  426. static struct omap_hwmod omap3xxx_uart1_hwmod = {
  427. .name = "uart1",
  428. .mpu_irqs = uart1_mpu_irqs,
  429. .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs),
  430. .sdma_reqs = uart1_sdma_reqs,
  431. .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
  432. .main_clk = "uart1_fck",
  433. .prcm = {
  434. .omap2 = {
  435. .module_offs = CORE_MOD,
  436. .prcm_reg_id = 1,
  437. .module_bit = OMAP3430_EN_UART1_SHIFT,
  438. .idlest_reg_id = 1,
  439. .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
  440. },
  441. },
  442. .slaves = omap3xxx_uart1_slaves,
  443. .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves),
  444. .class = &uart_class,
  445. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  446. };
  447. /* UART2 */
  448. static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
  449. { .irq = INT_24XX_UART2_IRQ, },
  450. };
  451. static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
  452. { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
  453. { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
  454. };
  455. static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
  456. &omap3_l4_core__uart2,
  457. };
  458. static struct omap_hwmod omap3xxx_uart2_hwmod = {
  459. .name = "uart2",
  460. .mpu_irqs = uart2_mpu_irqs,
  461. .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs),
  462. .sdma_reqs = uart2_sdma_reqs,
  463. .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
  464. .main_clk = "uart2_fck",
  465. .prcm = {
  466. .omap2 = {
  467. .module_offs = CORE_MOD,
  468. .prcm_reg_id = 1,
  469. .module_bit = OMAP3430_EN_UART2_SHIFT,
  470. .idlest_reg_id = 1,
  471. .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
  472. },
  473. },
  474. .slaves = omap3xxx_uart2_slaves,
  475. .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves),
  476. .class = &uart_class,
  477. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  478. };
  479. /* UART3 */
  480. static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
  481. { .irq = INT_24XX_UART3_IRQ, },
  482. };
  483. static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
  484. { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
  485. { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
  486. };
  487. static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
  488. &omap3_l4_per__uart3,
  489. };
  490. static struct omap_hwmod omap3xxx_uart3_hwmod = {
  491. .name = "uart3",
  492. .mpu_irqs = uart3_mpu_irqs,
  493. .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs),
  494. .sdma_reqs = uart3_sdma_reqs,
  495. .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
  496. .main_clk = "uart3_fck",
  497. .prcm = {
  498. .omap2 = {
  499. .module_offs = OMAP3430_PER_MOD,
  500. .prcm_reg_id = 1,
  501. .module_bit = OMAP3430_EN_UART3_SHIFT,
  502. .idlest_reg_id = 1,
  503. .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
  504. },
  505. },
  506. .slaves = omap3xxx_uart3_slaves,
  507. .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves),
  508. .class = &uart_class,
  509. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  510. };
  511. /* UART4 */
  512. static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
  513. { .irq = INT_36XX_UART4_IRQ, },
  514. };
  515. static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
  516. { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
  517. { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
  518. };
  519. static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
  520. &omap3_l4_per__uart4,
  521. };
  522. static struct omap_hwmod omap3xxx_uart4_hwmod = {
  523. .name = "uart4",
  524. .mpu_irqs = uart4_mpu_irqs,
  525. .mpu_irqs_cnt = ARRAY_SIZE(uart4_mpu_irqs),
  526. .sdma_reqs = uart4_sdma_reqs,
  527. .sdma_reqs_cnt = ARRAY_SIZE(uart4_sdma_reqs),
  528. .main_clk = "uart4_fck",
  529. .prcm = {
  530. .omap2 = {
  531. .module_offs = OMAP3430_PER_MOD,
  532. .prcm_reg_id = 1,
  533. .module_bit = OMAP3630_EN_UART4_SHIFT,
  534. .idlest_reg_id = 1,
  535. .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
  536. },
  537. },
  538. .slaves = omap3xxx_uart4_slaves,
  539. .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves),
  540. .class = &uart_class,
  541. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
  542. };
  543. static struct omap_hwmod_class i2c_class = {
  544. .name = "i2c",
  545. .sysc = &i2c_sysc,
  546. };
  547. /* I2C1 */
  548. static struct omap_i2c_dev_attr i2c1_dev_attr = {
  549. .fifo_depth = 8, /* bytes */
  550. };
  551. static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
  552. { .irq = INT_24XX_I2C1_IRQ, },
  553. };
  554. static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
  555. { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
  556. { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
  557. };
  558. static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
  559. &omap3_l4_core__i2c1,
  560. };
  561. static struct omap_hwmod omap3xxx_i2c1_hwmod = {
  562. .name = "i2c1",
  563. .mpu_irqs = i2c1_mpu_irqs,
  564. .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs),
  565. .sdma_reqs = i2c1_sdma_reqs,
  566. .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
  567. .main_clk = "i2c1_fck",
  568. .prcm = {
  569. .omap2 = {
  570. .module_offs = CORE_MOD,
  571. .prcm_reg_id = 1,
  572. .module_bit = OMAP3430_EN_I2C1_SHIFT,
  573. .idlest_reg_id = 1,
  574. .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
  575. },
  576. },
  577. .slaves = omap3xxx_i2c1_slaves,
  578. .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves),
  579. .class = &i2c_class,
  580. .dev_attr = &i2c1_dev_attr,
  581. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  582. };
  583. /* I2C2 */
  584. static struct omap_i2c_dev_attr i2c2_dev_attr = {
  585. .fifo_depth = 8, /* bytes */
  586. };
  587. static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
  588. { .irq = INT_24XX_I2C2_IRQ, },
  589. };
  590. static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
  591. { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
  592. { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
  593. };
  594. static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
  595. &omap3_l4_core__i2c2,
  596. };
  597. static struct omap_hwmod omap3xxx_i2c2_hwmod = {
  598. .name = "i2c2",
  599. .mpu_irqs = i2c2_mpu_irqs,
  600. .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs),
  601. .sdma_reqs = i2c2_sdma_reqs,
  602. .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
  603. .main_clk = "i2c2_fck",
  604. .prcm = {
  605. .omap2 = {
  606. .module_offs = CORE_MOD,
  607. .prcm_reg_id = 1,
  608. .module_bit = OMAP3430_EN_I2C2_SHIFT,
  609. .idlest_reg_id = 1,
  610. .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
  611. },
  612. },
  613. .slaves = omap3xxx_i2c2_slaves,
  614. .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves),
  615. .class = &i2c_class,
  616. .dev_attr = &i2c2_dev_attr,
  617. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  618. };
  619. /* I2C3 */
  620. static struct omap_i2c_dev_attr i2c3_dev_attr = {
  621. .fifo_depth = 64, /* bytes */
  622. };
  623. static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
  624. { .irq = INT_34XX_I2C3_IRQ, },
  625. };
  626. static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
  627. { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
  628. { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
  629. };
  630. static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
  631. &omap3_l4_core__i2c3,
  632. };
  633. static struct omap_hwmod omap3xxx_i2c3_hwmod = {
  634. .name = "i2c3",
  635. .mpu_irqs = i2c3_mpu_irqs,
  636. .mpu_irqs_cnt = ARRAY_SIZE(i2c3_mpu_irqs),
  637. .sdma_reqs = i2c3_sdma_reqs,
  638. .sdma_reqs_cnt = ARRAY_SIZE(i2c3_sdma_reqs),
  639. .main_clk = "i2c3_fck",
  640. .prcm = {
  641. .omap2 = {
  642. .module_offs = CORE_MOD,
  643. .prcm_reg_id = 1,
  644. .module_bit = OMAP3430_EN_I2C3_SHIFT,
  645. .idlest_reg_id = 1,
  646. .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
  647. },
  648. },
  649. .slaves = omap3xxx_i2c3_slaves,
  650. .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves),
  651. .class = &i2c_class,
  652. .dev_attr = &i2c3_dev_attr,
  653. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  654. };
  655. /* l4_wkup -> gpio1 */
  656. static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
  657. {
  658. .pa_start = 0x48310000,
  659. .pa_end = 0x483101ff,
  660. .flags = ADDR_TYPE_RT
  661. },
  662. };
  663. static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
  664. .master = &omap3xxx_l4_wkup_hwmod,
  665. .slave = &omap3xxx_gpio1_hwmod,
  666. .addr = omap3xxx_gpio1_addrs,
  667. .addr_cnt = ARRAY_SIZE(omap3xxx_gpio1_addrs),
  668. .user = OCP_USER_MPU | OCP_USER_SDMA,
  669. };
  670. /* l4_per -> gpio2 */
  671. static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
  672. {
  673. .pa_start = 0x49050000,
  674. .pa_end = 0x490501ff,
  675. .flags = ADDR_TYPE_RT
  676. },
  677. };
  678. static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
  679. .master = &omap3xxx_l4_per_hwmod,
  680. .slave = &omap3xxx_gpio2_hwmod,
  681. .addr = omap3xxx_gpio2_addrs,
  682. .addr_cnt = ARRAY_SIZE(omap3xxx_gpio2_addrs),
  683. .user = OCP_USER_MPU | OCP_USER_SDMA,
  684. };
  685. /* l4_per -> gpio3 */
  686. static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
  687. {
  688. .pa_start = 0x49052000,
  689. .pa_end = 0x490521ff,
  690. .flags = ADDR_TYPE_RT
  691. },
  692. };
  693. static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
  694. .master = &omap3xxx_l4_per_hwmod,
  695. .slave = &omap3xxx_gpio3_hwmod,
  696. .addr = omap3xxx_gpio3_addrs,
  697. .addr_cnt = ARRAY_SIZE(omap3xxx_gpio3_addrs),
  698. .user = OCP_USER_MPU | OCP_USER_SDMA,
  699. };
  700. /* l4_per -> gpio4 */
  701. static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
  702. {
  703. .pa_start = 0x49054000,
  704. .pa_end = 0x490541ff,
  705. .flags = ADDR_TYPE_RT
  706. },
  707. };
  708. static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
  709. .master = &omap3xxx_l4_per_hwmod,
  710. .slave = &omap3xxx_gpio4_hwmod,
  711. .addr = omap3xxx_gpio4_addrs,
  712. .addr_cnt = ARRAY_SIZE(omap3xxx_gpio4_addrs),
  713. .user = OCP_USER_MPU | OCP_USER_SDMA,
  714. };
  715. /* l4_per -> gpio5 */
  716. static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
  717. {
  718. .pa_start = 0x49056000,
  719. .pa_end = 0x490561ff,
  720. .flags = ADDR_TYPE_RT
  721. },
  722. };
  723. static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
  724. .master = &omap3xxx_l4_per_hwmod,
  725. .slave = &omap3xxx_gpio5_hwmod,
  726. .addr = omap3xxx_gpio5_addrs,
  727. .addr_cnt = ARRAY_SIZE(omap3xxx_gpio5_addrs),
  728. .user = OCP_USER_MPU | OCP_USER_SDMA,
  729. };
  730. /* l4_per -> gpio6 */
  731. static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
  732. {
  733. .pa_start = 0x49058000,
  734. .pa_end = 0x490581ff,
  735. .flags = ADDR_TYPE_RT
  736. },
  737. };
  738. static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
  739. .master = &omap3xxx_l4_per_hwmod,
  740. .slave = &omap3xxx_gpio6_hwmod,
  741. .addr = omap3xxx_gpio6_addrs,
  742. .addr_cnt = ARRAY_SIZE(omap3xxx_gpio6_addrs),
  743. .user = OCP_USER_MPU | OCP_USER_SDMA,
  744. };
  745. /*
  746. * 'gpio' class
  747. * general purpose io module
  748. */
  749. static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
  750. .rev_offs = 0x0000,
  751. .sysc_offs = 0x0010,
  752. .syss_offs = 0x0014,
  753. .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
  754. SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
  755. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  756. .sysc_fields = &omap_hwmod_sysc_type1,
  757. };
  758. static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
  759. .name = "gpio",
  760. .sysc = &omap3xxx_gpio_sysc,
  761. .rev = 1,
  762. };
  763. /* gpio_dev_attr*/
  764. static struct omap_gpio_dev_attr gpio_dev_attr = {
  765. .bank_width = 32,
  766. .dbck_flag = true,
  767. };
  768. /* gpio1 */
  769. static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs[] = {
  770. { .irq = 29 }, /* INT_34XX_GPIO_BANK1 */
  771. };
  772. static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
  773. { .role = "dbclk", .clk = "gpio1_dbck", },
  774. };
  775. static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
  776. &omap3xxx_l4_wkup__gpio1,
  777. };
  778. static struct omap_hwmod omap3xxx_gpio1_hwmod = {
  779. .name = "gpio1",
  780. .mpu_irqs = omap3xxx_gpio1_irqs,
  781. .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio1_irqs),
  782. .main_clk = "gpio1_ick",
  783. .opt_clks = gpio1_opt_clks,
  784. .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
  785. .prcm = {
  786. .omap2 = {
  787. .prcm_reg_id = 1,
  788. .module_bit = OMAP3430_EN_GPIO1_SHIFT,
  789. .module_offs = WKUP_MOD,
  790. .idlest_reg_id = 1,
  791. .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
  792. },
  793. },
  794. .slaves = omap3xxx_gpio1_slaves,
  795. .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves),
  796. .class = &omap3xxx_gpio_hwmod_class,
  797. .dev_attr = &gpio_dev_attr,
  798. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  799. };
  800. /* gpio2 */
  801. static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs[] = {
  802. { .irq = 30 }, /* INT_34XX_GPIO_BANK2 */
  803. };
  804. static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
  805. { .role = "dbclk", .clk = "gpio2_dbck", },
  806. };
  807. static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
  808. &omap3xxx_l4_per__gpio2,
  809. };
  810. static struct omap_hwmod omap3xxx_gpio2_hwmod = {
  811. .name = "gpio2",
  812. .mpu_irqs = omap3xxx_gpio2_irqs,
  813. .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio2_irqs),
  814. .main_clk = "gpio2_ick",
  815. .opt_clks = gpio2_opt_clks,
  816. .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
  817. .prcm = {
  818. .omap2 = {
  819. .prcm_reg_id = 1,
  820. .module_bit = OMAP3430_EN_GPIO2_SHIFT,
  821. .module_offs = OMAP3430_PER_MOD,
  822. .idlest_reg_id = 1,
  823. .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
  824. },
  825. },
  826. .slaves = omap3xxx_gpio2_slaves,
  827. .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves),
  828. .class = &omap3xxx_gpio_hwmod_class,
  829. .dev_attr = &gpio_dev_attr,
  830. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  831. };
  832. /* gpio3 */
  833. static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs[] = {
  834. { .irq = 31 }, /* INT_34XX_GPIO_BANK3 */
  835. };
  836. static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
  837. { .role = "dbclk", .clk = "gpio3_dbck", },
  838. };
  839. static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
  840. &omap3xxx_l4_per__gpio3,
  841. };
  842. static struct omap_hwmod omap3xxx_gpio3_hwmod = {
  843. .name = "gpio3",
  844. .mpu_irqs = omap3xxx_gpio3_irqs,
  845. .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio3_irqs),
  846. .main_clk = "gpio3_ick",
  847. .opt_clks = gpio3_opt_clks,
  848. .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
  849. .prcm = {
  850. .omap2 = {
  851. .prcm_reg_id = 1,
  852. .module_bit = OMAP3430_EN_GPIO3_SHIFT,
  853. .module_offs = OMAP3430_PER_MOD,
  854. .idlest_reg_id = 1,
  855. .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
  856. },
  857. },
  858. .slaves = omap3xxx_gpio3_slaves,
  859. .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves),
  860. .class = &omap3xxx_gpio_hwmod_class,
  861. .dev_attr = &gpio_dev_attr,
  862. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  863. };
  864. /* gpio4 */
  865. static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs[] = {
  866. { .irq = 32 }, /* INT_34XX_GPIO_BANK4 */
  867. };
  868. static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
  869. { .role = "dbclk", .clk = "gpio4_dbck", },
  870. };
  871. static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
  872. &omap3xxx_l4_per__gpio4,
  873. };
  874. static struct omap_hwmod omap3xxx_gpio4_hwmod = {
  875. .name = "gpio4",
  876. .mpu_irqs = omap3xxx_gpio4_irqs,
  877. .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio4_irqs),
  878. .main_clk = "gpio4_ick",
  879. .opt_clks = gpio4_opt_clks,
  880. .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
  881. .prcm = {
  882. .omap2 = {
  883. .prcm_reg_id = 1,
  884. .module_bit = OMAP3430_EN_GPIO4_SHIFT,
  885. .module_offs = OMAP3430_PER_MOD,
  886. .idlest_reg_id = 1,
  887. .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
  888. },
  889. },
  890. .slaves = omap3xxx_gpio4_slaves,
  891. .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves),
  892. .class = &omap3xxx_gpio_hwmod_class,
  893. .dev_attr = &gpio_dev_attr,
  894. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  895. };
  896. /* gpio5 */
  897. static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
  898. { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
  899. };
  900. static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
  901. { .role = "dbclk", .clk = "gpio5_dbck", },
  902. };
  903. static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
  904. &omap3xxx_l4_per__gpio5,
  905. };
  906. static struct omap_hwmod omap3xxx_gpio5_hwmod = {
  907. .name = "gpio5",
  908. .mpu_irqs = omap3xxx_gpio5_irqs,
  909. .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio5_irqs),
  910. .main_clk = "gpio5_ick",
  911. .opt_clks = gpio5_opt_clks,
  912. .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
  913. .prcm = {
  914. .omap2 = {
  915. .prcm_reg_id = 1,
  916. .module_bit = OMAP3430_EN_GPIO5_SHIFT,
  917. .module_offs = OMAP3430_PER_MOD,
  918. .idlest_reg_id = 1,
  919. .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
  920. },
  921. },
  922. .slaves = omap3xxx_gpio5_slaves,
  923. .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves),
  924. .class = &omap3xxx_gpio_hwmod_class,
  925. .dev_attr = &gpio_dev_attr,
  926. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  927. };
  928. /* gpio6 */
  929. static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
  930. { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
  931. };
  932. static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
  933. { .role = "dbclk", .clk = "gpio6_dbck", },
  934. };
  935. static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
  936. &omap3xxx_l4_per__gpio6,
  937. };
  938. static struct omap_hwmod omap3xxx_gpio6_hwmod = {
  939. .name = "gpio6",
  940. .mpu_irqs = omap3xxx_gpio6_irqs,
  941. .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio6_irqs),
  942. .main_clk = "gpio6_ick",
  943. .opt_clks = gpio6_opt_clks,
  944. .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
  945. .prcm = {
  946. .omap2 = {
  947. .prcm_reg_id = 1,
  948. .module_bit = OMAP3430_EN_GPIO6_SHIFT,
  949. .module_offs = OMAP3430_PER_MOD,
  950. .idlest_reg_id = 1,
  951. .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
  952. },
  953. },
  954. .slaves = omap3xxx_gpio6_slaves,
  955. .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves),
  956. .class = &omap3xxx_gpio_hwmod_class,
  957. .dev_attr = &gpio_dev_attr,
  958. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  959. };
  960. /* dma_system -> L3 */
  961. static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
  962. .master = &omap3xxx_dma_system_hwmod,
  963. .slave = &omap3xxx_l3_main_hwmod,
  964. .clk = "core_l3_ick",
  965. .user = OCP_USER_MPU | OCP_USER_SDMA,
  966. };
  967. /* dma attributes */
  968. static struct omap_dma_dev_attr dma_dev_attr = {
  969. .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
  970. IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
  971. .lch_count = 32,
  972. };
  973. static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
  974. .rev_offs = 0x0000,
  975. .sysc_offs = 0x002c,
  976. .syss_offs = 0x0028,
  977. .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
  978. SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
  979. SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
  980. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  981. MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
  982. .sysc_fields = &omap_hwmod_sysc_type1,
  983. };
  984. static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
  985. .name = "dma",
  986. .sysc = &omap3xxx_dma_sysc,
  987. };
  988. /* dma_system */
  989. static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = {
  990. { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
  991. { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
  992. { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
  993. { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
  994. };
  995. static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
  996. {
  997. .pa_start = 0x48056000,
  998. .pa_end = 0x4a0560ff,
  999. .flags = ADDR_TYPE_RT
  1000. },
  1001. };
  1002. /* dma_system master ports */
  1003. static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
  1004. &omap3xxx_dma_system__l3,
  1005. };
  1006. /* l4_cfg -> dma_system */
  1007. static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
  1008. .master = &omap3xxx_l4_core_hwmod,
  1009. .slave = &omap3xxx_dma_system_hwmod,
  1010. .clk = "core_l4_ick",
  1011. .addr = omap3xxx_dma_system_addrs,
  1012. .addr_cnt = ARRAY_SIZE(omap3xxx_dma_system_addrs),
  1013. .user = OCP_USER_MPU | OCP_USER_SDMA,
  1014. };
  1015. /* dma_system slave ports */
  1016. static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
  1017. &omap3xxx_l4_core__dma_system,
  1018. };
  1019. static struct omap_hwmod omap3xxx_dma_system_hwmod = {
  1020. .name = "dma",
  1021. .class = &omap3xxx_dma_hwmod_class,
  1022. .mpu_irqs = omap3xxx_dma_system_irqs,
  1023. .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dma_system_irqs),
  1024. .main_clk = "core_l3_ick",
  1025. .prcm = {
  1026. .omap2 = {
  1027. .module_offs = CORE_MOD,
  1028. .prcm_reg_id = 1,
  1029. .module_bit = OMAP3430_ST_SDMA_SHIFT,
  1030. .idlest_reg_id = 1,
  1031. .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
  1032. },
  1033. },
  1034. .slaves = omap3xxx_dma_system_slaves,
  1035. .slaves_cnt = ARRAY_SIZE(omap3xxx_dma_system_slaves),
  1036. .masters = omap3xxx_dma_system_masters,
  1037. .masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters),
  1038. .dev_attr = &dma_dev_attr,
  1039. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  1040. .flags = HWMOD_NO_IDLEST,
  1041. };
  1042. static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
  1043. &omap3xxx_l3_main_hwmod,
  1044. &omap3xxx_l4_core_hwmod,
  1045. &omap3xxx_l4_per_hwmod,
  1046. &omap3xxx_l4_wkup_hwmod,
  1047. &omap3xxx_mpu_hwmod,
  1048. &omap3xxx_iva_hwmod,
  1049. &omap3xxx_wd_timer2_hwmod,
  1050. &omap3xxx_uart1_hwmod,
  1051. &omap3xxx_uart2_hwmod,
  1052. &omap3xxx_uart3_hwmod,
  1053. &omap3xxx_uart4_hwmod,
  1054. &omap3xxx_i2c1_hwmod,
  1055. &omap3xxx_i2c2_hwmod,
  1056. &omap3xxx_i2c3_hwmod,
  1057. /* gpio class */
  1058. &omap3xxx_gpio1_hwmod,
  1059. &omap3xxx_gpio2_hwmod,
  1060. &omap3xxx_gpio3_hwmod,
  1061. &omap3xxx_gpio4_hwmod,
  1062. &omap3xxx_gpio5_hwmod,
  1063. &omap3xxx_gpio6_hwmod,
  1064. /* dma_system class*/
  1065. &omap3xxx_dma_system_hwmod,
  1066. NULL,
  1067. };
  1068. int __init omap3xxx_hwmod_init(void)
  1069. {
  1070. return omap_hwmod_init(omap3xxx_hwmods);
  1071. }