gadget.c 61 KB

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  1. /**
  2. * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
  3. *
  4. * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
  5. *
  6. * Authors: Felipe Balbi <balbi@ti.com>,
  7. * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
  8. *
  9. * Redistribution and use in source and binary forms, with or without
  10. * modification, are permitted provided that the following conditions
  11. * are met:
  12. * 1. Redistributions of source code must retain the above copyright
  13. * notice, this list of conditions, and the following disclaimer,
  14. * without modification.
  15. * 2. Redistributions in binary form must reproduce the above copyright
  16. * notice, this list of conditions and the following disclaimer in the
  17. * documentation and/or other materials provided with the distribution.
  18. * 3. The names of the above-listed copyright holders may not be used
  19. * to endorse or promote products derived from this software without
  20. * specific prior written permission.
  21. *
  22. * ALTERNATIVELY, this software may be distributed under the terms of the
  23. * GNU General Public License ("GPL") version 2, as published by the Free
  24. * Software Foundation.
  25. *
  26. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  27. * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  28. * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  29. * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  30. * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  31. * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  32. * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  33. * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  34. * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  35. * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  36. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37. */
  38. #include <linux/kernel.h>
  39. #include <linux/delay.h>
  40. #include <linux/slab.h>
  41. #include <linux/spinlock.h>
  42. #include <linux/platform_device.h>
  43. #include <linux/pm_runtime.h>
  44. #include <linux/interrupt.h>
  45. #include <linux/io.h>
  46. #include <linux/list.h>
  47. #include <linux/dma-mapping.h>
  48. #include <linux/usb/ch9.h>
  49. #include <linux/usb/gadget.h>
  50. #include "core.h"
  51. #include "gadget.h"
  52. #include "io.h"
  53. /**
  54. * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
  55. * @dwc: pointer to our context structure
  56. * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  57. *
  58. * Caller should take care of locking. This function will
  59. * return 0 on success or -EINVAL if wrong Test Selector
  60. * is passed
  61. */
  62. int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  63. {
  64. u32 reg;
  65. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  66. reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  67. switch (mode) {
  68. case TEST_J:
  69. case TEST_K:
  70. case TEST_SE0_NAK:
  71. case TEST_PACKET:
  72. case TEST_FORCE_EN:
  73. reg |= mode << 1;
  74. break;
  75. default:
  76. return -EINVAL;
  77. }
  78. dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  79. return 0;
  80. }
  81. /**
  82. * dwc3_gadget_set_link_state - Sets USB Link to a particular State
  83. * @dwc: pointer to our context structure
  84. * @state: the state to put link into
  85. *
  86. * Caller should take care of locking. This function will
  87. * return 0 on success or -ETIMEDOUT.
  88. */
  89. int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
  90. {
  91. int retries = 10000;
  92. u32 reg;
  93. /*
  94. * Wait until device controller is ready. Only applies to 1.94a and
  95. * later RTL.
  96. */
  97. if (dwc->revision >= DWC3_REVISION_194A) {
  98. while (--retries) {
  99. reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  100. if (reg & DWC3_DSTS_DCNRD)
  101. udelay(5);
  102. else
  103. break;
  104. }
  105. if (retries <= 0)
  106. return -ETIMEDOUT;
  107. }
  108. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  109. reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
  110. /* set requested state */
  111. reg |= DWC3_DCTL_ULSTCHNGREQ(state);
  112. dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  113. /*
  114. * The following code is racy when called from dwc3_gadget_wakeup,
  115. * and is not needed, at least on newer versions
  116. */
  117. if (dwc->revision >= DWC3_REVISION_194A)
  118. return 0;
  119. /* wait for a change in DSTS */
  120. retries = 10000;
  121. while (--retries) {
  122. reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  123. if (DWC3_DSTS_USBLNKST(reg) == state)
  124. return 0;
  125. udelay(5);
  126. }
  127. dev_vdbg(dwc->dev, "link state change request timed out\n");
  128. return -ETIMEDOUT;
  129. }
  130. /**
  131. * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
  132. * @dwc: pointer to our context structure
  133. *
  134. * This function will a best effort FIFO allocation in order
  135. * to improve FIFO usage and throughput, while still allowing
  136. * us to enable as many endpoints as possible.
  137. *
  138. * Keep in mind that this operation will be highly dependent
  139. * on the configured size for RAM1 - which contains TxFifo -,
  140. * the amount of endpoints enabled on coreConsultant tool, and
  141. * the width of the Master Bus.
  142. *
  143. * In the ideal world, we would always be able to satisfy the
  144. * following equation:
  145. *
  146. * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
  147. * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
  148. *
  149. * Unfortunately, due to many variables that's not always the case.
  150. */
  151. int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
  152. {
  153. int last_fifo_depth = 0;
  154. int ram1_depth;
  155. int fifo_size;
  156. int mdwidth;
  157. int num;
  158. if (!dwc->needs_fifo_resize)
  159. return 0;
  160. ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
  161. mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
  162. /* MDWIDTH is represented in bits, we need it in bytes */
  163. mdwidth >>= 3;
  164. /*
  165. * FIXME For now we will only allocate 1 wMaxPacketSize space
  166. * for each enabled endpoint, later patches will come to
  167. * improve this algorithm so that we better use the internal
  168. * FIFO space
  169. */
  170. for (num = 0; num < DWC3_ENDPOINTS_NUM; num++) {
  171. struct dwc3_ep *dep = dwc->eps[num];
  172. int fifo_number = dep->number >> 1;
  173. int mult = 1;
  174. int tmp;
  175. if (!(dep->number & 1))
  176. continue;
  177. if (!(dep->flags & DWC3_EP_ENABLED))
  178. continue;
  179. if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
  180. || usb_endpoint_xfer_isoc(dep->endpoint.desc))
  181. mult = 3;
  182. /*
  183. * REVISIT: the following assumes we will always have enough
  184. * space available on the FIFO RAM for all possible use cases.
  185. * Make sure that's true somehow and change FIFO allocation
  186. * accordingly.
  187. *
  188. * If we have Bulk or Isochronous endpoints, we want
  189. * them to be able to be very, very fast. So we're giving
  190. * those endpoints a fifo_size which is enough for 3 full
  191. * packets
  192. */
  193. tmp = mult * (dep->endpoint.maxpacket + mdwidth);
  194. tmp += mdwidth;
  195. fifo_size = DIV_ROUND_UP(tmp, mdwidth);
  196. fifo_size |= (last_fifo_depth << 16);
  197. dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
  198. dep->name, last_fifo_depth, fifo_size & 0xffff);
  199. dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(fifo_number),
  200. fifo_size);
  201. last_fifo_depth += (fifo_size & 0xffff);
  202. }
  203. return 0;
  204. }
  205. void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
  206. int status)
  207. {
  208. struct dwc3 *dwc = dep->dwc;
  209. if (req->queued) {
  210. if (req->request.num_mapped_sgs)
  211. dep->busy_slot += req->request.num_mapped_sgs;
  212. else
  213. dep->busy_slot++;
  214. /*
  215. * Skip LINK TRB. We can't use req->trb and check for
  216. * DWC3_TRBCTL_LINK_TRB because it points the TRB we just
  217. * completed (not the LINK TRB).
  218. */
  219. if (((dep->busy_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
  220. usb_endpoint_xfer_isoc(dep->endpoint.desc))
  221. dep->busy_slot++;
  222. }
  223. list_del(&req->list);
  224. req->trb = NULL;
  225. if (req->request.status == -EINPROGRESS)
  226. req->request.status = status;
  227. usb_gadget_unmap_request(&dwc->gadget, &req->request,
  228. req->direction);
  229. dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
  230. req, dep->name, req->request.actual,
  231. req->request.length, status);
  232. spin_unlock(&dwc->lock);
  233. req->request.complete(&dep->endpoint, &req->request);
  234. spin_lock(&dwc->lock);
  235. }
  236. static const char *dwc3_gadget_ep_cmd_string(u8 cmd)
  237. {
  238. switch (cmd) {
  239. case DWC3_DEPCMD_DEPSTARTCFG:
  240. return "Start New Configuration";
  241. case DWC3_DEPCMD_ENDTRANSFER:
  242. return "End Transfer";
  243. case DWC3_DEPCMD_UPDATETRANSFER:
  244. return "Update Transfer";
  245. case DWC3_DEPCMD_STARTTRANSFER:
  246. return "Start Transfer";
  247. case DWC3_DEPCMD_CLEARSTALL:
  248. return "Clear Stall";
  249. case DWC3_DEPCMD_SETSTALL:
  250. return "Set Stall";
  251. case DWC3_DEPCMD_GETEPSTATE:
  252. return "Get Endpoint State";
  253. case DWC3_DEPCMD_SETTRANSFRESOURCE:
  254. return "Set Endpoint Transfer Resource";
  255. case DWC3_DEPCMD_SETEPCONFIG:
  256. return "Set Endpoint Configuration";
  257. default:
  258. return "UNKNOWN command";
  259. }
  260. }
  261. int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param)
  262. {
  263. u32 timeout = 500;
  264. u32 reg;
  265. dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
  266. dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
  267. do {
  268. reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
  269. if (!(reg & DWC3_DGCMD_CMDACT)) {
  270. dev_vdbg(dwc->dev, "Command Complete --> %d\n",
  271. DWC3_DGCMD_STATUS(reg));
  272. return 0;
  273. }
  274. /*
  275. * We can't sleep here, because it's also called from
  276. * interrupt context.
  277. */
  278. timeout--;
  279. if (!timeout)
  280. return -ETIMEDOUT;
  281. udelay(1);
  282. } while (1);
  283. }
  284. int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
  285. unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
  286. {
  287. struct dwc3_ep *dep = dwc->eps[ep];
  288. u32 timeout = 500;
  289. u32 reg;
  290. dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n",
  291. dep->name,
  292. dwc3_gadget_ep_cmd_string(cmd), params->param0,
  293. params->param1, params->param2);
  294. dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
  295. dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
  296. dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
  297. dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
  298. do {
  299. reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
  300. if (!(reg & DWC3_DEPCMD_CMDACT)) {
  301. dev_vdbg(dwc->dev, "Command Complete --> %d\n",
  302. DWC3_DEPCMD_STATUS(reg));
  303. return 0;
  304. }
  305. /*
  306. * We can't sleep here, because it is also called from
  307. * interrupt context.
  308. */
  309. timeout--;
  310. if (!timeout)
  311. return -ETIMEDOUT;
  312. udelay(1);
  313. } while (1);
  314. }
  315. static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
  316. struct dwc3_trb *trb)
  317. {
  318. u32 offset = (char *) trb - (char *) dep->trb_pool;
  319. return dep->trb_pool_dma + offset;
  320. }
  321. static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
  322. {
  323. struct dwc3 *dwc = dep->dwc;
  324. if (dep->trb_pool)
  325. return 0;
  326. if (dep->number == 0 || dep->number == 1)
  327. return 0;
  328. dep->trb_pool = dma_alloc_coherent(dwc->dev,
  329. sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
  330. &dep->trb_pool_dma, GFP_KERNEL);
  331. if (!dep->trb_pool) {
  332. dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
  333. dep->name);
  334. return -ENOMEM;
  335. }
  336. return 0;
  337. }
  338. static void dwc3_free_trb_pool(struct dwc3_ep *dep)
  339. {
  340. struct dwc3 *dwc = dep->dwc;
  341. dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
  342. dep->trb_pool, dep->trb_pool_dma);
  343. dep->trb_pool = NULL;
  344. dep->trb_pool_dma = 0;
  345. }
  346. static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
  347. {
  348. struct dwc3_gadget_ep_cmd_params params;
  349. u32 cmd;
  350. memset(&params, 0x00, sizeof(params));
  351. if (dep->number != 1) {
  352. cmd = DWC3_DEPCMD_DEPSTARTCFG;
  353. /* XferRscIdx == 0 for ep0 and 2 for the remaining */
  354. if (dep->number > 1) {
  355. if (dwc->start_config_issued)
  356. return 0;
  357. dwc->start_config_issued = true;
  358. cmd |= DWC3_DEPCMD_PARAM(2);
  359. }
  360. return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
  361. }
  362. return 0;
  363. }
  364. static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
  365. const struct usb_endpoint_descriptor *desc,
  366. const struct usb_ss_ep_comp_descriptor *comp_desc)
  367. {
  368. struct dwc3_gadget_ep_cmd_params params;
  369. memset(&params, 0x00, sizeof(params));
  370. params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
  371. | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc))
  372. | DWC3_DEPCFG_BURST_SIZE(dep->endpoint.maxburst);
  373. params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
  374. | DWC3_DEPCFG_XFER_NOT_READY_EN;
  375. if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
  376. params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
  377. | DWC3_DEPCFG_STREAM_EVENT_EN;
  378. dep->stream_capable = true;
  379. }
  380. if (usb_endpoint_xfer_isoc(desc))
  381. params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
  382. /*
  383. * We are doing 1:1 mapping for endpoints, meaning
  384. * Physical Endpoints 2 maps to Logical Endpoint 2 and
  385. * so on. We consider the direction bit as part of the physical
  386. * endpoint number. So USB endpoint 0x81 is 0x03.
  387. */
  388. params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
  389. /*
  390. * We must use the lower 16 TX FIFOs even though
  391. * HW might have more
  392. */
  393. if (dep->direction)
  394. params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
  395. if (desc->bInterval) {
  396. params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
  397. dep->interval = 1 << (desc->bInterval - 1);
  398. }
  399. return dwc3_send_gadget_ep_cmd(dwc, dep->number,
  400. DWC3_DEPCMD_SETEPCONFIG, &params);
  401. }
  402. static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
  403. {
  404. struct dwc3_gadget_ep_cmd_params params;
  405. memset(&params, 0x00, sizeof(params));
  406. params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
  407. return dwc3_send_gadget_ep_cmd(dwc, dep->number,
  408. DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
  409. }
  410. /**
  411. * __dwc3_gadget_ep_enable - Initializes a HW endpoint
  412. * @dep: endpoint to be initialized
  413. * @desc: USB Endpoint Descriptor
  414. *
  415. * Caller should take care of locking
  416. */
  417. static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
  418. const struct usb_endpoint_descriptor *desc,
  419. const struct usb_ss_ep_comp_descriptor *comp_desc)
  420. {
  421. struct dwc3 *dwc = dep->dwc;
  422. u32 reg;
  423. int ret = -ENOMEM;
  424. if (!(dep->flags & DWC3_EP_ENABLED)) {
  425. ret = dwc3_gadget_start_config(dwc, dep);
  426. if (ret)
  427. return ret;
  428. }
  429. ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc);
  430. if (ret)
  431. return ret;
  432. if (!(dep->flags & DWC3_EP_ENABLED)) {
  433. struct dwc3_trb *trb_st_hw;
  434. struct dwc3_trb *trb_link;
  435. ret = dwc3_gadget_set_xfer_resource(dwc, dep);
  436. if (ret)
  437. return ret;
  438. dep->endpoint.desc = desc;
  439. dep->comp_desc = comp_desc;
  440. dep->type = usb_endpoint_type(desc);
  441. dep->flags |= DWC3_EP_ENABLED;
  442. reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
  443. reg |= DWC3_DALEPENA_EP(dep->number);
  444. dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
  445. if (!usb_endpoint_xfer_isoc(desc))
  446. return 0;
  447. memset(&trb_link, 0, sizeof(trb_link));
  448. /* Link TRB for ISOC. The HWO bit is never reset */
  449. trb_st_hw = &dep->trb_pool[0];
  450. trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
  451. trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
  452. trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
  453. trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
  454. trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
  455. }
  456. return 0;
  457. }
  458. static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum);
  459. static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
  460. {
  461. struct dwc3_request *req;
  462. if (!list_empty(&dep->req_queued))
  463. dwc3_stop_active_transfer(dwc, dep->number);
  464. while (!list_empty(&dep->request_list)) {
  465. req = next_request(&dep->request_list);
  466. dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
  467. }
  468. }
  469. /**
  470. * __dwc3_gadget_ep_disable - Disables a HW endpoint
  471. * @dep: the endpoint to disable
  472. *
  473. * This function also removes requests which are currently processed ny the
  474. * hardware and those which are not yet scheduled.
  475. * Caller should take care of locking.
  476. */
  477. static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
  478. {
  479. struct dwc3 *dwc = dep->dwc;
  480. u32 reg;
  481. dwc3_remove_requests(dwc, dep);
  482. reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
  483. reg &= ~DWC3_DALEPENA_EP(dep->number);
  484. dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
  485. dep->stream_capable = false;
  486. dep->endpoint.desc = NULL;
  487. dep->comp_desc = NULL;
  488. dep->type = 0;
  489. dep->flags = 0;
  490. return 0;
  491. }
  492. /* -------------------------------------------------------------------------- */
  493. static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
  494. const struct usb_endpoint_descriptor *desc)
  495. {
  496. return -EINVAL;
  497. }
  498. static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
  499. {
  500. return -EINVAL;
  501. }
  502. /* -------------------------------------------------------------------------- */
  503. static int dwc3_gadget_ep_enable(struct usb_ep *ep,
  504. const struct usb_endpoint_descriptor *desc)
  505. {
  506. struct dwc3_ep *dep;
  507. struct dwc3 *dwc;
  508. unsigned long flags;
  509. int ret;
  510. if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
  511. pr_debug("dwc3: invalid parameters\n");
  512. return -EINVAL;
  513. }
  514. if (!desc->wMaxPacketSize) {
  515. pr_debug("dwc3: missing wMaxPacketSize\n");
  516. return -EINVAL;
  517. }
  518. dep = to_dwc3_ep(ep);
  519. dwc = dep->dwc;
  520. switch (usb_endpoint_type(desc)) {
  521. case USB_ENDPOINT_XFER_CONTROL:
  522. strlcat(dep->name, "-control", sizeof(dep->name));
  523. break;
  524. case USB_ENDPOINT_XFER_ISOC:
  525. strlcat(dep->name, "-isoc", sizeof(dep->name));
  526. break;
  527. case USB_ENDPOINT_XFER_BULK:
  528. strlcat(dep->name, "-bulk", sizeof(dep->name));
  529. break;
  530. case USB_ENDPOINT_XFER_INT:
  531. strlcat(dep->name, "-int", sizeof(dep->name));
  532. break;
  533. default:
  534. dev_err(dwc->dev, "invalid endpoint transfer type\n");
  535. }
  536. if (dep->flags & DWC3_EP_ENABLED) {
  537. dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
  538. dep->name);
  539. return 0;
  540. }
  541. dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
  542. spin_lock_irqsave(&dwc->lock, flags);
  543. ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc);
  544. spin_unlock_irqrestore(&dwc->lock, flags);
  545. return ret;
  546. }
  547. static int dwc3_gadget_ep_disable(struct usb_ep *ep)
  548. {
  549. struct dwc3_ep *dep;
  550. struct dwc3 *dwc;
  551. unsigned long flags;
  552. int ret;
  553. if (!ep) {
  554. pr_debug("dwc3: invalid parameters\n");
  555. return -EINVAL;
  556. }
  557. dep = to_dwc3_ep(ep);
  558. dwc = dep->dwc;
  559. if (!(dep->flags & DWC3_EP_ENABLED)) {
  560. dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
  561. dep->name);
  562. return 0;
  563. }
  564. snprintf(dep->name, sizeof(dep->name), "ep%d%s",
  565. dep->number >> 1,
  566. (dep->number & 1) ? "in" : "out");
  567. spin_lock_irqsave(&dwc->lock, flags);
  568. ret = __dwc3_gadget_ep_disable(dep);
  569. spin_unlock_irqrestore(&dwc->lock, flags);
  570. return ret;
  571. }
  572. static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
  573. gfp_t gfp_flags)
  574. {
  575. struct dwc3_request *req;
  576. struct dwc3_ep *dep = to_dwc3_ep(ep);
  577. struct dwc3 *dwc = dep->dwc;
  578. req = kzalloc(sizeof(*req), gfp_flags);
  579. if (!req) {
  580. dev_err(dwc->dev, "not enough memory\n");
  581. return NULL;
  582. }
  583. req->epnum = dep->number;
  584. req->dep = dep;
  585. return &req->request;
  586. }
  587. static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
  588. struct usb_request *request)
  589. {
  590. struct dwc3_request *req = to_dwc3_request(request);
  591. kfree(req);
  592. }
  593. /**
  594. * dwc3_prepare_one_trb - setup one TRB from one request
  595. * @dep: endpoint for which this request is prepared
  596. * @req: dwc3_request pointer
  597. */
  598. static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
  599. struct dwc3_request *req, dma_addr_t dma,
  600. unsigned length, unsigned last, unsigned chain)
  601. {
  602. struct dwc3 *dwc = dep->dwc;
  603. struct dwc3_trb *trb;
  604. unsigned int cur_slot;
  605. dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
  606. dep->name, req, (unsigned long long) dma,
  607. length, last ? " last" : "",
  608. chain ? " chain" : "");
  609. trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
  610. cur_slot = dep->free_slot;
  611. dep->free_slot++;
  612. /* Skip the LINK-TRB on ISOC */
  613. if (((cur_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
  614. usb_endpoint_xfer_isoc(dep->endpoint.desc))
  615. return;
  616. if (!req->trb) {
  617. dwc3_gadget_move_request_queued(req);
  618. req->trb = trb;
  619. req->trb_dma = dwc3_trb_dma_offset(dep, trb);
  620. }
  621. trb->size = DWC3_TRB_SIZE_LENGTH(length);
  622. trb->bpl = lower_32_bits(dma);
  623. trb->bph = upper_32_bits(dma);
  624. switch (usb_endpoint_type(dep->endpoint.desc)) {
  625. case USB_ENDPOINT_XFER_CONTROL:
  626. trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
  627. break;
  628. case USB_ENDPOINT_XFER_ISOC:
  629. trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
  630. if (!req->request.no_interrupt)
  631. trb->ctrl |= DWC3_TRB_CTRL_IOC;
  632. break;
  633. case USB_ENDPOINT_XFER_BULK:
  634. case USB_ENDPOINT_XFER_INT:
  635. trb->ctrl = DWC3_TRBCTL_NORMAL;
  636. break;
  637. default:
  638. /*
  639. * This is only possible with faulty memory because we
  640. * checked it already :)
  641. */
  642. BUG();
  643. }
  644. if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
  645. trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
  646. trb->ctrl |= DWC3_TRB_CTRL_CSP;
  647. } else {
  648. if (chain)
  649. trb->ctrl |= DWC3_TRB_CTRL_CHN;
  650. if (last)
  651. trb->ctrl |= DWC3_TRB_CTRL_LST;
  652. }
  653. if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
  654. trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
  655. trb->ctrl |= DWC3_TRB_CTRL_HWO;
  656. }
  657. /*
  658. * dwc3_prepare_trbs - setup TRBs from requests
  659. * @dep: endpoint for which requests are being prepared
  660. * @starting: true if the endpoint is idle and no requests are queued.
  661. *
  662. * The function goes through the requests list and sets up TRBs for the
  663. * transfers. The function returns once there are no more TRBs available or
  664. * it runs out of requests.
  665. */
  666. static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
  667. {
  668. struct dwc3_request *req, *n;
  669. u32 trbs_left;
  670. u32 max;
  671. unsigned int last_one = 0;
  672. BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
  673. /* the first request must not be queued */
  674. trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
  675. /* Can't wrap around on a non-isoc EP since there's no link TRB */
  676. if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
  677. max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
  678. if (trbs_left > max)
  679. trbs_left = max;
  680. }
  681. /*
  682. * If busy & slot are equal than it is either full or empty. If we are
  683. * starting to process requests then we are empty. Otherwise we are
  684. * full and don't do anything
  685. */
  686. if (!trbs_left) {
  687. if (!starting)
  688. return;
  689. trbs_left = DWC3_TRB_NUM;
  690. /*
  691. * In case we start from scratch, we queue the ISOC requests
  692. * starting from slot 1. This is done because we use ring
  693. * buffer and have no LST bit to stop us. Instead, we place
  694. * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
  695. * after the first request so we start at slot 1 and have
  696. * 7 requests proceed before we hit the first IOC.
  697. * Other transfer types don't use the ring buffer and are
  698. * processed from the first TRB until the last one. Since we
  699. * don't wrap around we have to start at the beginning.
  700. */
  701. if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
  702. dep->busy_slot = 1;
  703. dep->free_slot = 1;
  704. } else {
  705. dep->busy_slot = 0;
  706. dep->free_slot = 0;
  707. }
  708. }
  709. /* The last TRB is a link TRB, not used for xfer */
  710. if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
  711. return;
  712. list_for_each_entry_safe(req, n, &dep->request_list, list) {
  713. unsigned length;
  714. dma_addr_t dma;
  715. if (req->request.num_mapped_sgs > 0) {
  716. struct usb_request *request = &req->request;
  717. struct scatterlist *sg = request->sg;
  718. struct scatterlist *s;
  719. int i;
  720. for_each_sg(sg, s, request->num_mapped_sgs, i) {
  721. unsigned chain = true;
  722. length = sg_dma_len(s);
  723. dma = sg_dma_address(s);
  724. if (i == (request->num_mapped_sgs - 1) ||
  725. sg_is_last(s)) {
  726. last_one = true;
  727. chain = false;
  728. }
  729. trbs_left--;
  730. if (!trbs_left)
  731. last_one = true;
  732. if (last_one)
  733. chain = false;
  734. dwc3_prepare_one_trb(dep, req, dma, length,
  735. last_one, chain);
  736. if (last_one)
  737. break;
  738. }
  739. } else {
  740. dma = req->request.dma;
  741. length = req->request.length;
  742. trbs_left--;
  743. if (!trbs_left)
  744. last_one = 1;
  745. /* Is this the last request? */
  746. if (list_is_last(&req->list, &dep->request_list))
  747. last_one = 1;
  748. dwc3_prepare_one_trb(dep, req, dma, length,
  749. last_one, false);
  750. if (last_one)
  751. break;
  752. }
  753. }
  754. }
  755. static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
  756. int start_new)
  757. {
  758. struct dwc3_gadget_ep_cmd_params params;
  759. struct dwc3_request *req;
  760. struct dwc3 *dwc = dep->dwc;
  761. int ret;
  762. u32 cmd;
  763. if (start_new && (dep->flags & DWC3_EP_BUSY)) {
  764. dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
  765. return -EBUSY;
  766. }
  767. dep->flags &= ~DWC3_EP_PENDING_REQUEST;
  768. /*
  769. * If we are getting here after a short-out-packet we don't enqueue any
  770. * new requests as we try to set the IOC bit only on the last request.
  771. */
  772. if (start_new) {
  773. if (list_empty(&dep->req_queued))
  774. dwc3_prepare_trbs(dep, start_new);
  775. /* req points to the first request which will be sent */
  776. req = next_request(&dep->req_queued);
  777. } else {
  778. dwc3_prepare_trbs(dep, start_new);
  779. /*
  780. * req points to the first request where HWO changed from 0 to 1
  781. */
  782. req = next_request(&dep->req_queued);
  783. }
  784. if (!req) {
  785. dep->flags |= DWC3_EP_PENDING_REQUEST;
  786. return 0;
  787. }
  788. memset(&params, 0, sizeof(params));
  789. params.param0 = upper_32_bits(req->trb_dma);
  790. params.param1 = lower_32_bits(req->trb_dma);
  791. if (start_new)
  792. cmd = DWC3_DEPCMD_STARTTRANSFER;
  793. else
  794. cmd = DWC3_DEPCMD_UPDATETRANSFER;
  795. cmd |= DWC3_DEPCMD_PARAM(cmd_param);
  796. ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
  797. if (ret < 0) {
  798. dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
  799. /*
  800. * FIXME we need to iterate over the list of requests
  801. * here and stop, unmap, free and del each of the linked
  802. * requests instead of what we do now.
  803. */
  804. usb_gadget_unmap_request(&dwc->gadget, &req->request,
  805. req->direction);
  806. list_del(&req->list);
  807. return ret;
  808. }
  809. dep->flags |= DWC3_EP_BUSY;
  810. if (start_new) {
  811. dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
  812. dep->number);
  813. WARN_ON_ONCE(!dep->res_trans_idx);
  814. }
  815. return 0;
  816. }
  817. static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
  818. {
  819. struct dwc3 *dwc = dep->dwc;
  820. int ret;
  821. req->request.actual = 0;
  822. req->request.status = -EINPROGRESS;
  823. req->direction = dep->direction;
  824. req->epnum = dep->number;
  825. /*
  826. * We only add to our list of requests now and
  827. * start consuming the list once we get XferNotReady
  828. * IRQ.
  829. *
  830. * That way, we avoid doing anything that we don't need
  831. * to do now and defer it until the point we receive a
  832. * particular token from the Host side.
  833. *
  834. * This will also avoid Host cancelling URBs due to too
  835. * many NAKs.
  836. */
  837. ret = usb_gadget_map_request(&dwc->gadget, &req->request,
  838. dep->direction);
  839. if (ret)
  840. return ret;
  841. list_add_tail(&req->list, &dep->request_list);
  842. if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && (dep->flags & DWC3_EP_BUSY))
  843. dep->flags |= DWC3_EP_PENDING_REQUEST;
  844. /*
  845. * There are two special cases:
  846. *
  847. * 1. XferNotReady with empty list of requests. We need to kick the
  848. * transfer here in that situation, otherwise we will be NAKing
  849. * forever. If we get XferNotReady before gadget driver has a
  850. * chance to queue a request, we will ACK the IRQ but won't be
  851. * able to receive the data until the next request is queued.
  852. * The following code is handling exactly that.
  853. *
  854. * 2. XferInProgress on Isoc EP with an active transfer. We need to
  855. * kick the transfer here after queuing a request, otherwise the
  856. * core may not see the modified TRB(s).
  857. */
  858. if (dep->flags & DWC3_EP_PENDING_REQUEST) {
  859. int ret;
  860. int start_trans = 1;
  861. u8 trans_idx = dep->res_trans_idx;
  862. if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
  863. (dep->flags & DWC3_EP_BUSY)) {
  864. start_trans = 0;
  865. WARN_ON_ONCE(!trans_idx);
  866. } else {
  867. trans_idx = 0;
  868. }
  869. ret = __dwc3_gadget_kick_transfer(dep, trans_idx, start_trans);
  870. if (ret && ret != -EBUSY) {
  871. struct dwc3 *dwc = dep->dwc;
  872. dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
  873. dep->name);
  874. }
  875. }
  876. return 0;
  877. }
  878. static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
  879. gfp_t gfp_flags)
  880. {
  881. struct dwc3_request *req = to_dwc3_request(request);
  882. struct dwc3_ep *dep = to_dwc3_ep(ep);
  883. struct dwc3 *dwc = dep->dwc;
  884. unsigned long flags;
  885. int ret;
  886. if (!dep->endpoint.desc) {
  887. dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
  888. request, ep->name);
  889. return -ESHUTDOWN;
  890. }
  891. dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
  892. request, ep->name, request->length);
  893. spin_lock_irqsave(&dwc->lock, flags);
  894. ret = __dwc3_gadget_ep_queue(dep, req);
  895. spin_unlock_irqrestore(&dwc->lock, flags);
  896. return ret;
  897. }
  898. static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
  899. struct usb_request *request)
  900. {
  901. struct dwc3_request *req = to_dwc3_request(request);
  902. struct dwc3_request *r = NULL;
  903. struct dwc3_ep *dep = to_dwc3_ep(ep);
  904. struct dwc3 *dwc = dep->dwc;
  905. unsigned long flags;
  906. int ret = 0;
  907. spin_lock_irqsave(&dwc->lock, flags);
  908. list_for_each_entry(r, &dep->request_list, list) {
  909. if (r == req)
  910. break;
  911. }
  912. if (r != req) {
  913. list_for_each_entry(r, &dep->req_queued, list) {
  914. if (r == req)
  915. break;
  916. }
  917. if (r == req) {
  918. /* wait until it is processed */
  919. dwc3_stop_active_transfer(dwc, dep->number);
  920. goto out0;
  921. }
  922. dev_err(dwc->dev, "request %p was not queued to %s\n",
  923. request, ep->name);
  924. ret = -EINVAL;
  925. goto out0;
  926. }
  927. /* giveback the request */
  928. dwc3_gadget_giveback(dep, req, -ECONNRESET);
  929. out0:
  930. spin_unlock_irqrestore(&dwc->lock, flags);
  931. return ret;
  932. }
  933. int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value)
  934. {
  935. struct dwc3_gadget_ep_cmd_params params;
  936. struct dwc3 *dwc = dep->dwc;
  937. int ret;
  938. memset(&params, 0x00, sizeof(params));
  939. if (value) {
  940. if (dep->number == 0 || dep->number == 1) {
  941. /*
  942. * Whenever EP0 is stalled, we will restart
  943. * the state machine, thus moving back to
  944. * Setup Phase
  945. */
  946. dwc->ep0state = EP0_SETUP_PHASE;
  947. }
  948. ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
  949. DWC3_DEPCMD_SETSTALL, &params);
  950. if (ret)
  951. dev_err(dwc->dev, "failed to %s STALL on %s\n",
  952. value ? "set" : "clear",
  953. dep->name);
  954. else
  955. dep->flags |= DWC3_EP_STALL;
  956. } else {
  957. if (dep->flags & DWC3_EP_WEDGE)
  958. return 0;
  959. ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
  960. DWC3_DEPCMD_CLEARSTALL, &params);
  961. if (ret)
  962. dev_err(dwc->dev, "failed to %s STALL on %s\n",
  963. value ? "set" : "clear",
  964. dep->name);
  965. else
  966. dep->flags &= ~DWC3_EP_STALL;
  967. }
  968. return ret;
  969. }
  970. static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
  971. {
  972. struct dwc3_ep *dep = to_dwc3_ep(ep);
  973. struct dwc3 *dwc = dep->dwc;
  974. unsigned long flags;
  975. int ret;
  976. spin_lock_irqsave(&dwc->lock, flags);
  977. if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
  978. dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
  979. ret = -EINVAL;
  980. goto out;
  981. }
  982. ret = __dwc3_gadget_ep_set_halt(dep, value);
  983. out:
  984. spin_unlock_irqrestore(&dwc->lock, flags);
  985. return ret;
  986. }
  987. static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
  988. {
  989. struct dwc3_ep *dep = to_dwc3_ep(ep);
  990. struct dwc3 *dwc = dep->dwc;
  991. unsigned long flags;
  992. spin_lock_irqsave(&dwc->lock, flags);
  993. dep->flags |= DWC3_EP_WEDGE;
  994. spin_unlock_irqrestore(&dwc->lock, flags);
  995. return dwc3_gadget_ep_set_halt(ep, 1);
  996. }
  997. /* -------------------------------------------------------------------------- */
  998. static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
  999. .bLength = USB_DT_ENDPOINT_SIZE,
  1000. .bDescriptorType = USB_DT_ENDPOINT,
  1001. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  1002. };
  1003. static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
  1004. .enable = dwc3_gadget_ep0_enable,
  1005. .disable = dwc3_gadget_ep0_disable,
  1006. .alloc_request = dwc3_gadget_ep_alloc_request,
  1007. .free_request = dwc3_gadget_ep_free_request,
  1008. .queue = dwc3_gadget_ep0_queue,
  1009. .dequeue = dwc3_gadget_ep_dequeue,
  1010. .set_halt = dwc3_gadget_ep_set_halt,
  1011. .set_wedge = dwc3_gadget_ep_set_wedge,
  1012. };
  1013. static const struct usb_ep_ops dwc3_gadget_ep_ops = {
  1014. .enable = dwc3_gadget_ep_enable,
  1015. .disable = dwc3_gadget_ep_disable,
  1016. .alloc_request = dwc3_gadget_ep_alloc_request,
  1017. .free_request = dwc3_gadget_ep_free_request,
  1018. .queue = dwc3_gadget_ep_queue,
  1019. .dequeue = dwc3_gadget_ep_dequeue,
  1020. .set_halt = dwc3_gadget_ep_set_halt,
  1021. .set_wedge = dwc3_gadget_ep_set_wedge,
  1022. };
  1023. /* -------------------------------------------------------------------------- */
  1024. static int dwc3_gadget_get_frame(struct usb_gadget *g)
  1025. {
  1026. struct dwc3 *dwc = gadget_to_dwc(g);
  1027. u32 reg;
  1028. reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  1029. return DWC3_DSTS_SOFFN(reg);
  1030. }
  1031. static int dwc3_gadget_wakeup(struct usb_gadget *g)
  1032. {
  1033. struct dwc3 *dwc = gadget_to_dwc(g);
  1034. unsigned long timeout;
  1035. unsigned long flags;
  1036. u32 reg;
  1037. int ret = 0;
  1038. u8 link_state;
  1039. u8 speed;
  1040. spin_lock_irqsave(&dwc->lock, flags);
  1041. /*
  1042. * According to the Databook Remote wakeup request should
  1043. * be issued only when the device is in early suspend state.
  1044. *
  1045. * We can check that via USB Link State bits in DSTS register.
  1046. */
  1047. reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  1048. speed = reg & DWC3_DSTS_CONNECTSPD;
  1049. if (speed == DWC3_DSTS_SUPERSPEED) {
  1050. dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
  1051. ret = -EINVAL;
  1052. goto out;
  1053. }
  1054. link_state = DWC3_DSTS_USBLNKST(reg);
  1055. switch (link_state) {
  1056. case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
  1057. case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
  1058. break;
  1059. default:
  1060. dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
  1061. link_state);
  1062. ret = -EINVAL;
  1063. goto out;
  1064. }
  1065. ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
  1066. if (ret < 0) {
  1067. dev_err(dwc->dev, "failed to put link in Recovery\n");
  1068. goto out;
  1069. }
  1070. /* Recent versions do this automatically */
  1071. if (dwc->revision < DWC3_REVISION_194A) {
  1072. /* write zeroes to Link Change Request */
  1073. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  1074. reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
  1075. dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  1076. }
  1077. /* poll until Link State changes to ON */
  1078. timeout = jiffies + msecs_to_jiffies(100);
  1079. while (!time_after(jiffies, timeout)) {
  1080. reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  1081. /* in HS, means ON */
  1082. if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
  1083. break;
  1084. }
  1085. if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
  1086. dev_err(dwc->dev, "failed to send remote wakeup\n");
  1087. ret = -EINVAL;
  1088. }
  1089. out:
  1090. spin_unlock_irqrestore(&dwc->lock, flags);
  1091. return ret;
  1092. }
  1093. static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
  1094. int is_selfpowered)
  1095. {
  1096. struct dwc3 *dwc = gadget_to_dwc(g);
  1097. unsigned long flags;
  1098. spin_lock_irqsave(&dwc->lock, flags);
  1099. dwc->is_selfpowered = !!is_selfpowered;
  1100. spin_unlock_irqrestore(&dwc->lock, flags);
  1101. return 0;
  1102. }
  1103. static void dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
  1104. {
  1105. u32 reg;
  1106. u32 timeout = 500;
  1107. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  1108. if (is_on) {
  1109. if (dwc->revision <= DWC3_REVISION_187A) {
  1110. reg &= ~DWC3_DCTL_TRGTULST_MASK;
  1111. reg |= DWC3_DCTL_TRGTULST_RX_DET;
  1112. }
  1113. if (dwc->revision >= DWC3_REVISION_194A)
  1114. reg &= ~DWC3_DCTL_KEEP_CONNECT;
  1115. reg |= DWC3_DCTL_RUN_STOP;
  1116. } else {
  1117. reg &= ~DWC3_DCTL_RUN_STOP;
  1118. }
  1119. dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  1120. do {
  1121. reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  1122. if (is_on) {
  1123. if (!(reg & DWC3_DSTS_DEVCTRLHLT))
  1124. break;
  1125. } else {
  1126. if (reg & DWC3_DSTS_DEVCTRLHLT)
  1127. break;
  1128. }
  1129. timeout--;
  1130. if (!timeout)
  1131. break;
  1132. udelay(1);
  1133. } while (1);
  1134. dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
  1135. dwc->gadget_driver
  1136. ? dwc->gadget_driver->function : "no-function",
  1137. is_on ? "connect" : "disconnect");
  1138. }
  1139. static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
  1140. {
  1141. struct dwc3 *dwc = gadget_to_dwc(g);
  1142. unsigned long flags;
  1143. is_on = !!is_on;
  1144. spin_lock_irqsave(&dwc->lock, flags);
  1145. dwc3_gadget_run_stop(dwc, is_on);
  1146. spin_unlock_irqrestore(&dwc->lock, flags);
  1147. return 0;
  1148. }
  1149. static int dwc3_gadget_start(struct usb_gadget *g,
  1150. struct usb_gadget_driver *driver)
  1151. {
  1152. struct dwc3 *dwc = gadget_to_dwc(g);
  1153. struct dwc3_ep *dep;
  1154. unsigned long flags;
  1155. int ret = 0;
  1156. u32 reg;
  1157. spin_lock_irqsave(&dwc->lock, flags);
  1158. if (dwc->gadget_driver) {
  1159. dev_err(dwc->dev, "%s is already bound to %s\n",
  1160. dwc->gadget.name,
  1161. dwc->gadget_driver->driver.name);
  1162. ret = -EBUSY;
  1163. goto err0;
  1164. }
  1165. dwc->gadget_driver = driver;
  1166. dwc->gadget.dev.driver = &driver->driver;
  1167. reg = dwc3_readl(dwc->regs, DWC3_DCFG);
  1168. reg &= ~(DWC3_DCFG_SPEED_MASK);
  1169. /**
  1170. * WORKAROUND: DWC3 revision < 2.20a have an issue
  1171. * which would cause metastability state on Run/Stop
  1172. * bit if we try to force the IP to USB2-only mode.
  1173. *
  1174. * Because of that, we cannot configure the IP to any
  1175. * speed other than the SuperSpeed
  1176. *
  1177. * Refers to:
  1178. *
  1179. * STAR#9000525659: Clock Domain Crossing on DCTL in
  1180. * USB 2.0 Mode
  1181. */
  1182. if (dwc->revision < DWC3_REVISION_220A)
  1183. reg |= DWC3_DCFG_SUPERSPEED;
  1184. else
  1185. reg |= dwc->maximum_speed;
  1186. dwc3_writel(dwc->regs, DWC3_DCFG, reg);
  1187. dwc->start_config_issued = false;
  1188. /* Start with SuperSpeed Default */
  1189. dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
  1190. dep = dwc->eps[0];
  1191. ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
  1192. if (ret) {
  1193. dev_err(dwc->dev, "failed to enable %s\n", dep->name);
  1194. goto err0;
  1195. }
  1196. dep = dwc->eps[1];
  1197. ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
  1198. if (ret) {
  1199. dev_err(dwc->dev, "failed to enable %s\n", dep->name);
  1200. goto err1;
  1201. }
  1202. /* begin to receive SETUP packets */
  1203. dwc->ep0state = EP0_SETUP_PHASE;
  1204. dwc3_ep0_out_start(dwc);
  1205. spin_unlock_irqrestore(&dwc->lock, flags);
  1206. return 0;
  1207. err1:
  1208. __dwc3_gadget_ep_disable(dwc->eps[0]);
  1209. err0:
  1210. spin_unlock_irqrestore(&dwc->lock, flags);
  1211. return ret;
  1212. }
  1213. static int dwc3_gadget_stop(struct usb_gadget *g,
  1214. struct usb_gadget_driver *driver)
  1215. {
  1216. struct dwc3 *dwc = gadget_to_dwc(g);
  1217. unsigned long flags;
  1218. spin_lock_irqsave(&dwc->lock, flags);
  1219. __dwc3_gadget_ep_disable(dwc->eps[0]);
  1220. __dwc3_gadget_ep_disable(dwc->eps[1]);
  1221. dwc->gadget_driver = NULL;
  1222. dwc->gadget.dev.driver = NULL;
  1223. spin_unlock_irqrestore(&dwc->lock, flags);
  1224. return 0;
  1225. }
  1226. static const struct usb_gadget_ops dwc3_gadget_ops = {
  1227. .get_frame = dwc3_gadget_get_frame,
  1228. .wakeup = dwc3_gadget_wakeup,
  1229. .set_selfpowered = dwc3_gadget_set_selfpowered,
  1230. .pullup = dwc3_gadget_pullup,
  1231. .udc_start = dwc3_gadget_start,
  1232. .udc_stop = dwc3_gadget_stop,
  1233. };
  1234. /* -------------------------------------------------------------------------- */
  1235. static int __devinit dwc3_gadget_init_endpoints(struct dwc3 *dwc)
  1236. {
  1237. struct dwc3_ep *dep;
  1238. u8 epnum;
  1239. INIT_LIST_HEAD(&dwc->gadget.ep_list);
  1240. for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
  1241. dep = kzalloc(sizeof(*dep), GFP_KERNEL);
  1242. if (!dep) {
  1243. dev_err(dwc->dev, "can't allocate endpoint %d\n",
  1244. epnum);
  1245. return -ENOMEM;
  1246. }
  1247. dep->dwc = dwc;
  1248. dep->number = epnum;
  1249. dwc->eps[epnum] = dep;
  1250. snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
  1251. (epnum & 1) ? "in" : "out");
  1252. dep->endpoint.name = dep->name;
  1253. dep->direction = (epnum & 1);
  1254. if (epnum == 0 || epnum == 1) {
  1255. dep->endpoint.maxpacket = 512;
  1256. dep->endpoint.ops = &dwc3_gadget_ep0_ops;
  1257. if (!epnum)
  1258. dwc->gadget.ep0 = &dep->endpoint;
  1259. } else {
  1260. int ret;
  1261. dep->endpoint.maxpacket = 1024;
  1262. dep->endpoint.max_streams = 15;
  1263. dep->endpoint.ops = &dwc3_gadget_ep_ops;
  1264. list_add_tail(&dep->endpoint.ep_list,
  1265. &dwc->gadget.ep_list);
  1266. ret = dwc3_alloc_trb_pool(dep);
  1267. if (ret)
  1268. return ret;
  1269. }
  1270. INIT_LIST_HEAD(&dep->request_list);
  1271. INIT_LIST_HEAD(&dep->req_queued);
  1272. }
  1273. return 0;
  1274. }
  1275. static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
  1276. {
  1277. struct dwc3_ep *dep;
  1278. u8 epnum;
  1279. for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
  1280. dep = dwc->eps[epnum];
  1281. dwc3_free_trb_pool(dep);
  1282. if (epnum != 0 && epnum != 1)
  1283. list_del(&dep->endpoint.ep_list);
  1284. kfree(dep);
  1285. }
  1286. }
  1287. static void dwc3_gadget_release(struct device *dev)
  1288. {
  1289. dev_dbg(dev, "%s\n", __func__);
  1290. }
  1291. /* -------------------------------------------------------------------------- */
  1292. static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
  1293. const struct dwc3_event_depevt *event, int status)
  1294. {
  1295. struct dwc3_request *req;
  1296. struct dwc3_trb *trb;
  1297. unsigned int count;
  1298. unsigned int s_pkt = 0;
  1299. do {
  1300. req = next_request(&dep->req_queued);
  1301. if (!req) {
  1302. WARN_ON_ONCE(1);
  1303. return 1;
  1304. }
  1305. trb = req->trb;
  1306. if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
  1307. /*
  1308. * We continue despite the error. There is not much we
  1309. * can do. If we don't clean it up we loop forever. If
  1310. * we skip the TRB then it gets overwritten after a
  1311. * while since we use them in a ring buffer. A BUG()
  1312. * would help. Lets hope that if this occurs, someone
  1313. * fixes the root cause instead of looking away :)
  1314. */
  1315. dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
  1316. dep->name, req->trb);
  1317. count = trb->size & DWC3_TRB_SIZE_MASK;
  1318. if (dep->direction) {
  1319. if (count) {
  1320. dev_err(dwc->dev, "incomplete IN transfer %s\n",
  1321. dep->name);
  1322. status = -ECONNRESET;
  1323. }
  1324. } else {
  1325. if (count && (event->status & DEPEVT_STATUS_SHORT))
  1326. s_pkt = 1;
  1327. }
  1328. /*
  1329. * We assume here we will always receive the entire data block
  1330. * which we should receive. Meaning, if we program RX to
  1331. * receive 4K but we receive only 2K, we assume that's all we
  1332. * should receive and we simply bounce the request back to the
  1333. * gadget driver for further processing.
  1334. */
  1335. req->request.actual += req->request.length - count;
  1336. dwc3_gadget_giveback(dep, req, status);
  1337. if (s_pkt)
  1338. break;
  1339. if ((event->status & DEPEVT_STATUS_LST) &&
  1340. (trb->ctrl & DWC3_TRB_CTRL_LST))
  1341. break;
  1342. if ((event->status & DEPEVT_STATUS_IOC) &&
  1343. (trb->ctrl & DWC3_TRB_CTRL_IOC))
  1344. break;
  1345. } while (1);
  1346. if ((event->status & DEPEVT_STATUS_IOC) &&
  1347. (trb->ctrl & DWC3_TRB_CTRL_IOC))
  1348. return 0;
  1349. return 1;
  1350. }
  1351. static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
  1352. struct dwc3_ep *dep, const struct dwc3_event_depevt *event,
  1353. int start_new)
  1354. {
  1355. unsigned status = 0;
  1356. int clean_busy;
  1357. if (event->status & DEPEVT_STATUS_BUSERR)
  1358. status = -ECONNRESET;
  1359. clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
  1360. if (clean_busy)
  1361. dep->flags &= ~DWC3_EP_BUSY;
  1362. /*
  1363. * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
  1364. * See dwc3_gadget_linksts_change_interrupt() for 1st half.
  1365. */
  1366. if (dwc->revision < DWC3_REVISION_183A) {
  1367. u32 reg;
  1368. int i;
  1369. for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
  1370. struct dwc3_ep *dep = dwc->eps[i];
  1371. if (!(dep->flags & DWC3_EP_ENABLED))
  1372. continue;
  1373. if (!list_empty(&dep->req_queued))
  1374. return;
  1375. }
  1376. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  1377. reg |= dwc->u1u2;
  1378. dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  1379. dwc->u1u2 = 0;
  1380. }
  1381. }
  1382. static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
  1383. struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
  1384. {
  1385. u32 uf, mask;
  1386. if (list_empty(&dep->request_list)) {
  1387. dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
  1388. dep->name);
  1389. return;
  1390. }
  1391. mask = ~(dep->interval - 1);
  1392. uf = event->parameters & mask;
  1393. /* 4 micro frames in the future */
  1394. uf += dep->interval * 4;
  1395. __dwc3_gadget_kick_transfer(dep, uf, 1);
  1396. }
  1397. static void dwc3_process_ep_cmd_complete(struct dwc3_ep *dep,
  1398. const struct dwc3_event_depevt *event)
  1399. {
  1400. struct dwc3 *dwc = dep->dwc;
  1401. struct dwc3_event_depevt mod_ev = *event;
  1402. /*
  1403. * We were asked to remove one request. It is possible that this
  1404. * request and a few others were started together and have the same
  1405. * transfer index. Since we stopped the complete endpoint we don't
  1406. * know how many requests were already completed (and not yet)
  1407. * reported and how could be done (later). We purge them all until
  1408. * the end of the list.
  1409. */
  1410. mod_ev.status = DEPEVT_STATUS_LST;
  1411. dwc3_cleanup_done_reqs(dwc, dep, &mod_ev, -ESHUTDOWN);
  1412. dep->flags &= ~DWC3_EP_BUSY;
  1413. /* pending requests are ignored and are queued on XferNotReady */
  1414. }
  1415. static void dwc3_ep_cmd_compl(struct dwc3_ep *dep,
  1416. const struct dwc3_event_depevt *event)
  1417. {
  1418. u32 param = event->parameters;
  1419. u32 cmd_type = (param >> 8) & ((1 << 5) - 1);
  1420. switch (cmd_type) {
  1421. case DWC3_DEPCMD_ENDTRANSFER:
  1422. dwc3_process_ep_cmd_complete(dep, event);
  1423. break;
  1424. case DWC3_DEPCMD_STARTTRANSFER:
  1425. dep->res_trans_idx = param & 0x7f;
  1426. break;
  1427. default:
  1428. printk(KERN_ERR "%s() unknown /unexpected type: %d\n",
  1429. __func__, cmd_type);
  1430. break;
  1431. };
  1432. }
  1433. static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
  1434. const struct dwc3_event_depevt *event)
  1435. {
  1436. struct dwc3_ep *dep;
  1437. u8 epnum = event->endpoint_number;
  1438. dep = dwc->eps[epnum];
  1439. dev_vdbg(dwc->dev, "%s: %s\n", dep->name,
  1440. dwc3_ep_event_string(event->endpoint_event));
  1441. if (epnum == 0 || epnum == 1) {
  1442. dwc3_ep0_interrupt(dwc, event);
  1443. return;
  1444. }
  1445. switch (event->endpoint_event) {
  1446. case DWC3_DEPEVT_XFERCOMPLETE:
  1447. dep->res_trans_idx = 0;
  1448. if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
  1449. dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
  1450. dep->name);
  1451. return;
  1452. }
  1453. dwc3_endpoint_transfer_complete(dwc, dep, event, 1);
  1454. break;
  1455. case DWC3_DEPEVT_XFERINPROGRESS:
  1456. if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
  1457. dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n",
  1458. dep->name);
  1459. return;
  1460. }
  1461. dwc3_endpoint_transfer_complete(dwc, dep, event, 0);
  1462. break;
  1463. case DWC3_DEPEVT_XFERNOTREADY:
  1464. if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
  1465. dwc3_gadget_start_isoc(dwc, dep, event);
  1466. } else {
  1467. int ret;
  1468. dev_vdbg(dwc->dev, "%s: reason %s\n",
  1469. dep->name, event->status &
  1470. DEPEVT_STATUS_TRANSFER_ACTIVE
  1471. ? "Transfer Active"
  1472. : "Transfer Not Active");
  1473. ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
  1474. if (!ret || ret == -EBUSY)
  1475. return;
  1476. dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
  1477. dep->name);
  1478. }
  1479. break;
  1480. case DWC3_DEPEVT_STREAMEVT:
  1481. if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
  1482. dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
  1483. dep->name);
  1484. return;
  1485. }
  1486. switch (event->status) {
  1487. case DEPEVT_STREAMEVT_FOUND:
  1488. dev_vdbg(dwc->dev, "Stream %d found and started\n",
  1489. event->parameters);
  1490. break;
  1491. case DEPEVT_STREAMEVT_NOTFOUND:
  1492. /* FALLTHROUGH */
  1493. default:
  1494. dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
  1495. }
  1496. break;
  1497. case DWC3_DEPEVT_RXTXFIFOEVT:
  1498. dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
  1499. break;
  1500. case DWC3_DEPEVT_EPCMDCMPLT:
  1501. dwc3_ep_cmd_compl(dep, event);
  1502. break;
  1503. }
  1504. }
  1505. static void dwc3_disconnect_gadget(struct dwc3 *dwc)
  1506. {
  1507. if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
  1508. spin_unlock(&dwc->lock);
  1509. dwc->gadget_driver->disconnect(&dwc->gadget);
  1510. spin_lock(&dwc->lock);
  1511. }
  1512. }
  1513. static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum)
  1514. {
  1515. struct dwc3_ep *dep;
  1516. struct dwc3_gadget_ep_cmd_params params;
  1517. u32 cmd;
  1518. int ret;
  1519. dep = dwc->eps[epnum];
  1520. WARN_ON(!dep->res_trans_idx);
  1521. if (dep->res_trans_idx) {
  1522. cmd = DWC3_DEPCMD_ENDTRANSFER;
  1523. cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC;
  1524. cmd |= DWC3_DEPCMD_PARAM(dep->res_trans_idx);
  1525. memset(&params, 0, sizeof(params));
  1526. ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
  1527. WARN_ON_ONCE(ret);
  1528. dep->res_trans_idx = 0;
  1529. }
  1530. }
  1531. static void dwc3_stop_active_transfers(struct dwc3 *dwc)
  1532. {
  1533. u32 epnum;
  1534. for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
  1535. struct dwc3_ep *dep;
  1536. dep = dwc->eps[epnum];
  1537. if (!(dep->flags & DWC3_EP_ENABLED))
  1538. continue;
  1539. dwc3_remove_requests(dwc, dep);
  1540. }
  1541. }
  1542. static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
  1543. {
  1544. u32 epnum;
  1545. for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
  1546. struct dwc3_ep *dep;
  1547. struct dwc3_gadget_ep_cmd_params params;
  1548. int ret;
  1549. dep = dwc->eps[epnum];
  1550. if (!(dep->flags & DWC3_EP_STALL))
  1551. continue;
  1552. dep->flags &= ~DWC3_EP_STALL;
  1553. memset(&params, 0, sizeof(params));
  1554. ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
  1555. DWC3_DEPCMD_CLEARSTALL, &params);
  1556. WARN_ON_ONCE(ret);
  1557. }
  1558. }
  1559. static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
  1560. {
  1561. int reg;
  1562. dev_vdbg(dwc->dev, "%s\n", __func__);
  1563. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  1564. reg &= ~DWC3_DCTL_INITU1ENA;
  1565. dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  1566. reg &= ~DWC3_DCTL_INITU2ENA;
  1567. dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  1568. dwc3_stop_active_transfers(dwc);
  1569. dwc3_disconnect_gadget(dwc);
  1570. dwc->start_config_issued = false;
  1571. dwc->gadget.speed = USB_SPEED_UNKNOWN;
  1572. dwc->setup_packet_pending = false;
  1573. }
  1574. static void dwc3_gadget_usb3_phy_suspend(struct dwc3 *dwc, int suspend)
  1575. {
  1576. u32 reg;
  1577. reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  1578. if (suspend)
  1579. reg |= DWC3_GUSB3PIPECTL_SUSPHY;
  1580. else
  1581. reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
  1582. dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  1583. }
  1584. static void dwc3_gadget_usb2_phy_suspend(struct dwc3 *dwc, int suspend)
  1585. {
  1586. u32 reg;
  1587. reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  1588. if (suspend)
  1589. reg |= DWC3_GUSB2PHYCFG_SUSPHY;
  1590. else
  1591. reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
  1592. dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  1593. }
  1594. static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
  1595. {
  1596. u32 reg;
  1597. dev_vdbg(dwc->dev, "%s\n", __func__);
  1598. /*
  1599. * WORKAROUND: DWC3 revisions <1.88a have an issue which
  1600. * would cause a missing Disconnect Event if there's a
  1601. * pending Setup Packet in the FIFO.
  1602. *
  1603. * There's no suggested workaround on the official Bug
  1604. * report, which states that "unless the driver/application
  1605. * is doing any special handling of a disconnect event,
  1606. * there is no functional issue".
  1607. *
  1608. * Unfortunately, it turns out that we _do_ some special
  1609. * handling of a disconnect event, namely complete all
  1610. * pending transfers, notify gadget driver of the
  1611. * disconnection, and so on.
  1612. *
  1613. * Our suggested workaround is to follow the Disconnect
  1614. * Event steps here, instead, based on a setup_packet_pending
  1615. * flag. Such flag gets set whenever we have a XferNotReady
  1616. * event on EP0 and gets cleared on XferComplete for the
  1617. * same endpoint.
  1618. *
  1619. * Refers to:
  1620. *
  1621. * STAR#9000466709: RTL: Device : Disconnect event not
  1622. * generated if setup packet pending in FIFO
  1623. */
  1624. if (dwc->revision < DWC3_REVISION_188A) {
  1625. if (dwc->setup_packet_pending)
  1626. dwc3_gadget_disconnect_interrupt(dwc);
  1627. }
  1628. /* after reset -> Default State */
  1629. dwc->dev_state = DWC3_DEFAULT_STATE;
  1630. /* Recent versions support automatic phy suspend and don't need this */
  1631. if (dwc->revision < DWC3_REVISION_194A) {
  1632. /* Resume PHYs */
  1633. dwc3_gadget_usb2_phy_suspend(dwc, false);
  1634. dwc3_gadget_usb3_phy_suspend(dwc, false);
  1635. }
  1636. if (dwc->gadget.speed != USB_SPEED_UNKNOWN)
  1637. dwc3_disconnect_gadget(dwc);
  1638. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  1639. reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  1640. reg &= ~(DWC3_DCTL_INITU1ENA | DWC3_DCTL_INITU2ENA);
  1641. reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
  1642. dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  1643. dwc->test_mode = false;
  1644. dwc3_stop_active_transfers(dwc);
  1645. dwc3_clear_stall_all_ep(dwc);
  1646. dwc->start_config_issued = false;
  1647. /* Reset device address to zero */
  1648. reg = dwc3_readl(dwc->regs, DWC3_DCFG);
  1649. reg &= ~(DWC3_DCFG_DEVADDR_MASK);
  1650. dwc3_writel(dwc->regs, DWC3_DCFG, reg);
  1651. }
  1652. static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
  1653. {
  1654. u32 reg;
  1655. u32 usb30_clock = DWC3_GCTL_CLK_BUS;
  1656. /*
  1657. * We change the clock only at SS but I dunno why I would want to do
  1658. * this. Maybe it becomes part of the power saving plan.
  1659. */
  1660. if (speed != DWC3_DSTS_SUPERSPEED)
  1661. return;
  1662. /*
  1663. * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
  1664. * each time on Connect Done.
  1665. */
  1666. if (!usb30_clock)
  1667. return;
  1668. reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  1669. reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
  1670. dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  1671. }
  1672. static void dwc3_gadget_phy_suspend(struct dwc3 *dwc, u8 speed)
  1673. {
  1674. switch (speed) {
  1675. case USB_SPEED_SUPER:
  1676. dwc3_gadget_usb2_phy_suspend(dwc, true);
  1677. break;
  1678. case USB_SPEED_HIGH:
  1679. case USB_SPEED_FULL:
  1680. case USB_SPEED_LOW:
  1681. dwc3_gadget_usb3_phy_suspend(dwc, true);
  1682. break;
  1683. }
  1684. }
  1685. static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
  1686. {
  1687. struct dwc3_gadget_ep_cmd_params params;
  1688. struct dwc3_ep *dep;
  1689. int ret;
  1690. u32 reg;
  1691. u8 speed;
  1692. dev_vdbg(dwc->dev, "%s\n", __func__);
  1693. memset(&params, 0x00, sizeof(params));
  1694. reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  1695. speed = reg & DWC3_DSTS_CONNECTSPD;
  1696. dwc->speed = speed;
  1697. dwc3_update_ram_clk_sel(dwc, speed);
  1698. switch (speed) {
  1699. case DWC3_DCFG_SUPERSPEED:
  1700. /*
  1701. * WORKAROUND: DWC3 revisions <1.90a have an issue which
  1702. * would cause a missing USB3 Reset event.
  1703. *
  1704. * In such situations, we should force a USB3 Reset
  1705. * event by calling our dwc3_gadget_reset_interrupt()
  1706. * routine.
  1707. *
  1708. * Refers to:
  1709. *
  1710. * STAR#9000483510: RTL: SS : USB3 reset event may
  1711. * not be generated always when the link enters poll
  1712. */
  1713. if (dwc->revision < DWC3_REVISION_190A)
  1714. dwc3_gadget_reset_interrupt(dwc);
  1715. dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
  1716. dwc->gadget.ep0->maxpacket = 512;
  1717. dwc->gadget.speed = USB_SPEED_SUPER;
  1718. break;
  1719. case DWC3_DCFG_HIGHSPEED:
  1720. dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
  1721. dwc->gadget.ep0->maxpacket = 64;
  1722. dwc->gadget.speed = USB_SPEED_HIGH;
  1723. break;
  1724. case DWC3_DCFG_FULLSPEED2:
  1725. case DWC3_DCFG_FULLSPEED1:
  1726. dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
  1727. dwc->gadget.ep0->maxpacket = 64;
  1728. dwc->gadget.speed = USB_SPEED_FULL;
  1729. break;
  1730. case DWC3_DCFG_LOWSPEED:
  1731. dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
  1732. dwc->gadget.ep0->maxpacket = 8;
  1733. dwc->gadget.speed = USB_SPEED_LOW;
  1734. break;
  1735. }
  1736. /* Recent versions support automatic phy suspend and don't need this */
  1737. if (dwc->revision < DWC3_REVISION_194A) {
  1738. /* Suspend unneeded PHY */
  1739. dwc3_gadget_phy_suspend(dwc, dwc->gadget.speed);
  1740. }
  1741. dep = dwc->eps[0];
  1742. ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
  1743. if (ret) {
  1744. dev_err(dwc->dev, "failed to enable %s\n", dep->name);
  1745. return;
  1746. }
  1747. dep = dwc->eps[1];
  1748. ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
  1749. if (ret) {
  1750. dev_err(dwc->dev, "failed to enable %s\n", dep->name);
  1751. return;
  1752. }
  1753. /*
  1754. * Configure PHY via GUSB3PIPECTLn if required.
  1755. *
  1756. * Update GTXFIFOSIZn
  1757. *
  1758. * In both cases reset values should be sufficient.
  1759. */
  1760. }
  1761. static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
  1762. {
  1763. dev_vdbg(dwc->dev, "%s\n", __func__);
  1764. /*
  1765. * TODO take core out of low power mode when that's
  1766. * implemented.
  1767. */
  1768. dwc->gadget_driver->resume(&dwc->gadget);
  1769. }
  1770. static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
  1771. unsigned int evtinfo)
  1772. {
  1773. enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
  1774. /*
  1775. * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
  1776. * on the link partner, the USB session might do multiple entry/exit
  1777. * of low power states before a transfer takes place.
  1778. *
  1779. * Due to this problem, we might experience lower throughput. The
  1780. * suggested workaround is to disable DCTL[12:9] bits if we're
  1781. * transitioning from U1/U2 to U0 and enable those bits again
  1782. * after a transfer completes and there are no pending transfers
  1783. * on any of the enabled endpoints.
  1784. *
  1785. * This is the first half of that workaround.
  1786. *
  1787. * Refers to:
  1788. *
  1789. * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
  1790. * core send LGO_Ux entering U0
  1791. */
  1792. if (dwc->revision < DWC3_REVISION_183A) {
  1793. if (next == DWC3_LINK_STATE_U0) {
  1794. u32 u1u2;
  1795. u32 reg;
  1796. switch (dwc->link_state) {
  1797. case DWC3_LINK_STATE_U1:
  1798. case DWC3_LINK_STATE_U2:
  1799. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  1800. u1u2 = reg & (DWC3_DCTL_INITU2ENA
  1801. | DWC3_DCTL_ACCEPTU2ENA
  1802. | DWC3_DCTL_INITU1ENA
  1803. | DWC3_DCTL_ACCEPTU1ENA);
  1804. if (!dwc->u1u2)
  1805. dwc->u1u2 = reg & u1u2;
  1806. reg &= ~u1u2;
  1807. dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  1808. break;
  1809. default:
  1810. /* do nothing */
  1811. break;
  1812. }
  1813. }
  1814. }
  1815. dwc->link_state = next;
  1816. dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state);
  1817. }
  1818. static void dwc3_gadget_interrupt(struct dwc3 *dwc,
  1819. const struct dwc3_event_devt *event)
  1820. {
  1821. switch (event->type) {
  1822. case DWC3_DEVICE_EVENT_DISCONNECT:
  1823. dwc3_gadget_disconnect_interrupt(dwc);
  1824. break;
  1825. case DWC3_DEVICE_EVENT_RESET:
  1826. dwc3_gadget_reset_interrupt(dwc);
  1827. break;
  1828. case DWC3_DEVICE_EVENT_CONNECT_DONE:
  1829. dwc3_gadget_conndone_interrupt(dwc);
  1830. break;
  1831. case DWC3_DEVICE_EVENT_WAKEUP:
  1832. dwc3_gadget_wakeup_interrupt(dwc);
  1833. break;
  1834. case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
  1835. dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
  1836. break;
  1837. case DWC3_DEVICE_EVENT_EOPF:
  1838. dev_vdbg(dwc->dev, "End of Periodic Frame\n");
  1839. break;
  1840. case DWC3_DEVICE_EVENT_SOF:
  1841. dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
  1842. break;
  1843. case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
  1844. dev_vdbg(dwc->dev, "Erratic Error\n");
  1845. break;
  1846. case DWC3_DEVICE_EVENT_CMD_CMPL:
  1847. dev_vdbg(dwc->dev, "Command Complete\n");
  1848. break;
  1849. case DWC3_DEVICE_EVENT_OVERFLOW:
  1850. dev_vdbg(dwc->dev, "Overflow\n");
  1851. break;
  1852. default:
  1853. dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
  1854. }
  1855. }
  1856. static void dwc3_process_event_entry(struct dwc3 *dwc,
  1857. const union dwc3_event *event)
  1858. {
  1859. /* Endpoint IRQ, handle it and return early */
  1860. if (event->type.is_devspec == 0) {
  1861. /* depevt */
  1862. return dwc3_endpoint_interrupt(dwc, &event->depevt);
  1863. }
  1864. switch (event->type.type) {
  1865. case DWC3_EVENT_TYPE_DEV:
  1866. dwc3_gadget_interrupt(dwc, &event->devt);
  1867. break;
  1868. /* REVISIT what to do with Carkit and I2C events ? */
  1869. default:
  1870. dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
  1871. }
  1872. }
  1873. static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
  1874. {
  1875. struct dwc3_event_buffer *evt;
  1876. int left;
  1877. u32 count;
  1878. count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
  1879. count &= DWC3_GEVNTCOUNT_MASK;
  1880. if (!count)
  1881. return IRQ_NONE;
  1882. evt = dwc->ev_buffs[buf];
  1883. left = count;
  1884. while (left > 0) {
  1885. union dwc3_event event;
  1886. event.raw = *(u32 *) (evt->buf + evt->lpos);
  1887. dwc3_process_event_entry(dwc, &event);
  1888. /*
  1889. * XXX we wrap around correctly to the next entry as almost all
  1890. * entries are 4 bytes in size. There is one entry which has 12
  1891. * bytes which is a regular entry followed by 8 bytes data. ATM
  1892. * I don't know how things are organized if were get next to the
  1893. * a boundary so I worry about that once we try to handle that.
  1894. */
  1895. evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
  1896. left -= 4;
  1897. dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
  1898. }
  1899. return IRQ_HANDLED;
  1900. }
  1901. static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
  1902. {
  1903. struct dwc3 *dwc = _dwc;
  1904. int i;
  1905. irqreturn_t ret = IRQ_NONE;
  1906. spin_lock(&dwc->lock);
  1907. for (i = 0; i < dwc->num_event_buffers; i++) {
  1908. irqreturn_t status;
  1909. status = dwc3_process_event_buf(dwc, i);
  1910. if (status == IRQ_HANDLED)
  1911. ret = status;
  1912. }
  1913. spin_unlock(&dwc->lock);
  1914. return ret;
  1915. }
  1916. /**
  1917. * dwc3_gadget_init - Initializes gadget related registers
  1918. * @dwc: pointer to our controller context structure
  1919. *
  1920. * Returns 0 on success otherwise negative errno.
  1921. */
  1922. int __devinit dwc3_gadget_init(struct dwc3 *dwc)
  1923. {
  1924. u32 reg;
  1925. int ret;
  1926. int irq;
  1927. dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
  1928. &dwc->ctrl_req_addr, GFP_KERNEL);
  1929. if (!dwc->ctrl_req) {
  1930. dev_err(dwc->dev, "failed to allocate ctrl request\n");
  1931. ret = -ENOMEM;
  1932. goto err0;
  1933. }
  1934. dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
  1935. &dwc->ep0_trb_addr, GFP_KERNEL);
  1936. if (!dwc->ep0_trb) {
  1937. dev_err(dwc->dev, "failed to allocate ep0 trb\n");
  1938. ret = -ENOMEM;
  1939. goto err1;
  1940. }
  1941. dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
  1942. if (!dwc->setup_buf) {
  1943. dev_err(dwc->dev, "failed to allocate setup buffer\n");
  1944. ret = -ENOMEM;
  1945. goto err2;
  1946. }
  1947. dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
  1948. DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
  1949. GFP_KERNEL);
  1950. if (!dwc->ep0_bounce) {
  1951. dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
  1952. ret = -ENOMEM;
  1953. goto err3;
  1954. }
  1955. dev_set_name(&dwc->gadget.dev, "gadget");
  1956. dwc->gadget.ops = &dwc3_gadget_ops;
  1957. dwc->gadget.max_speed = USB_SPEED_SUPER;
  1958. dwc->gadget.speed = USB_SPEED_UNKNOWN;
  1959. dwc->gadget.dev.parent = dwc->dev;
  1960. dwc->gadget.sg_supported = true;
  1961. dma_set_coherent_mask(&dwc->gadget.dev, dwc->dev->coherent_dma_mask);
  1962. dwc->gadget.dev.dma_parms = dwc->dev->dma_parms;
  1963. dwc->gadget.dev.dma_mask = dwc->dev->dma_mask;
  1964. dwc->gadget.dev.release = dwc3_gadget_release;
  1965. dwc->gadget.name = "dwc3-gadget";
  1966. /*
  1967. * REVISIT: Here we should clear all pending IRQs to be
  1968. * sure we're starting from a well known location.
  1969. */
  1970. ret = dwc3_gadget_init_endpoints(dwc);
  1971. if (ret)
  1972. goto err4;
  1973. irq = platform_get_irq(to_platform_device(dwc->dev), 0);
  1974. ret = request_irq(irq, dwc3_interrupt, IRQF_SHARED,
  1975. "dwc3", dwc);
  1976. if (ret) {
  1977. dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
  1978. irq, ret);
  1979. goto err5;
  1980. }
  1981. reg = dwc3_readl(dwc->regs, DWC3_DCFG);
  1982. reg |= DWC3_DCFG_LPM_CAP;
  1983. dwc3_writel(dwc->regs, DWC3_DCFG, reg);
  1984. /* Enable all but Start and End of Frame IRQs */
  1985. reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
  1986. DWC3_DEVTEN_EVNTOVERFLOWEN |
  1987. DWC3_DEVTEN_CMDCMPLTEN |
  1988. DWC3_DEVTEN_ERRTICERREN |
  1989. DWC3_DEVTEN_WKUPEVTEN |
  1990. DWC3_DEVTEN_ULSTCNGEN |
  1991. DWC3_DEVTEN_CONNECTDONEEN |
  1992. DWC3_DEVTEN_USBRSTEN |
  1993. DWC3_DEVTEN_DISCONNEVTEN);
  1994. dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
  1995. /* Enable USB2 LPM and automatic phy suspend only on recent versions */
  1996. if (dwc->revision >= DWC3_REVISION_194A) {
  1997. reg = dwc3_readl(dwc->regs, DWC3_DCFG);
  1998. reg |= DWC3_DCFG_LPM_CAP;
  1999. dwc3_writel(dwc->regs, DWC3_DCFG, reg);
  2000. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  2001. reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
  2002. /* TODO: This should be configurable */
  2003. reg |= DWC3_DCTL_HIRD_THRES(31);
  2004. dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  2005. dwc3_gadget_usb2_phy_suspend(dwc, true);
  2006. dwc3_gadget_usb3_phy_suspend(dwc, true);
  2007. }
  2008. ret = device_register(&dwc->gadget.dev);
  2009. if (ret) {
  2010. dev_err(dwc->dev, "failed to register gadget device\n");
  2011. put_device(&dwc->gadget.dev);
  2012. goto err6;
  2013. }
  2014. ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
  2015. if (ret) {
  2016. dev_err(dwc->dev, "failed to register udc\n");
  2017. goto err7;
  2018. }
  2019. return 0;
  2020. err7:
  2021. device_unregister(&dwc->gadget.dev);
  2022. err6:
  2023. dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
  2024. free_irq(irq, dwc);
  2025. err5:
  2026. dwc3_gadget_free_endpoints(dwc);
  2027. err4:
  2028. dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
  2029. dwc->ep0_bounce, dwc->ep0_bounce_addr);
  2030. err3:
  2031. kfree(dwc->setup_buf);
  2032. err2:
  2033. dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
  2034. dwc->ep0_trb, dwc->ep0_trb_addr);
  2035. err1:
  2036. dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
  2037. dwc->ctrl_req, dwc->ctrl_req_addr);
  2038. err0:
  2039. return ret;
  2040. }
  2041. void dwc3_gadget_exit(struct dwc3 *dwc)
  2042. {
  2043. int irq;
  2044. usb_del_gadget_udc(&dwc->gadget);
  2045. irq = platform_get_irq(to_platform_device(dwc->dev), 0);
  2046. dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
  2047. free_irq(irq, dwc);
  2048. dwc3_gadget_free_endpoints(dwc);
  2049. dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
  2050. dwc->ep0_bounce, dwc->ep0_bounce_addr);
  2051. kfree(dwc->setup_buf);
  2052. dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
  2053. dwc->ep0_trb, dwc->ep0_trb_addr);
  2054. dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
  2055. dwc->ctrl_req, dwc->ctrl_req_addr);
  2056. device_unregister(&dwc->gadget.dev);
  2057. }