pm.c 4.4 KB

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  1. /*
  2. * CPU complex suspend & resume functions for Tegra SoCs
  3. *
  4. * Copyright (c) 2009-2012, NVIDIA Corporation. All rights reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms and conditions of the GNU General Public License,
  8. * version 2, as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #include <linux/kernel.h>
  19. #include <linux/spinlock.h>
  20. #include <linux/io.h>
  21. #include <linux/cpumask.h>
  22. #include <linux/delay.h>
  23. #include <linux/cpu_pm.h>
  24. #include <linux/clk.h>
  25. #include <linux/err.h>
  26. #include <linux/clk/tegra.h>
  27. #include <asm/smp_plat.h>
  28. #include <asm/cacheflush.h>
  29. #include <asm/suspend.h>
  30. #include <asm/idmap.h>
  31. #include <asm/proc-fns.h>
  32. #include <asm/tlbflush.h>
  33. #include "iomap.h"
  34. #include "reset.h"
  35. #include "flowctrl.h"
  36. #include "fuse.h"
  37. #include "sleep.h"
  38. #define TEGRA_POWER_CPU_PWRREQ_OE (1 << 16) /* CPU pwr req enable */
  39. #define PMC_CTRL 0x0
  40. #define PMC_CPUPWRGOOD_TIMER 0xc8
  41. #define PMC_CPUPWROFF_TIMER 0xcc
  42. #ifdef CONFIG_PM_SLEEP
  43. static DEFINE_SPINLOCK(tegra_lp2_lock);
  44. static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
  45. static struct clk *tegra_pclk;
  46. void (*tegra_tear_down_cpu)(void);
  47. static void set_power_timers(unsigned long us_on, unsigned long us_off)
  48. {
  49. unsigned long long ticks;
  50. unsigned long long pclk;
  51. unsigned long rate;
  52. static unsigned long tegra_last_pclk;
  53. if (tegra_pclk == NULL) {
  54. tegra_pclk = clk_get_sys(NULL, "pclk");
  55. WARN_ON(IS_ERR(tegra_pclk));
  56. }
  57. rate = clk_get_rate(tegra_pclk);
  58. if (WARN_ON_ONCE(rate <= 0))
  59. pclk = 100000000;
  60. else
  61. pclk = rate;
  62. if ((rate != tegra_last_pclk)) {
  63. ticks = (us_on * pclk) + 999999ull;
  64. do_div(ticks, 1000000);
  65. writel((unsigned long)ticks, pmc + PMC_CPUPWRGOOD_TIMER);
  66. ticks = (us_off * pclk) + 999999ull;
  67. do_div(ticks, 1000000);
  68. writel((unsigned long)ticks, pmc + PMC_CPUPWROFF_TIMER);
  69. wmb();
  70. }
  71. tegra_last_pclk = pclk;
  72. }
  73. /*
  74. * restore_cpu_complex
  75. *
  76. * restores cpu clock setting, clears flow controller
  77. *
  78. * Always called on CPU 0.
  79. */
  80. static void restore_cpu_complex(void)
  81. {
  82. int cpu = smp_processor_id();
  83. BUG_ON(cpu != 0);
  84. #ifdef CONFIG_SMP
  85. cpu = cpu_logical_map(cpu);
  86. #endif
  87. /* Restore the CPU clock settings */
  88. tegra_cpu_clock_resume();
  89. flowctrl_cpu_suspend_exit(cpu);
  90. }
  91. /*
  92. * suspend_cpu_complex
  93. *
  94. * saves pll state for use by restart_plls, prepares flow controller for
  95. * transition to suspend state
  96. *
  97. * Must always be called on cpu 0.
  98. */
  99. static void suspend_cpu_complex(void)
  100. {
  101. int cpu = smp_processor_id();
  102. BUG_ON(cpu != 0);
  103. #ifdef CONFIG_SMP
  104. cpu = cpu_logical_map(cpu);
  105. #endif
  106. /* Save the CPU clock settings */
  107. tegra_cpu_clock_suspend();
  108. flowctrl_cpu_suspend_enter(cpu);
  109. }
  110. void tegra_clear_cpu_in_lp2(int phy_cpu_id)
  111. {
  112. u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;
  113. spin_lock(&tegra_lp2_lock);
  114. BUG_ON(!(*cpu_in_lp2 & BIT(phy_cpu_id)));
  115. *cpu_in_lp2 &= ~BIT(phy_cpu_id);
  116. spin_unlock(&tegra_lp2_lock);
  117. }
  118. bool tegra_set_cpu_in_lp2(int phy_cpu_id)
  119. {
  120. bool last_cpu = false;
  121. cpumask_t *cpu_lp2_mask = tegra_cpu_lp2_mask;
  122. u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;
  123. spin_lock(&tegra_lp2_lock);
  124. BUG_ON((*cpu_in_lp2 & BIT(phy_cpu_id)));
  125. *cpu_in_lp2 |= BIT(phy_cpu_id);
  126. if ((phy_cpu_id == 0) && cpumask_equal(cpu_lp2_mask, cpu_online_mask))
  127. last_cpu = true;
  128. else if (tegra_chip_id == TEGRA20 && phy_cpu_id == 1)
  129. tegra20_cpu_set_resettable_soon();
  130. spin_unlock(&tegra_lp2_lock);
  131. return last_cpu;
  132. }
  133. int tegra_cpu_do_idle(void)
  134. {
  135. return cpu_do_idle();
  136. }
  137. static int tegra_sleep_cpu(unsigned long v2p)
  138. {
  139. /* Switch to the identity mapping. */
  140. cpu_switch_mm(idmap_pgd, &init_mm);
  141. /* Flush the TLB. */
  142. local_flush_tlb_all();
  143. tegra_sleep_cpu_finish(v2p);
  144. /* should never here */
  145. BUG();
  146. return 0;
  147. }
  148. void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time)
  149. {
  150. u32 mode;
  151. /* Only the last cpu down does the final suspend steps */
  152. mode = readl(pmc + PMC_CTRL);
  153. mode |= TEGRA_POWER_CPU_PWRREQ_OE;
  154. writel(mode, pmc + PMC_CTRL);
  155. set_power_timers(cpu_on_time, cpu_off_time);
  156. cpu_cluster_pm_enter();
  157. suspend_cpu_complex();
  158. cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu);
  159. restore_cpu_complex();
  160. cpu_cluster_pm_exit();
  161. }
  162. #endif