ezbrd.c 18 KB

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  1. /*
  2. * File: arch/blackfin/mach-bf518/boards/ezbrd.c
  3. * Based on: arch/blackfin/mach-bf527/boards/ezbrd.c
  4. * Author: Bryan Wu <cooloney@kernel.org>
  5. *
  6. * Created:
  7. * Description:
  8. *
  9. * Modified:
  10. * Copyright 2005 National ICT Australia (NICTA)
  11. * Copyright 2004-2008 Analog Devices Inc.
  12. *
  13. * Bugs: Enter bugs at http://blackfin.uclinux.org/
  14. *
  15. * This program is free software; you can redistribute it and/or modify
  16. * it under the terms of the GNU General Public License as published by
  17. * the Free Software Foundation; either version 2 of the License, or
  18. * (at your option) any later version.
  19. *
  20. * This program is distributed in the hope that it will be useful,
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU General Public License for more details.
  24. *
  25. * You should have received a copy of the GNU General Public License
  26. * along with this program; if not, see the file COPYING, or write
  27. * to the Free Software Foundation, Inc.,
  28. * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  29. */
  30. #include <linux/device.h>
  31. #include <linux/platform_device.h>
  32. #include <linux/mtd/mtd.h>
  33. #include <linux/mtd/partitions.h>
  34. #include <linux/mtd/physmap.h>
  35. #include <linux/spi/spi.h>
  36. #include <linux/spi/flash.h>
  37. #include <linux/i2c.h>
  38. #include <linux/irq.h>
  39. #include <linux/interrupt.h>
  40. #include <asm/dma.h>
  41. #include <asm/bfin5xx_spi.h>
  42. #include <asm/reboot.h>
  43. #include <asm/portmux.h>
  44. #include <asm/dpmc.h>
  45. #include <asm/bfin_sdh.h>
  46. #include <linux/spi/ad7877.h>
  47. #include <net/dsa.h>
  48. /*
  49. * Name the Board for the /proc/cpuinfo
  50. */
  51. const char bfin_board_name[] = "ADI BF518F-EZBRD";
  52. /*
  53. * Driver needs to know address, irq and flag pin.
  54. */
  55. #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
  56. static struct mtd_partition ezbrd_partitions[] = {
  57. {
  58. .name = "bootloader(nor)",
  59. .size = 0x40000,
  60. .offset = 0,
  61. }, {
  62. .name = "linux kernel(nor)",
  63. .size = 0x1C0000,
  64. .offset = MTDPART_OFS_APPEND,
  65. }, {
  66. .name = "file system(nor)",
  67. .size = MTDPART_SIZ_FULL,
  68. .offset = MTDPART_OFS_APPEND,
  69. }
  70. };
  71. static struct physmap_flash_data ezbrd_flash_data = {
  72. .width = 2,
  73. .parts = ezbrd_partitions,
  74. .nr_parts = ARRAY_SIZE(ezbrd_partitions),
  75. };
  76. static struct resource ezbrd_flash_resource = {
  77. .start = 0x20000000,
  78. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  79. .end = 0x202fffff,
  80. #else
  81. .end = 0x203fffff,
  82. #endif
  83. .flags = IORESOURCE_MEM,
  84. };
  85. static struct platform_device ezbrd_flash_device = {
  86. .name = "physmap-flash",
  87. .id = 0,
  88. .dev = {
  89. .platform_data = &ezbrd_flash_data,
  90. },
  91. .num_resources = 1,
  92. .resource = &ezbrd_flash_resource,
  93. };
  94. #endif
  95. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  96. static struct platform_device rtc_device = {
  97. .name = "rtc-bfin",
  98. .id = -1,
  99. };
  100. #endif
  101. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  102. static struct platform_device bfin_mii_bus = {
  103. .name = "bfin_mii_bus",
  104. };
  105. static struct platform_device bfin_mac_device = {
  106. .name = "bfin_mac",
  107. .dev.platform_data = &bfin_mii_bus,
  108. };
  109. #if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
  110. static struct dsa_chip_data ksz8893m_switch_chip_data = {
  111. .mii_bus = &bfin_mii_bus.dev,
  112. .port_names = {
  113. NULL,
  114. "eth%d",
  115. "eth%d",
  116. "cpu",
  117. },
  118. };
  119. static struct dsa_platform_data ksz8893m_switch_data = {
  120. .nr_chips = 1,
  121. .netdev = &bfin_mac_device.dev,
  122. .chip = &ksz8893m_switch_chip_data,
  123. };
  124. static struct platform_device ksz8893m_switch_device = {
  125. .name = "dsa",
  126. .id = 0,
  127. .num_resources = 0,
  128. .dev.platform_data = &ksz8893m_switch_data,
  129. };
  130. #endif
  131. #endif
  132. #if defined(CONFIG_MTD_M25P80) \
  133. || defined(CONFIG_MTD_M25P80_MODULE)
  134. static struct mtd_partition bfin_spi_flash_partitions[] = {
  135. {
  136. .name = "bootloader(spi)",
  137. .size = 0x00040000,
  138. .offset = 0,
  139. .mask_flags = MTD_CAP_ROM
  140. }, {
  141. .name = "linux kernel(spi)",
  142. .size = MTDPART_SIZ_FULL,
  143. .offset = MTDPART_OFS_APPEND,
  144. }
  145. };
  146. static struct flash_platform_data bfin_spi_flash_data = {
  147. .name = "m25p80",
  148. .parts = bfin_spi_flash_partitions,
  149. .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
  150. .type = "m25p16",
  151. };
  152. /* SPI flash chip (m25p64) */
  153. static struct bfin5xx_spi_chip spi_flash_chip_info = {
  154. .enable_dma = 0, /* use dma transfer with this chip*/
  155. .bits_per_word = 8,
  156. };
  157. #endif
  158. #if defined(CONFIG_BFIN_SPI_ADC) \
  159. || defined(CONFIG_BFIN_SPI_ADC_MODULE)
  160. /* SPI ADC chip */
  161. static struct bfin5xx_spi_chip spi_adc_chip_info = {
  162. .enable_dma = 1, /* use dma transfer with this chip*/
  163. .bits_per_word = 16,
  164. };
  165. #endif
  166. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  167. #if defined(CONFIG_NET_DSA_KSZ8893M) \
  168. || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
  169. /* SPI SWITCH CHIP */
  170. static struct bfin5xx_spi_chip spi_switch_info = {
  171. .enable_dma = 0,
  172. .bits_per_word = 8,
  173. };
  174. #endif
  175. #endif
  176. #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
  177. static struct bfin5xx_spi_chip mmc_spi_chip_info = {
  178. .enable_dma = 0,
  179. .bits_per_word = 8,
  180. };
  181. #endif
  182. #if defined(CONFIG_PBX)
  183. static struct bfin5xx_spi_chip spi_si3xxx_chip_info = {
  184. .ctl_reg = 0x4, /* send zero */
  185. .enable_dma = 0,
  186. .bits_per_word = 8,
  187. .cs_change_per_word = 1,
  188. };
  189. #endif
  190. #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
  191. static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
  192. .enable_dma = 0,
  193. .bits_per_word = 16,
  194. };
  195. static const struct ad7877_platform_data bfin_ad7877_ts_info = {
  196. .model = 7877,
  197. .vref_delay_usecs = 50, /* internal, no capacitor */
  198. .x_plate_ohms = 419,
  199. .y_plate_ohms = 486,
  200. .pressure_max = 1000,
  201. .pressure_min = 0,
  202. .stopacq_polarity = 1,
  203. .first_conversion_delay = 3,
  204. .acquisition_time = 1,
  205. .averaging = 1,
  206. .pen_down_acc_interval = 1,
  207. };
  208. #endif
  209. #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
  210. && defined(CONFIG_SND_SOC_WM8731_SPI)
  211. static struct bfin5xx_spi_chip spi_wm8731_chip_info = {
  212. .enable_dma = 0,
  213. .bits_per_word = 16,
  214. };
  215. #endif
  216. #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
  217. static struct bfin5xx_spi_chip spidev_chip_info = {
  218. .enable_dma = 0,
  219. .bits_per_word = 8,
  220. };
  221. #endif
  222. static struct spi_board_info bfin_spi_board_info[] __initdata = {
  223. #if defined(CONFIG_MTD_M25P80) \
  224. || defined(CONFIG_MTD_M25P80_MODULE)
  225. {
  226. /* the modalias must be the same as spi device driver name */
  227. .modalias = "m25p80", /* Name of spi_driver for this device */
  228. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  229. .bus_num = 0, /* Framework bus number */
  230. .chip_select = 2, /* On BF518F-EZBRD it's SPI0_SSEL2 */
  231. .platform_data = &bfin_spi_flash_data,
  232. .controller_data = &spi_flash_chip_info,
  233. .mode = SPI_MODE_3,
  234. },
  235. #endif
  236. #if defined(CONFIG_BFIN_SPI_ADC) \
  237. || defined(CONFIG_BFIN_SPI_ADC_MODULE)
  238. {
  239. .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
  240. .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
  241. .bus_num = 0, /* Framework bus number */
  242. .chip_select = 1, /* Framework chip select. */
  243. .platform_data = NULL, /* No spi_driver specific config */
  244. .controller_data = &spi_adc_chip_info,
  245. },
  246. #endif
  247. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  248. #if defined(CONFIG_NET_DSA_KSZ8893M) \
  249. || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
  250. {
  251. .modalias = "ksz8893m",
  252. .max_speed_hz = 5000000,
  253. .bus_num = 0,
  254. .chip_select = 1,
  255. .platform_data = NULL,
  256. .controller_data = &spi_switch_info,
  257. .mode = SPI_MODE_3,
  258. },
  259. #endif
  260. #endif
  261. #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
  262. {
  263. .modalias = "mmc_spi",
  264. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  265. .bus_num = 0,
  266. .chip_select = 5,
  267. .controller_data = &mmc_spi_chip_info,
  268. .mode = SPI_MODE_3,
  269. },
  270. #endif
  271. #if defined(CONFIG_PBX)
  272. {
  273. .modalias = "fxs-spi",
  274. .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
  275. .bus_num = 0,
  276. .chip_select = 8 - CONFIG_J11_JUMPER,
  277. .controller_data = &spi_si3xxx_chip_info,
  278. .mode = SPI_MODE_3,
  279. },
  280. {
  281. .modalias = "fxo-spi",
  282. .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
  283. .bus_num = 0,
  284. .chip_select = 8 - CONFIG_J19_JUMPER,
  285. .controller_data = &spi_si3xxx_chip_info,
  286. .mode = SPI_MODE_3,
  287. },
  288. #endif
  289. #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
  290. {
  291. .modalias = "ad7877",
  292. .platform_data = &bfin_ad7877_ts_info,
  293. .irq = IRQ_PF8,
  294. .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
  295. .bus_num = 0,
  296. .chip_select = 2,
  297. .controller_data = &spi_ad7877_chip_info,
  298. },
  299. #endif
  300. #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
  301. && defined(CONFIG_SND_SOC_WM8731_SPI)
  302. {
  303. .modalias = "wm8731",
  304. .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
  305. .bus_num = 0,
  306. .chip_select = 5,
  307. .controller_data = &spi_wm8731_chip_info,
  308. .mode = SPI_MODE_0,
  309. },
  310. #endif
  311. #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
  312. {
  313. .modalias = "spidev",
  314. .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
  315. .bus_num = 0,
  316. .chip_select = 1,
  317. .controller_data = &spidev_chip_info,
  318. },
  319. #endif
  320. #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
  321. {
  322. .modalias = "bfin-lq035q1-spi",
  323. .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
  324. .bus_num = 0,
  325. .chip_select = 1,
  326. .controller_data = &lq035q1_spi_chip_info,
  327. .mode = SPI_CPHA | SPI_CPOL,
  328. },
  329. #endif
  330. };
  331. /* SPI controller data */
  332. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  333. /* SPI (0) */
  334. static struct bfin5xx_spi_master bfin_spi0_info = {
  335. .num_chipselect = 5,
  336. .enable_dma = 1, /* master has the ability to do dma transfer */
  337. .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
  338. };
  339. static struct resource bfin_spi0_resource[] = {
  340. [0] = {
  341. .start = SPI0_REGBASE,
  342. .end = SPI0_REGBASE + 0xFF,
  343. .flags = IORESOURCE_MEM,
  344. },
  345. [1] = {
  346. .start = CH_SPI0,
  347. .end = CH_SPI0,
  348. .flags = IORESOURCE_DMA,
  349. },
  350. [2] = {
  351. .start = IRQ_SPI0,
  352. .end = IRQ_SPI0,
  353. .flags = IORESOURCE_IRQ,
  354. },
  355. };
  356. static struct platform_device bfin_spi0_device = {
  357. .name = "bfin-spi",
  358. .id = 0, /* Bus number */
  359. .num_resources = ARRAY_SIZE(bfin_spi0_resource),
  360. .resource = bfin_spi0_resource,
  361. .dev = {
  362. .platform_data = &bfin_spi0_info, /* Passed to driver */
  363. },
  364. };
  365. /* SPI (1) */
  366. static struct bfin5xx_spi_master bfin_spi1_info = {
  367. .num_chipselect = 5,
  368. .enable_dma = 1, /* master has the ability to do dma transfer */
  369. .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
  370. };
  371. static struct resource bfin_spi1_resource[] = {
  372. [0] = {
  373. .start = SPI1_REGBASE,
  374. .end = SPI1_REGBASE + 0xFF,
  375. .flags = IORESOURCE_MEM,
  376. },
  377. [1] = {
  378. .start = CH_SPI1,
  379. .end = CH_SPI1,
  380. .flags = IORESOURCE_DMA,
  381. },
  382. [2] = {
  383. .start = IRQ_SPI1,
  384. .end = IRQ_SPI1,
  385. .flags = IORESOURCE_IRQ,
  386. },
  387. };
  388. static struct platform_device bfin_spi1_device = {
  389. .name = "bfin-spi",
  390. .id = 1, /* Bus number */
  391. .num_resources = ARRAY_SIZE(bfin_spi1_resource),
  392. .resource = bfin_spi1_resource,
  393. .dev = {
  394. .platform_data = &bfin_spi1_info, /* Passed to driver */
  395. },
  396. };
  397. #endif /* spi master and devices */
  398. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  399. static struct resource bfin_uart_resources[] = {
  400. #ifdef CONFIG_SERIAL_BFIN_UART0
  401. {
  402. .start = 0xFFC00400,
  403. .end = 0xFFC004FF,
  404. .flags = IORESOURCE_MEM,
  405. },
  406. #endif
  407. #ifdef CONFIG_SERIAL_BFIN_UART1
  408. {
  409. .start = 0xFFC02000,
  410. .end = 0xFFC020FF,
  411. .flags = IORESOURCE_MEM,
  412. },
  413. #endif
  414. };
  415. static struct platform_device bfin_uart_device = {
  416. .name = "bfin-uart",
  417. .id = 1,
  418. .num_resources = ARRAY_SIZE(bfin_uart_resources),
  419. .resource = bfin_uart_resources,
  420. };
  421. #endif
  422. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  423. #ifdef CONFIG_BFIN_SIR0
  424. static struct resource bfin_sir0_resources[] = {
  425. {
  426. .start = 0xFFC00400,
  427. .end = 0xFFC004FF,
  428. .flags = IORESOURCE_MEM,
  429. },
  430. {
  431. .start = IRQ_UART0_RX,
  432. .end = IRQ_UART0_RX+1,
  433. .flags = IORESOURCE_IRQ,
  434. },
  435. {
  436. .start = CH_UART0_RX,
  437. .end = CH_UART0_RX+1,
  438. .flags = IORESOURCE_DMA,
  439. },
  440. };
  441. static struct platform_device bfin_sir0_device = {
  442. .name = "bfin_sir",
  443. .id = 0,
  444. .num_resources = ARRAY_SIZE(bfin_sir0_resources),
  445. .resource = bfin_sir0_resources,
  446. };
  447. #endif
  448. #ifdef CONFIG_BFIN_SIR1
  449. static struct resource bfin_sir1_resources[] = {
  450. {
  451. .start = 0xFFC02000,
  452. .end = 0xFFC020FF,
  453. .flags = IORESOURCE_MEM,
  454. },
  455. {
  456. .start = IRQ_UART1_RX,
  457. .end = IRQ_UART1_RX+1,
  458. .flags = IORESOURCE_IRQ,
  459. },
  460. {
  461. .start = CH_UART1_RX,
  462. .end = CH_UART1_RX+1,
  463. .flags = IORESOURCE_DMA,
  464. },
  465. };
  466. static struct platform_device bfin_sir1_device = {
  467. .name = "bfin_sir",
  468. .id = 1,
  469. .num_resources = ARRAY_SIZE(bfin_sir1_resources),
  470. .resource = bfin_sir1_resources,
  471. };
  472. #endif
  473. #endif
  474. #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
  475. static struct resource bfin_twi0_resource[] = {
  476. [0] = {
  477. .start = TWI0_REGBASE,
  478. .end = TWI0_REGBASE,
  479. .flags = IORESOURCE_MEM,
  480. },
  481. [1] = {
  482. .start = IRQ_TWI,
  483. .end = IRQ_TWI,
  484. .flags = IORESOURCE_IRQ,
  485. },
  486. };
  487. static struct platform_device i2c_bfin_twi_device = {
  488. .name = "i2c-bfin-twi",
  489. .id = 0,
  490. .num_resources = ARRAY_SIZE(bfin_twi0_resource),
  491. .resource = bfin_twi0_resource,
  492. };
  493. #endif
  494. static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
  495. #if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
  496. {
  497. I2C_BOARD_INFO("pcf8574_lcd", 0x22),
  498. },
  499. #endif
  500. #if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE)
  501. {
  502. I2C_BOARD_INFO("pcf8574_keypad", 0x27),
  503. .irq = IRQ_PF8,
  504. },
  505. #endif
  506. };
  507. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  508. static struct platform_device bfin_sport0_uart_device = {
  509. .name = "bfin-sport-uart",
  510. .id = 0,
  511. };
  512. static struct platform_device bfin_sport1_uart_device = {
  513. .name = "bfin-sport-uart",
  514. .id = 1,
  515. };
  516. #endif
  517. #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
  518. #include <linux/input.h>
  519. #include <linux/gpio_keys.h>
  520. static struct gpio_keys_button bfin_gpio_keys_table[] = {
  521. {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
  522. {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
  523. };
  524. static struct gpio_keys_platform_data bfin_gpio_keys_data = {
  525. .buttons = bfin_gpio_keys_table,
  526. .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
  527. };
  528. static struct platform_device bfin_device_gpiokeys = {
  529. .name = "gpio-keys",
  530. .dev = {
  531. .platform_data = &bfin_gpio_keys_data,
  532. },
  533. };
  534. #endif
  535. #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
  536. static struct bfin_sd_host bfin_sdh_data = {
  537. .dma_chan = CH_RSI,
  538. .irq_int0 = IRQ_RSI_INT0,
  539. .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0},
  540. };
  541. static struct platform_device bf51x_sdh_device = {
  542. .name = "bfin-sdh",
  543. .id = 0,
  544. .dev = {
  545. .platform_data = &bfin_sdh_data,
  546. },
  547. };
  548. #endif
  549. static struct resource bfin_gpios_resources = {
  550. .start = 0,
  551. .end = MAX_BLACKFIN_GPIOS - 1,
  552. .flags = IORESOURCE_IRQ,
  553. };
  554. static struct platform_device bfin_gpios_device = {
  555. .name = "simple-gpio",
  556. .id = -1,
  557. .num_resources = 1,
  558. .resource = &bfin_gpios_resources,
  559. };
  560. static const unsigned int cclk_vlev_datasheet[] =
  561. {
  562. VRPAIR(VLEV_100, 400000000),
  563. VRPAIR(VLEV_105, 426000000),
  564. VRPAIR(VLEV_110, 500000000),
  565. VRPAIR(VLEV_115, 533000000),
  566. VRPAIR(VLEV_120, 600000000),
  567. };
  568. static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
  569. .tuple_tab = cclk_vlev_datasheet,
  570. .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
  571. .vr_settling_time = 25 /* us */,
  572. };
  573. static struct platform_device bfin_dpmc = {
  574. .name = "bfin dpmc",
  575. .dev = {
  576. .platform_data = &bfin_dmpc_vreg_data,
  577. },
  578. };
  579. static struct platform_device *stamp_devices[] __initdata = {
  580. &bfin_dpmc,
  581. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  582. &rtc_device,
  583. #endif
  584. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  585. &bfin_mii_bus,
  586. &bfin_mac_device,
  587. #if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
  588. &ksz8893m_switch_device,
  589. #endif
  590. #endif
  591. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  592. &bfin_spi0_device,
  593. &bfin_spi1_device,
  594. #endif
  595. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  596. &bfin_uart_device,
  597. #endif
  598. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  599. #ifdef CONFIG_BFIN_SIR0
  600. &bfin_sir0_device,
  601. #endif
  602. #ifdef CONFIG_BFIN_SIR1
  603. &bfin_sir1_device,
  604. #endif
  605. #endif
  606. #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
  607. &i2c_bfin_twi_device,
  608. #endif
  609. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  610. &bfin_sport0_uart_device,
  611. &bfin_sport1_uart_device,
  612. #endif
  613. #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
  614. &bfin_device_gpiokeys,
  615. #endif
  616. #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
  617. &bf51x_sdh_device,
  618. #endif
  619. #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
  620. &ezbrd_flash_device,
  621. #endif
  622. &bfin_gpios_device,
  623. };
  624. static int __init ezbrd_init(void)
  625. {
  626. printk(KERN_INFO "%s(): registering device resources\n", __func__);
  627. i2c_register_board_info(0, bfin_i2c_board_info,
  628. ARRAY_SIZE(bfin_i2c_board_info));
  629. platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
  630. spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
  631. /* setup BF518-EZBRD GPIO pin PG11 to AMS2, PG15 to AMS3. */
  632. peripheral_request(P_AMS2, "ParaFlash");
  633. #if !defined(CONFIG_SPI_BFIN) && !defined(CONFIG_SPI_BFIN_MODULE)
  634. peripheral_request(P_AMS3, "ParaFlash");
  635. #endif
  636. return 0;
  637. }
  638. arch_initcall(ezbrd_init);
  639. void native_machine_restart(char *cmd)
  640. {
  641. /* workaround reboot hang when booting from SPI */
  642. if ((bfin_read_SYSCR() & 0x7) == 0x3)
  643. bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
  644. }
  645. void bfin_get_ether_addr(char *addr)
  646. {
  647. /* the MAC is stored in OTP memory page 0xDF */
  648. u32 ret;
  649. u64 otp_mac;
  650. u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
  651. ret = otp_read(0xDF, 0x00, &otp_mac);
  652. if (!(ret & 0x1)) {
  653. char *otp_mac_p = (char *)&otp_mac;
  654. for (ret = 0; ret < 6; ++ret)
  655. addr[ret] = otp_mac_p[5 - ret];
  656. }
  657. }
  658. EXPORT_SYMBOL(bfin_get_ether_addr);