mpi2_cnfg.h 135 KB

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  1. /*
  2. * Copyright (c) 2000-2010 LSI Corporation.
  3. *
  4. *
  5. * Name: mpi2_cnfg.h
  6. * Title: MPI Configuration messages and pages
  7. * Creation Date: November 10, 2006
  8. *
  9. * mpi2_cnfg.h Version: 02.00.14
  10. *
  11. * Version History
  12. * ---------------
  13. *
  14. * Date Version Description
  15. * -------- -------- ------------------------------------------------------
  16. * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
  17. * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags.
  18. * Added Manufacturing Page 11.
  19. * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE
  20. * define.
  21. * 06-26-07 02.00.02 Adding generic structure for product-specific
  22. * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS.
  23. * Rework of BIOS Page 2 configuration page.
  24. * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the
  25. * forms.
  26. * Added configuration pages IOC Page 8 and Driver
  27. * Persistent Mapping Page 0.
  28. * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated
  29. * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1,
  30. * RAID Physical Disk Pages 0 and 1, RAID Configuration
  31. * Page 0).
  32. * Added new value for AccessStatus field of SAS Device
  33. * Page 0 (_SATA_NEEDS_INITIALIZATION).
  34. * 10-31-07 02.00.04 Added missing SEPDevHandle field to
  35. * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
  36. * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for
  37. * NVDATA.
  38. * Modified IOC Page 7 to use masks and added field for
  39. * SASBroadcastPrimitiveMasks.
  40. * Added MPI2_CONFIG_PAGE_BIOS_4.
  41. * Added MPI2_CONFIG_PAGE_LOG_0.
  42. * 02-29-08 02.00.06 Modified various names to make them 32-character unique.
  43. * Added SAS Device IDs.
  44. * Updated Integrated RAID configuration pages including
  45. * Manufacturing Page 4, IOC Page 6, and RAID Configuration
  46. * Page 0.
  47. * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA.
  48. * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION.
  49. * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING.
  50. * Added missing MaxNumRoutedSasAddresses field to
  51. * MPI2_CONFIG_PAGE_EXPANDER_0.
  52. * Added SAS Port Page 0.
  53. * Modified structure layout for
  54. * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0.
  55. * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use
  56. * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array.
  57. * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF
  58. * to 0x000000FF.
  59. * Added two new values for the Physical Disk Coercion Size
  60. * bits in the Flags field of Manufacturing Page 4.
  61. * Added product-specific Manufacturing pages 16 to 31.
  62. * Modified Flags bits for controlling write cache on SATA
  63. * drives in IO Unit Page 1.
  64. * Added new bit to AdditionalControlFlags of SAS IO Unit
  65. * Page 1 to control Invalid Topology Correction.
  66. * Added additional defines for RAID Volume Page 0
  67. * VolumeStatusFlags field.
  68. * Modified meaning of RAID Volume Page 0 VolumeSettings
  69. * define for auto-configure of hot-swap drives.
  70. * Added SupportedPhysDisks field to RAID Volume Page 1 and
  71. * added related defines.
  72. * Added PhysDiskAttributes field (and related defines) to
  73. * RAID Physical Disk Page 0.
  74. * Added MPI2_SAS_PHYINFO_PHY_VACANT define.
  75. * Added three new DiscoveryStatus bits for SAS IO Unit
  76. * Page 0 and SAS Expander Page 0.
  77. * Removed multiplexing information from SAS IO Unit pages.
  78. * Added BootDeviceWaitTime field to SAS IO Unit Page 4.
  79. * Removed Zone Address Resolved bit from PhyInfo and from
  80. * Expander Page 0 Flags field.
  81. * Added two new AccessStatus values to SAS Device Page 0
  82. * for indicating routing problems. Added 3 reserved words
  83. * to this page.
  84. * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3.
  85. * Inserted missing reserved field into structure for IOC
  86. * Page 6.
  87. * Added more pending task bits to RAID Volume Page 0
  88. * VolumeStatusFlags defines.
  89. * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define.
  90. * Added a new DiscoveryStatus bit for SAS IO Unit Page 0
  91. * and SAS Expander Page 0 to flag a downstream initiator
  92. * when in simplified routing mode.
  93. * Removed SATA Init Failure defines for DiscoveryStatus
  94. * fields of SAS IO Unit Page 0 and SAS Expander Page 0.
  95. * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define.
  96. * Added PortGroups, DmaGroup, and ControlGroup fields to
  97. * SAS Device Page 0.
  98. * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO
  99. * Unit Page 6.
  100. * Added expander reduced functionality data to SAS
  101. * Expander Page 0.
  102. * Added SAS PHY Page 2 and SAS PHY Page 3.
  103. * 07-30-09 02.00.12 Added IO Unit Page 7.
  104. * Added new device ids.
  105. * Added SAS IO Unit Page 5.
  106. * Added partial and slumber power management capable flags
  107. * to SAS Device Page 0 Flags field.
  108. * Added PhyInfo defines for power condition.
  109. * Added Ethernet configuration pages.
  110. * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY.
  111. * Added SAS PHY Page 4 structure and defines.
  112. * 02-10-10 02.00.14 Modified the comments for the configuration page
  113. * structures that contain an array of data. The host
  114. * should use the "count" field in the page data (e.g. the
  115. * NumPhys field) to determine the number of valid elements
  116. * in the array.
  117. * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines.
  118. * Added PowerManagementCapabilities to IO Unit Page 7.
  119. * Added PortWidthModGroup field to
  120. * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS.
  121. * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines.
  122. * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines.
  123. * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines.
  124. * --------------------------------------------------------------------------
  125. */
  126. #ifndef MPI2_CNFG_H
  127. #define MPI2_CNFG_H
  128. /*****************************************************************************
  129. * Configuration Page Header and defines
  130. *****************************************************************************/
  131. /* Config Page Header */
  132. typedef struct _MPI2_CONFIG_PAGE_HEADER
  133. {
  134. U8 PageVersion; /* 0x00 */
  135. U8 PageLength; /* 0x01 */
  136. U8 PageNumber; /* 0x02 */
  137. U8 PageType; /* 0x03 */
  138. } MPI2_CONFIG_PAGE_HEADER, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER,
  139. Mpi2ConfigPageHeader_t, MPI2_POINTER pMpi2ConfigPageHeader_t;
  140. typedef union _MPI2_CONFIG_PAGE_HEADER_UNION
  141. {
  142. MPI2_CONFIG_PAGE_HEADER Struct;
  143. U8 Bytes[4];
  144. U16 Word16[2];
  145. U32 Word32;
  146. } MPI2_CONFIG_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER_UNION,
  147. Mpi2ConfigPageHeaderUnion, MPI2_POINTER pMpi2ConfigPageHeaderUnion;
  148. /* Extended Config Page Header */
  149. typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER
  150. {
  151. U8 PageVersion; /* 0x00 */
  152. U8 Reserved1; /* 0x01 */
  153. U8 PageNumber; /* 0x02 */
  154. U8 PageType; /* 0x03 */
  155. U16 ExtPageLength; /* 0x04 */
  156. U8 ExtPageType; /* 0x06 */
  157. U8 Reserved2; /* 0x07 */
  158. } MPI2_CONFIG_EXTENDED_PAGE_HEADER,
  159. MPI2_POINTER PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER,
  160. Mpi2ConfigExtendedPageHeader_t, MPI2_POINTER pMpi2ConfigExtendedPageHeader_t;
  161. typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION
  162. {
  163. MPI2_CONFIG_PAGE_HEADER Struct;
  164. MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext;
  165. U8 Bytes[8];
  166. U16 Word16[4];
  167. U32 Word32[2];
  168. } MPI2_CONFIG_EXT_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION,
  169. Mpi2ConfigPageExtendedHeaderUnion, MPI2_POINTER pMpi2ConfigPageExtendedHeaderUnion;
  170. /* PageType field values */
  171. #define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00)
  172. #define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10)
  173. #define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20)
  174. #define MPI2_CONFIG_PAGEATTR_MASK (0xF0)
  175. #define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00)
  176. #define MPI2_CONFIG_PAGETYPE_IOC (0x01)
  177. #define MPI2_CONFIG_PAGETYPE_BIOS (0x02)
  178. #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08)
  179. #define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09)
  180. #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A)
  181. #define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F)
  182. #define MPI2_CONFIG_PAGETYPE_MASK (0x0F)
  183. #define MPI2_CONFIG_TYPENUM_MASK (0x0FFF)
  184. /* ExtPageType field values */
  185. #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10)
  186. #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11)
  187. #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12)
  188. #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13)
  189. #define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14)
  190. #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15)
  191. #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16)
  192. #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17)
  193. #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18)
  194. #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19)
  195. /*****************************************************************************
  196. * PageAddress defines
  197. *****************************************************************************/
  198. /* RAID Volume PageAddress format */
  199. #define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000)
  200. #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
  201. #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000)
  202. #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF)
  203. /* RAID Physical Disk PageAddress format */
  204. #define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000)
  205. #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000)
  206. #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000)
  207. #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000)
  208. #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF)
  209. #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF)
  210. /* SAS Expander PageAddress format */
  211. #define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000)
  212. #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000)
  213. #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000)
  214. #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000)
  215. #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF)
  216. #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000)
  217. #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16)
  218. /* SAS Device PageAddress format */
  219. #define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000)
  220. #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
  221. #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000)
  222. #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF)
  223. /* SAS PHY PageAddress format */
  224. #define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000)
  225. #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000)
  226. #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000)
  227. #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF)
  228. #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF)
  229. /* SAS Port PageAddress format */
  230. #define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000)
  231. #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000)
  232. #define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000)
  233. #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF)
  234. /* SAS Enclosure PageAddress format */
  235. #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000)
  236. #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
  237. #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000)
  238. #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF)
  239. /* RAID Configuration PageAddress format */
  240. #define MPI2_RAID_PGAD_FORM_MASK (0xF0000000)
  241. #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000)
  242. #define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000)
  243. #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000)
  244. #define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF)
  245. /* Driver Persistent Mapping PageAddress format */
  246. #define MPI2_DPM_PGAD_FORM_MASK (0xF0000000)
  247. #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000)
  248. #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000)
  249. #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16)
  250. #define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF)
  251. /* Ethernet PageAddress format */
  252. #define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000)
  253. #define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000)
  254. #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF)
  255. /****************************************************************************
  256. * Configuration messages
  257. ****************************************************************************/
  258. /* Configuration Request Message */
  259. typedef struct _MPI2_CONFIG_REQUEST
  260. {
  261. U8 Action; /* 0x00 */
  262. U8 SGLFlags; /* 0x01 */
  263. U8 ChainOffset; /* 0x02 */
  264. U8 Function; /* 0x03 */
  265. U16 ExtPageLength; /* 0x04 */
  266. U8 ExtPageType; /* 0x06 */
  267. U8 MsgFlags; /* 0x07 */
  268. U8 VP_ID; /* 0x08 */
  269. U8 VF_ID; /* 0x09 */
  270. U16 Reserved1; /* 0x0A */
  271. U32 Reserved2; /* 0x0C */
  272. U32 Reserved3; /* 0x10 */
  273. MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */
  274. U32 PageAddress; /* 0x18 */
  275. MPI2_SGE_IO_UNION PageBufferSGE; /* 0x1C */
  276. } MPI2_CONFIG_REQUEST, MPI2_POINTER PTR_MPI2_CONFIG_REQUEST,
  277. Mpi2ConfigRequest_t, MPI2_POINTER pMpi2ConfigRequest_t;
  278. /* values for the Action field */
  279. #define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00)
  280. #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01)
  281. #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02)
  282. #define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03)
  283. #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04)
  284. #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05)
  285. #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06)
  286. #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07)
  287. /* values for SGLFlags field are in the SGL section of mpi2.h */
  288. /* Config Reply Message */
  289. typedef struct _MPI2_CONFIG_REPLY
  290. {
  291. U8 Action; /* 0x00 */
  292. U8 SGLFlags; /* 0x01 */
  293. U8 MsgLength; /* 0x02 */
  294. U8 Function; /* 0x03 */
  295. U16 ExtPageLength; /* 0x04 */
  296. U8 ExtPageType; /* 0x06 */
  297. U8 MsgFlags; /* 0x07 */
  298. U8 VP_ID; /* 0x08 */
  299. U8 VF_ID; /* 0x09 */
  300. U16 Reserved1; /* 0x0A */
  301. U16 Reserved2; /* 0x0C */
  302. U16 IOCStatus; /* 0x0E */
  303. U32 IOCLogInfo; /* 0x10 */
  304. MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */
  305. } MPI2_CONFIG_REPLY, MPI2_POINTER PTR_MPI2_CONFIG_REPLY,
  306. Mpi2ConfigReply_t, MPI2_POINTER pMpi2ConfigReply_t;
  307. /*****************************************************************************
  308. *
  309. * C o n f i g u r a t i o n P a g e s
  310. *
  311. *****************************************************************************/
  312. /****************************************************************************
  313. * Manufacturing Config pages
  314. ****************************************************************************/
  315. #define MPI2_MFGPAGE_VENDORID_LSI (0x1000)
  316. /* SAS */
  317. #define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070)
  318. #define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072)
  319. #define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074)
  320. #define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076)
  321. #define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077)
  322. #define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064)
  323. #define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065)
  324. #define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080)
  325. #define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081)
  326. #define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082)
  327. #define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083)
  328. #define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084)
  329. #define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085)
  330. #define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086)
  331. #define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087)
  332. #define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E)
  333. /* Manufacturing Page 0 */
  334. typedef struct _MPI2_CONFIG_PAGE_MAN_0
  335. {
  336. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  337. U8 ChipName[16]; /* 0x04 */
  338. U8 ChipRevision[8]; /* 0x14 */
  339. U8 BoardName[16]; /* 0x1C */
  340. U8 BoardAssembly[16]; /* 0x2C */
  341. U8 BoardTracerNumber[16]; /* 0x3C */
  342. } MPI2_CONFIG_PAGE_MAN_0,
  343. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_0,
  344. Mpi2ManufacturingPage0_t, MPI2_POINTER pMpi2ManufacturingPage0_t;
  345. #define MPI2_MANUFACTURING0_PAGEVERSION (0x00)
  346. /* Manufacturing Page 1 */
  347. typedef struct _MPI2_CONFIG_PAGE_MAN_1
  348. {
  349. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  350. U8 VPD[256]; /* 0x04 */
  351. } MPI2_CONFIG_PAGE_MAN_1,
  352. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_1,
  353. Mpi2ManufacturingPage1_t, MPI2_POINTER pMpi2ManufacturingPage1_t;
  354. #define MPI2_MANUFACTURING1_PAGEVERSION (0x00)
  355. typedef struct _MPI2_CHIP_REVISION_ID
  356. {
  357. U16 DeviceID; /* 0x00 */
  358. U8 PCIRevisionID; /* 0x02 */
  359. U8 Reserved; /* 0x03 */
  360. } MPI2_CHIP_REVISION_ID, MPI2_POINTER PTR_MPI2_CHIP_REVISION_ID,
  361. Mpi2ChipRevisionId_t, MPI2_POINTER pMpi2ChipRevisionId_t;
  362. /* Manufacturing Page 2 */
  363. /*
  364. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  365. * one and check Header.PageLength at runtime.
  366. */
  367. #ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS
  368. #define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1)
  369. #endif
  370. typedef struct _MPI2_CONFIG_PAGE_MAN_2
  371. {
  372. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  373. MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */
  374. U32 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 0x08 */
  375. } MPI2_CONFIG_PAGE_MAN_2,
  376. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_2,
  377. Mpi2ManufacturingPage2_t, MPI2_POINTER pMpi2ManufacturingPage2_t;
  378. #define MPI2_MANUFACTURING2_PAGEVERSION (0x00)
  379. /* Manufacturing Page 3 */
  380. /*
  381. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  382. * one and check Header.PageLength at runtime.
  383. */
  384. #ifndef MPI2_MAN_PAGE_3_INFO_WORDS
  385. #define MPI2_MAN_PAGE_3_INFO_WORDS (1)
  386. #endif
  387. typedef struct _MPI2_CONFIG_PAGE_MAN_3
  388. {
  389. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  390. MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */
  391. U32 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/* 0x08 */
  392. } MPI2_CONFIG_PAGE_MAN_3,
  393. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_3,
  394. Mpi2ManufacturingPage3_t, MPI2_POINTER pMpi2ManufacturingPage3_t;
  395. #define MPI2_MANUFACTURING3_PAGEVERSION (0x00)
  396. /* Manufacturing Page 4 */
  397. typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS
  398. {
  399. U8 PowerSaveFlags; /* 0x00 */
  400. U8 InternalOperationsSleepTime; /* 0x01 */
  401. U8 InternalOperationsRunTime; /* 0x02 */
  402. U8 HostIdleTime; /* 0x03 */
  403. } MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
  404. MPI2_POINTER PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
  405. Mpi2ManPage4PwrSaveSettings_t, MPI2_POINTER pMpi2ManPage4PwrSaveSettings_t;
  406. /* defines for the PowerSaveFlags field */
  407. #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03)
  408. #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00)
  409. #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01)
  410. #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02)
  411. typedef struct _MPI2_CONFIG_PAGE_MAN_4
  412. {
  413. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  414. U32 Reserved1; /* 0x04 */
  415. U32 Flags; /* 0x08 */
  416. U8 InquirySize; /* 0x0C */
  417. U8 Reserved2; /* 0x0D */
  418. U16 Reserved3; /* 0x0E */
  419. U8 InquiryData[56]; /* 0x10 */
  420. U32 RAID0VolumeSettings; /* 0x48 */
  421. U32 RAID1EVolumeSettings; /* 0x4C */
  422. U32 RAID1VolumeSettings; /* 0x50 */
  423. U32 RAID10VolumeSettings; /* 0x54 */
  424. U32 Reserved4; /* 0x58 */
  425. U32 Reserved5; /* 0x5C */
  426. MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /* 0x60 */
  427. U8 MaxOCEDisks; /* 0x64 */
  428. U8 ResyncRate; /* 0x65 */
  429. U16 DataScrubDuration; /* 0x66 */
  430. U8 MaxHotSpares; /* 0x68 */
  431. U8 MaxPhysDisksPerVol; /* 0x69 */
  432. U8 MaxPhysDisks; /* 0x6A */
  433. U8 MaxVolumes; /* 0x6B */
  434. } MPI2_CONFIG_PAGE_MAN_4,
  435. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_4,
  436. Mpi2ManufacturingPage4_t, MPI2_POINTER pMpi2ManufacturingPage4_t;
  437. #define MPI2_MANUFACTURING4_PAGEVERSION (0x0A)
  438. /* Manufacturing Page 4 Flags field */
  439. #define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000)
  440. #define MPI2_MANPAGE4_METADATA_512MB (0x00000000)
  441. #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000)
  442. #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000)
  443. #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000)
  444. #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00)
  445. #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000)
  446. #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400)
  447. #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800)
  448. #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00)
  449. #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300)
  450. #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000)
  451. #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100)
  452. #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200)
  453. #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080)
  454. #define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040)
  455. #define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020)
  456. #define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010)
  457. #define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008)
  458. #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004)
  459. #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002)
  460. #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001)
  461. /* Manufacturing Page 5 */
  462. /*
  463. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  464. * one and check the value returned for NumPhys at runtime.
  465. */
  466. #ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES
  467. #define MPI2_MAN_PAGE_5_PHY_ENTRIES (1)
  468. #endif
  469. typedef struct _MPI2_MANUFACTURING5_ENTRY
  470. {
  471. U64 WWID; /* 0x00 */
  472. U64 DeviceName; /* 0x08 */
  473. } MPI2_MANUFACTURING5_ENTRY, MPI2_POINTER PTR_MPI2_MANUFACTURING5_ENTRY,
  474. Mpi2Manufacturing5Entry_t, MPI2_POINTER pMpi2Manufacturing5Entry_t;
  475. typedef struct _MPI2_CONFIG_PAGE_MAN_5
  476. {
  477. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  478. U8 NumPhys; /* 0x04 */
  479. U8 Reserved1; /* 0x05 */
  480. U16 Reserved2; /* 0x06 */
  481. U32 Reserved3; /* 0x08 */
  482. U32 Reserved4; /* 0x0C */
  483. MPI2_MANUFACTURING5_ENTRY Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/* 0x08 */
  484. } MPI2_CONFIG_PAGE_MAN_5,
  485. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_5,
  486. Mpi2ManufacturingPage5_t, MPI2_POINTER pMpi2ManufacturingPage5_t;
  487. #define MPI2_MANUFACTURING5_PAGEVERSION (0x03)
  488. /* Manufacturing Page 6 */
  489. typedef struct _MPI2_CONFIG_PAGE_MAN_6
  490. {
  491. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  492. U32 ProductSpecificInfo;/* 0x04 */
  493. } MPI2_CONFIG_PAGE_MAN_6,
  494. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_6,
  495. Mpi2ManufacturingPage6_t, MPI2_POINTER pMpi2ManufacturingPage6_t;
  496. #define MPI2_MANUFACTURING6_PAGEVERSION (0x00)
  497. /* Manufacturing Page 7 */
  498. typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO
  499. {
  500. U32 Pinout; /* 0x00 */
  501. U8 Connector[16]; /* 0x04 */
  502. U8 Location; /* 0x14 */
  503. U8 Reserved1; /* 0x15 */
  504. U16 Slot; /* 0x16 */
  505. U32 Reserved2; /* 0x18 */
  506. } MPI2_MANPAGE7_CONNECTOR_INFO, MPI2_POINTER PTR_MPI2_MANPAGE7_CONNECTOR_INFO,
  507. Mpi2ManPage7ConnectorInfo_t, MPI2_POINTER pMpi2ManPage7ConnectorInfo_t;
  508. /* defines for the Pinout field */
  509. #define MPI2_MANPAGE7_PINOUT_SFF_8484_L4 (0x00080000)
  510. #define MPI2_MANPAGE7_PINOUT_SFF_8484_L3 (0x00040000)
  511. #define MPI2_MANPAGE7_PINOUT_SFF_8484_L2 (0x00020000)
  512. #define MPI2_MANPAGE7_PINOUT_SFF_8484_L1 (0x00010000)
  513. #define MPI2_MANPAGE7_PINOUT_SFF_8470_L4 (0x00000800)
  514. #define MPI2_MANPAGE7_PINOUT_SFF_8470_L3 (0x00000400)
  515. #define MPI2_MANPAGE7_PINOUT_SFF_8470_L2 (0x00000200)
  516. #define MPI2_MANPAGE7_PINOUT_SFF_8470_L1 (0x00000100)
  517. #define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x00000002)
  518. #define MPI2_MANPAGE7_PINOUT_CONNECTION_UNKNOWN (0x00000001)
  519. /* defines for the Location field */
  520. #define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01)
  521. #define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02)
  522. #define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04)
  523. #define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08)
  524. #define MPI2_MANPAGE7_LOCATION_AUTO (0x10)
  525. #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20)
  526. #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80)
  527. /*
  528. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  529. * one and check the value returned for NumPhys at runtime.
  530. */
  531. #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX
  532. #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1)
  533. #endif
  534. typedef struct _MPI2_CONFIG_PAGE_MAN_7
  535. {
  536. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  537. U32 Reserved1; /* 0x04 */
  538. U32 Reserved2; /* 0x08 */
  539. U32 Flags; /* 0x0C */
  540. U8 EnclosureName[16]; /* 0x10 */
  541. U8 NumPhys; /* 0x20 */
  542. U8 Reserved3; /* 0x21 */
  543. U16 Reserved4; /* 0x22 */
  544. MPI2_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /* 0x24 */
  545. } MPI2_CONFIG_PAGE_MAN_7,
  546. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_7,
  547. Mpi2ManufacturingPage7_t, MPI2_POINTER pMpi2ManufacturingPage7_t;
  548. #define MPI2_MANUFACTURING7_PAGEVERSION (0x00)
  549. /* defines for the Flags field */
  550. #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001)
  551. /*
  552. * Generic structure to use for product-specific manufacturing pages
  553. * (currently Manufacturing Page 8 through Manufacturing Page 31).
  554. */
  555. typedef struct _MPI2_CONFIG_PAGE_MAN_PS
  556. {
  557. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  558. U32 ProductSpecificInfo;/* 0x04 */
  559. } MPI2_CONFIG_PAGE_MAN_PS,
  560. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_PS,
  561. Mpi2ManufacturingPagePS_t, MPI2_POINTER pMpi2ManufacturingPagePS_t;
  562. #define MPI2_MANUFACTURING8_PAGEVERSION (0x00)
  563. #define MPI2_MANUFACTURING9_PAGEVERSION (0x00)
  564. #define MPI2_MANUFACTURING10_PAGEVERSION (0x00)
  565. #define MPI2_MANUFACTURING11_PAGEVERSION (0x00)
  566. #define MPI2_MANUFACTURING12_PAGEVERSION (0x00)
  567. #define MPI2_MANUFACTURING13_PAGEVERSION (0x00)
  568. #define MPI2_MANUFACTURING14_PAGEVERSION (0x00)
  569. #define MPI2_MANUFACTURING15_PAGEVERSION (0x00)
  570. #define MPI2_MANUFACTURING16_PAGEVERSION (0x00)
  571. #define MPI2_MANUFACTURING17_PAGEVERSION (0x00)
  572. #define MPI2_MANUFACTURING18_PAGEVERSION (0x00)
  573. #define MPI2_MANUFACTURING19_PAGEVERSION (0x00)
  574. #define MPI2_MANUFACTURING20_PAGEVERSION (0x00)
  575. #define MPI2_MANUFACTURING21_PAGEVERSION (0x00)
  576. #define MPI2_MANUFACTURING22_PAGEVERSION (0x00)
  577. #define MPI2_MANUFACTURING23_PAGEVERSION (0x00)
  578. #define MPI2_MANUFACTURING24_PAGEVERSION (0x00)
  579. #define MPI2_MANUFACTURING25_PAGEVERSION (0x00)
  580. #define MPI2_MANUFACTURING26_PAGEVERSION (0x00)
  581. #define MPI2_MANUFACTURING27_PAGEVERSION (0x00)
  582. #define MPI2_MANUFACTURING28_PAGEVERSION (0x00)
  583. #define MPI2_MANUFACTURING29_PAGEVERSION (0x00)
  584. #define MPI2_MANUFACTURING30_PAGEVERSION (0x00)
  585. #define MPI2_MANUFACTURING31_PAGEVERSION (0x00)
  586. /****************************************************************************
  587. * IO Unit Config Pages
  588. ****************************************************************************/
  589. /* IO Unit Page 0 */
  590. typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0
  591. {
  592. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  593. U64 UniqueValue; /* 0x04 */
  594. MPI2_VERSION_UNION NvdataVersionDefault; /* 0x08 */
  595. MPI2_VERSION_UNION NvdataVersionPersistent; /* 0x0A */
  596. } MPI2_CONFIG_PAGE_IO_UNIT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_0,
  597. Mpi2IOUnitPage0_t, MPI2_POINTER pMpi2IOUnitPage0_t;
  598. #define MPI2_IOUNITPAGE0_PAGEVERSION (0x02)
  599. /* IO Unit Page 1 */
  600. typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1
  601. {
  602. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  603. U32 Flags; /* 0x04 */
  604. } MPI2_CONFIG_PAGE_IO_UNIT_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_1,
  605. Mpi2IOUnitPage1_t, MPI2_POINTER pMpi2IOUnitPage1_t;
  606. #define MPI2_IOUNITPAGE1_PAGEVERSION (0x04)
  607. /* IO Unit Page 1 Flags defines */
  608. #define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800)
  609. #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600)
  610. #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000)
  611. #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200)
  612. #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400)
  613. #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100)
  614. #define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040)
  615. #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020)
  616. #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004)
  617. #define MPI2_IOUNITPAGE1_MULTI_PATHING (0x00000002)
  618. #define MPI2_IOUNITPAGE1_SINGLE_PATHING (0x00000000)
  619. /* IO Unit Page 3 */
  620. /*
  621. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  622. * one and check the value returned for GPIOCount at runtime.
  623. */
  624. #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX
  625. #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1)
  626. #endif
  627. typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3
  628. {
  629. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  630. U8 GPIOCount; /* 0x04 */
  631. U8 Reserved1; /* 0x05 */
  632. U16 Reserved2; /* 0x06 */
  633. U16 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/* 0x08 */
  634. } MPI2_CONFIG_PAGE_IO_UNIT_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_3,
  635. Mpi2IOUnitPage3_t, MPI2_POINTER pMpi2IOUnitPage3_t;
  636. #define MPI2_IOUNITPAGE3_PAGEVERSION (0x01)
  637. /* defines for IO Unit Page 3 GPIOVal field */
  638. #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC)
  639. #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2)
  640. #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000)
  641. #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001)
  642. /* IO Unit Page 5 */
  643. /*
  644. * Upper layer code (drivers, utilities, etc.) should leave this define set to
  645. * one and check the value returned for NumDmaEngines at runtime.
  646. */
  647. #ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES
  648. #define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1)
  649. #endif
  650. typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 {
  651. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  652. U64 RaidAcceleratorBufferBaseAddress; /* 0x04 */
  653. U64 RaidAcceleratorBufferSize; /* 0x0C */
  654. U64 RaidAcceleratorControlBaseAddress; /* 0x14 */
  655. U8 RAControlSize; /* 0x1C */
  656. U8 NumDmaEngines; /* 0x1D */
  657. U8 RAMinControlSize; /* 0x1E */
  658. U8 RAMaxControlSize; /* 0x1F */
  659. U32 Reserved1; /* 0x20 */
  660. U32 Reserved2; /* 0x24 */
  661. U32 Reserved3; /* 0x28 */
  662. U32 DmaEngineCapabilities
  663. [MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /* 0x2C */
  664. } MPI2_CONFIG_PAGE_IO_UNIT_5, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_5,
  665. Mpi2IOUnitPage5_t, MPI2_POINTER pMpi2IOUnitPage5_t;
  666. #define MPI2_IOUNITPAGE5_PAGEVERSION (0x00)
  667. /* defines for IO Unit Page 5 DmaEngineCapabilities field */
  668. #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFF00)
  669. #define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16)
  670. #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008)
  671. #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004)
  672. #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002)
  673. #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001)
  674. /* IO Unit Page 6 */
  675. typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 {
  676. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  677. U16 Flags; /* 0x04 */
  678. U8 RAHostControlSize; /* 0x06 */
  679. U8 Reserved0; /* 0x07 */
  680. U64 RaidAcceleratorHostControlBaseAddress; /* 0x08 */
  681. U32 Reserved1; /* 0x10 */
  682. U32 Reserved2; /* 0x14 */
  683. U32 Reserved3; /* 0x18 */
  684. } MPI2_CONFIG_PAGE_IO_UNIT_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_6,
  685. Mpi2IOUnitPage6_t, MPI2_POINTER pMpi2IOUnitPage6_t;
  686. #define MPI2_IOUNITPAGE6_PAGEVERSION (0x00)
  687. /* defines for IO Unit Page 6 Flags field */
  688. #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001)
  689. /* IO Unit Page 7 */
  690. typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 {
  691. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  692. U16 Reserved1; /* 0x04 */
  693. U8 PCIeWidth; /* 0x06 */
  694. U8 PCIeSpeed; /* 0x07 */
  695. U32 ProcessorState; /* 0x08 */
  696. U32 PowerManagementCapabilities; /* 0x0C */
  697. U16 IOCTemperature; /* 0x10 */
  698. U8 IOCTemperatureUnits; /* 0x12 */
  699. U8 IOCSpeed; /* 0x13 */
  700. U32 Reserved3; /* 0x14 */
  701. } MPI2_CONFIG_PAGE_IO_UNIT_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_7,
  702. Mpi2IOUnitPage7_t, MPI2_POINTER pMpi2IOUnitPage7_t;
  703. #define MPI2_IOUNITPAGE7_PAGEVERSION (0x01)
  704. /* defines for IO Unit Page 7 PCIeWidth field */
  705. #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01)
  706. #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02)
  707. #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04)
  708. #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08)
  709. /* defines for IO Unit Page 7 PCIeSpeed field */
  710. #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00)
  711. #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01)
  712. #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02)
  713. /* defines for IO Unit Page 7 ProcessorState field */
  714. #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F)
  715. #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0)
  716. #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00)
  717. #define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01)
  718. #define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02)
  719. /* defines for IO Unit Page 7 PowerManagementCapabilities field */
  720. #define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400)
  721. #define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200)
  722. #define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100)
  723. #define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008)
  724. #define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004)
  725. /* defines for IO Unit Page 7 IOCTemperatureUnits field */
  726. #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00)
  727. #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01)
  728. #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02)
  729. /* defines for IO Unit Page 7 IOCSpeed field */
  730. #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01)
  731. #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02)
  732. #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04)
  733. #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08)
  734. /****************************************************************************
  735. * IOC Config Pages
  736. ****************************************************************************/
  737. /* IOC Page 0 */
  738. typedef struct _MPI2_CONFIG_PAGE_IOC_0
  739. {
  740. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  741. U32 Reserved1; /* 0x04 */
  742. U32 Reserved2; /* 0x08 */
  743. U16 VendorID; /* 0x0C */
  744. U16 DeviceID; /* 0x0E */
  745. U8 RevisionID; /* 0x10 */
  746. U8 Reserved3; /* 0x11 */
  747. U16 Reserved4; /* 0x12 */
  748. U32 ClassCode; /* 0x14 */
  749. U16 SubsystemVendorID; /* 0x18 */
  750. U16 SubsystemID; /* 0x1A */
  751. } MPI2_CONFIG_PAGE_IOC_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_0,
  752. Mpi2IOCPage0_t, MPI2_POINTER pMpi2IOCPage0_t;
  753. #define MPI2_IOCPAGE0_PAGEVERSION (0x02)
  754. /* IOC Page 1 */
  755. typedef struct _MPI2_CONFIG_PAGE_IOC_1
  756. {
  757. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  758. U32 Flags; /* 0x04 */
  759. U32 CoalescingTimeout; /* 0x08 */
  760. U8 CoalescingDepth; /* 0x0C */
  761. U8 PCISlotNum; /* 0x0D */
  762. U8 PCIBusNum; /* 0x0E */
  763. U8 PCIDomainSegment; /* 0x0F */
  764. U32 Reserved1; /* 0x10 */
  765. U32 Reserved2; /* 0x14 */
  766. } MPI2_CONFIG_PAGE_IOC_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_1,
  767. Mpi2IOCPage1_t, MPI2_POINTER pMpi2IOCPage1_t;
  768. #define MPI2_IOCPAGE1_PAGEVERSION (0x05)
  769. /* defines for IOC Page 1 Flags field */
  770. #define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001)
  771. #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF)
  772. #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF)
  773. #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF)
  774. /* IOC Page 6 */
  775. typedef struct _MPI2_CONFIG_PAGE_IOC_6
  776. {
  777. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  778. U32 CapabilitiesFlags; /* 0x04 */
  779. U8 MaxDrivesRAID0; /* 0x08 */
  780. U8 MaxDrivesRAID1; /* 0x09 */
  781. U8 MaxDrivesRAID1E; /* 0x0A */
  782. U8 MaxDrivesRAID10; /* 0x0B */
  783. U8 MinDrivesRAID0; /* 0x0C */
  784. U8 MinDrivesRAID1; /* 0x0D */
  785. U8 MinDrivesRAID1E; /* 0x0E */
  786. U8 MinDrivesRAID10; /* 0x0F */
  787. U32 Reserved1; /* 0x10 */
  788. U8 MaxGlobalHotSpares; /* 0x14 */
  789. U8 MaxPhysDisks; /* 0x15 */
  790. U8 MaxVolumes; /* 0x16 */
  791. U8 MaxConfigs; /* 0x17 */
  792. U8 MaxOCEDisks; /* 0x18 */
  793. U8 Reserved2; /* 0x19 */
  794. U16 Reserved3; /* 0x1A */
  795. U32 SupportedStripeSizeMapRAID0; /* 0x1C */
  796. U32 SupportedStripeSizeMapRAID1E; /* 0x20 */
  797. U32 SupportedStripeSizeMapRAID10; /* 0x24 */
  798. U32 Reserved4; /* 0x28 */
  799. U32 Reserved5; /* 0x2C */
  800. U16 DefaultMetadataSize; /* 0x30 */
  801. U16 Reserved6; /* 0x32 */
  802. U16 MaxBadBlockTableEntries; /* 0x34 */
  803. U16 Reserved7; /* 0x36 */
  804. U32 IRNvsramVersion; /* 0x38 */
  805. } MPI2_CONFIG_PAGE_IOC_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_6,
  806. Mpi2IOCPage6_t, MPI2_POINTER pMpi2IOCPage6_t;
  807. #define MPI2_IOCPAGE6_PAGEVERSION (0x04)
  808. /* defines for IOC Page 6 CapabilitiesFlags */
  809. #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010)
  810. #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008)
  811. #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004)
  812. #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002)
  813. #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001)
  814. /* IOC Page 7 */
  815. #define MPI2_IOCPAGE7_EVENTMASK_WORDS (4)
  816. typedef struct _MPI2_CONFIG_PAGE_IOC_7
  817. {
  818. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  819. U32 Reserved1; /* 0x04 */
  820. U32 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/* 0x08 */
  821. U16 SASBroadcastPrimitiveMasks; /* 0x18 */
  822. U16 Reserved2; /* 0x1A */
  823. U32 Reserved3; /* 0x1C */
  824. } MPI2_CONFIG_PAGE_IOC_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_7,
  825. Mpi2IOCPage7_t, MPI2_POINTER pMpi2IOCPage7_t;
  826. #define MPI2_IOCPAGE7_PAGEVERSION (0x01)
  827. /* IOC Page 8 */
  828. typedef struct _MPI2_CONFIG_PAGE_IOC_8
  829. {
  830. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  831. U8 NumDevsPerEnclosure; /* 0x04 */
  832. U8 Reserved1; /* 0x05 */
  833. U16 Reserved2; /* 0x06 */
  834. U16 MaxPersistentEntries; /* 0x08 */
  835. U16 MaxNumPhysicalMappedIDs; /* 0x0A */
  836. U16 Flags; /* 0x0C */
  837. U16 Reserved3; /* 0x0E */
  838. U16 IRVolumeMappingFlags; /* 0x10 */
  839. U16 Reserved4; /* 0x12 */
  840. U32 Reserved5; /* 0x14 */
  841. } MPI2_CONFIG_PAGE_IOC_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_8,
  842. Mpi2IOCPage8_t, MPI2_POINTER pMpi2IOCPage8_t;
  843. #define MPI2_IOCPAGE8_PAGEVERSION (0x00)
  844. /* defines for IOC Page 8 Flags field */
  845. #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020)
  846. #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010)
  847. #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E)
  848. #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000)
  849. #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002)
  850. #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001)
  851. #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000)
  852. /* defines for IOC Page 8 IRVolumeMappingFlags */
  853. #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003)
  854. #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000)
  855. #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001)
  856. /****************************************************************************
  857. * BIOS Config Pages
  858. ****************************************************************************/
  859. /* BIOS Page 1 */
  860. typedef struct _MPI2_CONFIG_PAGE_BIOS_1
  861. {
  862. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  863. U32 BiosOptions; /* 0x04 */
  864. U32 IOCSettings; /* 0x08 */
  865. U32 Reserved1; /* 0x0C */
  866. U32 DeviceSettings; /* 0x10 */
  867. U16 NumberOfDevices; /* 0x14 */
  868. U16 Reserved2; /* 0x16 */
  869. U16 IOTimeoutBlockDevicesNonRM; /* 0x18 */
  870. U16 IOTimeoutSequential; /* 0x1A */
  871. U16 IOTimeoutOther; /* 0x1C */
  872. U16 IOTimeoutBlockDevicesRM; /* 0x1E */
  873. } MPI2_CONFIG_PAGE_BIOS_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_1,
  874. Mpi2BiosPage1_t, MPI2_POINTER pMpi2BiosPage1_t;
  875. #define MPI2_BIOSPAGE1_PAGEVERSION (0x04)
  876. /* values for BIOS Page 1 BiosOptions field */
  877. #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001)
  878. /* values for BIOS Page 1 IOCSettings field */
  879. #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000)
  880. #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000)
  881. #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000)
  882. #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0)
  883. #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000)
  884. #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040)
  885. #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080)
  886. #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030)
  887. #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000)
  888. #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010)
  889. #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020)
  890. #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030)
  891. #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008)
  892. /* values for BIOS Page 1 DeviceSettings field */
  893. #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010)
  894. #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008)
  895. #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004)
  896. #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002)
  897. #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001)
  898. /* BIOS Page 2 */
  899. typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER
  900. {
  901. U32 Reserved1; /* 0x00 */
  902. U32 Reserved2; /* 0x04 */
  903. U32 Reserved3; /* 0x08 */
  904. U32 Reserved4; /* 0x0C */
  905. U32 Reserved5; /* 0x10 */
  906. U32 Reserved6; /* 0x14 */
  907. } MPI2_BOOT_DEVICE_ADAPTER_ORDER,
  908. MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER,
  909. Mpi2BootDeviceAdapterOrder_t, MPI2_POINTER pMpi2BootDeviceAdapterOrder_t;
  910. typedef struct _MPI2_BOOT_DEVICE_SAS_WWID
  911. {
  912. U64 SASAddress; /* 0x00 */
  913. U8 LUN[8]; /* 0x08 */
  914. U32 Reserved1; /* 0x10 */
  915. U32 Reserved2; /* 0x14 */
  916. } MPI2_BOOT_DEVICE_SAS_WWID, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_SAS_WWID,
  917. Mpi2BootDeviceSasWwid_t, MPI2_POINTER pMpi2BootDeviceSasWwid_t;
  918. typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT
  919. {
  920. U64 EnclosureLogicalID; /* 0x00 */
  921. U32 Reserved1; /* 0x08 */
  922. U32 Reserved2; /* 0x0C */
  923. U16 SlotNumber; /* 0x10 */
  924. U16 Reserved3; /* 0x12 */
  925. U32 Reserved4; /* 0x14 */
  926. } MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
  927. MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
  928. Mpi2BootDeviceEnclosureSlot_t, MPI2_POINTER pMpi2BootDeviceEnclosureSlot_t;
  929. typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME
  930. {
  931. U64 DeviceName; /* 0x00 */
  932. U8 LUN[8]; /* 0x08 */
  933. U32 Reserved1; /* 0x10 */
  934. U32 Reserved2; /* 0x14 */
  935. } MPI2_BOOT_DEVICE_DEVICE_NAME, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_DEVICE_NAME,
  936. Mpi2BootDeviceDeviceName_t, MPI2_POINTER pMpi2BootDeviceDeviceName_t;
  937. typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE
  938. {
  939. MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder;
  940. MPI2_BOOT_DEVICE_SAS_WWID SasWwid;
  941. MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot;
  942. MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName;
  943. } MPI2_BIOSPAGE2_BOOT_DEVICE, MPI2_POINTER PTR_MPI2_BIOSPAGE2_BOOT_DEVICE,
  944. Mpi2BiosPage2BootDevice_t, MPI2_POINTER pMpi2BiosPage2BootDevice_t;
  945. typedef struct _MPI2_CONFIG_PAGE_BIOS_2
  946. {
  947. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  948. U32 Reserved1; /* 0x04 */
  949. U32 Reserved2; /* 0x08 */
  950. U32 Reserved3; /* 0x0C */
  951. U32 Reserved4; /* 0x10 */
  952. U32 Reserved5; /* 0x14 */
  953. U32 Reserved6; /* 0x18 */
  954. U8 ReqBootDeviceForm; /* 0x1C */
  955. U8 Reserved7; /* 0x1D */
  956. U16 Reserved8; /* 0x1E */
  957. MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /* 0x20 */
  958. U8 ReqAltBootDeviceForm; /* 0x38 */
  959. U8 Reserved9; /* 0x39 */
  960. U16 Reserved10; /* 0x3A */
  961. MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /* 0x3C */
  962. U8 CurrentBootDeviceForm; /* 0x58 */
  963. U8 Reserved11; /* 0x59 */
  964. U16 Reserved12; /* 0x5A */
  965. MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /* 0x58 */
  966. } MPI2_CONFIG_PAGE_BIOS_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_2,
  967. Mpi2BiosPage2_t, MPI2_POINTER pMpi2BiosPage2_t;
  968. #define MPI2_BIOSPAGE2_PAGEVERSION (0x04)
  969. /* values for BIOS Page 2 BootDeviceForm fields */
  970. #define MPI2_BIOSPAGE2_FORM_MASK (0x0F)
  971. #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00)
  972. #define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05)
  973. #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06)
  974. #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07)
  975. /* BIOS Page 3 */
  976. typedef struct _MPI2_ADAPTER_INFO
  977. {
  978. U8 PciBusNumber; /* 0x00 */
  979. U8 PciDeviceAndFunctionNumber; /* 0x01 */
  980. U16 AdapterFlags; /* 0x02 */
  981. } MPI2_ADAPTER_INFO, MPI2_POINTER PTR_MPI2_ADAPTER_INFO,
  982. Mpi2AdapterInfo_t, MPI2_POINTER pMpi2AdapterInfo_t;
  983. #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001)
  984. #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002)
  985. typedef struct _MPI2_CONFIG_PAGE_BIOS_3
  986. {
  987. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  988. U32 GlobalFlags; /* 0x04 */
  989. U32 BiosVersion; /* 0x08 */
  990. MPI2_ADAPTER_INFO AdapterOrder[4]; /* 0x0C */
  991. U32 Reserved1; /* 0x1C */
  992. } MPI2_CONFIG_PAGE_BIOS_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_3,
  993. Mpi2BiosPage3_t, MPI2_POINTER pMpi2BiosPage3_t;
  994. #define MPI2_BIOSPAGE3_PAGEVERSION (0x00)
  995. /* values for BIOS Page 3 GlobalFlags */
  996. #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002)
  997. #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004)
  998. #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010)
  999. #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0)
  1000. #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000)
  1001. #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020)
  1002. #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040)
  1003. /* BIOS Page 4 */
  1004. /*
  1005. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  1006. * one and check the value returned for NumPhys at runtime.
  1007. */
  1008. #ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES
  1009. #define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1)
  1010. #endif
  1011. typedef struct _MPI2_BIOS4_ENTRY
  1012. {
  1013. U64 ReassignmentWWID; /* 0x00 */
  1014. U64 ReassignmentDeviceName; /* 0x08 */
  1015. } MPI2_BIOS4_ENTRY, MPI2_POINTER PTR_MPI2_BIOS4_ENTRY,
  1016. Mpi2MBios4Entry_t, MPI2_POINTER pMpi2Bios4Entry_t;
  1017. typedef struct _MPI2_CONFIG_PAGE_BIOS_4
  1018. {
  1019. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  1020. U8 NumPhys; /* 0x04 */
  1021. U8 Reserved1; /* 0x05 */
  1022. U16 Reserved2; /* 0x06 */
  1023. MPI2_BIOS4_ENTRY Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /* 0x08 */
  1024. } MPI2_CONFIG_PAGE_BIOS_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_4,
  1025. Mpi2BiosPage4_t, MPI2_POINTER pMpi2BiosPage4_t;
  1026. #define MPI2_BIOSPAGE4_PAGEVERSION (0x01)
  1027. /****************************************************************************
  1028. * RAID Volume Config Pages
  1029. ****************************************************************************/
  1030. /* RAID Volume Page 0 */
  1031. typedef struct _MPI2_RAIDVOL0_PHYS_DISK
  1032. {
  1033. U8 RAIDSetNum; /* 0x00 */
  1034. U8 PhysDiskMap; /* 0x01 */
  1035. U8 PhysDiskNum; /* 0x02 */
  1036. U8 Reserved; /* 0x03 */
  1037. } MPI2_RAIDVOL0_PHYS_DISK, MPI2_POINTER PTR_MPI2_RAIDVOL0_PHYS_DISK,
  1038. Mpi2RaidVol0PhysDisk_t, MPI2_POINTER pMpi2RaidVol0PhysDisk_t;
  1039. /* defines for the PhysDiskMap field */
  1040. #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01)
  1041. #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02)
  1042. typedef struct _MPI2_RAIDVOL0_SETTINGS
  1043. {
  1044. U16 Settings; /* 0x00 */
  1045. U8 HotSparePool; /* 0x01 */
  1046. U8 Reserved; /* 0x02 */
  1047. } MPI2_RAIDVOL0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDVOL0_SETTINGS,
  1048. Mpi2RaidVol0Settings_t, MPI2_POINTER pMpi2RaidVol0Settings_t;
  1049. /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
  1050. #define MPI2_RAID_HOT_SPARE_POOL_0 (0x01)
  1051. #define MPI2_RAID_HOT_SPARE_POOL_1 (0x02)
  1052. #define MPI2_RAID_HOT_SPARE_POOL_2 (0x04)
  1053. #define MPI2_RAID_HOT_SPARE_POOL_3 (0x08)
  1054. #define MPI2_RAID_HOT_SPARE_POOL_4 (0x10)
  1055. #define MPI2_RAID_HOT_SPARE_POOL_5 (0x20)
  1056. #define MPI2_RAID_HOT_SPARE_POOL_6 (0x40)
  1057. #define MPI2_RAID_HOT_SPARE_POOL_7 (0x80)
  1058. /* RAID Volume Page 0 VolumeSettings defines */
  1059. #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008)
  1060. #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004)
  1061. #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003)
  1062. #define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000)
  1063. #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001)
  1064. #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002)
  1065. /*
  1066. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  1067. * one and check the value returned for NumPhysDisks at runtime.
  1068. */
  1069. #ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX
  1070. #define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1)
  1071. #endif
  1072. typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0
  1073. {
  1074. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  1075. U16 DevHandle; /* 0x04 */
  1076. U8 VolumeState; /* 0x06 */
  1077. U8 VolumeType; /* 0x07 */
  1078. U32 VolumeStatusFlags; /* 0x08 */
  1079. MPI2_RAIDVOL0_SETTINGS VolumeSettings; /* 0x0C */
  1080. U64 MaxLBA; /* 0x10 */
  1081. U32 StripeSize; /* 0x18 */
  1082. U16 BlockSize; /* 0x1C */
  1083. U16 Reserved1; /* 0x1E */
  1084. U8 SupportedPhysDisks; /* 0x20 */
  1085. U8 ResyncRate; /* 0x21 */
  1086. U16 DataScrubDuration; /* 0x22 */
  1087. U8 NumPhysDisks; /* 0x24 */
  1088. U8 Reserved2; /* 0x25 */
  1089. U8 Reserved3; /* 0x26 */
  1090. U8 InactiveStatus; /* 0x27 */
  1091. MPI2_RAIDVOL0_PHYS_DISK PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /* 0x28 */
  1092. } MPI2_CONFIG_PAGE_RAID_VOL_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_0,
  1093. Mpi2RaidVolPage0_t, MPI2_POINTER pMpi2RaidVolPage0_t;
  1094. #define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A)
  1095. /* values for RAID VolumeState */
  1096. #define MPI2_RAID_VOL_STATE_MISSING (0x00)
  1097. #define MPI2_RAID_VOL_STATE_FAILED (0x01)
  1098. #define MPI2_RAID_VOL_STATE_INITIALIZING (0x02)
  1099. #define MPI2_RAID_VOL_STATE_ONLINE (0x03)
  1100. #define MPI2_RAID_VOL_STATE_DEGRADED (0x04)
  1101. #define MPI2_RAID_VOL_STATE_OPTIMAL (0x05)
  1102. /* values for RAID VolumeType */
  1103. #define MPI2_RAID_VOL_TYPE_RAID0 (0x00)
  1104. #define MPI2_RAID_VOL_TYPE_RAID1E (0x01)
  1105. #define MPI2_RAID_VOL_TYPE_RAID1 (0x02)
  1106. #define MPI2_RAID_VOL_TYPE_RAID10 (0x05)
  1107. #define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF)
  1108. /* values for RAID Volume Page 0 VolumeStatusFlags field */
  1109. #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000)
  1110. #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000)
  1111. #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000)
  1112. #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000)
  1113. #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000)
  1114. #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000)
  1115. #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000)
  1116. #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000)
  1117. #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000)
  1118. #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000)
  1119. #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040)
  1120. #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020)
  1121. #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000)
  1122. #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010)
  1123. #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008)
  1124. #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004)
  1125. #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002)
  1126. #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001)
  1127. /* values for RAID Volume Page 0 SupportedPhysDisks field */
  1128. #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08)
  1129. #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04)
  1130. #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02)
  1131. #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01)
  1132. /* values for RAID Volume Page 0 InactiveStatus field */
  1133. #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00)
  1134. #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01)
  1135. #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02)
  1136. #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03)
  1137. #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04)
  1138. #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05)
  1139. #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06)
  1140. /* RAID Volume Page 1 */
  1141. typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1
  1142. {
  1143. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  1144. U16 DevHandle; /* 0x04 */
  1145. U16 Reserved0; /* 0x06 */
  1146. U8 GUID[24]; /* 0x08 */
  1147. U8 Name[16]; /* 0x20 */
  1148. U64 WWID; /* 0x30 */
  1149. U32 Reserved1; /* 0x38 */
  1150. U32 Reserved2; /* 0x3C */
  1151. } MPI2_CONFIG_PAGE_RAID_VOL_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_1,
  1152. Mpi2RaidVolPage1_t, MPI2_POINTER pMpi2RaidVolPage1_t;
  1153. #define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03)
  1154. /****************************************************************************
  1155. * RAID Physical Disk Config Pages
  1156. ****************************************************************************/
  1157. /* RAID Physical Disk Page 0 */
  1158. typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS
  1159. {
  1160. U16 Reserved1; /* 0x00 */
  1161. U8 HotSparePool; /* 0x02 */
  1162. U8 Reserved2; /* 0x03 */
  1163. } MPI2_RAIDPHYSDISK0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_SETTINGS,
  1164. Mpi2RaidPhysDisk0Settings_t, MPI2_POINTER pMpi2RaidPhysDisk0Settings_t;
  1165. /* use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */
  1166. typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA
  1167. {
  1168. U8 VendorID[8]; /* 0x00 */
  1169. U8 ProductID[16]; /* 0x08 */
  1170. U8 ProductRevLevel[4]; /* 0x18 */
  1171. U8 SerialNum[32]; /* 0x1C */
  1172. } MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
  1173. MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
  1174. Mpi2RaidPhysDisk0InquiryData_t, MPI2_POINTER pMpi2RaidPhysDisk0InquiryData_t;
  1175. typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0
  1176. {
  1177. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  1178. U16 DevHandle; /* 0x04 */
  1179. U8 Reserved1; /* 0x06 */
  1180. U8 PhysDiskNum; /* 0x07 */
  1181. MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /* 0x08 */
  1182. U32 Reserved2; /* 0x0C */
  1183. MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /* 0x10 */
  1184. U32 Reserved3; /* 0x4C */
  1185. U8 PhysDiskState; /* 0x50 */
  1186. U8 OfflineReason; /* 0x51 */
  1187. U8 IncompatibleReason; /* 0x52 */
  1188. U8 PhysDiskAttributes; /* 0x53 */
  1189. U32 PhysDiskStatusFlags; /* 0x54 */
  1190. U64 DeviceMaxLBA; /* 0x58 */
  1191. U64 HostMaxLBA; /* 0x60 */
  1192. U64 CoercedMaxLBA; /* 0x68 */
  1193. U16 BlockSize; /* 0x70 */
  1194. U16 Reserved5; /* 0x72 */
  1195. U32 Reserved6; /* 0x74 */
  1196. } MPI2_CONFIG_PAGE_RD_PDISK_0,
  1197. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_0,
  1198. Mpi2RaidPhysDiskPage0_t, MPI2_POINTER pMpi2RaidPhysDiskPage0_t;
  1199. #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05)
  1200. /* PhysDiskState defines */
  1201. #define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00)
  1202. #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01)
  1203. #define MPI2_RAID_PD_STATE_OFFLINE (0x02)
  1204. #define MPI2_RAID_PD_STATE_ONLINE (0x03)
  1205. #define MPI2_RAID_PD_STATE_HOT_SPARE (0x04)
  1206. #define MPI2_RAID_PD_STATE_DEGRADED (0x05)
  1207. #define MPI2_RAID_PD_STATE_REBUILDING (0x06)
  1208. #define MPI2_RAID_PD_STATE_OPTIMAL (0x07)
  1209. /* OfflineReason defines */
  1210. #define MPI2_PHYSDISK0_ONLINE (0x00)
  1211. #define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01)
  1212. #define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03)
  1213. #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04)
  1214. #define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05)
  1215. #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06)
  1216. #define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF)
  1217. /* IncompatibleReason defines */
  1218. #define MPI2_PHYSDISK0_COMPATIBLE (0x00)
  1219. #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01)
  1220. #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02)
  1221. #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03)
  1222. #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04)
  1223. #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05)
  1224. #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF)
  1225. /* PhysDiskAttributes defines */
  1226. #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08)
  1227. #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04)
  1228. #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02)
  1229. #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01)
  1230. /* PhysDiskStatusFlags defines */
  1231. #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040)
  1232. #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020)
  1233. #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010)
  1234. #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000)
  1235. #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008)
  1236. #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004)
  1237. #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002)
  1238. #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001)
  1239. /* RAID Physical Disk Page 1 */
  1240. /*
  1241. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  1242. * one and check the value returned for NumPhysDiskPaths at runtime.
  1243. */
  1244. #ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX
  1245. #define MPI2_RAID_PHYS_DISK1_PATH_MAX (1)
  1246. #endif
  1247. typedef struct _MPI2_RAIDPHYSDISK1_PATH
  1248. {
  1249. U16 DevHandle; /* 0x00 */
  1250. U16 Reserved1; /* 0x02 */
  1251. U64 WWID; /* 0x04 */
  1252. U64 OwnerWWID; /* 0x0C */
  1253. U8 OwnerIdentifier; /* 0x14 */
  1254. U8 Reserved2; /* 0x15 */
  1255. U16 Flags; /* 0x16 */
  1256. } MPI2_RAIDPHYSDISK1_PATH, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK1_PATH,
  1257. Mpi2RaidPhysDisk1Path_t, MPI2_POINTER pMpi2RaidPhysDisk1Path_t;
  1258. /* RAID Physical Disk Page 1 Physical Disk Path Flags field defines */
  1259. #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004)
  1260. #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002)
  1261. #define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001)
  1262. typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1
  1263. {
  1264. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  1265. U8 NumPhysDiskPaths; /* 0x04 */
  1266. U8 PhysDiskNum; /* 0x05 */
  1267. U16 Reserved1; /* 0x06 */
  1268. U32 Reserved2; /* 0x08 */
  1269. MPI2_RAIDPHYSDISK1_PATH PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/* 0x0C */
  1270. } MPI2_CONFIG_PAGE_RD_PDISK_1,
  1271. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_1,
  1272. Mpi2RaidPhysDiskPage1_t, MPI2_POINTER pMpi2RaidPhysDiskPage1_t;
  1273. #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02)
  1274. /****************************************************************************
  1275. * values for fields used by several types of SAS Config Pages
  1276. ****************************************************************************/
  1277. /* values for NegotiatedLinkRates fields */
  1278. #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0)
  1279. #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4)
  1280. #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F)
  1281. /* link rates used for Negotiated Physical and Logical Link Rate */
  1282. #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00)
  1283. #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01)
  1284. #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02)
  1285. #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03)
  1286. #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04)
  1287. #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05)
  1288. #define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08)
  1289. #define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09)
  1290. #define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A)
  1291. /* values for AttachedPhyInfo fields */
  1292. #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040)
  1293. #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020)
  1294. #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010)
  1295. #define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F)
  1296. #define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000)
  1297. #define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001)
  1298. #define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002)
  1299. #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003)
  1300. #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004)
  1301. #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005)
  1302. #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006)
  1303. #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007)
  1304. #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008)
  1305. /* values for PhyInfo fields */
  1306. #define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000)
  1307. #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000)
  1308. #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000)
  1309. #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000)
  1310. #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000)
  1311. #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000)
  1312. #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000)
  1313. #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000)
  1314. #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000)
  1315. #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000)
  1316. #define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000)
  1317. #define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000)
  1318. #define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000)
  1319. #define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000)
  1320. #define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000)
  1321. #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000)
  1322. #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000)
  1323. #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000)
  1324. #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000)
  1325. #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000)
  1326. #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000)
  1327. #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000)
  1328. #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000)
  1329. #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000)
  1330. #define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000)
  1331. #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00)
  1332. #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8)
  1333. #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0)
  1334. #define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000)
  1335. #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010)
  1336. #define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020)
  1337. /* values for SAS ProgrammedLinkRate fields */
  1338. #define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0)
  1339. #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00)
  1340. #define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80)
  1341. #define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90)
  1342. #define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0)
  1343. #define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F)
  1344. #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00)
  1345. #define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08)
  1346. #define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09)
  1347. #define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A)
  1348. /* values for SAS HwLinkRate fields */
  1349. #define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0)
  1350. #define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80)
  1351. #define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90)
  1352. #define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0)
  1353. #define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F)
  1354. #define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08)
  1355. #define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09)
  1356. #define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A)
  1357. /****************************************************************************
  1358. * SAS IO Unit Config Pages
  1359. ****************************************************************************/
  1360. /* SAS IO Unit Page 0 */
  1361. typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA
  1362. {
  1363. U8 Port; /* 0x00 */
  1364. U8 PortFlags; /* 0x01 */
  1365. U8 PhyFlags; /* 0x02 */
  1366. U8 NegotiatedLinkRate; /* 0x03 */
  1367. U32 ControllerPhyDeviceInfo;/* 0x04 */
  1368. U16 AttachedDevHandle; /* 0x08 */
  1369. U16 ControllerDevHandle; /* 0x0A */
  1370. U32 DiscoveryStatus; /* 0x0C */
  1371. U32 Reserved; /* 0x10 */
  1372. } MPI2_SAS_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT0_PHY_DATA,
  1373. Mpi2SasIOUnit0PhyData_t, MPI2_POINTER pMpi2SasIOUnit0PhyData_t;
  1374. /*
  1375. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  1376. * one and check the value returned for NumPhys at runtime.
  1377. */
  1378. #ifndef MPI2_SAS_IOUNIT0_PHY_MAX
  1379. #define MPI2_SAS_IOUNIT0_PHY_MAX (1)
  1380. #endif
  1381. typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0
  1382. {
  1383. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  1384. U32 Reserved1; /* 0x08 */
  1385. U8 NumPhys; /* 0x0C */
  1386. U8 Reserved2; /* 0x0D */
  1387. U16 Reserved3; /* 0x0E */
  1388. MPI2_SAS_IO_UNIT0_PHY_DATA PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /* 0x10 */
  1389. } MPI2_CONFIG_PAGE_SASIOUNIT_0,
  1390. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0,
  1391. Mpi2SasIOUnitPage0_t, MPI2_POINTER pMpi2SasIOUnitPage0_t;
  1392. #define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05)
  1393. /* values for SAS IO Unit Page 0 PortFlags */
  1394. #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08)
  1395. #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01)
  1396. /* values for SAS IO Unit Page 0 PhyFlags */
  1397. #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10)
  1398. #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08)
  1399. /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
  1400. /* see mpi2_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
  1401. /* values for SAS IO Unit Page 0 DiscoveryStatus */
  1402. #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
  1403. #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
  1404. #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000)
  1405. #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
  1406. #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000)
  1407. #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
  1408. #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
  1409. #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000)
  1410. #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
  1411. #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800)
  1412. #define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400)
  1413. #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200)
  1414. #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100)
  1415. #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080)
  1416. #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040)
  1417. #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020)
  1418. #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010)
  1419. #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004)
  1420. #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002)
  1421. #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001)
  1422. /* SAS IO Unit Page 1 */
  1423. typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA
  1424. {
  1425. U8 Port; /* 0x00 */
  1426. U8 PortFlags; /* 0x01 */
  1427. U8 PhyFlags; /* 0x02 */
  1428. U8 MaxMinLinkRate; /* 0x03 */
  1429. U32 ControllerPhyDeviceInfo; /* 0x04 */
  1430. U16 MaxTargetPortConnectTime; /* 0x08 */
  1431. U16 Reserved1; /* 0x0A */
  1432. } MPI2_SAS_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT1_PHY_DATA,
  1433. Mpi2SasIOUnit1PhyData_t, MPI2_POINTER pMpi2SasIOUnit1PhyData_t;
  1434. /*
  1435. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  1436. * one and check the value returned for NumPhys at runtime.
  1437. */
  1438. #ifndef MPI2_SAS_IOUNIT1_PHY_MAX
  1439. #define MPI2_SAS_IOUNIT1_PHY_MAX (1)
  1440. #endif
  1441. typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1
  1442. {
  1443. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  1444. U16 ControlFlags; /* 0x08 */
  1445. U16 SASNarrowMaxQueueDepth; /* 0x0A */
  1446. U16 AdditionalControlFlags; /* 0x0C */
  1447. U16 SASWideMaxQueueDepth; /* 0x0E */
  1448. U8 NumPhys; /* 0x10 */
  1449. U8 SATAMaxQDepth; /* 0x11 */
  1450. U8 ReportDeviceMissingDelay; /* 0x12 */
  1451. U8 IODeviceMissingDelay; /* 0x13 */
  1452. MPI2_SAS_IO_UNIT1_PHY_DATA PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /* 0x14 */
  1453. } MPI2_CONFIG_PAGE_SASIOUNIT_1,
  1454. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1,
  1455. Mpi2SasIOUnitPage1_t, MPI2_POINTER pMpi2SasIOUnitPage1_t;
  1456. #define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09)
  1457. /* values for SAS IO Unit Page 1 ControlFlags */
  1458. #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000)
  1459. #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000)
  1460. #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000)
  1461. #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000)
  1462. #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600)
  1463. #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9)
  1464. #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0)
  1465. #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1)
  1466. #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2)
  1467. #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080)
  1468. #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040)
  1469. #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020)
  1470. #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010)
  1471. #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008)
  1472. #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004)
  1473. #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002)
  1474. #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001)
  1475. /* values for SAS IO Unit Page 1 AdditionalControlFlags */
  1476. #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080)
  1477. #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040)
  1478. #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020)
  1479. #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010)
  1480. #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008)
  1481. #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004)
  1482. #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002)
  1483. #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001)
  1484. /* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */
  1485. #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F)
  1486. #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80)
  1487. /* values for SAS IO Unit Page 1 PortFlags */
  1488. #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
  1489. /* values for SAS IO Unit Page 1 PhyFlags */
  1490. #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10)
  1491. #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08)
  1492. /* values for SAS IO Unit Page 1 MaxMinLinkRate */
  1493. #define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0)
  1494. #define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80)
  1495. #define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90)
  1496. #define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0)
  1497. #define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F)
  1498. #define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08)
  1499. #define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09)
  1500. #define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A)
  1501. /* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
  1502. /* SAS IO Unit Page 4 */
  1503. typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP
  1504. {
  1505. U8 MaxTargetSpinup; /* 0x00 */
  1506. U8 SpinupDelay; /* 0x01 */
  1507. U16 Reserved1; /* 0x02 */
  1508. } MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP,
  1509. Mpi2SasIOUnit4SpinupGroup_t, MPI2_POINTER pMpi2SasIOUnit4SpinupGroup_t;
  1510. /*
  1511. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  1512. * one and check the value returned for NumPhys at runtime.
  1513. */
  1514. #ifndef MPI2_SAS_IOUNIT4_PHY_MAX
  1515. #define MPI2_SAS_IOUNIT4_PHY_MAX (4)
  1516. #endif
  1517. typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4
  1518. {
  1519. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  1520. MPI2_SAS_IOUNIT4_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */
  1521. U32 Reserved1; /* 0x18 */
  1522. U32 Reserved2; /* 0x1C */
  1523. U32 Reserved3; /* 0x20 */
  1524. U8 BootDeviceWaitTime; /* 0x24 */
  1525. U8 Reserved4; /* 0x25 */
  1526. U16 Reserved5; /* 0x26 */
  1527. U8 NumPhys; /* 0x28 */
  1528. U8 PEInitialSpinupDelay; /* 0x29 */
  1529. U8 PEReplyDelay; /* 0x2A */
  1530. U8 Flags; /* 0x2B */
  1531. U8 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /* 0x2C */
  1532. } MPI2_CONFIG_PAGE_SASIOUNIT_4,
  1533. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4,
  1534. Mpi2SasIOUnitPage4_t, MPI2_POINTER pMpi2SasIOUnitPage4_t;
  1535. #define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02)
  1536. /* defines for Flags field */
  1537. #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01)
  1538. /* defines for PHY field */
  1539. #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03)
  1540. /* SAS IO Unit Page 5 */
  1541. typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS {
  1542. U8 ControlFlags; /* 0x00 */
  1543. U8 PortWidthModGroup; /* 0x01 */
  1544. U16 InactivityTimerExponent; /* 0x02 */
  1545. U8 SATAPartialTimeout; /* 0x04 */
  1546. U8 Reserved2; /* 0x05 */
  1547. U8 SATASlumberTimeout; /* 0x06 */
  1548. U8 Reserved3; /* 0x07 */
  1549. U8 SASPartialTimeout; /* 0x08 */
  1550. U8 Reserved4; /* 0x09 */
  1551. U8 SASSlumberTimeout; /* 0x0A */
  1552. U8 Reserved5; /* 0x0B */
  1553. } MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
  1554. MPI2_POINTER PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
  1555. Mpi2SasIOUnit5PhyPmSettings_t, MPI2_POINTER pMpi2SasIOUnit5PhyPmSettings_t;
  1556. /* defines for ControlFlags field */
  1557. #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08)
  1558. #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04)
  1559. #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02)
  1560. #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01)
  1561. /* defines for PortWidthModeGroup field */
  1562. #define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF)
  1563. /* defines for InactivityTimerExponent field */
  1564. #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000)
  1565. #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12)
  1566. #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700)
  1567. #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8)
  1568. #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070)
  1569. #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4)
  1570. #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007)
  1571. #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0)
  1572. #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7)
  1573. #define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6)
  1574. #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5)
  1575. #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4)
  1576. #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3)
  1577. #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2)
  1578. #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1)
  1579. #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0)
  1580. /*
  1581. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  1582. * one and check the value returned for NumPhys at runtime.
  1583. */
  1584. #ifndef MPI2_SAS_IOUNIT5_PHY_MAX
  1585. #define MPI2_SAS_IOUNIT5_PHY_MAX (1)
  1586. #endif
  1587. typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 {
  1588. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  1589. U8 NumPhys; /* 0x08 */
  1590. U8 Reserved1; /* 0x09 */
  1591. U16 Reserved2; /* 0x0A */
  1592. U32 Reserved3; /* 0x0C */
  1593. MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS SASPhyPowerManagementSettings
  1594. [MPI2_SAS_IOUNIT5_PHY_MAX]; /* 0x10 */
  1595. } MPI2_CONFIG_PAGE_SASIOUNIT_5,
  1596. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5,
  1597. Mpi2SasIOUnitPage5_t, MPI2_POINTER pMpi2SasIOUnitPage5_t;
  1598. #define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01)
  1599. /* SAS IO Unit Page 6 */
  1600. typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS {
  1601. U8 CurrentStatus; /* 0x00 */
  1602. U8 CurrentModulation; /* 0x01 */
  1603. U8 CurrentUtilization; /* 0x02 */
  1604. U8 Reserved1; /* 0x03 */
  1605. U32 Reserved2; /* 0x04 */
  1606. } MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
  1607. MPI2_POINTER PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
  1608. Mpi2SasIOUnit6PortWidthModGroupStatus_t,
  1609. MPI2_POINTER pMpi2SasIOUnit6PortWidthModGroupStatus_t;
  1610. /* defines for CurrentStatus field */
  1611. #define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00)
  1612. #define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01)
  1613. #define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02)
  1614. #define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03)
  1615. #define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04)
  1616. #define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05)
  1617. #define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06)
  1618. #define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07)
  1619. /* defines for CurrentModulation field */
  1620. #define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00)
  1621. #define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01)
  1622. #define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02)
  1623. #define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03)
  1624. /*
  1625. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  1626. * one and check the value returned for NumGroups at runtime.
  1627. */
  1628. #ifndef MPI2_SAS_IOUNIT6_GROUP_MAX
  1629. #define MPI2_SAS_IOUNIT6_GROUP_MAX (1)
  1630. #endif
  1631. typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6 {
  1632. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  1633. U32 Reserved1; /* 0x08 */
  1634. U32 Reserved2; /* 0x0C */
  1635. U8 NumGroups; /* 0x10 */
  1636. U8 Reserved3; /* 0x11 */
  1637. U16 Reserved4; /* 0x12 */
  1638. MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS
  1639. PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /* 0x14 */
  1640. } MPI2_CONFIG_PAGE_SASIOUNIT_6,
  1641. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6,
  1642. Mpi2SasIOUnitPage6_t, MPI2_POINTER pMpi2SasIOUnitPage6_t;
  1643. #define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00)
  1644. /* SAS IO Unit Page 7 */
  1645. typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS {
  1646. U8 Flags; /* 0x00 */
  1647. U8 Reserved1; /* 0x01 */
  1648. U16 Reserved2; /* 0x02 */
  1649. U8 Threshold75Pct; /* 0x04 */
  1650. U8 Threshold50Pct; /* 0x05 */
  1651. U8 Threshold25Pct; /* 0x06 */
  1652. U8 Reserved3; /* 0x07 */
  1653. } MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
  1654. MPI2_POINTER PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
  1655. Mpi2SasIOUnit7PortWidthModGroupSettings_t,
  1656. MPI2_POINTER pMpi2SasIOUnit7PortWidthModGroupSettings_t;
  1657. /* defines for Flags field */
  1658. #define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01)
  1659. /*
  1660. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  1661. * one and check the value returned for NumGroups at runtime.
  1662. */
  1663. #ifndef MPI2_SAS_IOUNIT7_GROUP_MAX
  1664. #define MPI2_SAS_IOUNIT7_GROUP_MAX (1)
  1665. #endif
  1666. typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7 {
  1667. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  1668. U8 SamplingInterval; /* 0x08 */
  1669. U8 WindowLength; /* 0x09 */
  1670. U16 Reserved1; /* 0x0A */
  1671. U32 Reserved2; /* 0x0C */
  1672. U32 Reserved3; /* 0x10 */
  1673. U8 NumGroups; /* 0x14 */
  1674. U8 Reserved4; /* 0x15 */
  1675. U16 Reserved5; /* 0x16 */
  1676. MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS
  1677. PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX]; /* 0x18 */
  1678. } MPI2_CONFIG_PAGE_SASIOUNIT_7,
  1679. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7,
  1680. Mpi2SasIOUnitPage7_t, MPI2_POINTER pMpi2SasIOUnitPage7_t;
  1681. #define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00)
  1682. /* SAS IO Unit Page 8 */
  1683. typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8 {
  1684. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  1685. U32 Reserved1; /* 0x08 */
  1686. U32 PowerManagementCapabilities;/* 0x0C */
  1687. U32 Reserved2; /* 0x10 */
  1688. } MPI2_CONFIG_PAGE_SASIOUNIT_8,
  1689. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8,
  1690. Mpi2SasIOUnitPage8_t, MPI2_POINTER pMpi2SasIOUnitPage8_t;
  1691. #define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00)
  1692. /* defines for PowerManagementCapabilities field */
  1693. #define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x000001000)
  1694. #define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x000000800)
  1695. #define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x000000400)
  1696. #define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x000000200)
  1697. #define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x000000100)
  1698. #define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x000000010)
  1699. #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x000000008)
  1700. #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x000000004)
  1701. #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x000000002)
  1702. #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x000000001)
  1703. /****************************************************************************
  1704. * SAS Expander Config Pages
  1705. ****************************************************************************/
  1706. /* SAS Expander Page 0 */
  1707. typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0
  1708. {
  1709. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  1710. U8 PhysicalPort; /* 0x08 */
  1711. U8 ReportGenLength; /* 0x09 */
  1712. U16 EnclosureHandle; /* 0x0A */
  1713. U64 SASAddress; /* 0x0C */
  1714. U32 DiscoveryStatus; /* 0x14 */
  1715. U16 DevHandle; /* 0x18 */
  1716. U16 ParentDevHandle; /* 0x1A */
  1717. U16 ExpanderChangeCount; /* 0x1C */
  1718. U16 ExpanderRouteIndexes; /* 0x1E */
  1719. U8 NumPhys; /* 0x20 */
  1720. U8 SASLevel; /* 0x21 */
  1721. U16 Flags; /* 0x22 */
  1722. U16 STPBusInactivityTimeLimit; /* 0x24 */
  1723. U16 STPMaxConnectTimeLimit; /* 0x26 */
  1724. U16 STP_SMP_NexusLossTime; /* 0x28 */
  1725. U16 MaxNumRoutedSasAddresses; /* 0x2A */
  1726. U64 ActiveZoneManagerSASAddress;/* 0x2C */
  1727. U16 ZoneLockInactivityLimit; /* 0x34 */
  1728. U16 Reserved1; /* 0x36 */
  1729. U8 TimeToReducedFunc; /* 0x38 */
  1730. U8 InitialTimeToReducedFunc; /* 0x39 */
  1731. U8 MaxReducedFuncTime; /* 0x3A */
  1732. U8 Reserved2; /* 0x3B */
  1733. } MPI2_CONFIG_PAGE_EXPANDER_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_0,
  1734. Mpi2ExpanderPage0_t, MPI2_POINTER pMpi2ExpanderPage0_t;
  1735. #define MPI2_SASEXPANDER0_PAGEVERSION (0x06)
  1736. /* values for SAS Expander Page 0 DiscoveryStatus field */
  1737. #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
  1738. #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
  1739. #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000)
  1740. #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
  1741. #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000)
  1742. #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
  1743. #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
  1744. #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000)
  1745. #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
  1746. #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800)
  1747. #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400)
  1748. #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200)
  1749. #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100)
  1750. #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080)
  1751. #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040)
  1752. #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020)
  1753. #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010)
  1754. #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004)
  1755. #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002)
  1756. #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001)
  1757. /* values for SAS Expander Page 0 Flags field */
  1758. #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000)
  1759. #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000)
  1760. #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800)
  1761. #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400)
  1762. #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200)
  1763. #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100)
  1764. #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080)
  1765. #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010)
  1766. #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004)
  1767. #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002)
  1768. #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001)
  1769. /* SAS Expander Page 1 */
  1770. typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1
  1771. {
  1772. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  1773. U8 PhysicalPort; /* 0x08 */
  1774. U8 Reserved1; /* 0x09 */
  1775. U16 Reserved2; /* 0x0A */
  1776. U8 NumPhys; /* 0x0C */
  1777. U8 Phy; /* 0x0D */
  1778. U16 NumTableEntriesProgrammed; /* 0x0E */
  1779. U8 ProgrammedLinkRate; /* 0x10 */
  1780. U8 HwLinkRate; /* 0x11 */
  1781. U16 AttachedDevHandle; /* 0x12 */
  1782. U32 PhyInfo; /* 0x14 */
  1783. U32 AttachedDeviceInfo; /* 0x18 */
  1784. U16 ExpanderDevHandle; /* 0x1C */
  1785. U8 ChangeCount; /* 0x1E */
  1786. U8 NegotiatedLinkRate; /* 0x1F */
  1787. U8 PhyIdentifier; /* 0x20 */
  1788. U8 AttachedPhyIdentifier; /* 0x21 */
  1789. U8 Reserved3; /* 0x22 */
  1790. U8 DiscoveryInfo; /* 0x23 */
  1791. U32 AttachedPhyInfo; /* 0x24 */
  1792. U8 ZoneGroup; /* 0x28 */
  1793. U8 SelfConfigStatus; /* 0x29 */
  1794. U16 Reserved4; /* 0x2A */
  1795. } MPI2_CONFIG_PAGE_EXPANDER_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_1,
  1796. Mpi2ExpanderPage1_t, MPI2_POINTER pMpi2ExpanderPage1_t;
  1797. #define MPI2_SASEXPANDER1_PAGEVERSION (0x02)
  1798. /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
  1799. /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
  1800. /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
  1801. /* see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines used for the AttachedDeviceInfo field */
  1802. /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
  1803. /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
  1804. /* values for SAS Expander Page 1 DiscoveryInfo field */
  1805. #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04)
  1806. #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02)
  1807. #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01)
  1808. /****************************************************************************
  1809. * SAS Device Config Pages
  1810. ****************************************************************************/
  1811. /* SAS Device Page 0 */
  1812. typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0
  1813. {
  1814. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  1815. U16 Slot; /* 0x08 */
  1816. U16 EnclosureHandle; /* 0x0A */
  1817. U64 SASAddress; /* 0x0C */
  1818. U16 ParentDevHandle; /* 0x14 */
  1819. U8 PhyNum; /* 0x16 */
  1820. U8 AccessStatus; /* 0x17 */
  1821. U16 DevHandle; /* 0x18 */
  1822. U8 AttachedPhyIdentifier; /* 0x1A */
  1823. U8 ZoneGroup; /* 0x1B */
  1824. U32 DeviceInfo; /* 0x1C */
  1825. U16 Flags; /* 0x20 */
  1826. U8 PhysicalPort; /* 0x22 */
  1827. U8 MaxPortConnections; /* 0x23 */
  1828. U64 DeviceName; /* 0x24 */
  1829. U8 PortGroups; /* 0x2C */
  1830. U8 DmaGroup; /* 0x2D */
  1831. U8 ControlGroup; /* 0x2E */
  1832. U8 Reserved1; /* 0x2F */
  1833. U32 Reserved2; /* 0x30 */
  1834. U32 Reserved3; /* 0x34 */
  1835. } MPI2_CONFIG_PAGE_SAS_DEV_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_0,
  1836. Mpi2SasDevicePage0_t, MPI2_POINTER pMpi2SasDevicePage0_t;
  1837. #define MPI2_SASDEVICE0_PAGEVERSION (0x08)
  1838. /* values for SAS Device Page 0 AccessStatus field */
  1839. #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00)
  1840. #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01)
  1841. #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02)
  1842. #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03)
  1843. #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04)
  1844. #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05)
  1845. #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06)
  1846. #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07)
  1847. /* specific values for SATA Init failures */
  1848. #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10)
  1849. #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11)
  1850. #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12)
  1851. #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13)
  1852. #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14)
  1853. #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15)
  1854. #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16)
  1855. #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17)
  1856. #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18)
  1857. #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19)
  1858. #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F)
  1859. /* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */
  1860. /* values for SAS Device Page 0 Flags field */
  1861. #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000)
  1862. #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800)
  1863. #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400)
  1864. #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200)
  1865. #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100)
  1866. #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080)
  1867. #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040)
  1868. #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020)
  1869. #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010)
  1870. #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008)
  1871. #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001)
  1872. /* SAS Device Page 1 */
  1873. typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1
  1874. {
  1875. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  1876. U32 Reserved1; /* 0x08 */
  1877. U64 SASAddress; /* 0x0C */
  1878. U32 Reserved2; /* 0x14 */
  1879. U16 DevHandle; /* 0x18 */
  1880. U16 Reserved3; /* 0x1A */
  1881. U8 InitialRegDeviceFIS[20];/* 0x1C */
  1882. } MPI2_CONFIG_PAGE_SAS_DEV_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_1,
  1883. Mpi2SasDevicePage1_t, MPI2_POINTER pMpi2SasDevicePage1_t;
  1884. #define MPI2_SASDEVICE1_PAGEVERSION (0x01)
  1885. /****************************************************************************
  1886. * SAS PHY Config Pages
  1887. ****************************************************************************/
  1888. /* SAS PHY Page 0 */
  1889. typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0
  1890. {
  1891. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  1892. U16 OwnerDevHandle; /* 0x08 */
  1893. U16 Reserved1; /* 0x0A */
  1894. U16 AttachedDevHandle; /* 0x0C */
  1895. U8 AttachedPhyIdentifier; /* 0x0E */
  1896. U8 Reserved2; /* 0x0F */
  1897. U32 AttachedPhyInfo; /* 0x10 */
  1898. U8 ProgrammedLinkRate; /* 0x14 */
  1899. U8 HwLinkRate; /* 0x15 */
  1900. U8 ChangeCount; /* 0x16 */
  1901. U8 Flags; /* 0x17 */
  1902. U32 PhyInfo; /* 0x18 */
  1903. U8 NegotiatedLinkRate; /* 0x1C */
  1904. U8 Reserved3; /* 0x1D */
  1905. U16 Reserved4; /* 0x1E */
  1906. } MPI2_CONFIG_PAGE_SAS_PHY_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_0,
  1907. Mpi2SasPhyPage0_t, MPI2_POINTER pMpi2SasPhyPage0_t;
  1908. #define MPI2_SASPHY0_PAGEVERSION (0x03)
  1909. /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
  1910. /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
  1911. /* values for SAS PHY Page 0 Flags field */
  1912. #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01)
  1913. /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
  1914. /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
  1915. /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
  1916. /* SAS PHY Page 1 */
  1917. typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1
  1918. {
  1919. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  1920. U32 Reserved1; /* 0x08 */
  1921. U32 InvalidDwordCount; /* 0x0C */
  1922. U32 RunningDisparityErrorCount; /* 0x10 */
  1923. U32 LossDwordSynchCount; /* 0x14 */
  1924. U32 PhyResetProblemCount; /* 0x18 */
  1925. } MPI2_CONFIG_PAGE_SAS_PHY_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_1,
  1926. Mpi2SasPhyPage1_t, MPI2_POINTER pMpi2SasPhyPage1_t;
  1927. #define MPI2_SASPHY1_PAGEVERSION (0x01)
  1928. /* SAS PHY Page 2 */
  1929. typedef struct _MPI2_SASPHY2_PHY_EVENT {
  1930. U8 PhyEventCode; /* 0x00 */
  1931. U8 Reserved1; /* 0x01 */
  1932. U16 Reserved2; /* 0x02 */
  1933. U32 PhyEventInfo; /* 0x04 */
  1934. } MPI2_SASPHY2_PHY_EVENT, MPI2_POINTER PTR_MPI2_SASPHY2_PHY_EVENT,
  1935. Mpi2SasPhy2PhyEvent_t, MPI2_POINTER pMpi2SasPhy2PhyEvent_t;
  1936. /* use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */
  1937. /*
  1938. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  1939. * one and check the value returned for NumPhyEvents at runtime.
  1940. */
  1941. #ifndef MPI2_SASPHY2_PHY_EVENT_MAX
  1942. #define MPI2_SASPHY2_PHY_EVENT_MAX (1)
  1943. #endif
  1944. typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 {
  1945. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  1946. U32 Reserved1; /* 0x08 */
  1947. U8 NumPhyEvents; /* 0x0C */
  1948. U8 Reserved2; /* 0x0D */
  1949. U16 Reserved3; /* 0x0E */
  1950. MPI2_SASPHY2_PHY_EVENT PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX];
  1951. /* 0x10 */
  1952. } MPI2_CONFIG_PAGE_SAS_PHY_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_2,
  1953. Mpi2SasPhyPage2_t, MPI2_POINTER pMpi2SasPhyPage2_t;
  1954. #define MPI2_SASPHY2_PAGEVERSION (0x00)
  1955. /* SAS PHY Page 3 */
  1956. typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG {
  1957. U8 PhyEventCode; /* 0x00 */
  1958. U8 Reserved1; /* 0x01 */
  1959. U16 Reserved2; /* 0x02 */
  1960. U8 CounterType; /* 0x04 */
  1961. U8 ThresholdWindow; /* 0x05 */
  1962. U8 TimeUnits; /* 0x06 */
  1963. U8 Reserved3; /* 0x07 */
  1964. U32 EventThreshold; /* 0x08 */
  1965. U16 ThresholdFlags; /* 0x0C */
  1966. U16 Reserved4; /* 0x0E */
  1967. } MPI2_SASPHY3_PHY_EVENT_CONFIG, MPI2_POINTER PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG,
  1968. Mpi2SasPhy3PhyEventConfig_t, MPI2_POINTER pMpi2SasPhy3PhyEventConfig_t;
  1969. /* values for PhyEventCode field */
  1970. #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00)
  1971. #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01)
  1972. #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02)
  1973. #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03)
  1974. #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04)
  1975. #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05)
  1976. #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06)
  1977. #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20)
  1978. #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21)
  1979. #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22)
  1980. #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23)
  1981. #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24)
  1982. #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25)
  1983. #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26)
  1984. #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27)
  1985. #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28)
  1986. #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29)
  1987. #define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A)
  1988. #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B)
  1989. #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C)
  1990. #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D)
  1991. #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E)
  1992. #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40)
  1993. #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41)
  1994. #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42)
  1995. #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43)
  1996. #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44)
  1997. #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45)
  1998. #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50)
  1999. #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51)
  2000. #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52)
  2001. #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60)
  2002. #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61)
  2003. #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63)
  2004. #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0)
  2005. #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1)
  2006. #define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2)
  2007. /* values for the CounterType field */
  2008. #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00)
  2009. #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01)
  2010. #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02)
  2011. /* values for the TimeUnits field */
  2012. #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00)
  2013. #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01)
  2014. #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02)
  2015. #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03)
  2016. /* values for the ThresholdFlags field */
  2017. #define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002)
  2018. #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001)
  2019. /*
  2020. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  2021. * one and check the value returned for NumPhyEvents at runtime.
  2022. */
  2023. #ifndef MPI2_SASPHY3_PHY_EVENT_MAX
  2024. #define MPI2_SASPHY3_PHY_EVENT_MAX (1)
  2025. #endif
  2026. typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 {
  2027. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  2028. U32 Reserved1; /* 0x08 */
  2029. U8 NumPhyEvents; /* 0x0C */
  2030. U8 Reserved2; /* 0x0D */
  2031. U16 Reserved3; /* 0x0E */
  2032. MPI2_SASPHY3_PHY_EVENT_CONFIG PhyEventConfig
  2033. [MPI2_SASPHY3_PHY_EVENT_MAX]; /* 0x10 */
  2034. } MPI2_CONFIG_PAGE_SAS_PHY_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_3,
  2035. Mpi2SasPhyPage3_t, MPI2_POINTER pMpi2SasPhyPage3_t;
  2036. #define MPI2_SASPHY3_PAGEVERSION (0x00)
  2037. /* SAS PHY Page 4 */
  2038. typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 {
  2039. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  2040. U16 Reserved1; /* 0x08 */
  2041. U8 Reserved2; /* 0x0A */
  2042. U8 Flags; /* 0x0B */
  2043. U8 InitialFrame[28]; /* 0x0C */
  2044. } MPI2_CONFIG_PAGE_SAS_PHY_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_4,
  2045. Mpi2SasPhyPage4_t, MPI2_POINTER pMpi2SasPhyPage4_t;
  2046. #define MPI2_SASPHY4_PAGEVERSION (0x00)
  2047. /* values for the Flags field */
  2048. #define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02)
  2049. #define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01)
  2050. /****************************************************************************
  2051. * SAS Port Config Pages
  2052. ****************************************************************************/
  2053. /* SAS Port Page 0 */
  2054. typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0
  2055. {
  2056. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  2057. U8 PortNumber; /* 0x08 */
  2058. U8 PhysicalPort; /* 0x09 */
  2059. U8 PortWidth; /* 0x0A */
  2060. U8 PhysicalPortWidth; /* 0x0B */
  2061. U8 ZoneGroup; /* 0x0C */
  2062. U8 Reserved1; /* 0x0D */
  2063. U16 Reserved2; /* 0x0E */
  2064. U64 SASAddress; /* 0x10 */
  2065. U32 DeviceInfo; /* 0x18 */
  2066. U32 Reserved3; /* 0x1C */
  2067. U32 Reserved4; /* 0x20 */
  2068. } MPI2_CONFIG_PAGE_SAS_PORT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PORT_0,
  2069. Mpi2SasPortPage0_t, MPI2_POINTER pMpi2SasPortPage0_t;
  2070. #define MPI2_SASPORT0_PAGEVERSION (0x00)
  2071. /* see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */
  2072. /****************************************************************************
  2073. * SAS Enclosure Config Pages
  2074. ****************************************************************************/
  2075. /* SAS Enclosure Page 0 */
  2076. typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0
  2077. {
  2078. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  2079. U32 Reserved1; /* 0x08 */
  2080. U64 EnclosureLogicalID; /* 0x0C */
  2081. U16 Flags; /* 0x14 */
  2082. U16 EnclosureHandle; /* 0x16 */
  2083. U16 NumSlots; /* 0x18 */
  2084. U16 StartSlot; /* 0x1A */
  2085. U16 Reserved2; /* 0x1C */
  2086. U16 SEPDevHandle; /* 0x1E */
  2087. U32 Reserved3; /* 0x20 */
  2088. U32 Reserved4; /* 0x24 */
  2089. } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
  2090. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
  2091. Mpi2SasEnclosurePage0_t, MPI2_POINTER pMpi2SasEnclosurePage0_t;
  2092. #define MPI2_SASENCLOSURE0_PAGEVERSION (0x03)
  2093. /* values for SAS Enclosure Page 0 Flags field */
  2094. #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F)
  2095. #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000)
  2096. #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001)
  2097. #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002)
  2098. #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003)
  2099. #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004)
  2100. #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005)
  2101. /****************************************************************************
  2102. * Log Config Page
  2103. ****************************************************************************/
  2104. /* Log Page 0 */
  2105. /*
  2106. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  2107. * one and check the value returned for NumLogEntries at runtime.
  2108. */
  2109. #ifndef MPI2_LOG_0_NUM_LOG_ENTRIES
  2110. #define MPI2_LOG_0_NUM_LOG_ENTRIES (1)
  2111. #endif
  2112. #define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C)
  2113. typedef struct _MPI2_LOG_0_ENTRY
  2114. {
  2115. U64 TimeStamp; /* 0x00 */
  2116. U32 Reserved1; /* 0x08 */
  2117. U16 LogSequence; /* 0x0C */
  2118. U16 LogEntryQualifier; /* 0x0E */
  2119. U8 VP_ID; /* 0x10 */
  2120. U8 VF_ID; /* 0x11 */
  2121. U16 Reserved2; /* 0x12 */
  2122. U8 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/* 0x14 */
  2123. } MPI2_LOG_0_ENTRY, MPI2_POINTER PTR_MPI2_LOG_0_ENTRY,
  2124. Mpi2Log0Entry_t, MPI2_POINTER pMpi2Log0Entry_t;
  2125. /* values for Log Page 0 LogEntry LogEntryQualifier field */
  2126. #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000)
  2127. #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001)
  2128. #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002)
  2129. #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000)
  2130. #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF)
  2131. typedef struct _MPI2_CONFIG_PAGE_LOG_0
  2132. {
  2133. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  2134. U32 Reserved1; /* 0x08 */
  2135. U32 Reserved2; /* 0x0C */
  2136. U16 NumLogEntries; /* 0x10 */
  2137. U16 Reserved3; /* 0x12 */
  2138. MPI2_LOG_0_ENTRY LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /* 0x14 */
  2139. } MPI2_CONFIG_PAGE_LOG_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_LOG_0,
  2140. Mpi2LogPage0_t, MPI2_POINTER pMpi2LogPage0_t;
  2141. #define MPI2_LOG_0_PAGEVERSION (0x02)
  2142. /****************************************************************************
  2143. * RAID Config Page
  2144. ****************************************************************************/
  2145. /* RAID Page 0 */
  2146. /*
  2147. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  2148. * one and check the value returned for NumElements at runtime.
  2149. */
  2150. #ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS
  2151. #define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1)
  2152. #endif
  2153. typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT
  2154. {
  2155. U16 ElementFlags; /* 0x00 */
  2156. U16 VolDevHandle; /* 0x02 */
  2157. U8 HotSparePool; /* 0x04 */
  2158. U8 PhysDiskNum; /* 0x05 */
  2159. U16 PhysDiskDevHandle; /* 0x06 */
  2160. } MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
  2161. MPI2_POINTER PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
  2162. Mpi2RaidConfig0ConfigElement_t, MPI2_POINTER pMpi2RaidConfig0ConfigElement_t;
  2163. /* values for the ElementFlags field */
  2164. #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F)
  2165. #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000)
  2166. #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001)
  2167. #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002)
  2168. #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003)
  2169. typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0
  2170. {
  2171. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  2172. U8 NumHotSpares; /* 0x08 */
  2173. U8 NumPhysDisks; /* 0x09 */
  2174. U8 NumVolumes; /* 0x0A */
  2175. U8 ConfigNum; /* 0x0B */
  2176. U32 Flags; /* 0x0C */
  2177. U8 ConfigGUID[24]; /* 0x10 */
  2178. U32 Reserved1; /* 0x28 */
  2179. U8 NumElements; /* 0x2C */
  2180. U8 Reserved2; /* 0x2D */
  2181. U16 Reserved3; /* 0x2E */
  2182. MPI2_RAIDCONFIG0_CONFIG_ELEMENT ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /* 0x30 */
  2183. } MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
  2184. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
  2185. Mpi2RaidConfigurationPage0_t, MPI2_POINTER pMpi2RaidConfigurationPage0_t;
  2186. #define MPI2_RAIDCONFIG0_PAGEVERSION (0x00)
  2187. /* values for RAID Configuration Page 0 Flags field */
  2188. #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001)
  2189. /****************************************************************************
  2190. * Driver Persistent Mapping Config Pages
  2191. ****************************************************************************/
  2192. /* Driver Persistent Mapping Page 0 */
  2193. typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY
  2194. {
  2195. U64 PhysicalIdentifier; /* 0x00 */
  2196. U16 MappingInformation; /* 0x08 */
  2197. U16 DeviceIndex; /* 0x0A */
  2198. U32 PhysicalBitsMapping; /* 0x0C */
  2199. U32 Reserved1; /* 0x10 */
  2200. } MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
  2201. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
  2202. Mpi2DriverMap0Entry_t, MPI2_POINTER pMpi2DriverMap0Entry_t;
  2203. typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0
  2204. {
  2205. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  2206. MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /* 0x08 */
  2207. } MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
  2208. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
  2209. Mpi2DriverMappingPage0_t, MPI2_POINTER pMpi2DriverMappingPage0_t;
  2210. #define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00)
  2211. /* values for Driver Persistent Mapping Page 0 MappingInformation field */
  2212. #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0)
  2213. #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4)
  2214. #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F)
  2215. /****************************************************************************
  2216. * Ethernet Config Pages
  2217. ****************************************************************************/
  2218. /* Ethernet Page 0 */
  2219. /* IP address (union of IPv4 and IPv6) */
  2220. typedef union _MPI2_ETHERNET_IP_ADDR {
  2221. U32 IPv4Addr;
  2222. U32 IPv6Addr[4];
  2223. } MPI2_ETHERNET_IP_ADDR, MPI2_POINTER PTR_MPI2_ETHERNET_IP_ADDR,
  2224. Mpi2EthernetIpAddr_t, MPI2_POINTER pMpi2EthernetIpAddr_t;
  2225. #define MPI2_ETHERNET_HOST_NAME_LENGTH (32)
  2226. typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 {
  2227. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  2228. U8 NumInterfaces; /* 0x08 */
  2229. U8 Reserved0; /* 0x09 */
  2230. U16 Reserved1; /* 0x0A */
  2231. U32 Status; /* 0x0C */
  2232. U8 MediaState; /* 0x10 */
  2233. U8 Reserved2; /* 0x11 */
  2234. U16 Reserved3; /* 0x12 */
  2235. U8 MacAddress[6]; /* 0x14 */
  2236. U8 Reserved4; /* 0x1A */
  2237. U8 Reserved5; /* 0x1B */
  2238. MPI2_ETHERNET_IP_ADDR IpAddress; /* 0x1C */
  2239. MPI2_ETHERNET_IP_ADDR SubnetMask; /* 0x2C */
  2240. MPI2_ETHERNET_IP_ADDR GatewayIpAddress; /* 0x3C */
  2241. MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /* 0x4C */
  2242. MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /* 0x5C */
  2243. MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /* 0x6C */
  2244. U8 HostName
  2245. [MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
  2246. } MPI2_CONFIG_PAGE_ETHERNET_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_0,
  2247. Mpi2EthernetPage0_t, MPI2_POINTER pMpi2EthernetPage0_t;
  2248. #define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00)
  2249. /* values for Ethernet Page 0 Status field */
  2250. #define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000)
  2251. #define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000)
  2252. #define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000)
  2253. #define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100)
  2254. #define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080)
  2255. #define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040)
  2256. #define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020)
  2257. #define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010)
  2258. #define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008)
  2259. #define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004)
  2260. #define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002)
  2261. #define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001)
  2262. /* values for Ethernet Page 0 MediaState field */
  2263. #define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80)
  2264. #define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00)
  2265. #define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80)
  2266. #define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07)
  2267. #define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00)
  2268. #define MPI2_ETHPG0_MS_10MBIT (0x01)
  2269. #define MPI2_ETHPG0_MS_100MBIT (0x02)
  2270. #define MPI2_ETHPG0_MS_1GBIT (0x03)
  2271. /* Ethernet Page 1 */
  2272. typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 {
  2273. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  2274. U32 Reserved0; /* 0x08 */
  2275. U32 Flags; /* 0x0C */
  2276. U8 MediaState; /* 0x10 */
  2277. U8 Reserved1; /* 0x11 */
  2278. U16 Reserved2; /* 0x12 */
  2279. U8 MacAddress[6]; /* 0x14 */
  2280. U8 Reserved3; /* 0x1A */
  2281. U8 Reserved4; /* 0x1B */
  2282. MPI2_ETHERNET_IP_ADDR StaticIpAddress; /* 0x1C */
  2283. MPI2_ETHERNET_IP_ADDR StaticSubnetMask; /* 0x2C */
  2284. MPI2_ETHERNET_IP_ADDR StaticGatewayIpAddress; /* 0x3C */
  2285. MPI2_ETHERNET_IP_ADDR StaticDNS1IpAddress; /* 0x4C */
  2286. MPI2_ETHERNET_IP_ADDR StaticDNS2IpAddress; /* 0x5C */
  2287. U32 Reserved5; /* 0x6C */
  2288. U32 Reserved6; /* 0x70 */
  2289. U32 Reserved7; /* 0x74 */
  2290. U32 Reserved8; /* 0x78 */
  2291. U8 HostName
  2292. [MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
  2293. } MPI2_CONFIG_PAGE_ETHERNET_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_1,
  2294. Mpi2EthernetPage1_t, MPI2_POINTER pMpi2EthernetPage1_t;
  2295. #define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00)
  2296. /* values for Ethernet Page 1 Flags field */
  2297. #define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100)
  2298. #define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080)
  2299. #define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040)
  2300. #define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020)
  2301. #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010)
  2302. #define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008)
  2303. #define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004)
  2304. #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002)
  2305. #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001)
  2306. /* values for Ethernet Page 1 MediaState field */
  2307. #define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80)
  2308. #define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00)
  2309. #define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80)
  2310. #define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07)
  2311. #define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00)
  2312. #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01)
  2313. #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02)
  2314. #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03)
  2315. #endif