radeon_pm.c 14 KB

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  1. /*
  2. * Permission is hereby granted, free of charge, to any person obtaining a
  3. * copy of this software and associated documentation files (the "Software"),
  4. * to deal in the Software without restriction, including without limitation
  5. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  6. * and/or sell copies of the Software, and to permit persons to whom the
  7. * Software is furnished to do so, subject to the following conditions:
  8. *
  9. * The above copyright notice and this permission notice shall be included in
  10. * all copies or substantial portions of the Software.
  11. *
  12. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  15. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  16. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  17. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  18. * OTHER DEALINGS IN THE SOFTWARE.
  19. *
  20. * Authors: Rafał Miłecki <zajec5@gmail.com>
  21. * Alex Deucher <alexdeucher@gmail.com>
  22. */
  23. #include "drmP.h"
  24. #include "radeon.h"
  25. #include "avivod.h"
  26. #define RADEON_IDLE_LOOP_MS 100
  27. #define RADEON_RECLOCK_DELAY_MS 200
  28. #define RADEON_WAIT_VBLANK_TIMEOUT 200
  29. #define RADEON_WAIT_IDLE_TIMEOUT 200
  30. static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
  31. static void radeon_pm_set_clocks_locked(struct radeon_device *rdev);
  32. static void radeon_pm_set_clocks(struct radeon_device *rdev);
  33. static void radeon_pm_idle_work_handler(struct work_struct *work);
  34. static int radeon_debugfs_pm_init(struct radeon_device *rdev);
  35. static const char *pm_state_names[4] = {
  36. "PM_STATE_DISABLED",
  37. "PM_STATE_MINIMUM",
  38. "PM_STATE_PAUSED",
  39. "PM_STATE_ACTIVE"
  40. };
  41. static const char *pm_state_types[5] = {
  42. "Default",
  43. "Powersave",
  44. "Battery",
  45. "Balanced",
  46. "Performance",
  47. };
  48. static void radeon_print_power_mode_info(struct radeon_device *rdev)
  49. {
  50. int i, j;
  51. bool is_default;
  52. DRM_INFO("%d Power State(s)\n", rdev->pm.num_power_states);
  53. for (i = 0; i < rdev->pm.num_power_states; i++) {
  54. if (rdev->pm.default_power_state == &rdev->pm.power_state[i])
  55. is_default = true;
  56. else
  57. is_default = false;
  58. DRM_INFO("State %d %s %s\n", i,
  59. pm_state_types[rdev->pm.power_state[i].type],
  60. is_default ? "(default)" : "");
  61. if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
  62. DRM_INFO("\t%d PCIE Lanes\n", rdev->pm.power_state[i].non_clock_info.pcie_lanes);
  63. DRM_INFO("\t%d Clock Mode(s)\n", rdev->pm.power_state[i].num_clock_modes);
  64. for (j = 0; j < rdev->pm.power_state[i].num_clock_modes; j++) {
  65. if (rdev->flags & RADEON_IS_IGP)
  66. DRM_INFO("\t\t%d engine: %d\n",
  67. j,
  68. rdev->pm.power_state[i].clock_info[j].sclk * 10);
  69. else
  70. DRM_INFO("\t\t%d engine/memory: %d/%d\n",
  71. j,
  72. rdev->pm.power_state[i].clock_info[j].sclk * 10,
  73. rdev->pm.power_state[i].clock_info[j].mclk * 10);
  74. }
  75. }
  76. }
  77. static struct radeon_power_state * radeon_pick_power_state(struct radeon_device *rdev,
  78. enum radeon_pm_state_type type)
  79. {
  80. int i, j;
  81. enum radeon_pm_state_type wanted_types[2];
  82. int wanted_count;
  83. switch (type) {
  84. case POWER_STATE_TYPE_DEFAULT:
  85. default:
  86. return rdev->pm.default_power_state;
  87. case POWER_STATE_TYPE_POWERSAVE:
  88. if (rdev->flags & RADEON_IS_MOBILITY) {
  89. wanted_types[0] = POWER_STATE_TYPE_POWERSAVE;
  90. wanted_types[1] = POWER_STATE_TYPE_BATTERY;
  91. wanted_count = 2;
  92. } else {
  93. wanted_types[0] = POWER_STATE_TYPE_PERFORMANCE;
  94. wanted_count = 1;
  95. }
  96. break;
  97. case POWER_STATE_TYPE_BATTERY:
  98. if (rdev->flags & RADEON_IS_MOBILITY) {
  99. wanted_types[0] = POWER_STATE_TYPE_BATTERY;
  100. wanted_types[1] = POWER_STATE_TYPE_POWERSAVE;
  101. wanted_count = 2;
  102. } else {
  103. wanted_types[0] = POWER_STATE_TYPE_PERFORMANCE;
  104. wanted_count = 1;
  105. }
  106. break;
  107. case POWER_STATE_TYPE_BALANCED:
  108. case POWER_STATE_TYPE_PERFORMANCE:
  109. wanted_types[0] = type;
  110. wanted_count = 1;
  111. break;
  112. }
  113. for (i = 0; i < wanted_count; i++) {
  114. for (j = 0; j < rdev->pm.num_power_states; j++) {
  115. if (rdev->pm.power_state[j].type == wanted_types[i])
  116. return &rdev->pm.power_state[j];
  117. }
  118. }
  119. return rdev->pm.default_power_state;
  120. }
  121. static struct radeon_pm_clock_info * radeon_pick_clock_mode(struct radeon_device *rdev,
  122. struct radeon_power_state *power_state,
  123. enum radeon_pm_clock_mode_type type)
  124. {
  125. switch (type) {
  126. case POWER_MODE_TYPE_DEFAULT:
  127. default:
  128. return power_state->default_clock_mode;
  129. case POWER_MODE_TYPE_LOW:
  130. return &power_state->clock_info[0];
  131. case POWER_MODE_TYPE_MID:
  132. if (power_state->num_clock_modes > 2)
  133. return &power_state->clock_info[1];
  134. else
  135. return &power_state->clock_info[0];
  136. break;
  137. case POWER_MODE_TYPE_HIGH:
  138. return &power_state->clock_info[power_state->num_clock_modes - 1];
  139. }
  140. }
  141. static void radeon_get_power_state(struct radeon_device *rdev,
  142. enum radeon_pm_action action)
  143. {
  144. switch (action) {
  145. case PM_ACTION_MINIMUM:
  146. rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_BATTERY);
  147. rdev->pm.requested_clock_mode =
  148. radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_LOW);
  149. break;
  150. case PM_ACTION_DOWNCLOCK:
  151. rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_POWERSAVE);
  152. rdev->pm.requested_clock_mode =
  153. radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_MID);
  154. break;
  155. case PM_ACTION_UPCLOCK:
  156. rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_DEFAULT);
  157. rdev->pm.requested_clock_mode =
  158. radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_HIGH);
  159. break;
  160. case PM_ACTION_NONE:
  161. default:
  162. DRM_ERROR("Requested mode for not defined action\n");
  163. return;
  164. }
  165. DRM_INFO("Requested: e: %d m: %d p: %d\n",
  166. rdev->pm.requested_clock_mode->sclk,
  167. rdev->pm.requested_clock_mode->mclk,
  168. rdev->pm.requested_power_state->non_clock_info.pcie_lanes);
  169. }
  170. static inline void radeon_sync_with_vblank(struct radeon_device *rdev)
  171. {
  172. if (rdev->pm.active_crtcs) {
  173. rdev->pm.vblank_sync = false;
  174. wait_event_timeout(
  175. rdev->irq.vblank_queue, rdev->pm.vblank_sync,
  176. msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
  177. }
  178. }
  179. static void radeon_set_power_state(struct radeon_device *rdev)
  180. {
  181. /* if *_clock_mode are the same, *_power_state are as well */
  182. if (rdev->pm.requested_clock_mode == rdev->pm.current_clock_mode)
  183. return;
  184. DRM_INFO("Setting: e: %d m: %d p: %d\n",
  185. rdev->pm.requested_clock_mode->sclk,
  186. rdev->pm.requested_clock_mode->mclk,
  187. rdev->pm.requested_power_state->non_clock_info.pcie_lanes);
  188. /* set pcie lanes */
  189. /* TODO */
  190. /* set voltage */
  191. /* TODO */
  192. /* set engine clock */
  193. radeon_sync_with_vblank(rdev);
  194. radeon_pm_debug_check_in_vbl(rdev, false);
  195. radeon_set_engine_clock(rdev, rdev->pm.requested_clock_mode->sclk);
  196. radeon_pm_debug_check_in_vbl(rdev, true);
  197. #if 0
  198. /* set memory clock */
  199. if (rdev->asic->set_memory_clock) {
  200. radeon_sync_with_vblank(rdev);
  201. radeon_pm_debug_check_in_vbl(rdev, false);
  202. radeon_set_memory_clock(rdev, rdev->pm.requested_clock_mode->mclk);
  203. radeon_pm_debug_check_in_vbl(rdev, true);
  204. }
  205. #endif
  206. rdev->pm.current_power_state = rdev->pm.requested_power_state;
  207. rdev->pm.current_clock_mode = rdev->pm.requested_clock_mode;
  208. }
  209. int radeon_pm_init(struct radeon_device *rdev)
  210. {
  211. rdev->pm.state = PM_STATE_DISABLED;
  212. rdev->pm.planned_action = PM_ACTION_NONE;
  213. rdev->pm.downclocked = false;
  214. if (rdev->bios) {
  215. if (rdev->is_atom_bios)
  216. radeon_atombios_get_power_modes(rdev);
  217. else
  218. radeon_combios_get_power_modes(rdev);
  219. radeon_print_power_mode_info(rdev);
  220. }
  221. if (radeon_debugfs_pm_init(rdev)) {
  222. DRM_ERROR("Failed to register debugfs file for PM!\n");
  223. }
  224. INIT_DELAYED_WORK(&rdev->pm.idle_work, radeon_pm_idle_work_handler);
  225. if (radeon_dynpm != -1 && radeon_dynpm) {
  226. rdev->pm.state = PM_STATE_PAUSED;
  227. DRM_INFO("radeon: dynamic power management enabled\n");
  228. }
  229. DRM_INFO("radeon: power management initialized\n");
  230. return 0;
  231. }
  232. void radeon_pm_fini(struct radeon_device *rdev)
  233. {
  234. if (rdev->pm.i2c_bus)
  235. radeon_i2c_destroy(rdev->pm.i2c_bus);
  236. }
  237. void radeon_pm_compute_clocks(struct radeon_device *rdev)
  238. {
  239. struct drm_device *ddev = rdev->ddev;
  240. struct drm_connector *connector;
  241. struct radeon_crtc *radeon_crtc;
  242. int count = 0;
  243. if (rdev->pm.state == PM_STATE_DISABLED)
  244. return;
  245. mutex_lock(&rdev->pm.mutex);
  246. rdev->pm.active_crtcs = 0;
  247. list_for_each_entry(connector,
  248. &ddev->mode_config.connector_list, head) {
  249. if (connector->encoder &&
  250. connector->encoder->crtc &&
  251. connector->dpms != DRM_MODE_DPMS_OFF) {
  252. radeon_crtc = to_radeon_crtc(connector->encoder->crtc);
  253. rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
  254. ++count;
  255. }
  256. }
  257. if (count > 1) {
  258. if (rdev->pm.state == PM_STATE_ACTIVE) {
  259. cancel_delayed_work(&rdev->pm.idle_work);
  260. rdev->pm.state = PM_STATE_PAUSED;
  261. rdev->pm.planned_action = PM_ACTION_UPCLOCK;
  262. if (rdev->pm.downclocked)
  263. radeon_pm_set_clocks(rdev);
  264. DRM_DEBUG("radeon: dynamic power management deactivated\n");
  265. }
  266. } else if (count == 1) {
  267. /* TODO: Increase clocks if needed for current mode */
  268. if (rdev->pm.state == PM_STATE_MINIMUM) {
  269. rdev->pm.state = PM_STATE_ACTIVE;
  270. rdev->pm.planned_action = PM_ACTION_UPCLOCK;
  271. radeon_pm_set_clocks(rdev);
  272. queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
  273. msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
  274. }
  275. else if (rdev->pm.state == PM_STATE_PAUSED) {
  276. rdev->pm.state = PM_STATE_ACTIVE;
  277. queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
  278. msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
  279. DRM_DEBUG("radeon: dynamic power management activated\n");
  280. }
  281. }
  282. else { /* count == 0 */
  283. if (rdev->pm.state != PM_STATE_MINIMUM) {
  284. cancel_delayed_work(&rdev->pm.idle_work);
  285. rdev->pm.state = PM_STATE_MINIMUM;
  286. rdev->pm.planned_action = PM_ACTION_MINIMUM;
  287. radeon_pm_set_clocks(rdev);
  288. }
  289. }
  290. mutex_unlock(&rdev->pm.mutex);
  291. }
  292. static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
  293. {
  294. u32 stat_crtc1 = 0, stat_crtc2 = 0;
  295. bool in_vbl = true;
  296. if (ASIC_IS_AVIVO(rdev)) {
  297. if (rdev->pm.active_crtcs & (1 << 0)) {
  298. stat_crtc1 = RREG32(D1CRTC_STATUS);
  299. if (!(stat_crtc1 & 1))
  300. in_vbl = false;
  301. }
  302. if (rdev->pm.active_crtcs & (1 << 1)) {
  303. stat_crtc2 = RREG32(D2CRTC_STATUS);
  304. if (!(stat_crtc2 & 1))
  305. in_vbl = false;
  306. }
  307. }
  308. if (in_vbl == false)
  309. DRM_INFO("not in vbl for pm change %08x %08x at %s\n", stat_crtc1,
  310. stat_crtc2, finish ? "exit" : "entry");
  311. return in_vbl;
  312. }
  313. static void radeon_pm_set_clocks_locked(struct radeon_device *rdev)
  314. {
  315. /*radeon_fence_wait_last(rdev);*/
  316. switch (rdev->pm.planned_action) {
  317. case PM_ACTION_UPCLOCK:
  318. rdev->pm.downclocked = false;
  319. break;
  320. case PM_ACTION_DOWNCLOCK:
  321. rdev->pm.downclocked = true;
  322. break;
  323. case PM_ACTION_MINIMUM:
  324. break;
  325. case PM_ACTION_NONE:
  326. DRM_ERROR("%s: PM_ACTION_NONE\n", __func__);
  327. break;
  328. }
  329. radeon_set_power_state(rdev);
  330. rdev->pm.planned_action = PM_ACTION_NONE;
  331. }
  332. static void radeon_pm_set_clocks(struct radeon_device *rdev)
  333. {
  334. radeon_get_power_state(rdev, rdev->pm.planned_action);
  335. mutex_lock(&rdev->cp.mutex);
  336. if (rdev->pm.active_crtcs & (1 << 0)) {
  337. rdev->pm.req_vblank |= (1 << 0);
  338. drm_vblank_get(rdev->ddev, 0);
  339. }
  340. if (rdev->pm.active_crtcs & (1 << 1)) {
  341. rdev->pm.req_vblank |= (1 << 1);
  342. drm_vblank_get(rdev->ddev, 1);
  343. }
  344. radeon_pm_set_clocks_locked(rdev);
  345. if (rdev->pm.req_vblank & (1 << 0)) {
  346. rdev->pm.req_vblank &= ~(1 << 0);
  347. drm_vblank_put(rdev->ddev, 0);
  348. }
  349. if (rdev->pm.req_vblank & (1 << 1)) {
  350. rdev->pm.req_vblank &= ~(1 << 1);
  351. drm_vblank_put(rdev->ddev, 1);
  352. }
  353. mutex_unlock(&rdev->cp.mutex);
  354. }
  355. static void radeon_pm_idle_work_handler(struct work_struct *work)
  356. {
  357. struct radeon_device *rdev;
  358. rdev = container_of(work, struct radeon_device,
  359. pm.idle_work.work);
  360. mutex_lock(&rdev->pm.mutex);
  361. if (rdev->pm.state == PM_STATE_ACTIVE) {
  362. unsigned long irq_flags;
  363. int not_processed = 0;
  364. read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  365. if (!list_empty(&rdev->fence_drv.emited)) {
  366. struct list_head *ptr;
  367. list_for_each(ptr, &rdev->fence_drv.emited) {
  368. /* count up to 3, that's enought info */
  369. if (++not_processed >= 3)
  370. break;
  371. }
  372. }
  373. read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  374. if (not_processed >= 3) { /* should upclock */
  375. if (rdev->pm.planned_action == PM_ACTION_DOWNCLOCK) {
  376. rdev->pm.planned_action = PM_ACTION_NONE;
  377. } else if (rdev->pm.planned_action == PM_ACTION_NONE &&
  378. rdev->pm.downclocked) {
  379. rdev->pm.planned_action =
  380. PM_ACTION_UPCLOCK;
  381. rdev->pm.action_timeout = jiffies +
  382. msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
  383. }
  384. } else if (not_processed == 0) { /* should downclock */
  385. if (rdev->pm.planned_action == PM_ACTION_UPCLOCK) {
  386. rdev->pm.planned_action = PM_ACTION_NONE;
  387. } else if (rdev->pm.planned_action == PM_ACTION_NONE &&
  388. !rdev->pm.downclocked) {
  389. rdev->pm.planned_action =
  390. PM_ACTION_DOWNCLOCK;
  391. rdev->pm.action_timeout = jiffies +
  392. msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
  393. }
  394. }
  395. if (rdev->pm.planned_action != PM_ACTION_NONE &&
  396. jiffies > rdev->pm.action_timeout) {
  397. radeon_pm_set_clocks(rdev);
  398. }
  399. }
  400. mutex_unlock(&rdev->pm.mutex);
  401. queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
  402. msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
  403. }
  404. /*
  405. * Debugfs info
  406. */
  407. #if defined(CONFIG_DEBUG_FS)
  408. static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
  409. {
  410. struct drm_info_node *node = (struct drm_info_node *) m->private;
  411. struct drm_device *dev = node->minor->dev;
  412. struct radeon_device *rdev = dev->dev_private;
  413. seq_printf(m, "state: %s\n", pm_state_names[rdev->pm.state]);
  414. seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk);
  415. seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
  416. seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
  417. if (rdev->asic->get_memory_clock)
  418. seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
  419. if (rdev->asic->get_pcie_lanes)
  420. seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
  421. return 0;
  422. }
  423. static struct drm_info_list radeon_pm_info_list[] = {
  424. {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
  425. };
  426. #endif
  427. static int radeon_debugfs_pm_init(struct radeon_device *rdev)
  428. {
  429. #if defined(CONFIG_DEBUG_FS)
  430. return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
  431. #else
  432. return 0;
  433. #endif
  434. }