r100.c 109 KB

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  1. /*
  2. * Copyright 2008 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. * Copyright 2009 Jerome Glisse.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors: Dave Airlie
  25. * Alex Deucher
  26. * Jerome Glisse
  27. */
  28. #include <linux/seq_file.h>
  29. #include <linux/slab.h>
  30. #include "drmP.h"
  31. #include "drm.h"
  32. #include "radeon_drm.h"
  33. #include "radeon_reg.h"
  34. #include "radeon.h"
  35. #include "radeon_asic.h"
  36. #include "r100d.h"
  37. #include "rs100d.h"
  38. #include "rv200d.h"
  39. #include "rv250d.h"
  40. #include "atom.h"
  41. #include <linux/firmware.h>
  42. #include <linux/platform_device.h>
  43. #include "r100_reg_safe.h"
  44. #include "rn50_reg_safe.h"
  45. /* Firmware Names */
  46. #define FIRMWARE_R100 "radeon/R100_cp.bin"
  47. #define FIRMWARE_R200 "radeon/R200_cp.bin"
  48. #define FIRMWARE_R300 "radeon/R300_cp.bin"
  49. #define FIRMWARE_R420 "radeon/R420_cp.bin"
  50. #define FIRMWARE_RS690 "radeon/RS690_cp.bin"
  51. #define FIRMWARE_RS600 "radeon/RS600_cp.bin"
  52. #define FIRMWARE_R520 "radeon/R520_cp.bin"
  53. MODULE_FIRMWARE(FIRMWARE_R100);
  54. MODULE_FIRMWARE(FIRMWARE_R200);
  55. MODULE_FIRMWARE(FIRMWARE_R300);
  56. MODULE_FIRMWARE(FIRMWARE_R420);
  57. MODULE_FIRMWARE(FIRMWARE_RS690);
  58. MODULE_FIRMWARE(FIRMWARE_RS600);
  59. MODULE_FIRMWARE(FIRMWARE_R520);
  60. #include "r100_track.h"
  61. /* This files gather functions specifics to:
  62. * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
  63. */
  64. void r100_pm_get_dynpm_state(struct radeon_device *rdev)
  65. {
  66. int i;
  67. rdev->pm.dynpm_can_upclock = true;
  68. rdev->pm.dynpm_can_downclock = true;
  69. switch (rdev->pm.dynpm_planned_action) {
  70. case DYNPM_ACTION_MINIMUM:
  71. rdev->pm.requested_power_state_index = 0;
  72. rdev->pm.dynpm_can_downclock = false;
  73. break;
  74. case DYNPM_ACTION_DOWNCLOCK:
  75. if (rdev->pm.current_power_state_index == 0) {
  76. rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
  77. rdev->pm.dynpm_can_downclock = false;
  78. } else {
  79. if (rdev->pm.active_crtc_count > 1) {
  80. for (i = 0; i < rdev->pm.num_power_states; i++) {
  81. if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
  82. continue;
  83. else if (i >= rdev->pm.current_power_state_index) {
  84. rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
  85. break;
  86. } else {
  87. rdev->pm.requested_power_state_index = i;
  88. break;
  89. }
  90. }
  91. } else
  92. rdev->pm.requested_power_state_index =
  93. rdev->pm.current_power_state_index - 1;
  94. }
  95. /* don't use the power state if crtcs are active and no display flag is set */
  96. if ((rdev->pm.active_crtc_count > 0) &&
  97. (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
  98. RADEON_PM_MODE_NO_DISPLAY)) {
  99. rdev->pm.requested_power_state_index++;
  100. }
  101. break;
  102. case DYNPM_ACTION_UPCLOCK:
  103. if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
  104. rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
  105. rdev->pm.dynpm_can_upclock = false;
  106. } else {
  107. if (rdev->pm.active_crtc_count > 1) {
  108. for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
  109. if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
  110. continue;
  111. else if (i <= rdev->pm.current_power_state_index) {
  112. rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
  113. break;
  114. } else {
  115. rdev->pm.requested_power_state_index = i;
  116. break;
  117. }
  118. }
  119. } else
  120. rdev->pm.requested_power_state_index =
  121. rdev->pm.current_power_state_index + 1;
  122. }
  123. break;
  124. case DYNPM_ACTION_DEFAULT:
  125. rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
  126. rdev->pm.dynpm_can_upclock = false;
  127. break;
  128. case DYNPM_ACTION_NONE:
  129. default:
  130. DRM_ERROR("Requested mode for not defined action\n");
  131. return;
  132. }
  133. /* only one clock mode per power state */
  134. rdev->pm.requested_clock_mode_index = 0;
  135. DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
  136. rdev->pm.power_state[rdev->pm.requested_power_state_index].
  137. clock_info[rdev->pm.requested_clock_mode_index].sclk,
  138. rdev->pm.power_state[rdev->pm.requested_power_state_index].
  139. clock_info[rdev->pm.requested_clock_mode_index].mclk,
  140. rdev->pm.power_state[rdev->pm.requested_power_state_index].
  141. pcie_lanes);
  142. }
  143. void r100_pm_init_profile(struct radeon_device *rdev)
  144. {
  145. /* default */
  146. rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
  147. rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
  148. rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
  149. rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
  150. /* low sh */
  151. rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
  152. rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
  153. rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
  154. rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
  155. /* mid sh */
  156. rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
  157. rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
  158. rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
  159. rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
  160. /* high sh */
  161. rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
  162. rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
  163. rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
  164. rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
  165. /* low mh */
  166. rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
  167. rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
  168. rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
  169. rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
  170. /* mid mh */
  171. rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
  172. rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
  173. rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
  174. rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
  175. /* high mh */
  176. rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
  177. rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
  178. rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
  179. rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
  180. }
  181. void r100_pm_misc(struct radeon_device *rdev)
  182. {
  183. int requested_index = rdev->pm.requested_power_state_index;
  184. struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
  185. struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
  186. u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
  187. if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
  188. if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
  189. tmp = RREG32(voltage->gpio.reg);
  190. if (voltage->active_high)
  191. tmp |= voltage->gpio.mask;
  192. else
  193. tmp &= ~(voltage->gpio.mask);
  194. WREG32(voltage->gpio.reg, tmp);
  195. if (voltage->delay)
  196. udelay(voltage->delay);
  197. } else {
  198. tmp = RREG32(voltage->gpio.reg);
  199. if (voltage->active_high)
  200. tmp &= ~voltage->gpio.mask;
  201. else
  202. tmp |= voltage->gpio.mask;
  203. WREG32(voltage->gpio.reg, tmp);
  204. if (voltage->delay)
  205. udelay(voltage->delay);
  206. }
  207. }
  208. sclk_cntl = RREG32_PLL(SCLK_CNTL);
  209. sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
  210. sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
  211. sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
  212. sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
  213. if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
  214. sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
  215. if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
  216. sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
  217. else
  218. sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
  219. if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
  220. sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
  221. else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
  222. sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
  223. } else
  224. sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
  225. if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
  226. sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
  227. if (voltage->delay) {
  228. sclk_more_cntl |= VOLTAGE_DROP_SYNC;
  229. switch (voltage->delay) {
  230. case 33:
  231. sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
  232. break;
  233. case 66:
  234. sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
  235. break;
  236. case 99:
  237. sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
  238. break;
  239. case 132:
  240. sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
  241. break;
  242. }
  243. } else
  244. sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
  245. } else
  246. sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
  247. if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
  248. sclk_cntl &= ~FORCE_HDP;
  249. else
  250. sclk_cntl |= FORCE_HDP;
  251. WREG32_PLL(SCLK_CNTL, sclk_cntl);
  252. WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
  253. WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
  254. /* set pcie lanes */
  255. if ((rdev->flags & RADEON_IS_PCIE) &&
  256. !(rdev->flags & RADEON_IS_IGP) &&
  257. rdev->asic->set_pcie_lanes &&
  258. (ps->pcie_lanes !=
  259. rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
  260. radeon_set_pcie_lanes(rdev,
  261. ps->pcie_lanes);
  262. DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
  263. }
  264. }
  265. void r100_pm_prepare(struct radeon_device *rdev)
  266. {
  267. struct drm_device *ddev = rdev->ddev;
  268. struct drm_crtc *crtc;
  269. struct radeon_crtc *radeon_crtc;
  270. u32 tmp;
  271. /* disable any active CRTCs */
  272. list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
  273. radeon_crtc = to_radeon_crtc(crtc);
  274. if (radeon_crtc->enabled) {
  275. if (radeon_crtc->crtc_id) {
  276. tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
  277. tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
  278. WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
  279. } else {
  280. tmp = RREG32(RADEON_CRTC_GEN_CNTL);
  281. tmp |= RADEON_CRTC_DISP_REQ_EN_B;
  282. WREG32(RADEON_CRTC_GEN_CNTL, tmp);
  283. }
  284. }
  285. }
  286. }
  287. void r100_pm_finish(struct radeon_device *rdev)
  288. {
  289. struct drm_device *ddev = rdev->ddev;
  290. struct drm_crtc *crtc;
  291. struct radeon_crtc *radeon_crtc;
  292. u32 tmp;
  293. /* enable any active CRTCs */
  294. list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
  295. radeon_crtc = to_radeon_crtc(crtc);
  296. if (radeon_crtc->enabled) {
  297. if (radeon_crtc->crtc_id) {
  298. tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
  299. tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
  300. WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
  301. } else {
  302. tmp = RREG32(RADEON_CRTC_GEN_CNTL);
  303. tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
  304. WREG32(RADEON_CRTC_GEN_CNTL, tmp);
  305. }
  306. }
  307. }
  308. }
  309. bool r100_gui_idle(struct radeon_device *rdev)
  310. {
  311. if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
  312. return false;
  313. else
  314. return true;
  315. }
  316. /* hpd for digital panel detect/disconnect */
  317. bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
  318. {
  319. bool connected = false;
  320. switch (hpd) {
  321. case RADEON_HPD_1:
  322. if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
  323. connected = true;
  324. break;
  325. case RADEON_HPD_2:
  326. if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
  327. connected = true;
  328. break;
  329. default:
  330. break;
  331. }
  332. return connected;
  333. }
  334. void r100_hpd_set_polarity(struct radeon_device *rdev,
  335. enum radeon_hpd_id hpd)
  336. {
  337. u32 tmp;
  338. bool connected = r100_hpd_sense(rdev, hpd);
  339. switch (hpd) {
  340. case RADEON_HPD_1:
  341. tmp = RREG32(RADEON_FP_GEN_CNTL);
  342. if (connected)
  343. tmp &= ~RADEON_FP_DETECT_INT_POL;
  344. else
  345. tmp |= RADEON_FP_DETECT_INT_POL;
  346. WREG32(RADEON_FP_GEN_CNTL, tmp);
  347. break;
  348. case RADEON_HPD_2:
  349. tmp = RREG32(RADEON_FP2_GEN_CNTL);
  350. if (connected)
  351. tmp &= ~RADEON_FP2_DETECT_INT_POL;
  352. else
  353. tmp |= RADEON_FP2_DETECT_INT_POL;
  354. WREG32(RADEON_FP2_GEN_CNTL, tmp);
  355. break;
  356. default:
  357. break;
  358. }
  359. }
  360. void r100_hpd_init(struct radeon_device *rdev)
  361. {
  362. struct drm_device *dev = rdev->ddev;
  363. struct drm_connector *connector;
  364. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  365. struct radeon_connector *radeon_connector = to_radeon_connector(connector);
  366. switch (radeon_connector->hpd.hpd) {
  367. case RADEON_HPD_1:
  368. rdev->irq.hpd[0] = true;
  369. break;
  370. case RADEON_HPD_2:
  371. rdev->irq.hpd[1] = true;
  372. break;
  373. default:
  374. break;
  375. }
  376. }
  377. if (rdev->irq.installed)
  378. r100_irq_set(rdev);
  379. }
  380. void r100_hpd_fini(struct radeon_device *rdev)
  381. {
  382. struct drm_device *dev = rdev->ddev;
  383. struct drm_connector *connector;
  384. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  385. struct radeon_connector *radeon_connector = to_radeon_connector(connector);
  386. switch (radeon_connector->hpd.hpd) {
  387. case RADEON_HPD_1:
  388. rdev->irq.hpd[0] = false;
  389. break;
  390. case RADEON_HPD_2:
  391. rdev->irq.hpd[1] = false;
  392. break;
  393. default:
  394. break;
  395. }
  396. }
  397. }
  398. /*
  399. * PCI GART
  400. */
  401. void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
  402. {
  403. /* TODO: can we do somethings here ? */
  404. /* It seems hw only cache one entry so we should discard this
  405. * entry otherwise if first GPU GART read hit this entry it
  406. * could end up in wrong address. */
  407. }
  408. int r100_pci_gart_init(struct radeon_device *rdev)
  409. {
  410. int r;
  411. if (rdev->gart.table.ram.ptr) {
  412. WARN(1, "R100 PCI GART already initialized\n");
  413. return 0;
  414. }
  415. /* Initialize common gart structure */
  416. r = radeon_gart_init(rdev);
  417. if (r)
  418. return r;
  419. rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
  420. rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
  421. rdev->asic->gart_set_page = &r100_pci_gart_set_page;
  422. return radeon_gart_table_ram_alloc(rdev);
  423. }
  424. /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
  425. void r100_enable_bm(struct radeon_device *rdev)
  426. {
  427. uint32_t tmp;
  428. /* Enable bus mastering */
  429. tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
  430. WREG32(RADEON_BUS_CNTL, tmp);
  431. }
  432. int r100_pci_gart_enable(struct radeon_device *rdev)
  433. {
  434. uint32_t tmp;
  435. radeon_gart_restore(rdev);
  436. /* discard memory request outside of configured range */
  437. tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
  438. WREG32(RADEON_AIC_CNTL, tmp);
  439. /* set address range for PCI address translate */
  440. WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
  441. WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
  442. /* set PCI GART page-table base address */
  443. WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
  444. tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
  445. WREG32(RADEON_AIC_CNTL, tmp);
  446. r100_pci_gart_tlb_flush(rdev);
  447. rdev->gart.ready = true;
  448. return 0;
  449. }
  450. void r100_pci_gart_disable(struct radeon_device *rdev)
  451. {
  452. uint32_t tmp;
  453. /* discard memory request outside of configured range */
  454. tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
  455. WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
  456. WREG32(RADEON_AIC_LO_ADDR, 0);
  457. WREG32(RADEON_AIC_HI_ADDR, 0);
  458. }
  459. int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
  460. {
  461. if (i < 0 || i > rdev->gart.num_gpu_pages) {
  462. return -EINVAL;
  463. }
  464. rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
  465. return 0;
  466. }
  467. void r100_pci_gart_fini(struct radeon_device *rdev)
  468. {
  469. radeon_gart_fini(rdev);
  470. r100_pci_gart_disable(rdev);
  471. radeon_gart_table_ram_free(rdev);
  472. }
  473. int r100_irq_set(struct radeon_device *rdev)
  474. {
  475. uint32_t tmp = 0;
  476. if (!rdev->irq.installed) {
  477. WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
  478. WREG32(R_000040_GEN_INT_CNTL, 0);
  479. return -EINVAL;
  480. }
  481. if (rdev->irq.sw_int) {
  482. tmp |= RADEON_SW_INT_ENABLE;
  483. }
  484. if (rdev->irq.gui_idle) {
  485. tmp |= RADEON_GUI_IDLE_MASK;
  486. }
  487. if (rdev->irq.crtc_vblank_int[0]) {
  488. tmp |= RADEON_CRTC_VBLANK_MASK;
  489. }
  490. if (rdev->irq.crtc_vblank_int[1]) {
  491. tmp |= RADEON_CRTC2_VBLANK_MASK;
  492. }
  493. if (rdev->irq.hpd[0]) {
  494. tmp |= RADEON_FP_DETECT_MASK;
  495. }
  496. if (rdev->irq.hpd[1]) {
  497. tmp |= RADEON_FP2_DETECT_MASK;
  498. }
  499. WREG32(RADEON_GEN_INT_CNTL, tmp);
  500. return 0;
  501. }
  502. void r100_irq_disable(struct radeon_device *rdev)
  503. {
  504. u32 tmp;
  505. WREG32(R_000040_GEN_INT_CNTL, 0);
  506. /* Wait and acknowledge irq */
  507. mdelay(1);
  508. tmp = RREG32(R_000044_GEN_INT_STATUS);
  509. WREG32(R_000044_GEN_INT_STATUS, tmp);
  510. }
  511. static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
  512. {
  513. uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
  514. uint32_t irq_mask = RADEON_SW_INT_TEST |
  515. RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
  516. RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
  517. /* the interrupt works, but the status bit is permanently asserted */
  518. if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
  519. if (!rdev->irq.gui_idle_acked)
  520. irq_mask |= RADEON_GUI_IDLE_STAT;
  521. }
  522. if (irqs) {
  523. WREG32(RADEON_GEN_INT_STATUS, irqs);
  524. }
  525. return irqs & irq_mask;
  526. }
  527. int r100_irq_process(struct radeon_device *rdev)
  528. {
  529. uint32_t status, msi_rearm;
  530. bool queue_hotplug = false;
  531. /* reset gui idle ack. the status bit is broken */
  532. rdev->irq.gui_idle_acked = false;
  533. status = r100_irq_ack(rdev);
  534. if (!status) {
  535. return IRQ_NONE;
  536. }
  537. if (rdev->shutdown) {
  538. return IRQ_NONE;
  539. }
  540. while (status) {
  541. /* SW interrupt */
  542. if (status & RADEON_SW_INT_TEST) {
  543. radeon_fence_process(rdev);
  544. }
  545. /* gui idle interrupt */
  546. if (status & RADEON_GUI_IDLE_STAT) {
  547. rdev->irq.gui_idle_acked = true;
  548. rdev->pm.gui_idle = true;
  549. wake_up(&rdev->irq.idle_queue);
  550. }
  551. /* Vertical blank interrupts */
  552. if (status & RADEON_CRTC_VBLANK_STAT) {
  553. drm_handle_vblank(rdev->ddev, 0);
  554. rdev->pm.vblank_sync = true;
  555. wake_up(&rdev->irq.vblank_queue);
  556. }
  557. if (status & RADEON_CRTC2_VBLANK_STAT) {
  558. drm_handle_vblank(rdev->ddev, 1);
  559. rdev->pm.vblank_sync = true;
  560. wake_up(&rdev->irq.vblank_queue);
  561. }
  562. if (status & RADEON_FP_DETECT_STAT) {
  563. queue_hotplug = true;
  564. DRM_DEBUG("HPD1\n");
  565. }
  566. if (status & RADEON_FP2_DETECT_STAT) {
  567. queue_hotplug = true;
  568. DRM_DEBUG("HPD2\n");
  569. }
  570. status = r100_irq_ack(rdev);
  571. }
  572. /* reset gui idle ack. the status bit is broken */
  573. rdev->irq.gui_idle_acked = false;
  574. if (queue_hotplug)
  575. queue_work(rdev->wq, &rdev->hotplug_work);
  576. if (rdev->msi_enabled) {
  577. switch (rdev->family) {
  578. case CHIP_RS400:
  579. case CHIP_RS480:
  580. msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
  581. WREG32(RADEON_AIC_CNTL, msi_rearm);
  582. WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
  583. break;
  584. default:
  585. msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
  586. WREG32(RADEON_MSI_REARM_EN, msi_rearm);
  587. WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
  588. break;
  589. }
  590. }
  591. return IRQ_HANDLED;
  592. }
  593. u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
  594. {
  595. if (crtc == 0)
  596. return RREG32(RADEON_CRTC_CRNT_FRAME);
  597. else
  598. return RREG32(RADEON_CRTC2_CRNT_FRAME);
  599. }
  600. /* Who ever call radeon_fence_emit should call ring_lock and ask
  601. * for enough space (today caller are ib schedule and buffer move) */
  602. void r100_fence_ring_emit(struct radeon_device *rdev,
  603. struct radeon_fence *fence)
  604. {
  605. /* We have to make sure that caches are flushed before
  606. * CPU might read something from VRAM. */
  607. radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
  608. radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
  609. radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
  610. radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
  611. /* Wait until IDLE & CLEAN */
  612. radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
  613. radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
  614. radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
  615. radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
  616. RADEON_HDP_READ_BUFFER_INVALIDATE);
  617. radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
  618. radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
  619. /* Emit fence sequence & fire IRQ */
  620. radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
  621. radeon_ring_write(rdev, fence->seq);
  622. radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
  623. radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
  624. }
  625. int r100_copy_blit(struct radeon_device *rdev,
  626. uint64_t src_offset,
  627. uint64_t dst_offset,
  628. unsigned num_pages,
  629. struct radeon_fence *fence)
  630. {
  631. uint32_t cur_pages;
  632. uint32_t stride_bytes = PAGE_SIZE;
  633. uint32_t pitch;
  634. uint32_t stride_pixels;
  635. unsigned ndw;
  636. int num_loops;
  637. int r = 0;
  638. /* radeon limited to 16k stride */
  639. stride_bytes &= 0x3fff;
  640. /* radeon pitch is /64 */
  641. pitch = stride_bytes / 64;
  642. stride_pixels = stride_bytes / 4;
  643. num_loops = DIV_ROUND_UP(num_pages, 8191);
  644. /* Ask for enough room for blit + flush + fence */
  645. ndw = 64 + (10 * num_loops);
  646. r = radeon_ring_lock(rdev, ndw);
  647. if (r) {
  648. DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
  649. return -EINVAL;
  650. }
  651. while (num_pages > 0) {
  652. cur_pages = num_pages;
  653. if (cur_pages > 8191) {
  654. cur_pages = 8191;
  655. }
  656. num_pages -= cur_pages;
  657. /* pages are in Y direction - height
  658. page width in X direction - width */
  659. radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
  660. radeon_ring_write(rdev,
  661. RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
  662. RADEON_GMC_DST_PITCH_OFFSET_CNTL |
  663. RADEON_GMC_SRC_CLIPPING |
  664. RADEON_GMC_DST_CLIPPING |
  665. RADEON_GMC_BRUSH_NONE |
  666. (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
  667. RADEON_GMC_SRC_DATATYPE_COLOR |
  668. RADEON_ROP3_S |
  669. RADEON_DP_SRC_SOURCE_MEMORY |
  670. RADEON_GMC_CLR_CMP_CNTL_DIS |
  671. RADEON_GMC_WR_MSK_DIS);
  672. radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
  673. radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
  674. radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
  675. radeon_ring_write(rdev, 0);
  676. radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
  677. radeon_ring_write(rdev, num_pages);
  678. radeon_ring_write(rdev, num_pages);
  679. radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
  680. }
  681. radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
  682. radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
  683. radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
  684. radeon_ring_write(rdev,
  685. RADEON_WAIT_2D_IDLECLEAN |
  686. RADEON_WAIT_HOST_IDLECLEAN |
  687. RADEON_WAIT_DMA_GUI_IDLE);
  688. if (fence) {
  689. r = radeon_fence_emit(rdev, fence);
  690. }
  691. radeon_ring_unlock_commit(rdev);
  692. return r;
  693. }
  694. static int r100_cp_wait_for_idle(struct radeon_device *rdev)
  695. {
  696. unsigned i;
  697. u32 tmp;
  698. for (i = 0; i < rdev->usec_timeout; i++) {
  699. tmp = RREG32(R_000E40_RBBM_STATUS);
  700. if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
  701. return 0;
  702. }
  703. udelay(1);
  704. }
  705. return -1;
  706. }
  707. void r100_ring_start(struct radeon_device *rdev)
  708. {
  709. int r;
  710. r = radeon_ring_lock(rdev, 2);
  711. if (r) {
  712. return;
  713. }
  714. radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
  715. radeon_ring_write(rdev,
  716. RADEON_ISYNC_ANY2D_IDLE3D |
  717. RADEON_ISYNC_ANY3D_IDLE2D |
  718. RADEON_ISYNC_WAIT_IDLEGUI |
  719. RADEON_ISYNC_CPSCRATCH_IDLEGUI);
  720. radeon_ring_unlock_commit(rdev);
  721. }
  722. /* Load the microcode for the CP */
  723. static int r100_cp_init_microcode(struct radeon_device *rdev)
  724. {
  725. struct platform_device *pdev;
  726. const char *fw_name = NULL;
  727. int err;
  728. DRM_DEBUG_KMS("\n");
  729. pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
  730. err = IS_ERR(pdev);
  731. if (err) {
  732. printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
  733. return -EINVAL;
  734. }
  735. if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
  736. (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
  737. (rdev->family == CHIP_RS200)) {
  738. DRM_INFO("Loading R100 Microcode\n");
  739. fw_name = FIRMWARE_R100;
  740. } else if ((rdev->family == CHIP_R200) ||
  741. (rdev->family == CHIP_RV250) ||
  742. (rdev->family == CHIP_RV280) ||
  743. (rdev->family == CHIP_RS300)) {
  744. DRM_INFO("Loading R200 Microcode\n");
  745. fw_name = FIRMWARE_R200;
  746. } else if ((rdev->family == CHIP_R300) ||
  747. (rdev->family == CHIP_R350) ||
  748. (rdev->family == CHIP_RV350) ||
  749. (rdev->family == CHIP_RV380) ||
  750. (rdev->family == CHIP_RS400) ||
  751. (rdev->family == CHIP_RS480)) {
  752. DRM_INFO("Loading R300 Microcode\n");
  753. fw_name = FIRMWARE_R300;
  754. } else if ((rdev->family == CHIP_R420) ||
  755. (rdev->family == CHIP_R423) ||
  756. (rdev->family == CHIP_RV410)) {
  757. DRM_INFO("Loading R400 Microcode\n");
  758. fw_name = FIRMWARE_R420;
  759. } else if ((rdev->family == CHIP_RS690) ||
  760. (rdev->family == CHIP_RS740)) {
  761. DRM_INFO("Loading RS690/RS740 Microcode\n");
  762. fw_name = FIRMWARE_RS690;
  763. } else if (rdev->family == CHIP_RS600) {
  764. DRM_INFO("Loading RS600 Microcode\n");
  765. fw_name = FIRMWARE_RS600;
  766. } else if ((rdev->family == CHIP_RV515) ||
  767. (rdev->family == CHIP_R520) ||
  768. (rdev->family == CHIP_RV530) ||
  769. (rdev->family == CHIP_R580) ||
  770. (rdev->family == CHIP_RV560) ||
  771. (rdev->family == CHIP_RV570)) {
  772. DRM_INFO("Loading R500 Microcode\n");
  773. fw_name = FIRMWARE_R520;
  774. }
  775. err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
  776. platform_device_unregister(pdev);
  777. if (err) {
  778. printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
  779. fw_name);
  780. } else if (rdev->me_fw->size % 8) {
  781. printk(KERN_ERR
  782. "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
  783. rdev->me_fw->size, fw_name);
  784. err = -EINVAL;
  785. release_firmware(rdev->me_fw);
  786. rdev->me_fw = NULL;
  787. }
  788. return err;
  789. }
  790. static void r100_cp_load_microcode(struct radeon_device *rdev)
  791. {
  792. const __be32 *fw_data;
  793. int i, size;
  794. if (r100_gui_wait_for_idle(rdev)) {
  795. printk(KERN_WARNING "Failed to wait GUI idle while "
  796. "programming pipes. Bad things might happen.\n");
  797. }
  798. if (rdev->me_fw) {
  799. size = rdev->me_fw->size / 4;
  800. fw_data = (const __be32 *)&rdev->me_fw->data[0];
  801. WREG32(RADEON_CP_ME_RAM_ADDR, 0);
  802. for (i = 0; i < size; i += 2) {
  803. WREG32(RADEON_CP_ME_RAM_DATAH,
  804. be32_to_cpup(&fw_data[i]));
  805. WREG32(RADEON_CP_ME_RAM_DATAL,
  806. be32_to_cpup(&fw_data[i + 1]));
  807. }
  808. }
  809. }
  810. int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
  811. {
  812. unsigned rb_bufsz;
  813. unsigned rb_blksz;
  814. unsigned max_fetch;
  815. unsigned pre_write_timer;
  816. unsigned pre_write_limit;
  817. unsigned indirect2_start;
  818. unsigned indirect1_start;
  819. uint32_t tmp;
  820. int r;
  821. if (r100_debugfs_cp_init(rdev)) {
  822. DRM_ERROR("Failed to register debugfs file for CP !\n");
  823. }
  824. if (!rdev->me_fw) {
  825. r = r100_cp_init_microcode(rdev);
  826. if (r) {
  827. DRM_ERROR("Failed to load firmware!\n");
  828. return r;
  829. }
  830. }
  831. /* Align ring size */
  832. rb_bufsz = drm_order(ring_size / 8);
  833. ring_size = (1 << (rb_bufsz + 1)) * 4;
  834. r100_cp_load_microcode(rdev);
  835. r = radeon_ring_init(rdev, ring_size);
  836. if (r) {
  837. return r;
  838. }
  839. /* Each time the cp read 1024 bytes (16 dword/quadword) update
  840. * the rptr copy in system ram */
  841. rb_blksz = 9;
  842. /* cp will read 128bytes at a time (4 dwords) */
  843. max_fetch = 1;
  844. rdev->cp.align_mask = 16 - 1;
  845. /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
  846. pre_write_timer = 64;
  847. /* Force CP_RB_WPTR write if written more than one time before the
  848. * delay expire
  849. */
  850. pre_write_limit = 0;
  851. /* Setup the cp cache like this (cache size is 96 dwords) :
  852. * RING 0 to 15
  853. * INDIRECT1 16 to 79
  854. * INDIRECT2 80 to 95
  855. * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
  856. * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
  857. * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
  858. * Idea being that most of the gpu cmd will be through indirect1 buffer
  859. * so it gets the bigger cache.
  860. */
  861. indirect2_start = 80;
  862. indirect1_start = 16;
  863. /* cp setup */
  864. WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
  865. tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
  866. REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
  867. REG_SET(RADEON_MAX_FETCH, max_fetch));
  868. #ifdef __BIG_ENDIAN
  869. tmp |= RADEON_BUF_SWAP_32BIT;
  870. #endif
  871. WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
  872. /* Set ring address */
  873. DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
  874. WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
  875. /* Force read & write ptr to 0 */
  876. WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
  877. WREG32(RADEON_CP_RB_RPTR_WR, 0);
  878. WREG32(RADEON_CP_RB_WPTR, 0);
  879. /* set the wb address whether it's enabled or not */
  880. WREG32(R_00070C_CP_RB_RPTR_ADDR,
  881. S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
  882. WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
  883. if (rdev->wb.enabled)
  884. WREG32(R_000770_SCRATCH_UMSK, 0xff);
  885. else {
  886. tmp |= RADEON_RB_NO_UPDATE;
  887. WREG32(R_000770_SCRATCH_UMSK, 0);
  888. }
  889. WREG32(RADEON_CP_RB_CNTL, tmp);
  890. udelay(10);
  891. rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
  892. rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
  893. /* protect against crazy HW on resume */
  894. rdev->cp.wptr &= rdev->cp.ptr_mask;
  895. /* Set cp mode to bus mastering & enable cp*/
  896. WREG32(RADEON_CP_CSQ_MODE,
  897. REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
  898. REG_SET(RADEON_INDIRECT1_START, indirect1_start));
  899. WREG32(0x718, 0);
  900. WREG32(0x744, 0x00004D4D);
  901. WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
  902. radeon_ring_start(rdev);
  903. r = radeon_ring_test(rdev);
  904. if (r) {
  905. DRM_ERROR("radeon: cp isn't working (%d).\n", r);
  906. return r;
  907. }
  908. rdev->cp.ready = true;
  909. rdev->mc.active_vram_size = rdev->mc.real_vram_size;
  910. return 0;
  911. }
  912. void r100_cp_fini(struct radeon_device *rdev)
  913. {
  914. if (r100_cp_wait_for_idle(rdev)) {
  915. DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
  916. }
  917. /* Disable ring */
  918. r100_cp_disable(rdev);
  919. radeon_ring_fini(rdev);
  920. DRM_INFO("radeon: cp finalized\n");
  921. }
  922. void r100_cp_disable(struct radeon_device *rdev)
  923. {
  924. /* Disable ring */
  925. rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
  926. rdev->cp.ready = false;
  927. WREG32(RADEON_CP_CSQ_MODE, 0);
  928. WREG32(RADEON_CP_CSQ_CNTL, 0);
  929. WREG32(R_000770_SCRATCH_UMSK, 0);
  930. if (r100_gui_wait_for_idle(rdev)) {
  931. printk(KERN_WARNING "Failed to wait GUI idle while "
  932. "programming pipes. Bad things might happen.\n");
  933. }
  934. }
  935. void r100_cp_commit(struct radeon_device *rdev)
  936. {
  937. WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
  938. (void)RREG32(RADEON_CP_RB_WPTR);
  939. }
  940. /*
  941. * CS functions
  942. */
  943. int r100_cs_parse_packet0(struct radeon_cs_parser *p,
  944. struct radeon_cs_packet *pkt,
  945. const unsigned *auth, unsigned n,
  946. radeon_packet0_check_t check)
  947. {
  948. unsigned reg;
  949. unsigned i, j, m;
  950. unsigned idx;
  951. int r;
  952. idx = pkt->idx + 1;
  953. reg = pkt->reg;
  954. /* Check that register fall into register range
  955. * determined by the number of entry (n) in the
  956. * safe register bitmap.
  957. */
  958. if (pkt->one_reg_wr) {
  959. if ((reg >> 7) > n) {
  960. return -EINVAL;
  961. }
  962. } else {
  963. if (((reg + (pkt->count << 2)) >> 7) > n) {
  964. return -EINVAL;
  965. }
  966. }
  967. for (i = 0; i <= pkt->count; i++, idx++) {
  968. j = (reg >> 7);
  969. m = 1 << ((reg >> 2) & 31);
  970. if (auth[j] & m) {
  971. r = check(p, pkt, idx, reg);
  972. if (r) {
  973. return r;
  974. }
  975. }
  976. if (pkt->one_reg_wr) {
  977. if (!(auth[j] & m)) {
  978. break;
  979. }
  980. } else {
  981. reg += 4;
  982. }
  983. }
  984. return 0;
  985. }
  986. void r100_cs_dump_packet(struct radeon_cs_parser *p,
  987. struct radeon_cs_packet *pkt)
  988. {
  989. volatile uint32_t *ib;
  990. unsigned i;
  991. unsigned idx;
  992. ib = p->ib->ptr;
  993. idx = pkt->idx;
  994. for (i = 0; i <= (pkt->count + 1); i++, idx++) {
  995. DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
  996. }
  997. }
  998. /**
  999. * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
  1000. * @parser: parser structure holding parsing context.
  1001. * @pkt: where to store packet informations
  1002. *
  1003. * Assume that chunk_ib_index is properly set. Will return -EINVAL
  1004. * if packet is bigger than remaining ib size. or if packets is unknown.
  1005. **/
  1006. int r100_cs_packet_parse(struct radeon_cs_parser *p,
  1007. struct radeon_cs_packet *pkt,
  1008. unsigned idx)
  1009. {
  1010. struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
  1011. uint32_t header;
  1012. if (idx >= ib_chunk->length_dw) {
  1013. DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
  1014. idx, ib_chunk->length_dw);
  1015. return -EINVAL;
  1016. }
  1017. header = radeon_get_ib_value(p, idx);
  1018. pkt->idx = idx;
  1019. pkt->type = CP_PACKET_GET_TYPE(header);
  1020. pkt->count = CP_PACKET_GET_COUNT(header);
  1021. switch (pkt->type) {
  1022. case PACKET_TYPE0:
  1023. pkt->reg = CP_PACKET0_GET_REG(header);
  1024. pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
  1025. break;
  1026. case PACKET_TYPE3:
  1027. pkt->opcode = CP_PACKET3_GET_OPCODE(header);
  1028. break;
  1029. case PACKET_TYPE2:
  1030. pkt->count = -1;
  1031. break;
  1032. default:
  1033. DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
  1034. return -EINVAL;
  1035. }
  1036. if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
  1037. DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
  1038. pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
  1039. return -EINVAL;
  1040. }
  1041. return 0;
  1042. }
  1043. /**
  1044. * r100_cs_packet_next_vline() - parse userspace VLINE packet
  1045. * @parser: parser structure holding parsing context.
  1046. *
  1047. * Userspace sends a special sequence for VLINE waits.
  1048. * PACKET0 - VLINE_START_END + value
  1049. * PACKET0 - WAIT_UNTIL +_value
  1050. * RELOC (P3) - crtc_id in reloc.
  1051. *
  1052. * This function parses this and relocates the VLINE START END
  1053. * and WAIT UNTIL packets to the correct crtc.
  1054. * It also detects a switched off crtc and nulls out the
  1055. * wait in that case.
  1056. */
  1057. int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
  1058. {
  1059. struct drm_mode_object *obj;
  1060. struct drm_crtc *crtc;
  1061. struct radeon_crtc *radeon_crtc;
  1062. struct radeon_cs_packet p3reloc, waitreloc;
  1063. int crtc_id;
  1064. int r;
  1065. uint32_t header, h_idx, reg;
  1066. volatile uint32_t *ib;
  1067. ib = p->ib->ptr;
  1068. /* parse the wait until */
  1069. r = r100_cs_packet_parse(p, &waitreloc, p->idx);
  1070. if (r)
  1071. return r;
  1072. /* check its a wait until and only 1 count */
  1073. if (waitreloc.reg != RADEON_WAIT_UNTIL ||
  1074. waitreloc.count != 0) {
  1075. DRM_ERROR("vline wait had illegal wait until segment\n");
  1076. r = -EINVAL;
  1077. return r;
  1078. }
  1079. if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
  1080. DRM_ERROR("vline wait had illegal wait until\n");
  1081. r = -EINVAL;
  1082. return r;
  1083. }
  1084. /* jump over the NOP */
  1085. r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
  1086. if (r)
  1087. return r;
  1088. h_idx = p->idx - 2;
  1089. p->idx += waitreloc.count + 2;
  1090. p->idx += p3reloc.count + 2;
  1091. header = radeon_get_ib_value(p, h_idx);
  1092. crtc_id = radeon_get_ib_value(p, h_idx + 5);
  1093. reg = CP_PACKET0_GET_REG(header);
  1094. obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
  1095. if (!obj) {
  1096. DRM_ERROR("cannot find crtc %d\n", crtc_id);
  1097. r = -EINVAL;
  1098. goto out;
  1099. }
  1100. crtc = obj_to_crtc(obj);
  1101. radeon_crtc = to_radeon_crtc(crtc);
  1102. crtc_id = radeon_crtc->crtc_id;
  1103. if (!crtc->enabled) {
  1104. /* if the CRTC isn't enabled - we need to nop out the wait until */
  1105. ib[h_idx + 2] = PACKET2(0);
  1106. ib[h_idx + 3] = PACKET2(0);
  1107. } else if (crtc_id == 1) {
  1108. switch (reg) {
  1109. case AVIVO_D1MODE_VLINE_START_END:
  1110. header &= ~R300_CP_PACKET0_REG_MASK;
  1111. header |= AVIVO_D2MODE_VLINE_START_END >> 2;
  1112. break;
  1113. case RADEON_CRTC_GUI_TRIG_VLINE:
  1114. header &= ~R300_CP_PACKET0_REG_MASK;
  1115. header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
  1116. break;
  1117. default:
  1118. DRM_ERROR("unknown crtc reloc\n");
  1119. r = -EINVAL;
  1120. goto out;
  1121. }
  1122. ib[h_idx] = header;
  1123. ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
  1124. }
  1125. out:
  1126. return r;
  1127. }
  1128. /**
  1129. * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
  1130. * @parser: parser structure holding parsing context.
  1131. * @data: pointer to relocation data
  1132. * @offset_start: starting offset
  1133. * @offset_mask: offset mask (to align start offset on)
  1134. * @reloc: reloc informations
  1135. *
  1136. * Check next packet is relocation packet3, do bo validation and compute
  1137. * GPU offset using the provided start.
  1138. **/
  1139. int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
  1140. struct radeon_cs_reloc **cs_reloc)
  1141. {
  1142. struct radeon_cs_chunk *relocs_chunk;
  1143. struct radeon_cs_packet p3reloc;
  1144. unsigned idx;
  1145. int r;
  1146. if (p->chunk_relocs_idx == -1) {
  1147. DRM_ERROR("No relocation chunk !\n");
  1148. return -EINVAL;
  1149. }
  1150. *cs_reloc = NULL;
  1151. relocs_chunk = &p->chunks[p->chunk_relocs_idx];
  1152. r = r100_cs_packet_parse(p, &p3reloc, p->idx);
  1153. if (r) {
  1154. return r;
  1155. }
  1156. p->idx += p3reloc.count + 2;
  1157. if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
  1158. DRM_ERROR("No packet3 for relocation for packet at %d.\n",
  1159. p3reloc.idx);
  1160. r100_cs_dump_packet(p, &p3reloc);
  1161. return -EINVAL;
  1162. }
  1163. idx = radeon_get_ib_value(p, p3reloc.idx + 1);
  1164. if (idx >= relocs_chunk->length_dw) {
  1165. DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
  1166. idx, relocs_chunk->length_dw);
  1167. r100_cs_dump_packet(p, &p3reloc);
  1168. return -EINVAL;
  1169. }
  1170. /* FIXME: we assume reloc size is 4 dwords */
  1171. *cs_reloc = p->relocs_ptr[(idx / 4)];
  1172. return 0;
  1173. }
  1174. static int r100_get_vtx_size(uint32_t vtx_fmt)
  1175. {
  1176. int vtx_size;
  1177. vtx_size = 2;
  1178. /* ordered according to bits in spec */
  1179. if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
  1180. vtx_size++;
  1181. if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
  1182. vtx_size += 3;
  1183. if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
  1184. vtx_size++;
  1185. if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
  1186. vtx_size++;
  1187. if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
  1188. vtx_size += 3;
  1189. if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
  1190. vtx_size++;
  1191. if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
  1192. vtx_size++;
  1193. if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
  1194. vtx_size += 2;
  1195. if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
  1196. vtx_size += 2;
  1197. if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
  1198. vtx_size++;
  1199. if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
  1200. vtx_size += 2;
  1201. if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
  1202. vtx_size++;
  1203. if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
  1204. vtx_size += 2;
  1205. if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
  1206. vtx_size++;
  1207. if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
  1208. vtx_size++;
  1209. /* blend weight */
  1210. if (vtx_fmt & (0x7 << 15))
  1211. vtx_size += (vtx_fmt >> 15) & 0x7;
  1212. if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
  1213. vtx_size += 3;
  1214. if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
  1215. vtx_size += 2;
  1216. if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
  1217. vtx_size++;
  1218. if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
  1219. vtx_size++;
  1220. if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
  1221. vtx_size++;
  1222. if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
  1223. vtx_size++;
  1224. return vtx_size;
  1225. }
  1226. static int r100_packet0_check(struct radeon_cs_parser *p,
  1227. struct radeon_cs_packet *pkt,
  1228. unsigned idx, unsigned reg)
  1229. {
  1230. struct radeon_cs_reloc *reloc;
  1231. struct r100_cs_track *track;
  1232. volatile uint32_t *ib;
  1233. uint32_t tmp;
  1234. int r;
  1235. int i, face;
  1236. u32 tile_flags = 0;
  1237. u32 idx_value;
  1238. ib = p->ib->ptr;
  1239. track = (struct r100_cs_track *)p->track;
  1240. idx_value = radeon_get_ib_value(p, idx);
  1241. switch (reg) {
  1242. case RADEON_CRTC_GUI_TRIG_VLINE:
  1243. r = r100_cs_packet_parse_vline(p);
  1244. if (r) {
  1245. DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
  1246. idx, reg);
  1247. r100_cs_dump_packet(p, pkt);
  1248. return r;
  1249. }
  1250. break;
  1251. /* FIXME: only allow PACKET3 blit? easier to check for out of
  1252. * range access */
  1253. case RADEON_DST_PITCH_OFFSET:
  1254. case RADEON_SRC_PITCH_OFFSET:
  1255. r = r100_reloc_pitch_offset(p, pkt, idx, reg);
  1256. if (r)
  1257. return r;
  1258. break;
  1259. case RADEON_RB3D_DEPTHOFFSET:
  1260. r = r100_cs_packet_next_reloc(p, &reloc);
  1261. if (r) {
  1262. DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
  1263. idx, reg);
  1264. r100_cs_dump_packet(p, pkt);
  1265. return r;
  1266. }
  1267. track->zb.robj = reloc->robj;
  1268. track->zb.offset = idx_value;
  1269. ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
  1270. break;
  1271. case RADEON_RB3D_COLOROFFSET:
  1272. r = r100_cs_packet_next_reloc(p, &reloc);
  1273. if (r) {
  1274. DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
  1275. idx, reg);
  1276. r100_cs_dump_packet(p, pkt);
  1277. return r;
  1278. }
  1279. track->cb[0].robj = reloc->robj;
  1280. track->cb[0].offset = idx_value;
  1281. ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
  1282. break;
  1283. case RADEON_PP_TXOFFSET_0:
  1284. case RADEON_PP_TXOFFSET_1:
  1285. case RADEON_PP_TXOFFSET_2:
  1286. i = (reg - RADEON_PP_TXOFFSET_0) / 24;
  1287. r = r100_cs_packet_next_reloc(p, &reloc);
  1288. if (r) {
  1289. DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
  1290. idx, reg);
  1291. r100_cs_dump_packet(p, pkt);
  1292. return r;
  1293. }
  1294. ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
  1295. track->textures[i].robj = reloc->robj;
  1296. break;
  1297. case RADEON_PP_CUBIC_OFFSET_T0_0:
  1298. case RADEON_PP_CUBIC_OFFSET_T0_1:
  1299. case RADEON_PP_CUBIC_OFFSET_T0_2:
  1300. case RADEON_PP_CUBIC_OFFSET_T0_3:
  1301. case RADEON_PP_CUBIC_OFFSET_T0_4:
  1302. i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
  1303. r = r100_cs_packet_next_reloc(p, &reloc);
  1304. if (r) {
  1305. DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
  1306. idx, reg);
  1307. r100_cs_dump_packet(p, pkt);
  1308. return r;
  1309. }
  1310. track->textures[0].cube_info[i].offset = idx_value;
  1311. ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
  1312. track->textures[0].cube_info[i].robj = reloc->robj;
  1313. break;
  1314. case RADEON_PP_CUBIC_OFFSET_T1_0:
  1315. case RADEON_PP_CUBIC_OFFSET_T1_1:
  1316. case RADEON_PP_CUBIC_OFFSET_T1_2:
  1317. case RADEON_PP_CUBIC_OFFSET_T1_3:
  1318. case RADEON_PP_CUBIC_OFFSET_T1_4:
  1319. i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
  1320. r = r100_cs_packet_next_reloc(p, &reloc);
  1321. if (r) {
  1322. DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
  1323. idx, reg);
  1324. r100_cs_dump_packet(p, pkt);
  1325. return r;
  1326. }
  1327. track->textures[1].cube_info[i].offset = idx_value;
  1328. ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
  1329. track->textures[1].cube_info[i].robj = reloc->robj;
  1330. break;
  1331. case RADEON_PP_CUBIC_OFFSET_T2_0:
  1332. case RADEON_PP_CUBIC_OFFSET_T2_1:
  1333. case RADEON_PP_CUBIC_OFFSET_T2_2:
  1334. case RADEON_PP_CUBIC_OFFSET_T2_3:
  1335. case RADEON_PP_CUBIC_OFFSET_T2_4:
  1336. i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
  1337. r = r100_cs_packet_next_reloc(p, &reloc);
  1338. if (r) {
  1339. DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
  1340. idx, reg);
  1341. r100_cs_dump_packet(p, pkt);
  1342. return r;
  1343. }
  1344. track->textures[2].cube_info[i].offset = idx_value;
  1345. ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
  1346. track->textures[2].cube_info[i].robj = reloc->robj;
  1347. break;
  1348. case RADEON_RE_WIDTH_HEIGHT:
  1349. track->maxy = ((idx_value >> 16) & 0x7FF);
  1350. break;
  1351. case RADEON_RB3D_COLORPITCH:
  1352. r = r100_cs_packet_next_reloc(p, &reloc);
  1353. if (r) {
  1354. DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
  1355. idx, reg);
  1356. r100_cs_dump_packet(p, pkt);
  1357. return r;
  1358. }
  1359. if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
  1360. tile_flags |= RADEON_COLOR_TILE_ENABLE;
  1361. if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
  1362. tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
  1363. tmp = idx_value & ~(0x7 << 16);
  1364. tmp |= tile_flags;
  1365. ib[idx] = tmp;
  1366. track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
  1367. break;
  1368. case RADEON_RB3D_DEPTHPITCH:
  1369. track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
  1370. break;
  1371. case RADEON_RB3D_CNTL:
  1372. switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
  1373. case 7:
  1374. case 8:
  1375. case 9:
  1376. case 11:
  1377. case 12:
  1378. track->cb[0].cpp = 1;
  1379. break;
  1380. case 3:
  1381. case 4:
  1382. case 15:
  1383. track->cb[0].cpp = 2;
  1384. break;
  1385. case 6:
  1386. track->cb[0].cpp = 4;
  1387. break;
  1388. default:
  1389. DRM_ERROR("Invalid color buffer format (%d) !\n",
  1390. ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
  1391. return -EINVAL;
  1392. }
  1393. track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
  1394. break;
  1395. case RADEON_RB3D_ZSTENCILCNTL:
  1396. switch (idx_value & 0xf) {
  1397. case 0:
  1398. track->zb.cpp = 2;
  1399. break;
  1400. case 2:
  1401. case 3:
  1402. case 4:
  1403. case 5:
  1404. case 9:
  1405. case 11:
  1406. track->zb.cpp = 4;
  1407. break;
  1408. default:
  1409. break;
  1410. }
  1411. break;
  1412. case RADEON_RB3D_ZPASS_ADDR:
  1413. r = r100_cs_packet_next_reloc(p, &reloc);
  1414. if (r) {
  1415. DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
  1416. idx, reg);
  1417. r100_cs_dump_packet(p, pkt);
  1418. return r;
  1419. }
  1420. ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
  1421. break;
  1422. case RADEON_PP_CNTL:
  1423. {
  1424. uint32_t temp = idx_value >> 4;
  1425. for (i = 0; i < track->num_texture; i++)
  1426. track->textures[i].enabled = !!(temp & (1 << i));
  1427. }
  1428. break;
  1429. case RADEON_SE_VF_CNTL:
  1430. track->vap_vf_cntl = idx_value;
  1431. break;
  1432. case RADEON_SE_VTX_FMT:
  1433. track->vtx_size = r100_get_vtx_size(idx_value);
  1434. break;
  1435. case RADEON_PP_TEX_SIZE_0:
  1436. case RADEON_PP_TEX_SIZE_1:
  1437. case RADEON_PP_TEX_SIZE_2:
  1438. i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
  1439. track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
  1440. track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
  1441. break;
  1442. case RADEON_PP_TEX_PITCH_0:
  1443. case RADEON_PP_TEX_PITCH_1:
  1444. case RADEON_PP_TEX_PITCH_2:
  1445. i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
  1446. track->textures[i].pitch = idx_value + 32;
  1447. break;
  1448. case RADEON_PP_TXFILTER_0:
  1449. case RADEON_PP_TXFILTER_1:
  1450. case RADEON_PP_TXFILTER_2:
  1451. i = (reg - RADEON_PP_TXFILTER_0) / 24;
  1452. track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
  1453. >> RADEON_MAX_MIP_LEVEL_SHIFT);
  1454. tmp = (idx_value >> 23) & 0x7;
  1455. if (tmp == 2 || tmp == 6)
  1456. track->textures[i].roundup_w = false;
  1457. tmp = (idx_value >> 27) & 0x7;
  1458. if (tmp == 2 || tmp == 6)
  1459. track->textures[i].roundup_h = false;
  1460. break;
  1461. case RADEON_PP_TXFORMAT_0:
  1462. case RADEON_PP_TXFORMAT_1:
  1463. case RADEON_PP_TXFORMAT_2:
  1464. i = (reg - RADEON_PP_TXFORMAT_0) / 24;
  1465. if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
  1466. track->textures[i].use_pitch = 1;
  1467. } else {
  1468. track->textures[i].use_pitch = 0;
  1469. track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
  1470. track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
  1471. }
  1472. if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
  1473. track->textures[i].tex_coord_type = 2;
  1474. switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
  1475. case RADEON_TXFORMAT_I8:
  1476. case RADEON_TXFORMAT_RGB332:
  1477. case RADEON_TXFORMAT_Y8:
  1478. track->textures[i].cpp = 1;
  1479. track->textures[i].compress_format = R100_TRACK_COMP_NONE;
  1480. break;
  1481. case RADEON_TXFORMAT_AI88:
  1482. case RADEON_TXFORMAT_ARGB1555:
  1483. case RADEON_TXFORMAT_RGB565:
  1484. case RADEON_TXFORMAT_ARGB4444:
  1485. case RADEON_TXFORMAT_VYUY422:
  1486. case RADEON_TXFORMAT_YVYU422:
  1487. case RADEON_TXFORMAT_SHADOW16:
  1488. case RADEON_TXFORMAT_LDUDV655:
  1489. case RADEON_TXFORMAT_DUDV88:
  1490. track->textures[i].cpp = 2;
  1491. track->textures[i].compress_format = R100_TRACK_COMP_NONE;
  1492. break;
  1493. case RADEON_TXFORMAT_ARGB8888:
  1494. case RADEON_TXFORMAT_RGBA8888:
  1495. case RADEON_TXFORMAT_SHADOW32:
  1496. case RADEON_TXFORMAT_LDUDUV8888:
  1497. track->textures[i].cpp = 4;
  1498. track->textures[i].compress_format = R100_TRACK_COMP_NONE;
  1499. break;
  1500. case RADEON_TXFORMAT_DXT1:
  1501. track->textures[i].cpp = 1;
  1502. track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
  1503. break;
  1504. case RADEON_TXFORMAT_DXT23:
  1505. case RADEON_TXFORMAT_DXT45:
  1506. track->textures[i].cpp = 1;
  1507. track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
  1508. break;
  1509. }
  1510. track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
  1511. track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
  1512. break;
  1513. case RADEON_PP_CUBIC_FACES_0:
  1514. case RADEON_PP_CUBIC_FACES_1:
  1515. case RADEON_PP_CUBIC_FACES_2:
  1516. tmp = idx_value;
  1517. i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
  1518. for (face = 0; face < 4; face++) {
  1519. track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
  1520. track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
  1521. }
  1522. break;
  1523. default:
  1524. printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
  1525. reg, idx);
  1526. return -EINVAL;
  1527. }
  1528. return 0;
  1529. }
  1530. int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
  1531. struct radeon_cs_packet *pkt,
  1532. struct radeon_bo *robj)
  1533. {
  1534. unsigned idx;
  1535. u32 value;
  1536. idx = pkt->idx + 1;
  1537. value = radeon_get_ib_value(p, idx + 2);
  1538. if ((value + 1) > radeon_bo_size(robj)) {
  1539. DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
  1540. "(need %u have %lu) !\n",
  1541. value + 1,
  1542. radeon_bo_size(robj));
  1543. return -EINVAL;
  1544. }
  1545. return 0;
  1546. }
  1547. static int r100_packet3_check(struct radeon_cs_parser *p,
  1548. struct radeon_cs_packet *pkt)
  1549. {
  1550. struct radeon_cs_reloc *reloc;
  1551. struct r100_cs_track *track;
  1552. unsigned idx;
  1553. volatile uint32_t *ib;
  1554. int r;
  1555. ib = p->ib->ptr;
  1556. idx = pkt->idx + 1;
  1557. track = (struct r100_cs_track *)p->track;
  1558. switch (pkt->opcode) {
  1559. case PACKET3_3D_LOAD_VBPNTR:
  1560. r = r100_packet3_load_vbpntr(p, pkt, idx);
  1561. if (r)
  1562. return r;
  1563. break;
  1564. case PACKET3_INDX_BUFFER:
  1565. r = r100_cs_packet_next_reloc(p, &reloc);
  1566. if (r) {
  1567. DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
  1568. r100_cs_dump_packet(p, pkt);
  1569. return r;
  1570. }
  1571. ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
  1572. r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
  1573. if (r) {
  1574. return r;
  1575. }
  1576. break;
  1577. case 0x23:
  1578. /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
  1579. r = r100_cs_packet_next_reloc(p, &reloc);
  1580. if (r) {
  1581. DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
  1582. r100_cs_dump_packet(p, pkt);
  1583. return r;
  1584. }
  1585. ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
  1586. track->num_arrays = 1;
  1587. track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
  1588. track->arrays[0].robj = reloc->robj;
  1589. track->arrays[0].esize = track->vtx_size;
  1590. track->max_indx = radeon_get_ib_value(p, idx+1);
  1591. track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
  1592. track->immd_dwords = pkt->count - 1;
  1593. r = r100_cs_track_check(p->rdev, track);
  1594. if (r)
  1595. return r;
  1596. break;
  1597. case PACKET3_3D_DRAW_IMMD:
  1598. if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
  1599. DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
  1600. return -EINVAL;
  1601. }
  1602. track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
  1603. track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
  1604. track->immd_dwords = pkt->count - 1;
  1605. r = r100_cs_track_check(p->rdev, track);
  1606. if (r)
  1607. return r;
  1608. break;
  1609. /* triggers drawing using in-packet vertex data */
  1610. case PACKET3_3D_DRAW_IMMD_2:
  1611. if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
  1612. DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
  1613. return -EINVAL;
  1614. }
  1615. track->vap_vf_cntl = radeon_get_ib_value(p, idx);
  1616. track->immd_dwords = pkt->count;
  1617. r = r100_cs_track_check(p->rdev, track);
  1618. if (r)
  1619. return r;
  1620. break;
  1621. /* triggers drawing using in-packet vertex data */
  1622. case PACKET3_3D_DRAW_VBUF_2:
  1623. track->vap_vf_cntl = radeon_get_ib_value(p, idx);
  1624. r = r100_cs_track_check(p->rdev, track);
  1625. if (r)
  1626. return r;
  1627. break;
  1628. /* triggers drawing of vertex buffers setup elsewhere */
  1629. case PACKET3_3D_DRAW_INDX_2:
  1630. track->vap_vf_cntl = radeon_get_ib_value(p, idx);
  1631. r = r100_cs_track_check(p->rdev, track);
  1632. if (r)
  1633. return r;
  1634. break;
  1635. /* triggers drawing using indices to vertex buffer */
  1636. case PACKET3_3D_DRAW_VBUF:
  1637. track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
  1638. r = r100_cs_track_check(p->rdev, track);
  1639. if (r)
  1640. return r;
  1641. break;
  1642. /* triggers drawing of vertex buffers setup elsewhere */
  1643. case PACKET3_3D_DRAW_INDX:
  1644. track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
  1645. r = r100_cs_track_check(p->rdev, track);
  1646. if (r)
  1647. return r;
  1648. break;
  1649. /* triggers drawing using indices to vertex buffer */
  1650. case PACKET3_3D_CLEAR_HIZ:
  1651. case PACKET3_3D_CLEAR_ZMASK:
  1652. if (p->rdev->hyperz_filp != p->filp)
  1653. return -EINVAL;
  1654. break;
  1655. case PACKET3_NOP:
  1656. break;
  1657. default:
  1658. DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
  1659. return -EINVAL;
  1660. }
  1661. return 0;
  1662. }
  1663. int r100_cs_parse(struct radeon_cs_parser *p)
  1664. {
  1665. struct radeon_cs_packet pkt;
  1666. struct r100_cs_track *track;
  1667. int r;
  1668. track = kzalloc(sizeof(*track), GFP_KERNEL);
  1669. r100_cs_track_clear(p->rdev, track);
  1670. p->track = track;
  1671. do {
  1672. r = r100_cs_packet_parse(p, &pkt, p->idx);
  1673. if (r) {
  1674. return r;
  1675. }
  1676. p->idx += pkt.count + 2;
  1677. switch (pkt.type) {
  1678. case PACKET_TYPE0:
  1679. if (p->rdev->family >= CHIP_R200)
  1680. r = r100_cs_parse_packet0(p, &pkt,
  1681. p->rdev->config.r100.reg_safe_bm,
  1682. p->rdev->config.r100.reg_safe_bm_size,
  1683. &r200_packet0_check);
  1684. else
  1685. r = r100_cs_parse_packet0(p, &pkt,
  1686. p->rdev->config.r100.reg_safe_bm,
  1687. p->rdev->config.r100.reg_safe_bm_size,
  1688. &r100_packet0_check);
  1689. break;
  1690. case PACKET_TYPE2:
  1691. break;
  1692. case PACKET_TYPE3:
  1693. r = r100_packet3_check(p, &pkt);
  1694. break;
  1695. default:
  1696. DRM_ERROR("Unknown packet type %d !\n",
  1697. pkt.type);
  1698. return -EINVAL;
  1699. }
  1700. if (r) {
  1701. return r;
  1702. }
  1703. } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
  1704. return 0;
  1705. }
  1706. /*
  1707. * Global GPU functions
  1708. */
  1709. void r100_errata(struct radeon_device *rdev)
  1710. {
  1711. rdev->pll_errata = 0;
  1712. if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
  1713. rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
  1714. }
  1715. if (rdev->family == CHIP_RV100 ||
  1716. rdev->family == CHIP_RS100 ||
  1717. rdev->family == CHIP_RS200) {
  1718. rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
  1719. }
  1720. }
  1721. /* Wait for vertical sync on primary CRTC */
  1722. void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
  1723. {
  1724. uint32_t crtc_gen_cntl, tmp;
  1725. int i;
  1726. crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
  1727. if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
  1728. !(crtc_gen_cntl & RADEON_CRTC_EN)) {
  1729. return;
  1730. }
  1731. /* Clear the CRTC_VBLANK_SAVE bit */
  1732. WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
  1733. for (i = 0; i < rdev->usec_timeout; i++) {
  1734. tmp = RREG32(RADEON_CRTC_STATUS);
  1735. if (tmp & RADEON_CRTC_VBLANK_SAVE) {
  1736. return;
  1737. }
  1738. DRM_UDELAY(1);
  1739. }
  1740. }
  1741. /* Wait for vertical sync on secondary CRTC */
  1742. void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
  1743. {
  1744. uint32_t crtc2_gen_cntl, tmp;
  1745. int i;
  1746. crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
  1747. if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
  1748. !(crtc2_gen_cntl & RADEON_CRTC2_EN))
  1749. return;
  1750. /* Clear the CRTC_VBLANK_SAVE bit */
  1751. WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
  1752. for (i = 0; i < rdev->usec_timeout; i++) {
  1753. tmp = RREG32(RADEON_CRTC2_STATUS);
  1754. if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
  1755. return;
  1756. }
  1757. DRM_UDELAY(1);
  1758. }
  1759. }
  1760. int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
  1761. {
  1762. unsigned i;
  1763. uint32_t tmp;
  1764. for (i = 0; i < rdev->usec_timeout; i++) {
  1765. tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
  1766. if (tmp >= n) {
  1767. return 0;
  1768. }
  1769. DRM_UDELAY(1);
  1770. }
  1771. return -1;
  1772. }
  1773. int r100_gui_wait_for_idle(struct radeon_device *rdev)
  1774. {
  1775. unsigned i;
  1776. uint32_t tmp;
  1777. if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
  1778. printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
  1779. " Bad things might happen.\n");
  1780. }
  1781. for (i = 0; i < rdev->usec_timeout; i++) {
  1782. tmp = RREG32(RADEON_RBBM_STATUS);
  1783. if (!(tmp & RADEON_RBBM_ACTIVE)) {
  1784. return 0;
  1785. }
  1786. DRM_UDELAY(1);
  1787. }
  1788. return -1;
  1789. }
  1790. int r100_mc_wait_for_idle(struct radeon_device *rdev)
  1791. {
  1792. unsigned i;
  1793. uint32_t tmp;
  1794. for (i = 0; i < rdev->usec_timeout; i++) {
  1795. /* read MC_STATUS */
  1796. tmp = RREG32(RADEON_MC_STATUS);
  1797. if (tmp & RADEON_MC_IDLE) {
  1798. return 0;
  1799. }
  1800. DRM_UDELAY(1);
  1801. }
  1802. return -1;
  1803. }
  1804. void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
  1805. {
  1806. lockup->last_cp_rptr = cp->rptr;
  1807. lockup->last_jiffies = jiffies;
  1808. }
  1809. /**
  1810. * r100_gpu_cp_is_lockup() - check if CP is lockup by recording information
  1811. * @rdev: radeon device structure
  1812. * @lockup: r100_gpu_lockup structure holding CP lockup tracking informations
  1813. * @cp: radeon_cp structure holding CP information
  1814. *
  1815. * We don't need to initialize the lockup tracking information as we will either
  1816. * have CP rptr to a different value of jiffies wrap around which will force
  1817. * initialization of the lockup tracking informations.
  1818. *
  1819. * A possible false positivie is if we get call after while and last_cp_rptr ==
  1820. * the current CP rptr, even if it's unlikely it might happen. To avoid this
  1821. * if the elapsed time since last call is bigger than 2 second than we return
  1822. * false and update the tracking information. Due to this the caller must call
  1823. * r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported
  1824. * the fencing code should be cautious about that.
  1825. *
  1826. * Caller should write to the ring to force CP to do something so we don't get
  1827. * false positive when CP is just gived nothing to do.
  1828. *
  1829. **/
  1830. bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
  1831. {
  1832. unsigned long cjiffies, elapsed;
  1833. cjiffies = jiffies;
  1834. if (!time_after(cjiffies, lockup->last_jiffies)) {
  1835. /* likely a wrap around */
  1836. lockup->last_cp_rptr = cp->rptr;
  1837. lockup->last_jiffies = jiffies;
  1838. return false;
  1839. }
  1840. if (cp->rptr != lockup->last_cp_rptr) {
  1841. /* CP is still working no lockup */
  1842. lockup->last_cp_rptr = cp->rptr;
  1843. lockup->last_jiffies = jiffies;
  1844. return false;
  1845. }
  1846. elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies);
  1847. if (elapsed >= 10000) {
  1848. dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
  1849. return true;
  1850. }
  1851. /* give a chance to the GPU ... */
  1852. return false;
  1853. }
  1854. bool r100_gpu_is_lockup(struct radeon_device *rdev)
  1855. {
  1856. u32 rbbm_status;
  1857. int r;
  1858. rbbm_status = RREG32(R_000E40_RBBM_STATUS);
  1859. if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
  1860. r100_gpu_lockup_update(&rdev->config.r100.lockup, &rdev->cp);
  1861. return false;
  1862. }
  1863. /* force CP activities */
  1864. r = radeon_ring_lock(rdev, 2);
  1865. if (!r) {
  1866. /* PACKET2 NOP */
  1867. radeon_ring_write(rdev, 0x80000000);
  1868. radeon_ring_write(rdev, 0x80000000);
  1869. radeon_ring_unlock_commit(rdev);
  1870. }
  1871. rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
  1872. return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp);
  1873. }
  1874. void r100_bm_disable(struct radeon_device *rdev)
  1875. {
  1876. u32 tmp;
  1877. /* disable bus mastering */
  1878. tmp = RREG32(R_000030_BUS_CNTL);
  1879. WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
  1880. mdelay(1);
  1881. WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
  1882. mdelay(1);
  1883. WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
  1884. tmp = RREG32(RADEON_BUS_CNTL);
  1885. mdelay(1);
  1886. pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp);
  1887. pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB);
  1888. mdelay(1);
  1889. }
  1890. int r100_asic_reset(struct radeon_device *rdev)
  1891. {
  1892. struct r100_mc_save save;
  1893. u32 status, tmp;
  1894. r100_mc_stop(rdev, &save);
  1895. status = RREG32(R_000E40_RBBM_STATUS);
  1896. if (!G_000E40_GUI_ACTIVE(status)) {
  1897. return 0;
  1898. }
  1899. status = RREG32(R_000E40_RBBM_STATUS);
  1900. dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
  1901. /* stop CP */
  1902. WREG32(RADEON_CP_CSQ_CNTL, 0);
  1903. tmp = RREG32(RADEON_CP_RB_CNTL);
  1904. WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
  1905. WREG32(RADEON_CP_RB_RPTR_WR, 0);
  1906. WREG32(RADEON_CP_RB_WPTR, 0);
  1907. WREG32(RADEON_CP_RB_CNTL, tmp);
  1908. /* save PCI state */
  1909. pci_save_state(rdev->pdev);
  1910. /* disable bus mastering */
  1911. r100_bm_disable(rdev);
  1912. WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
  1913. S_0000F0_SOFT_RESET_RE(1) |
  1914. S_0000F0_SOFT_RESET_PP(1) |
  1915. S_0000F0_SOFT_RESET_RB(1));
  1916. RREG32(R_0000F0_RBBM_SOFT_RESET);
  1917. mdelay(500);
  1918. WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
  1919. mdelay(1);
  1920. status = RREG32(R_000E40_RBBM_STATUS);
  1921. dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
  1922. /* reset CP */
  1923. WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
  1924. RREG32(R_0000F0_RBBM_SOFT_RESET);
  1925. mdelay(500);
  1926. WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
  1927. mdelay(1);
  1928. status = RREG32(R_000E40_RBBM_STATUS);
  1929. dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
  1930. /* restore PCI & busmastering */
  1931. pci_restore_state(rdev->pdev);
  1932. r100_enable_bm(rdev);
  1933. /* Check if GPU is idle */
  1934. if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
  1935. G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
  1936. dev_err(rdev->dev, "failed to reset GPU\n");
  1937. rdev->gpu_lockup = true;
  1938. return -1;
  1939. }
  1940. r100_mc_resume(rdev, &save);
  1941. dev_info(rdev->dev, "GPU reset succeed\n");
  1942. return 0;
  1943. }
  1944. void r100_set_common_regs(struct radeon_device *rdev)
  1945. {
  1946. struct drm_device *dev = rdev->ddev;
  1947. bool force_dac2 = false;
  1948. u32 tmp;
  1949. /* set these so they don't interfere with anything */
  1950. WREG32(RADEON_OV0_SCALE_CNTL, 0);
  1951. WREG32(RADEON_SUBPIC_CNTL, 0);
  1952. WREG32(RADEON_VIPH_CONTROL, 0);
  1953. WREG32(RADEON_I2C_CNTL_1, 0);
  1954. WREG32(RADEON_DVI_I2C_CNTL_1, 0);
  1955. WREG32(RADEON_CAP0_TRIG_CNTL, 0);
  1956. WREG32(RADEON_CAP1_TRIG_CNTL, 0);
  1957. /* always set up dac2 on rn50 and some rv100 as lots
  1958. * of servers seem to wire it up to a VGA port but
  1959. * don't report it in the bios connector
  1960. * table.
  1961. */
  1962. switch (dev->pdev->device) {
  1963. /* RN50 */
  1964. case 0x515e:
  1965. case 0x5969:
  1966. force_dac2 = true;
  1967. break;
  1968. /* RV100*/
  1969. case 0x5159:
  1970. case 0x515a:
  1971. /* DELL triple head servers */
  1972. if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
  1973. ((dev->pdev->subsystem_device == 0x016c) ||
  1974. (dev->pdev->subsystem_device == 0x016d) ||
  1975. (dev->pdev->subsystem_device == 0x016e) ||
  1976. (dev->pdev->subsystem_device == 0x016f) ||
  1977. (dev->pdev->subsystem_device == 0x0170) ||
  1978. (dev->pdev->subsystem_device == 0x017d) ||
  1979. (dev->pdev->subsystem_device == 0x017e) ||
  1980. (dev->pdev->subsystem_device == 0x0183) ||
  1981. (dev->pdev->subsystem_device == 0x018a) ||
  1982. (dev->pdev->subsystem_device == 0x019a)))
  1983. force_dac2 = true;
  1984. break;
  1985. }
  1986. if (force_dac2) {
  1987. u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
  1988. u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
  1989. u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
  1990. /* For CRT on DAC2, don't turn it on if BIOS didn't
  1991. enable it, even it's detected.
  1992. */
  1993. /* force it to crtc0 */
  1994. dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
  1995. dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
  1996. disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
  1997. /* set up the TV DAC */
  1998. tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
  1999. RADEON_TV_DAC_STD_MASK |
  2000. RADEON_TV_DAC_RDACPD |
  2001. RADEON_TV_DAC_GDACPD |
  2002. RADEON_TV_DAC_BDACPD |
  2003. RADEON_TV_DAC_BGADJ_MASK |
  2004. RADEON_TV_DAC_DACADJ_MASK);
  2005. tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
  2006. RADEON_TV_DAC_NHOLD |
  2007. RADEON_TV_DAC_STD_PS2 |
  2008. (0x58 << 16));
  2009. WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
  2010. WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
  2011. WREG32(RADEON_DAC_CNTL2, dac2_cntl);
  2012. }
  2013. /* switch PM block to ACPI mode */
  2014. tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
  2015. tmp &= ~RADEON_PM_MODE_SEL;
  2016. WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
  2017. }
  2018. /*
  2019. * VRAM info
  2020. */
  2021. static void r100_vram_get_type(struct radeon_device *rdev)
  2022. {
  2023. uint32_t tmp;
  2024. rdev->mc.vram_is_ddr = false;
  2025. if (rdev->flags & RADEON_IS_IGP)
  2026. rdev->mc.vram_is_ddr = true;
  2027. else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
  2028. rdev->mc.vram_is_ddr = true;
  2029. if ((rdev->family == CHIP_RV100) ||
  2030. (rdev->family == CHIP_RS100) ||
  2031. (rdev->family == CHIP_RS200)) {
  2032. tmp = RREG32(RADEON_MEM_CNTL);
  2033. if (tmp & RV100_HALF_MODE) {
  2034. rdev->mc.vram_width = 32;
  2035. } else {
  2036. rdev->mc.vram_width = 64;
  2037. }
  2038. if (rdev->flags & RADEON_SINGLE_CRTC) {
  2039. rdev->mc.vram_width /= 4;
  2040. rdev->mc.vram_is_ddr = true;
  2041. }
  2042. } else if (rdev->family <= CHIP_RV280) {
  2043. tmp = RREG32(RADEON_MEM_CNTL);
  2044. if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
  2045. rdev->mc.vram_width = 128;
  2046. } else {
  2047. rdev->mc.vram_width = 64;
  2048. }
  2049. } else {
  2050. /* newer IGPs */
  2051. rdev->mc.vram_width = 128;
  2052. }
  2053. }
  2054. static u32 r100_get_accessible_vram(struct radeon_device *rdev)
  2055. {
  2056. u32 aper_size;
  2057. u8 byte;
  2058. aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
  2059. /* Set HDP_APER_CNTL only on cards that are known not to be broken,
  2060. * that is has the 2nd generation multifunction PCI interface
  2061. */
  2062. if (rdev->family == CHIP_RV280 ||
  2063. rdev->family >= CHIP_RV350) {
  2064. WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
  2065. ~RADEON_HDP_APER_CNTL);
  2066. DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
  2067. return aper_size * 2;
  2068. }
  2069. /* Older cards have all sorts of funny issues to deal with. First
  2070. * check if it's a multifunction card by reading the PCI config
  2071. * header type... Limit those to one aperture size
  2072. */
  2073. pci_read_config_byte(rdev->pdev, 0xe, &byte);
  2074. if (byte & 0x80) {
  2075. DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
  2076. DRM_INFO("Limiting VRAM to one aperture\n");
  2077. return aper_size;
  2078. }
  2079. /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
  2080. * have set it up. We don't write this as it's broken on some ASICs but
  2081. * we expect the BIOS to have done the right thing (might be too optimistic...)
  2082. */
  2083. if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
  2084. return aper_size * 2;
  2085. return aper_size;
  2086. }
  2087. void r100_vram_init_sizes(struct radeon_device *rdev)
  2088. {
  2089. u64 config_aper_size;
  2090. /* work out accessible VRAM */
  2091. rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
  2092. rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
  2093. rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
  2094. /* FIXME we don't use the second aperture yet when we could use it */
  2095. if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
  2096. rdev->mc.visible_vram_size = rdev->mc.aper_size;
  2097. rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
  2098. config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
  2099. if (rdev->flags & RADEON_IS_IGP) {
  2100. uint32_t tom;
  2101. /* read NB_TOM to get the amount of ram stolen for the GPU */
  2102. tom = RREG32(RADEON_NB_TOM);
  2103. rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
  2104. WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
  2105. rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
  2106. } else {
  2107. rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
  2108. /* Some production boards of m6 will report 0
  2109. * if it's 8 MB
  2110. */
  2111. if (rdev->mc.real_vram_size == 0) {
  2112. rdev->mc.real_vram_size = 8192 * 1024;
  2113. WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
  2114. }
  2115. /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
  2116. * Novell bug 204882 + along with lots of ubuntu ones
  2117. */
  2118. if (rdev->mc.aper_size > config_aper_size)
  2119. config_aper_size = rdev->mc.aper_size;
  2120. if (config_aper_size > rdev->mc.real_vram_size)
  2121. rdev->mc.mc_vram_size = config_aper_size;
  2122. else
  2123. rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
  2124. }
  2125. }
  2126. void r100_vga_set_state(struct radeon_device *rdev, bool state)
  2127. {
  2128. uint32_t temp;
  2129. temp = RREG32(RADEON_CONFIG_CNTL);
  2130. if (state == false) {
  2131. temp &= ~(1<<8);
  2132. temp |= (1<<9);
  2133. } else {
  2134. temp &= ~(1<<9);
  2135. }
  2136. WREG32(RADEON_CONFIG_CNTL, temp);
  2137. }
  2138. void r100_mc_init(struct radeon_device *rdev)
  2139. {
  2140. u64 base;
  2141. r100_vram_get_type(rdev);
  2142. r100_vram_init_sizes(rdev);
  2143. base = rdev->mc.aper_base;
  2144. if (rdev->flags & RADEON_IS_IGP)
  2145. base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
  2146. radeon_vram_location(rdev, &rdev->mc, base);
  2147. rdev->mc.gtt_base_align = 0;
  2148. if (!(rdev->flags & RADEON_IS_AGP))
  2149. radeon_gtt_location(rdev, &rdev->mc);
  2150. radeon_update_bandwidth_info(rdev);
  2151. }
  2152. /*
  2153. * Indirect registers accessor
  2154. */
  2155. void r100_pll_errata_after_index(struct radeon_device *rdev)
  2156. {
  2157. if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
  2158. (void)RREG32(RADEON_CLOCK_CNTL_DATA);
  2159. (void)RREG32(RADEON_CRTC_GEN_CNTL);
  2160. }
  2161. }
  2162. static void r100_pll_errata_after_data(struct radeon_device *rdev)
  2163. {
  2164. /* This workarounds is necessary on RV100, RS100 and RS200 chips
  2165. * or the chip could hang on a subsequent access
  2166. */
  2167. if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
  2168. udelay(5000);
  2169. }
  2170. /* This function is required to workaround a hardware bug in some (all?)
  2171. * revisions of the R300. This workaround should be called after every
  2172. * CLOCK_CNTL_INDEX register access. If not, register reads afterward
  2173. * may not be correct.
  2174. */
  2175. if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
  2176. uint32_t save, tmp;
  2177. save = RREG32(RADEON_CLOCK_CNTL_INDEX);
  2178. tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
  2179. WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
  2180. tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
  2181. WREG32(RADEON_CLOCK_CNTL_INDEX, save);
  2182. }
  2183. }
  2184. uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
  2185. {
  2186. uint32_t data;
  2187. WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
  2188. r100_pll_errata_after_index(rdev);
  2189. data = RREG32(RADEON_CLOCK_CNTL_DATA);
  2190. r100_pll_errata_after_data(rdev);
  2191. return data;
  2192. }
  2193. void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  2194. {
  2195. WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
  2196. r100_pll_errata_after_index(rdev);
  2197. WREG32(RADEON_CLOCK_CNTL_DATA, v);
  2198. r100_pll_errata_after_data(rdev);
  2199. }
  2200. void r100_set_safe_registers(struct radeon_device *rdev)
  2201. {
  2202. if (ASIC_IS_RN50(rdev)) {
  2203. rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
  2204. rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
  2205. } else if (rdev->family < CHIP_R200) {
  2206. rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
  2207. rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
  2208. } else {
  2209. r200_set_safe_registers(rdev);
  2210. }
  2211. }
  2212. /*
  2213. * Debugfs info
  2214. */
  2215. #if defined(CONFIG_DEBUG_FS)
  2216. static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
  2217. {
  2218. struct drm_info_node *node = (struct drm_info_node *) m->private;
  2219. struct drm_device *dev = node->minor->dev;
  2220. struct radeon_device *rdev = dev->dev_private;
  2221. uint32_t reg, value;
  2222. unsigned i;
  2223. seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
  2224. seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
  2225. seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
  2226. for (i = 0; i < 64; i++) {
  2227. WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
  2228. reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
  2229. WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
  2230. value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
  2231. seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
  2232. }
  2233. return 0;
  2234. }
  2235. static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
  2236. {
  2237. struct drm_info_node *node = (struct drm_info_node *) m->private;
  2238. struct drm_device *dev = node->minor->dev;
  2239. struct radeon_device *rdev = dev->dev_private;
  2240. uint32_t rdp, wdp;
  2241. unsigned count, i, j;
  2242. radeon_ring_free_size(rdev);
  2243. rdp = RREG32(RADEON_CP_RB_RPTR);
  2244. wdp = RREG32(RADEON_CP_RB_WPTR);
  2245. count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
  2246. seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
  2247. seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
  2248. seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
  2249. seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
  2250. seq_printf(m, "%u dwords in ring\n", count);
  2251. for (j = 0; j <= count; j++) {
  2252. i = (rdp + j) & rdev->cp.ptr_mask;
  2253. seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
  2254. }
  2255. return 0;
  2256. }
  2257. static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
  2258. {
  2259. struct drm_info_node *node = (struct drm_info_node *) m->private;
  2260. struct drm_device *dev = node->minor->dev;
  2261. struct radeon_device *rdev = dev->dev_private;
  2262. uint32_t csq_stat, csq2_stat, tmp;
  2263. unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
  2264. unsigned i;
  2265. seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
  2266. seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
  2267. csq_stat = RREG32(RADEON_CP_CSQ_STAT);
  2268. csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
  2269. r_rptr = (csq_stat >> 0) & 0x3ff;
  2270. r_wptr = (csq_stat >> 10) & 0x3ff;
  2271. ib1_rptr = (csq_stat >> 20) & 0x3ff;
  2272. ib1_wptr = (csq2_stat >> 0) & 0x3ff;
  2273. ib2_rptr = (csq2_stat >> 10) & 0x3ff;
  2274. ib2_wptr = (csq2_stat >> 20) & 0x3ff;
  2275. seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
  2276. seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
  2277. seq_printf(m, "Ring rptr %u\n", r_rptr);
  2278. seq_printf(m, "Ring wptr %u\n", r_wptr);
  2279. seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
  2280. seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
  2281. seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
  2282. seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
  2283. /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
  2284. * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
  2285. seq_printf(m, "Ring fifo:\n");
  2286. for (i = 0; i < 256; i++) {
  2287. WREG32(RADEON_CP_CSQ_ADDR, i << 2);
  2288. tmp = RREG32(RADEON_CP_CSQ_DATA);
  2289. seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
  2290. }
  2291. seq_printf(m, "Indirect1 fifo:\n");
  2292. for (i = 256; i <= 512; i++) {
  2293. WREG32(RADEON_CP_CSQ_ADDR, i << 2);
  2294. tmp = RREG32(RADEON_CP_CSQ_DATA);
  2295. seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
  2296. }
  2297. seq_printf(m, "Indirect2 fifo:\n");
  2298. for (i = 640; i < ib1_wptr; i++) {
  2299. WREG32(RADEON_CP_CSQ_ADDR, i << 2);
  2300. tmp = RREG32(RADEON_CP_CSQ_DATA);
  2301. seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
  2302. }
  2303. return 0;
  2304. }
  2305. static int r100_debugfs_mc_info(struct seq_file *m, void *data)
  2306. {
  2307. struct drm_info_node *node = (struct drm_info_node *) m->private;
  2308. struct drm_device *dev = node->minor->dev;
  2309. struct radeon_device *rdev = dev->dev_private;
  2310. uint32_t tmp;
  2311. tmp = RREG32(RADEON_CONFIG_MEMSIZE);
  2312. seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
  2313. tmp = RREG32(RADEON_MC_FB_LOCATION);
  2314. seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
  2315. tmp = RREG32(RADEON_BUS_CNTL);
  2316. seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
  2317. tmp = RREG32(RADEON_MC_AGP_LOCATION);
  2318. seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
  2319. tmp = RREG32(RADEON_AGP_BASE);
  2320. seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
  2321. tmp = RREG32(RADEON_HOST_PATH_CNTL);
  2322. seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
  2323. tmp = RREG32(0x01D0);
  2324. seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
  2325. tmp = RREG32(RADEON_AIC_LO_ADDR);
  2326. seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
  2327. tmp = RREG32(RADEON_AIC_HI_ADDR);
  2328. seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
  2329. tmp = RREG32(0x01E4);
  2330. seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
  2331. return 0;
  2332. }
  2333. static struct drm_info_list r100_debugfs_rbbm_list[] = {
  2334. {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
  2335. };
  2336. static struct drm_info_list r100_debugfs_cp_list[] = {
  2337. {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
  2338. {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
  2339. };
  2340. static struct drm_info_list r100_debugfs_mc_info_list[] = {
  2341. {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
  2342. };
  2343. #endif
  2344. int r100_debugfs_rbbm_init(struct radeon_device *rdev)
  2345. {
  2346. #if defined(CONFIG_DEBUG_FS)
  2347. return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
  2348. #else
  2349. return 0;
  2350. #endif
  2351. }
  2352. int r100_debugfs_cp_init(struct radeon_device *rdev)
  2353. {
  2354. #if defined(CONFIG_DEBUG_FS)
  2355. return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
  2356. #else
  2357. return 0;
  2358. #endif
  2359. }
  2360. int r100_debugfs_mc_info_init(struct radeon_device *rdev)
  2361. {
  2362. #if defined(CONFIG_DEBUG_FS)
  2363. return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
  2364. #else
  2365. return 0;
  2366. #endif
  2367. }
  2368. int r100_set_surface_reg(struct radeon_device *rdev, int reg,
  2369. uint32_t tiling_flags, uint32_t pitch,
  2370. uint32_t offset, uint32_t obj_size)
  2371. {
  2372. int surf_index = reg * 16;
  2373. int flags = 0;
  2374. if (rdev->family <= CHIP_RS200) {
  2375. if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
  2376. == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
  2377. flags |= RADEON_SURF_TILE_COLOR_BOTH;
  2378. if (tiling_flags & RADEON_TILING_MACRO)
  2379. flags |= RADEON_SURF_TILE_COLOR_MACRO;
  2380. } else if (rdev->family <= CHIP_RV280) {
  2381. if (tiling_flags & (RADEON_TILING_MACRO))
  2382. flags |= R200_SURF_TILE_COLOR_MACRO;
  2383. if (tiling_flags & RADEON_TILING_MICRO)
  2384. flags |= R200_SURF_TILE_COLOR_MICRO;
  2385. } else {
  2386. if (tiling_flags & RADEON_TILING_MACRO)
  2387. flags |= R300_SURF_TILE_MACRO;
  2388. if (tiling_flags & RADEON_TILING_MICRO)
  2389. flags |= R300_SURF_TILE_MICRO;
  2390. }
  2391. if (tiling_flags & RADEON_TILING_SWAP_16BIT)
  2392. flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
  2393. if (tiling_flags & RADEON_TILING_SWAP_32BIT)
  2394. flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
  2395. /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */
  2396. if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) {
  2397. if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO)))
  2398. if (ASIC_IS_RN50(rdev))
  2399. pitch /= 16;
  2400. }
  2401. /* r100/r200 divide by 16 */
  2402. if (rdev->family < CHIP_R300)
  2403. flags |= pitch / 16;
  2404. else
  2405. flags |= pitch / 8;
  2406. DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
  2407. WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
  2408. WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
  2409. WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
  2410. return 0;
  2411. }
  2412. void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
  2413. {
  2414. int surf_index = reg * 16;
  2415. WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
  2416. }
  2417. void r100_bandwidth_update(struct radeon_device *rdev)
  2418. {
  2419. fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
  2420. fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
  2421. fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
  2422. uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
  2423. fixed20_12 memtcas_ff[8] = {
  2424. dfixed_init(1),
  2425. dfixed_init(2),
  2426. dfixed_init(3),
  2427. dfixed_init(0),
  2428. dfixed_init_half(1),
  2429. dfixed_init_half(2),
  2430. dfixed_init(0),
  2431. };
  2432. fixed20_12 memtcas_rs480_ff[8] = {
  2433. dfixed_init(0),
  2434. dfixed_init(1),
  2435. dfixed_init(2),
  2436. dfixed_init(3),
  2437. dfixed_init(0),
  2438. dfixed_init_half(1),
  2439. dfixed_init_half(2),
  2440. dfixed_init_half(3),
  2441. };
  2442. fixed20_12 memtcas2_ff[8] = {
  2443. dfixed_init(0),
  2444. dfixed_init(1),
  2445. dfixed_init(2),
  2446. dfixed_init(3),
  2447. dfixed_init(4),
  2448. dfixed_init(5),
  2449. dfixed_init(6),
  2450. dfixed_init(7),
  2451. };
  2452. fixed20_12 memtrbs[8] = {
  2453. dfixed_init(1),
  2454. dfixed_init_half(1),
  2455. dfixed_init(2),
  2456. dfixed_init_half(2),
  2457. dfixed_init(3),
  2458. dfixed_init_half(3),
  2459. dfixed_init(4),
  2460. dfixed_init_half(4)
  2461. };
  2462. fixed20_12 memtrbs_r4xx[8] = {
  2463. dfixed_init(4),
  2464. dfixed_init(5),
  2465. dfixed_init(6),
  2466. dfixed_init(7),
  2467. dfixed_init(8),
  2468. dfixed_init(9),
  2469. dfixed_init(10),
  2470. dfixed_init(11)
  2471. };
  2472. fixed20_12 min_mem_eff;
  2473. fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
  2474. fixed20_12 cur_latency_mclk, cur_latency_sclk;
  2475. fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
  2476. disp_drain_rate2, read_return_rate;
  2477. fixed20_12 time_disp1_drop_priority;
  2478. int c;
  2479. int cur_size = 16; /* in octawords */
  2480. int critical_point = 0, critical_point2;
  2481. /* uint32_t read_return_rate, time_disp1_drop_priority; */
  2482. int stop_req, max_stop_req;
  2483. struct drm_display_mode *mode1 = NULL;
  2484. struct drm_display_mode *mode2 = NULL;
  2485. uint32_t pixel_bytes1 = 0;
  2486. uint32_t pixel_bytes2 = 0;
  2487. radeon_update_display_priority(rdev);
  2488. if (rdev->mode_info.crtcs[0]->base.enabled) {
  2489. mode1 = &rdev->mode_info.crtcs[0]->base.mode;
  2490. pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
  2491. }
  2492. if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
  2493. if (rdev->mode_info.crtcs[1]->base.enabled) {
  2494. mode2 = &rdev->mode_info.crtcs[1]->base.mode;
  2495. pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
  2496. }
  2497. }
  2498. min_mem_eff.full = dfixed_const_8(0);
  2499. /* get modes */
  2500. if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
  2501. uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
  2502. mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
  2503. mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
  2504. /* check crtc enables */
  2505. if (mode2)
  2506. mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
  2507. if (mode1)
  2508. mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
  2509. WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
  2510. }
  2511. /*
  2512. * determine is there is enough bw for current mode
  2513. */
  2514. sclk_ff = rdev->pm.sclk;
  2515. mclk_ff = rdev->pm.mclk;
  2516. temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
  2517. temp_ff.full = dfixed_const(temp);
  2518. mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
  2519. pix_clk.full = 0;
  2520. pix_clk2.full = 0;
  2521. peak_disp_bw.full = 0;
  2522. if (mode1) {
  2523. temp_ff.full = dfixed_const(1000);
  2524. pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
  2525. pix_clk.full = dfixed_div(pix_clk, temp_ff);
  2526. temp_ff.full = dfixed_const(pixel_bytes1);
  2527. peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
  2528. }
  2529. if (mode2) {
  2530. temp_ff.full = dfixed_const(1000);
  2531. pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
  2532. pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
  2533. temp_ff.full = dfixed_const(pixel_bytes2);
  2534. peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
  2535. }
  2536. mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
  2537. if (peak_disp_bw.full >= mem_bw.full) {
  2538. DRM_ERROR("You may not have enough display bandwidth for current mode\n"
  2539. "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
  2540. }
  2541. /* Get values from the EXT_MEM_CNTL register...converting its contents. */
  2542. temp = RREG32(RADEON_MEM_TIMING_CNTL);
  2543. if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
  2544. mem_trcd = ((temp >> 2) & 0x3) + 1;
  2545. mem_trp = ((temp & 0x3)) + 1;
  2546. mem_tras = ((temp & 0x70) >> 4) + 1;
  2547. } else if (rdev->family == CHIP_R300 ||
  2548. rdev->family == CHIP_R350) { /* r300, r350 */
  2549. mem_trcd = (temp & 0x7) + 1;
  2550. mem_trp = ((temp >> 8) & 0x7) + 1;
  2551. mem_tras = ((temp >> 11) & 0xf) + 4;
  2552. } else if (rdev->family == CHIP_RV350 ||
  2553. rdev->family <= CHIP_RV380) {
  2554. /* rv3x0 */
  2555. mem_trcd = (temp & 0x7) + 3;
  2556. mem_trp = ((temp >> 8) & 0x7) + 3;
  2557. mem_tras = ((temp >> 11) & 0xf) + 6;
  2558. } else if (rdev->family == CHIP_R420 ||
  2559. rdev->family == CHIP_R423 ||
  2560. rdev->family == CHIP_RV410) {
  2561. /* r4xx */
  2562. mem_trcd = (temp & 0xf) + 3;
  2563. if (mem_trcd > 15)
  2564. mem_trcd = 15;
  2565. mem_trp = ((temp >> 8) & 0xf) + 3;
  2566. if (mem_trp > 15)
  2567. mem_trp = 15;
  2568. mem_tras = ((temp >> 12) & 0x1f) + 6;
  2569. if (mem_tras > 31)
  2570. mem_tras = 31;
  2571. } else { /* RV200, R200 */
  2572. mem_trcd = (temp & 0x7) + 1;
  2573. mem_trp = ((temp >> 8) & 0x7) + 1;
  2574. mem_tras = ((temp >> 12) & 0xf) + 4;
  2575. }
  2576. /* convert to FF */
  2577. trcd_ff.full = dfixed_const(mem_trcd);
  2578. trp_ff.full = dfixed_const(mem_trp);
  2579. tras_ff.full = dfixed_const(mem_tras);
  2580. /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
  2581. temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
  2582. data = (temp & (7 << 20)) >> 20;
  2583. if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
  2584. if (rdev->family == CHIP_RS480) /* don't think rs400 */
  2585. tcas_ff = memtcas_rs480_ff[data];
  2586. else
  2587. tcas_ff = memtcas_ff[data];
  2588. } else
  2589. tcas_ff = memtcas2_ff[data];
  2590. if (rdev->family == CHIP_RS400 ||
  2591. rdev->family == CHIP_RS480) {
  2592. /* extra cas latency stored in bits 23-25 0-4 clocks */
  2593. data = (temp >> 23) & 0x7;
  2594. if (data < 5)
  2595. tcas_ff.full += dfixed_const(data);
  2596. }
  2597. if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
  2598. /* on the R300, Tcas is included in Trbs.
  2599. */
  2600. temp = RREG32(RADEON_MEM_CNTL);
  2601. data = (R300_MEM_NUM_CHANNELS_MASK & temp);
  2602. if (data == 1) {
  2603. if (R300_MEM_USE_CD_CH_ONLY & temp) {
  2604. temp = RREG32(R300_MC_IND_INDEX);
  2605. temp &= ~R300_MC_IND_ADDR_MASK;
  2606. temp |= R300_MC_READ_CNTL_CD_mcind;
  2607. WREG32(R300_MC_IND_INDEX, temp);
  2608. temp = RREG32(R300_MC_IND_DATA);
  2609. data = (R300_MEM_RBS_POSITION_C_MASK & temp);
  2610. } else {
  2611. temp = RREG32(R300_MC_READ_CNTL_AB);
  2612. data = (R300_MEM_RBS_POSITION_A_MASK & temp);
  2613. }
  2614. } else {
  2615. temp = RREG32(R300_MC_READ_CNTL_AB);
  2616. data = (R300_MEM_RBS_POSITION_A_MASK & temp);
  2617. }
  2618. if (rdev->family == CHIP_RV410 ||
  2619. rdev->family == CHIP_R420 ||
  2620. rdev->family == CHIP_R423)
  2621. trbs_ff = memtrbs_r4xx[data];
  2622. else
  2623. trbs_ff = memtrbs[data];
  2624. tcas_ff.full += trbs_ff.full;
  2625. }
  2626. sclk_eff_ff.full = sclk_ff.full;
  2627. if (rdev->flags & RADEON_IS_AGP) {
  2628. fixed20_12 agpmode_ff;
  2629. agpmode_ff.full = dfixed_const(radeon_agpmode);
  2630. temp_ff.full = dfixed_const_666(16);
  2631. sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
  2632. }
  2633. /* TODO PCIE lanes may affect this - agpmode == 16?? */
  2634. if (ASIC_IS_R300(rdev)) {
  2635. sclk_delay_ff.full = dfixed_const(250);
  2636. } else {
  2637. if ((rdev->family == CHIP_RV100) ||
  2638. rdev->flags & RADEON_IS_IGP) {
  2639. if (rdev->mc.vram_is_ddr)
  2640. sclk_delay_ff.full = dfixed_const(41);
  2641. else
  2642. sclk_delay_ff.full = dfixed_const(33);
  2643. } else {
  2644. if (rdev->mc.vram_width == 128)
  2645. sclk_delay_ff.full = dfixed_const(57);
  2646. else
  2647. sclk_delay_ff.full = dfixed_const(41);
  2648. }
  2649. }
  2650. mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
  2651. if (rdev->mc.vram_is_ddr) {
  2652. if (rdev->mc.vram_width == 32) {
  2653. k1.full = dfixed_const(40);
  2654. c = 3;
  2655. } else {
  2656. k1.full = dfixed_const(20);
  2657. c = 1;
  2658. }
  2659. } else {
  2660. k1.full = dfixed_const(40);
  2661. c = 3;
  2662. }
  2663. temp_ff.full = dfixed_const(2);
  2664. mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
  2665. temp_ff.full = dfixed_const(c);
  2666. mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
  2667. temp_ff.full = dfixed_const(4);
  2668. mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
  2669. mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
  2670. mc_latency_mclk.full += k1.full;
  2671. mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
  2672. mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
  2673. /*
  2674. HW cursor time assuming worst case of full size colour cursor.
  2675. */
  2676. temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
  2677. temp_ff.full += trcd_ff.full;
  2678. if (temp_ff.full < tras_ff.full)
  2679. temp_ff.full = tras_ff.full;
  2680. cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
  2681. temp_ff.full = dfixed_const(cur_size);
  2682. cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
  2683. /*
  2684. Find the total latency for the display data.
  2685. */
  2686. disp_latency_overhead.full = dfixed_const(8);
  2687. disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
  2688. mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
  2689. mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
  2690. if (mc_latency_mclk.full > mc_latency_sclk.full)
  2691. disp_latency.full = mc_latency_mclk.full;
  2692. else
  2693. disp_latency.full = mc_latency_sclk.full;
  2694. /* setup Max GRPH_STOP_REQ default value */
  2695. if (ASIC_IS_RV100(rdev))
  2696. max_stop_req = 0x5c;
  2697. else
  2698. max_stop_req = 0x7c;
  2699. if (mode1) {
  2700. /* CRTC1
  2701. Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
  2702. GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
  2703. */
  2704. stop_req = mode1->hdisplay * pixel_bytes1 / 16;
  2705. if (stop_req > max_stop_req)
  2706. stop_req = max_stop_req;
  2707. /*
  2708. Find the drain rate of the display buffer.
  2709. */
  2710. temp_ff.full = dfixed_const((16/pixel_bytes1));
  2711. disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
  2712. /*
  2713. Find the critical point of the display buffer.
  2714. */
  2715. crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
  2716. crit_point_ff.full += dfixed_const_half(0);
  2717. critical_point = dfixed_trunc(crit_point_ff);
  2718. if (rdev->disp_priority == 2) {
  2719. critical_point = 0;
  2720. }
  2721. /*
  2722. The critical point should never be above max_stop_req-4. Setting
  2723. GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
  2724. */
  2725. if (max_stop_req - critical_point < 4)
  2726. critical_point = 0;
  2727. if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
  2728. /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
  2729. critical_point = 0x10;
  2730. }
  2731. temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
  2732. temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
  2733. temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
  2734. temp &= ~(RADEON_GRPH_START_REQ_MASK);
  2735. if ((rdev->family == CHIP_R350) &&
  2736. (stop_req > 0x15)) {
  2737. stop_req -= 0x10;
  2738. }
  2739. temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
  2740. temp |= RADEON_GRPH_BUFFER_SIZE;
  2741. temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
  2742. RADEON_GRPH_CRITICAL_AT_SOF |
  2743. RADEON_GRPH_STOP_CNTL);
  2744. /*
  2745. Write the result into the register.
  2746. */
  2747. WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
  2748. (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
  2749. #if 0
  2750. if ((rdev->family == CHIP_RS400) ||
  2751. (rdev->family == CHIP_RS480)) {
  2752. /* attempt to program RS400 disp regs correctly ??? */
  2753. temp = RREG32(RS400_DISP1_REG_CNTL);
  2754. temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
  2755. RS400_DISP1_STOP_REQ_LEVEL_MASK);
  2756. WREG32(RS400_DISP1_REQ_CNTL1, (temp |
  2757. (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
  2758. (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
  2759. temp = RREG32(RS400_DMIF_MEM_CNTL1);
  2760. temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
  2761. RS400_DISP1_CRITICAL_POINT_STOP_MASK);
  2762. WREG32(RS400_DMIF_MEM_CNTL1, (temp |
  2763. (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
  2764. (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
  2765. }
  2766. #endif
  2767. DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
  2768. /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
  2769. (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
  2770. }
  2771. if (mode2) {
  2772. u32 grph2_cntl;
  2773. stop_req = mode2->hdisplay * pixel_bytes2 / 16;
  2774. if (stop_req > max_stop_req)
  2775. stop_req = max_stop_req;
  2776. /*
  2777. Find the drain rate of the display buffer.
  2778. */
  2779. temp_ff.full = dfixed_const((16/pixel_bytes2));
  2780. disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
  2781. grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
  2782. grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
  2783. grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
  2784. grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
  2785. if ((rdev->family == CHIP_R350) &&
  2786. (stop_req > 0x15)) {
  2787. stop_req -= 0x10;
  2788. }
  2789. grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
  2790. grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
  2791. grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
  2792. RADEON_GRPH_CRITICAL_AT_SOF |
  2793. RADEON_GRPH_STOP_CNTL);
  2794. if ((rdev->family == CHIP_RS100) ||
  2795. (rdev->family == CHIP_RS200))
  2796. critical_point2 = 0;
  2797. else {
  2798. temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
  2799. temp_ff.full = dfixed_const(temp);
  2800. temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
  2801. if (sclk_ff.full < temp_ff.full)
  2802. temp_ff.full = sclk_ff.full;
  2803. read_return_rate.full = temp_ff.full;
  2804. if (mode1) {
  2805. temp_ff.full = read_return_rate.full - disp_drain_rate.full;
  2806. time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
  2807. } else {
  2808. time_disp1_drop_priority.full = 0;
  2809. }
  2810. crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
  2811. crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
  2812. crit_point_ff.full += dfixed_const_half(0);
  2813. critical_point2 = dfixed_trunc(crit_point_ff);
  2814. if (rdev->disp_priority == 2) {
  2815. critical_point2 = 0;
  2816. }
  2817. if (max_stop_req - critical_point2 < 4)
  2818. critical_point2 = 0;
  2819. }
  2820. if (critical_point2 == 0 && rdev->family == CHIP_R300) {
  2821. /* some R300 cards have problem with this set to 0 */
  2822. critical_point2 = 0x10;
  2823. }
  2824. WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
  2825. (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
  2826. if ((rdev->family == CHIP_RS400) ||
  2827. (rdev->family == CHIP_RS480)) {
  2828. #if 0
  2829. /* attempt to program RS400 disp2 regs correctly ??? */
  2830. temp = RREG32(RS400_DISP2_REQ_CNTL1);
  2831. temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
  2832. RS400_DISP2_STOP_REQ_LEVEL_MASK);
  2833. WREG32(RS400_DISP2_REQ_CNTL1, (temp |
  2834. (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
  2835. (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
  2836. temp = RREG32(RS400_DISP2_REQ_CNTL2);
  2837. temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
  2838. RS400_DISP2_CRITICAL_POINT_STOP_MASK);
  2839. WREG32(RS400_DISP2_REQ_CNTL2, (temp |
  2840. (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
  2841. (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
  2842. #endif
  2843. WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
  2844. WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
  2845. WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
  2846. WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
  2847. }
  2848. DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
  2849. (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
  2850. }
  2851. }
  2852. static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
  2853. {
  2854. DRM_ERROR("pitch %d\n", t->pitch);
  2855. DRM_ERROR("use_pitch %d\n", t->use_pitch);
  2856. DRM_ERROR("width %d\n", t->width);
  2857. DRM_ERROR("width_11 %d\n", t->width_11);
  2858. DRM_ERROR("height %d\n", t->height);
  2859. DRM_ERROR("height_11 %d\n", t->height_11);
  2860. DRM_ERROR("num levels %d\n", t->num_levels);
  2861. DRM_ERROR("depth %d\n", t->txdepth);
  2862. DRM_ERROR("bpp %d\n", t->cpp);
  2863. DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
  2864. DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
  2865. DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
  2866. DRM_ERROR("compress format %d\n", t->compress_format);
  2867. }
  2868. static int r100_track_compress_size(int compress_format, int w, int h)
  2869. {
  2870. int block_width, block_height, block_bytes;
  2871. int wblocks, hblocks;
  2872. int min_wblocks;
  2873. int sz;
  2874. block_width = 4;
  2875. block_height = 4;
  2876. switch (compress_format) {
  2877. case R100_TRACK_COMP_DXT1:
  2878. block_bytes = 8;
  2879. min_wblocks = 4;
  2880. break;
  2881. default:
  2882. case R100_TRACK_COMP_DXT35:
  2883. block_bytes = 16;
  2884. min_wblocks = 2;
  2885. break;
  2886. }
  2887. hblocks = (h + block_height - 1) / block_height;
  2888. wblocks = (w + block_width - 1) / block_width;
  2889. if (wblocks < min_wblocks)
  2890. wblocks = min_wblocks;
  2891. sz = wblocks * hblocks * block_bytes;
  2892. return sz;
  2893. }
  2894. static int r100_cs_track_cube(struct radeon_device *rdev,
  2895. struct r100_cs_track *track, unsigned idx)
  2896. {
  2897. unsigned face, w, h;
  2898. struct radeon_bo *cube_robj;
  2899. unsigned long size;
  2900. unsigned compress_format = track->textures[idx].compress_format;
  2901. for (face = 0; face < 5; face++) {
  2902. cube_robj = track->textures[idx].cube_info[face].robj;
  2903. w = track->textures[idx].cube_info[face].width;
  2904. h = track->textures[idx].cube_info[face].height;
  2905. if (compress_format) {
  2906. size = r100_track_compress_size(compress_format, w, h);
  2907. } else
  2908. size = w * h;
  2909. size *= track->textures[idx].cpp;
  2910. size += track->textures[idx].cube_info[face].offset;
  2911. if (size > radeon_bo_size(cube_robj)) {
  2912. DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
  2913. size, radeon_bo_size(cube_robj));
  2914. r100_cs_track_texture_print(&track->textures[idx]);
  2915. return -1;
  2916. }
  2917. }
  2918. return 0;
  2919. }
  2920. static int r100_cs_track_texture_check(struct radeon_device *rdev,
  2921. struct r100_cs_track *track)
  2922. {
  2923. struct radeon_bo *robj;
  2924. unsigned long size;
  2925. unsigned u, i, w, h, d;
  2926. int ret;
  2927. for (u = 0; u < track->num_texture; u++) {
  2928. if (!track->textures[u].enabled)
  2929. continue;
  2930. if (track->textures[u].lookup_disable)
  2931. continue;
  2932. robj = track->textures[u].robj;
  2933. if (robj == NULL) {
  2934. DRM_ERROR("No texture bound to unit %u\n", u);
  2935. return -EINVAL;
  2936. }
  2937. size = 0;
  2938. for (i = 0; i <= track->textures[u].num_levels; i++) {
  2939. if (track->textures[u].use_pitch) {
  2940. if (rdev->family < CHIP_R300)
  2941. w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
  2942. else
  2943. w = track->textures[u].pitch / (1 << i);
  2944. } else {
  2945. w = track->textures[u].width;
  2946. if (rdev->family >= CHIP_RV515)
  2947. w |= track->textures[u].width_11;
  2948. w = w / (1 << i);
  2949. if (track->textures[u].roundup_w)
  2950. w = roundup_pow_of_two(w);
  2951. }
  2952. h = track->textures[u].height;
  2953. if (rdev->family >= CHIP_RV515)
  2954. h |= track->textures[u].height_11;
  2955. h = h / (1 << i);
  2956. if (track->textures[u].roundup_h)
  2957. h = roundup_pow_of_two(h);
  2958. if (track->textures[u].tex_coord_type == 1) {
  2959. d = (1 << track->textures[u].txdepth) / (1 << i);
  2960. if (!d)
  2961. d = 1;
  2962. } else {
  2963. d = 1;
  2964. }
  2965. if (track->textures[u].compress_format) {
  2966. size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
  2967. /* compressed textures are block based */
  2968. } else
  2969. size += w * h * d;
  2970. }
  2971. size *= track->textures[u].cpp;
  2972. switch (track->textures[u].tex_coord_type) {
  2973. case 0:
  2974. case 1:
  2975. break;
  2976. case 2:
  2977. if (track->separate_cube) {
  2978. ret = r100_cs_track_cube(rdev, track, u);
  2979. if (ret)
  2980. return ret;
  2981. } else
  2982. size *= 6;
  2983. break;
  2984. default:
  2985. DRM_ERROR("Invalid texture coordinate type %u for unit "
  2986. "%u\n", track->textures[u].tex_coord_type, u);
  2987. return -EINVAL;
  2988. }
  2989. if (size > radeon_bo_size(robj)) {
  2990. DRM_ERROR("Texture of unit %u needs %lu bytes but is "
  2991. "%lu\n", u, size, radeon_bo_size(robj));
  2992. r100_cs_track_texture_print(&track->textures[u]);
  2993. return -EINVAL;
  2994. }
  2995. }
  2996. return 0;
  2997. }
  2998. int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
  2999. {
  3000. unsigned i;
  3001. unsigned long size;
  3002. unsigned prim_walk;
  3003. unsigned nverts;
  3004. unsigned num_cb = track->num_cb;
  3005. if (!track->zb_cb_clear && !track->color_channel_mask &&
  3006. !track->blend_read_enable)
  3007. num_cb = 0;
  3008. for (i = 0; i < num_cb; i++) {
  3009. if (track->cb[i].robj == NULL) {
  3010. DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
  3011. return -EINVAL;
  3012. }
  3013. size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
  3014. size += track->cb[i].offset;
  3015. if (size > radeon_bo_size(track->cb[i].robj)) {
  3016. DRM_ERROR("[drm] Buffer too small for color buffer %d "
  3017. "(need %lu have %lu) !\n", i, size,
  3018. radeon_bo_size(track->cb[i].robj));
  3019. DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
  3020. i, track->cb[i].pitch, track->cb[i].cpp,
  3021. track->cb[i].offset, track->maxy);
  3022. return -EINVAL;
  3023. }
  3024. }
  3025. if (track->z_enabled) {
  3026. if (track->zb.robj == NULL) {
  3027. DRM_ERROR("[drm] No buffer for z buffer !\n");
  3028. return -EINVAL;
  3029. }
  3030. size = track->zb.pitch * track->zb.cpp * track->maxy;
  3031. size += track->zb.offset;
  3032. if (size > radeon_bo_size(track->zb.robj)) {
  3033. DRM_ERROR("[drm] Buffer too small for z buffer "
  3034. "(need %lu have %lu) !\n", size,
  3035. radeon_bo_size(track->zb.robj));
  3036. DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
  3037. track->zb.pitch, track->zb.cpp,
  3038. track->zb.offset, track->maxy);
  3039. return -EINVAL;
  3040. }
  3041. }
  3042. prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
  3043. if (track->vap_vf_cntl & (1 << 14)) {
  3044. nverts = track->vap_alt_nverts;
  3045. } else {
  3046. nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
  3047. }
  3048. switch (prim_walk) {
  3049. case 1:
  3050. for (i = 0; i < track->num_arrays; i++) {
  3051. size = track->arrays[i].esize * track->max_indx * 4;
  3052. if (track->arrays[i].robj == NULL) {
  3053. DRM_ERROR("(PW %u) Vertex array %u no buffer "
  3054. "bound\n", prim_walk, i);
  3055. return -EINVAL;
  3056. }
  3057. if (size > radeon_bo_size(track->arrays[i].robj)) {
  3058. dev_err(rdev->dev, "(PW %u) Vertex array %u "
  3059. "need %lu dwords have %lu dwords\n",
  3060. prim_walk, i, size >> 2,
  3061. radeon_bo_size(track->arrays[i].robj)
  3062. >> 2);
  3063. DRM_ERROR("Max indices %u\n", track->max_indx);
  3064. return -EINVAL;
  3065. }
  3066. }
  3067. break;
  3068. case 2:
  3069. for (i = 0; i < track->num_arrays; i++) {
  3070. size = track->arrays[i].esize * (nverts - 1) * 4;
  3071. if (track->arrays[i].robj == NULL) {
  3072. DRM_ERROR("(PW %u) Vertex array %u no buffer "
  3073. "bound\n", prim_walk, i);
  3074. return -EINVAL;
  3075. }
  3076. if (size > radeon_bo_size(track->arrays[i].robj)) {
  3077. dev_err(rdev->dev, "(PW %u) Vertex array %u "
  3078. "need %lu dwords have %lu dwords\n",
  3079. prim_walk, i, size >> 2,
  3080. radeon_bo_size(track->arrays[i].robj)
  3081. >> 2);
  3082. return -EINVAL;
  3083. }
  3084. }
  3085. break;
  3086. case 3:
  3087. size = track->vtx_size * nverts;
  3088. if (size != track->immd_dwords) {
  3089. DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
  3090. track->immd_dwords, size);
  3091. DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
  3092. nverts, track->vtx_size);
  3093. return -EINVAL;
  3094. }
  3095. break;
  3096. default:
  3097. DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
  3098. prim_walk);
  3099. return -EINVAL;
  3100. }
  3101. return r100_cs_track_texture_check(rdev, track);
  3102. }
  3103. void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
  3104. {
  3105. unsigned i, face;
  3106. if (rdev->family < CHIP_R300) {
  3107. track->num_cb = 1;
  3108. if (rdev->family <= CHIP_RS200)
  3109. track->num_texture = 3;
  3110. else
  3111. track->num_texture = 6;
  3112. track->maxy = 2048;
  3113. track->separate_cube = 1;
  3114. } else {
  3115. track->num_cb = 4;
  3116. track->num_texture = 16;
  3117. track->maxy = 4096;
  3118. track->separate_cube = 0;
  3119. }
  3120. for (i = 0; i < track->num_cb; i++) {
  3121. track->cb[i].robj = NULL;
  3122. track->cb[i].pitch = 8192;
  3123. track->cb[i].cpp = 16;
  3124. track->cb[i].offset = 0;
  3125. }
  3126. track->z_enabled = true;
  3127. track->zb.robj = NULL;
  3128. track->zb.pitch = 8192;
  3129. track->zb.cpp = 4;
  3130. track->zb.offset = 0;
  3131. track->vtx_size = 0x7F;
  3132. track->immd_dwords = 0xFFFFFFFFUL;
  3133. track->num_arrays = 11;
  3134. track->max_indx = 0x00FFFFFFUL;
  3135. for (i = 0; i < track->num_arrays; i++) {
  3136. track->arrays[i].robj = NULL;
  3137. track->arrays[i].esize = 0x7F;
  3138. }
  3139. for (i = 0; i < track->num_texture; i++) {
  3140. track->textures[i].compress_format = R100_TRACK_COMP_NONE;
  3141. track->textures[i].pitch = 16536;
  3142. track->textures[i].width = 16536;
  3143. track->textures[i].height = 16536;
  3144. track->textures[i].width_11 = 1 << 11;
  3145. track->textures[i].height_11 = 1 << 11;
  3146. track->textures[i].num_levels = 12;
  3147. if (rdev->family <= CHIP_RS200) {
  3148. track->textures[i].tex_coord_type = 0;
  3149. track->textures[i].txdepth = 0;
  3150. } else {
  3151. track->textures[i].txdepth = 16;
  3152. track->textures[i].tex_coord_type = 1;
  3153. }
  3154. track->textures[i].cpp = 64;
  3155. track->textures[i].robj = NULL;
  3156. /* CS IB emission code makes sure texture unit are disabled */
  3157. track->textures[i].enabled = false;
  3158. track->textures[i].lookup_disable = false;
  3159. track->textures[i].roundup_w = true;
  3160. track->textures[i].roundup_h = true;
  3161. if (track->separate_cube)
  3162. for (face = 0; face < 5; face++) {
  3163. track->textures[i].cube_info[face].robj = NULL;
  3164. track->textures[i].cube_info[face].width = 16536;
  3165. track->textures[i].cube_info[face].height = 16536;
  3166. track->textures[i].cube_info[face].offset = 0;
  3167. }
  3168. }
  3169. }
  3170. int r100_ring_test(struct radeon_device *rdev)
  3171. {
  3172. uint32_t scratch;
  3173. uint32_t tmp = 0;
  3174. unsigned i;
  3175. int r;
  3176. r = radeon_scratch_get(rdev, &scratch);
  3177. if (r) {
  3178. DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
  3179. return r;
  3180. }
  3181. WREG32(scratch, 0xCAFEDEAD);
  3182. r = radeon_ring_lock(rdev, 2);
  3183. if (r) {
  3184. DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
  3185. radeon_scratch_free(rdev, scratch);
  3186. return r;
  3187. }
  3188. radeon_ring_write(rdev, PACKET0(scratch, 0));
  3189. radeon_ring_write(rdev, 0xDEADBEEF);
  3190. radeon_ring_unlock_commit(rdev);
  3191. for (i = 0; i < rdev->usec_timeout; i++) {
  3192. tmp = RREG32(scratch);
  3193. if (tmp == 0xDEADBEEF) {
  3194. break;
  3195. }
  3196. DRM_UDELAY(1);
  3197. }
  3198. if (i < rdev->usec_timeout) {
  3199. DRM_INFO("ring test succeeded in %d usecs\n", i);
  3200. } else {
  3201. DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
  3202. scratch, tmp);
  3203. r = -EINVAL;
  3204. }
  3205. radeon_scratch_free(rdev, scratch);
  3206. return r;
  3207. }
  3208. void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
  3209. {
  3210. radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
  3211. radeon_ring_write(rdev, ib->gpu_addr);
  3212. radeon_ring_write(rdev, ib->length_dw);
  3213. }
  3214. int r100_ib_test(struct radeon_device *rdev)
  3215. {
  3216. struct radeon_ib *ib;
  3217. uint32_t scratch;
  3218. uint32_t tmp = 0;
  3219. unsigned i;
  3220. int r;
  3221. r = radeon_scratch_get(rdev, &scratch);
  3222. if (r) {
  3223. DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
  3224. return r;
  3225. }
  3226. WREG32(scratch, 0xCAFEDEAD);
  3227. r = radeon_ib_get(rdev, &ib);
  3228. if (r) {
  3229. return r;
  3230. }
  3231. ib->ptr[0] = PACKET0(scratch, 0);
  3232. ib->ptr[1] = 0xDEADBEEF;
  3233. ib->ptr[2] = PACKET2(0);
  3234. ib->ptr[3] = PACKET2(0);
  3235. ib->ptr[4] = PACKET2(0);
  3236. ib->ptr[5] = PACKET2(0);
  3237. ib->ptr[6] = PACKET2(0);
  3238. ib->ptr[7] = PACKET2(0);
  3239. ib->length_dw = 8;
  3240. r = radeon_ib_schedule(rdev, ib);
  3241. if (r) {
  3242. radeon_scratch_free(rdev, scratch);
  3243. radeon_ib_free(rdev, &ib);
  3244. return r;
  3245. }
  3246. r = radeon_fence_wait(ib->fence, false);
  3247. if (r) {
  3248. return r;
  3249. }
  3250. for (i = 0; i < rdev->usec_timeout; i++) {
  3251. tmp = RREG32(scratch);
  3252. if (tmp == 0xDEADBEEF) {
  3253. break;
  3254. }
  3255. DRM_UDELAY(1);
  3256. }
  3257. if (i < rdev->usec_timeout) {
  3258. DRM_INFO("ib test succeeded in %u usecs\n", i);
  3259. } else {
  3260. DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
  3261. scratch, tmp);
  3262. r = -EINVAL;
  3263. }
  3264. radeon_scratch_free(rdev, scratch);
  3265. radeon_ib_free(rdev, &ib);
  3266. return r;
  3267. }
  3268. void r100_ib_fini(struct radeon_device *rdev)
  3269. {
  3270. radeon_ib_pool_fini(rdev);
  3271. }
  3272. int r100_ib_init(struct radeon_device *rdev)
  3273. {
  3274. int r;
  3275. r = radeon_ib_pool_init(rdev);
  3276. if (r) {
  3277. dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
  3278. r100_ib_fini(rdev);
  3279. return r;
  3280. }
  3281. r = r100_ib_test(rdev);
  3282. if (r) {
  3283. dev_err(rdev->dev, "failled testing IB (%d).\n", r);
  3284. r100_ib_fini(rdev);
  3285. return r;
  3286. }
  3287. return 0;
  3288. }
  3289. void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
  3290. {
  3291. /* Shutdown CP we shouldn't need to do that but better be safe than
  3292. * sorry
  3293. */
  3294. rdev->cp.ready = false;
  3295. WREG32(R_000740_CP_CSQ_CNTL, 0);
  3296. /* Save few CRTC registers */
  3297. save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
  3298. save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
  3299. save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
  3300. save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
  3301. if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
  3302. save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
  3303. save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
  3304. }
  3305. /* Disable VGA aperture access */
  3306. WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
  3307. /* Disable cursor, overlay, crtc */
  3308. WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
  3309. WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
  3310. S_000054_CRTC_DISPLAY_DIS(1));
  3311. WREG32(R_000050_CRTC_GEN_CNTL,
  3312. (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
  3313. S_000050_CRTC_DISP_REQ_EN_B(1));
  3314. WREG32(R_000420_OV0_SCALE_CNTL,
  3315. C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
  3316. WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
  3317. if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
  3318. WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
  3319. S_000360_CUR2_LOCK(1));
  3320. WREG32(R_0003F8_CRTC2_GEN_CNTL,
  3321. (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
  3322. S_0003F8_CRTC2_DISPLAY_DIS(1) |
  3323. S_0003F8_CRTC2_DISP_REQ_EN_B(1));
  3324. WREG32(R_000360_CUR2_OFFSET,
  3325. C_000360_CUR2_LOCK & save->CUR2_OFFSET);
  3326. }
  3327. }
  3328. void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
  3329. {
  3330. /* Update base address for crtc */
  3331. WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
  3332. if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
  3333. WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
  3334. }
  3335. /* Restore CRTC registers */
  3336. WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
  3337. WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
  3338. WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
  3339. if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
  3340. WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
  3341. }
  3342. }
  3343. void r100_vga_render_disable(struct radeon_device *rdev)
  3344. {
  3345. u32 tmp;
  3346. tmp = RREG8(R_0003C2_GENMO_WT);
  3347. WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
  3348. }
  3349. static void r100_debugfs(struct radeon_device *rdev)
  3350. {
  3351. int r;
  3352. r = r100_debugfs_mc_info_init(rdev);
  3353. if (r)
  3354. dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
  3355. }
  3356. static void r100_mc_program(struct radeon_device *rdev)
  3357. {
  3358. struct r100_mc_save save;
  3359. /* Stops all mc clients */
  3360. r100_mc_stop(rdev, &save);
  3361. if (rdev->flags & RADEON_IS_AGP) {
  3362. WREG32(R_00014C_MC_AGP_LOCATION,
  3363. S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
  3364. S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
  3365. WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
  3366. if (rdev->family > CHIP_RV200)
  3367. WREG32(R_00015C_AGP_BASE_2,
  3368. upper_32_bits(rdev->mc.agp_base) & 0xff);
  3369. } else {
  3370. WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
  3371. WREG32(R_000170_AGP_BASE, 0);
  3372. if (rdev->family > CHIP_RV200)
  3373. WREG32(R_00015C_AGP_BASE_2, 0);
  3374. }
  3375. /* Wait for mc idle */
  3376. if (r100_mc_wait_for_idle(rdev))
  3377. dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
  3378. /* Program MC, should be a 32bits limited address space */
  3379. WREG32(R_000148_MC_FB_LOCATION,
  3380. S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
  3381. S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
  3382. r100_mc_resume(rdev, &save);
  3383. }
  3384. void r100_clock_startup(struct radeon_device *rdev)
  3385. {
  3386. u32 tmp;
  3387. if (radeon_dynclks != -1 && radeon_dynclks)
  3388. radeon_legacy_set_clock_gating(rdev, 1);
  3389. /* We need to force on some of the block */
  3390. tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
  3391. tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
  3392. if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
  3393. tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
  3394. WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
  3395. }
  3396. static int r100_startup(struct radeon_device *rdev)
  3397. {
  3398. int r;
  3399. /* set common regs */
  3400. r100_set_common_regs(rdev);
  3401. /* program mc */
  3402. r100_mc_program(rdev);
  3403. /* Resume clock */
  3404. r100_clock_startup(rdev);
  3405. /* Initialize GPU configuration (# pipes, ...) */
  3406. // r100_gpu_init(rdev);
  3407. /* Initialize GART (initialize after TTM so we can allocate
  3408. * memory through TTM but finalize after TTM) */
  3409. r100_enable_bm(rdev);
  3410. if (rdev->flags & RADEON_IS_PCI) {
  3411. r = r100_pci_gart_enable(rdev);
  3412. if (r)
  3413. return r;
  3414. }
  3415. /* allocate wb buffer */
  3416. r = radeon_wb_init(rdev);
  3417. if (r)
  3418. return r;
  3419. /* Enable IRQ */
  3420. r100_irq_set(rdev);
  3421. rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
  3422. /* 1M ring buffer */
  3423. r = r100_cp_init(rdev, 1024 * 1024);
  3424. if (r) {
  3425. dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
  3426. return r;
  3427. }
  3428. r = r100_ib_init(rdev);
  3429. if (r) {
  3430. dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
  3431. return r;
  3432. }
  3433. return 0;
  3434. }
  3435. int r100_resume(struct radeon_device *rdev)
  3436. {
  3437. /* Make sur GART are not working */
  3438. if (rdev->flags & RADEON_IS_PCI)
  3439. r100_pci_gart_disable(rdev);
  3440. /* Resume clock before doing reset */
  3441. r100_clock_startup(rdev);
  3442. /* Reset gpu before posting otherwise ATOM will enter infinite loop */
  3443. if (radeon_asic_reset(rdev)) {
  3444. dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
  3445. RREG32(R_000E40_RBBM_STATUS),
  3446. RREG32(R_0007C0_CP_STAT));
  3447. }
  3448. /* post */
  3449. radeon_combios_asic_init(rdev->ddev);
  3450. /* Resume clock after posting */
  3451. r100_clock_startup(rdev);
  3452. /* Initialize surface registers */
  3453. radeon_surface_init(rdev);
  3454. return r100_startup(rdev);
  3455. }
  3456. int r100_suspend(struct radeon_device *rdev)
  3457. {
  3458. r100_cp_disable(rdev);
  3459. radeon_wb_disable(rdev);
  3460. r100_irq_disable(rdev);
  3461. if (rdev->flags & RADEON_IS_PCI)
  3462. r100_pci_gart_disable(rdev);
  3463. return 0;
  3464. }
  3465. void r100_fini(struct radeon_device *rdev)
  3466. {
  3467. r100_cp_fini(rdev);
  3468. radeon_wb_fini(rdev);
  3469. r100_ib_fini(rdev);
  3470. radeon_gem_fini(rdev);
  3471. if (rdev->flags & RADEON_IS_PCI)
  3472. r100_pci_gart_fini(rdev);
  3473. radeon_agp_fini(rdev);
  3474. radeon_irq_kms_fini(rdev);
  3475. radeon_fence_driver_fini(rdev);
  3476. radeon_bo_fini(rdev);
  3477. radeon_atombios_fini(rdev);
  3478. kfree(rdev->bios);
  3479. rdev->bios = NULL;
  3480. }
  3481. /*
  3482. * Due to how kexec works, it can leave the hw fully initialised when it
  3483. * boots the new kernel. However doing our init sequence with the CP and
  3484. * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
  3485. * do some quick sanity checks and restore sane values to avoid this
  3486. * problem.
  3487. */
  3488. void r100_restore_sanity(struct radeon_device *rdev)
  3489. {
  3490. u32 tmp;
  3491. tmp = RREG32(RADEON_CP_CSQ_CNTL);
  3492. if (tmp) {
  3493. WREG32(RADEON_CP_CSQ_CNTL, 0);
  3494. }
  3495. tmp = RREG32(RADEON_CP_RB_CNTL);
  3496. if (tmp) {
  3497. WREG32(RADEON_CP_RB_CNTL, 0);
  3498. }
  3499. tmp = RREG32(RADEON_SCRATCH_UMSK);
  3500. if (tmp) {
  3501. WREG32(RADEON_SCRATCH_UMSK, 0);
  3502. }
  3503. }
  3504. int r100_init(struct radeon_device *rdev)
  3505. {
  3506. int r;
  3507. /* Register debugfs file specific to this group of asics */
  3508. r100_debugfs(rdev);
  3509. /* Disable VGA */
  3510. r100_vga_render_disable(rdev);
  3511. /* Initialize scratch registers */
  3512. radeon_scratch_init(rdev);
  3513. /* Initialize surface registers */
  3514. radeon_surface_init(rdev);
  3515. /* sanity check some register to avoid hangs like after kexec */
  3516. r100_restore_sanity(rdev);
  3517. /* TODO: disable VGA need to use VGA request */
  3518. /* BIOS*/
  3519. if (!radeon_get_bios(rdev)) {
  3520. if (ASIC_IS_AVIVO(rdev))
  3521. return -EINVAL;
  3522. }
  3523. if (rdev->is_atom_bios) {
  3524. dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
  3525. return -EINVAL;
  3526. } else {
  3527. r = radeon_combios_init(rdev);
  3528. if (r)
  3529. return r;
  3530. }
  3531. /* Reset gpu before posting otherwise ATOM will enter infinite loop */
  3532. if (radeon_asic_reset(rdev)) {
  3533. dev_warn(rdev->dev,
  3534. "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
  3535. RREG32(R_000E40_RBBM_STATUS),
  3536. RREG32(R_0007C0_CP_STAT));
  3537. }
  3538. /* check if cards are posted or not */
  3539. if (radeon_boot_test_post_card(rdev) == false)
  3540. return -EINVAL;
  3541. /* Set asic errata */
  3542. r100_errata(rdev);
  3543. /* Initialize clocks */
  3544. radeon_get_clock_info(rdev->ddev);
  3545. /* initialize AGP */
  3546. if (rdev->flags & RADEON_IS_AGP) {
  3547. r = radeon_agp_init(rdev);
  3548. if (r) {
  3549. radeon_agp_disable(rdev);
  3550. }
  3551. }
  3552. /* initialize VRAM */
  3553. r100_mc_init(rdev);
  3554. /* Fence driver */
  3555. r = radeon_fence_driver_init(rdev);
  3556. if (r)
  3557. return r;
  3558. r = radeon_irq_kms_init(rdev);
  3559. if (r)
  3560. return r;
  3561. /* Memory manager */
  3562. r = radeon_bo_init(rdev);
  3563. if (r)
  3564. return r;
  3565. if (rdev->flags & RADEON_IS_PCI) {
  3566. r = r100_pci_gart_init(rdev);
  3567. if (r)
  3568. return r;
  3569. }
  3570. r100_set_safe_registers(rdev);
  3571. rdev->accel_working = true;
  3572. r = r100_startup(rdev);
  3573. if (r) {
  3574. /* Somethings want wront with the accel init stop accel */
  3575. dev_err(rdev->dev, "Disabling GPU acceleration\n");
  3576. r100_cp_fini(rdev);
  3577. radeon_wb_fini(rdev);
  3578. r100_ib_fini(rdev);
  3579. radeon_irq_kms_fini(rdev);
  3580. if (rdev->flags & RADEON_IS_PCI)
  3581. r100_pci_gart_fini(rdev);
  3582. rdev->accel_working = false;
  3583. }
  3584. return 0;
  3585. }