nouveau_object.c 25 KB

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  1. /*
  2. * Copyright (C) 2006 Ben Skeggs.
  3. *
  4. * All Rights Reserved.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining
  7. * a copy of this software and associated documentation files (the
  8. * "Software"), to deal in the Software without restriction, including
  9. * without limitation the rights to use, copy, modify, merge, publish,
  10. * distribute, sublicense, and/or sell copies of the Software, and to
  11. * permit persons to whom the Software is furnished to do so, subject to
  12. * the following conditions:
  13. *
  14. * The above copyright notice and this permission notice (including the
  15. * next paragraph) shall be included in all copies or substantial
  16. * portions of the Software.
  17. *
  18. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21. * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22. * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23. * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24. * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25. *
  26. */
  27. /*
  28. * Authors:
  29. * Ben Skeggs <darktama@iinet.net.au>
  30. */
  31. #include "drmP.h"
  32. #include "drm.h"
  33. #include "nouveau_drv.h"
  34. #include "nouveau_drm.h"
  35. #include "nouveau_ramht.h"
  36. /* NVidia uses context objects to drive drawing operations.
  37. Context objects can be selected into 8 subchannels in the FIFO,
  38. and then used via DMA command buffers.
  39. A context object is referenced by a user defined handle (CARD32). The HW
  40. looks up graphics objects in a hash table in the instance RAM.
  41. An entry in the hash table consists of 2 CARD32. The first CARD32 contains
  42. the handle, the second one a bitfield, that contains the address of the
  43. object in instance RAM.
  44. The format of the second CARD32 seems to be:
  45. NV4 to NV30:
  46. 15: 0 instance_addr >> 4
  47. 17:16 engine (here uses 1 = graphics)
  48. 28:24 channel id (here uses 0)
  49. 31 valid (use 1)
  50. NV40:
  51. 15: 0 instance_addr >> 4 (maybe 19-0)
  52. 21:20 engine (here uses 1 = graphics)
  53. I'm unsure about the other bits, but using 0 seems to work.
  54. The key into the hash table depends on the object handle and channel id and
  55. is given as:
  56. */
  57. int
  58. nouveau_gpuobj_new(struct drm_device *dev, struct nouveau_channel *chan,
  59. uint32_t size, int align, uint32_t flags,
  60. struct nouveau_gpuobj **gpuobj_ret)
  61. {
  62. struct drm_nouveau_private *dev_priv = dev->dev_private;
  63. struct nouveau_engine *engine = &dev_priv->engine;
  64. struct nouveau_gpuobj *gpuobj;
  65. struct drm_mm_node *ramin = NULL;
  66. int ret;
  67. NV_DEBUG(dev, "ch%d size=%u align=%d flags=0x%08x\n",
  68. chan ? chan->id : -1, size, align, flags);
  69. if (!dev_priv || !gpuobj_ret || *gpuobj_ret != NULL)
  70. return -EINVAL;
  71. gpuobj = kzalloc(sizeof(*gpuobj), GFP_KERNEL);
  72. if (!gpuobj)
  73. return -ENOMEM;
  74. NV_DEBUG(dev, "gpuobj %p\n", gpuobj);
  75. gpuobj->dev = dev;
  76. gpuobj->flags = flags;
  77. kref_init(&gpuobj->refcount);
  78. gpuobj->size = size;
  79. spin_lock(&dev_priv->ramin_lock);
  80. list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list);
  81. spin_unlock(&dev_priv->ramin_lock);
  82. if (chan) {
  83. NV_DEBUG(dev, "channel heap\n");
  84. ramin = drm_mm_search_free(&chan->ramin_heap, size, align, 0);
  85. if (ramin)
  86. ramin = drm_mm_get_block(ramin, size, align);
  87. if (!ramin) {
  88. nouveau_gpuobj_ref(NULL, &gpuobj);
  89. return -ENOMEM;
  90. }
  91. } else {
  92. NV_DEBUG(dev, "global heap\n");
  93. /* allocate backing pages, sets vinst */
  94. ret = engine->instmem.populate(dev, gpuobj, &size);
  95. if (ret) {
  96. nouveau_gpuobj_ref(NULL, &gpuobj);
  97. return ret;
  98. }
  99. /* try and get aperture space */
  100. do {
  101. if (drm_mm_pre_get(&dev_priv->ramin_heap))
  102. return -ENOMEM;
  103. spin_lock(&dev_priv->ramin_lock);
  104. ramin = drm_mm_search_free(&dev_priv->ramin_heap, size,
  105. align, 0);
  106. if (ramin == NULL) {
  107. spin_unlock(&dev_priv->ramin_lock);
  108. nouveau_gpuobj_ref(NULL, &gpuobj);
  109. return -ENOMEM;
  110. }
  111. ramin = drm_mm_get_block_atomic(ramin, size, align);
  112. spin_unlock(&dev_priv->ramin_lock);
  113. } while (ramin == NULL);
  114. /* on nv50 it's ok to fail, we have a fallback path */
  115. if (!ramin && dev_priv->card_type < NV_50) {
  116. nouveau_gpuobj_ref(NULL, &gpuobj);
  117. return -ENOMEM;
  118. }
  119. }
  120. /* if we got a chunk of the aperture, map pages into it */
  121. gpuobj->im_pramin = ramin;
  122. if (!chan && gpuobj->im_pramin && dev_priv->ramin_available) {
  123. ret = engine->instmem.bind(dev, gpuobj);
  124. if (ret) {
  125. nouveau_gpuobj_ref(NULL, &gpuobj);
  126. return ret;
  127. }
  128. }
  129. /* calculate the various different addresses for the object */
  130. if (chan) {
  131. gpuobj->pinst = chan->ramin->pinst;
  132. if (gpuobj->pinst != ~0)
  133. gpuobj->pinst += gpuobj->im_pramin->start;
  134. if (dev_priv->card_type < NV_50) {
  135. gpuobj->cinst = gpuobj->pinst;
  136. } else {
  137. gpuobj->cinst = gpuobj->im_pramin->start;
  138. gpuobj->vinst = gpuobj->im_pramin->start +
  139. chan->ramin->vinst;
  140. }
  141. } else {
  142. if (gpuobj->im_pramin)
  143. gpuobj->pinst = gpuobj->im_pramin->start;
  144. else
  145. gpuobj->pinst = ~0;
  146. gpuobj->cinst = 0xdeadbeef;
  147. }
  148. if (gpuobj->flags & NVOBJ_FLAG_ZERO_ALLOC) {
  149. int i;
  150. for (i = 0; i < gpuobj->size; i += 4)
  151. nv_wo32(gpuobj, i, 0);
  152. engine->instmem.flush(dev);
  153. }
  154. *gpuobj_ret = gpuobj;
  155. return 0;
  156. }
  157. int
  158. nouveau_gpuobj_init(struct drm_device *dev)
  159. {
  160. struct drm_nouveau_private *dev_priv = dev->dev_private;
  161. NV_DEBUG(dev, "\n");
  162. INIT_LIST_HEAD(&dev_priv->gpuobj_list);
  163. spin_lock_init(&dev_priv->ramin_lock);
  164. dev_priv->ramin_base = ~0;
  165. return 0;
  166. }
  167. void
  168. nouveau_gpuobj_takedown(struct drm_device *dev)
  169. {
  170. struct drm_nouveau_private *dev_priv = dev->dev_private;
  171. NV_DEBUG(dev, "\n");
  172. BUG_ON(!list_empty(&dev_priv->gpuobj_list));
  173. }
  174. static void
  175. nouveau_gpuobj_del(struct kref *ref)
  176. {
  177. struct nouveau_gpuobj *gpuobj =
  178. container_of(ref, struct nouveau_gpuobj, refcount);
  179. struct drm_device *dev = gpuobj->dev;
  180. struct drm_nouveau_private *dev_priv = dev->dev_private;
  181. struct nouveau_engine *engine = &dev_priv->engine;
  182. int i;
  183. NV_DEBUG(dev, "gpuobj %p\n", gpuobj);
  184. if (gpuobj->im_pramin && (gpuobj->flags & NVOBJ_FLAG_ZERO_FREE)) {
  185. for (i = 0; i < gpuobj->size; i += 4)
  186. nv_wo32(gpuobj, i, 0);
  187. engine->instmem.flush(dev);
  188. }
  189. if (gpuobj->dtor)
  190. gpuobj->dtor(dev, gpuobj);
  191. if (gpuobj->im_backing)
  192. engine->instmem.clear(dev, gpuobj);
  193. spin_lock(&dev_priv->ramin_lock);
  194. if (gpuobj->im_pramin)
  195. drm_mm_put_block(gpuobj->im_pramin);
  196. list_del(&gpuobj->list);
  197. spin_unlock(&dev_priv->ramin_lock);
  198. kfree(gpuobj);
  199. }
  200. void
  201. nouveau_gpuobj_ref(struct nouveau_gpuobj *ref, struct nouveau_gpuobj **ptr)
  202. {
  203. if (ref)
  204. kref_get(&ref->refcount);
  205. if (*ptr)
  206. kref_put(&(*ptr)->refcount, nouveau_gpuobj_del);
  207. *ptr = ref;
  208. }
  209. int
  210. nouveau_gpuobj_new_fake(struct drm_device *dev, u32 pinst, u64 vinst,
  211. u32 size, u32 flags, struct nouveau_gpuobj **pgpuobj)
  212. {
  213. struct drm_nouveau_private *dev_priv = dev->dev_private;
  214. struct nouveau_gpuobj *gpuobj = NULL;
  215. int i;
  216. NV_DEBUG(dev,
  217. "pinst=0x%08x vinst=0x%010llx size=0x%08x flags=0x%08x\n",
  218. pinst, vinst, size, flags);
  219. gpuobj = kzalloc(sizeof(*gpuobj), GFP_KERNEL);
  220. if (!gpuobj)
  221. return -ENOMEM;
  222. NV_DEBUG(dev, "gpuobj %p\n", gpuobj);
  223. gpuobj->dev = dev;
  224. gpuobj->flags = flags;
  225. kref_init(&gpuobj->refcount);
  226. gpuobj->size = size;
  227. gpuobj->pinst = pinst;
  228. gpuobj->cinst = 0xdeadbeef;
  229. gpuobj->vinst = vinst;
  230. if (gpuobj->flags & NVOBJ_FLAG_ZERO_ALLOC) {
  231. for (i = 0; i < gpuobj->size; i += 4)
  232. nv_wo32(gpuobj, i, 0);
  233. dev_priv->engine.instmem.flush(dev);
  234. }
  235. spin_lock(&dev_priv->ramin_lock);
  236. list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list);
  237. spin_unlock(&dev_priv->ramin_lock);
  238. *pgpuobj = gpuobj;
  239. return 0;
  240. }
  241. static uint32_t
  242. nouveau_gpuobj_class_instmem_size(struct drm_device *dev, int class)
  243. {
  244. struct drm_nouveau_private *dev_priv = dev->dev_private;
  245. /*XXX: dodgy hack for now */
  246. if (dev_priv->card_type >= NV_50)
  247. return 24;
  248. if (dev_priv->card_type >= NV_40)
  249. return 32;
  250. return 16;
  251. }
  252. /*
  253. DMA objects are used to reference a piece of memory in the
  254. framebuffer, PCI or AGP address space. Each object is 16 bytes big
  255. and looks as follows:
  256. entry[0]
  257. 11:0 class (seems like I can always use 0 here)
  258. 12 page table present?
  259. 13 page entry linear?
  260. 15:14 access: 0 rw, 1 ro, 2 wo
  261. 17:16 target: 0 NV memory, 1 NV memory tiled, 2 PCI, 3 AGP
  262. 31:20 dma adjust (bits 0-11 of the address)
  263. entry[1]
  264. dma limit (size of transfer)
  265. entry[X]
  266. 1 0 readonly, 1 readwrite
  267. 31:12 dma frame address of the page (bits 12-31 of the address)
  268. entry[N]
  269. page table terminator, same value as the first pte, as does nvidia
  270. rivatv uses 0xffffffff
  271. Non linear page tables need a list of frame addresses afterwards,
  272. the rivatv project has some info on this.
  273. The method below creates a DMA object in instance RAM and returns a handle
  274. to it that can be used to set up context objects.
  275. */
  276. int
  277. nouveau_gpuobj_dma_new(struct nouveau_channel *chan, int class,
  278. uint64_t offset, uint64_t size, int access,
  279. int target, struct nouveau_gpuobj **gpuobj)
  280. {
  281. struct drm_device *dev = chan->dev;
  282. struct drm_nouveau_private *dev_priv = dev->dev_private;
  283. struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem;
  284. int ret;
  285. NV_DEBUG(dev, "ch%d class=0x%04x offset=0x%llx size=0x%llx\n",
  286. chan->id, class, offset, size);
  287. NV_DEBUG(dev, "access=%d target=%d\n", access, target);
  288. switch (target) {
  289. case NV_DMA_TARGET_AGP:
  290. offset += dev_priv->gart_info.aper_base;
  291. break;
  292. default:
  293. break;
  294. }
  295. ret = nouveau_gpuobj_new(dev, chan,
  296. nouveau_gpuobj_class_instmem_size(dev, class),
  297. 16, NVOBJ_FLAG_ZERO_ALLOC |
  298. NVOBJ_FLAG_ZERO_FREE, gpuobj);
  299. if (ret) {
  300. NV_ERROR(dev, "Error creating gpuobj: %d\n", ret);
  301. return ret;
  302. }
  303. if (dev_priv->card_type < NV_50) {
  304. uint32_t frame, adjust, pte_flags = 0;
  305. if (access != NV_DMA_ACCESS_RO)
  306. pte_flags |= (1<<1);
  307. adjust = offset & 0x00000fff;
  308. frame = offset & ~0x00000fff;
  309. nv_wo32(*gpuobj, 0, ((1<<12) | (1<<13) | (adjust << 20) |
  310. (access << 14) | (target << 16) |
  311. class));
  312. nv_wo32(*gpuobj, 4, size - 1);
  313. nv_wo32(*gpuobj, 8, frame | pte_flags);
  314. nv_wo32(*gpuobj, 12, frame | pte_flags);
  315. } else {
  316. uint64_t limit = offset + size - 1;
  317. uint32_t flags0, flags5;
  318. if (target == NV_DMA_TARGET_VIDMEM) {
  319. flags0 = 0x00190000;
  320. flags5 = 0x00010000;
  321. } else {
  322. flags0 = 0x7fc00000;
  323. flags5 = 0x00080000;
  324. }
  325. nv_wo32(*gpuobj, 0, flags0 | class);
  326. nv_wo32(*gpuobj, 4, lower_32_bits(limit));
  327. nv_wo32(*gpuobj, 8, lower_32_bits(offset));
  328. nv_wo32(*gpuobj, 12, ((upper_32_bits(limit) & 0xff) << 24) |
  329. (upper_32_bits(offset) & 0xff));
  330. nv_wo32(*gpuobj, 20, flags5);
  331. }
  332. instmem->flush(dev);
  333. (*gpuobj)->engine = NVOBJ_ENGINE_SW;
  334. (*gpuobj)->class = class;
  335. return 0;
  336. }
  337. int
  338. nouveau_gpuobj_gart_dma_new(struct nouveau_channel *chan,
  339. uint64_t offset, uint64_t size, int access,
  340. struct nouveau_gpuobj **gpuobj,
  341. uint32_t *o_ret)
  342. {
  343. struct drm_device *dev = chan->dev;
  344. struct drm_nouveau_private *dev_priv = dev->dev_private;
  345. int ret;
  346. if (dev_priv->gart_info.type == NOUVEAU_GART_AGP ||
  347. (dev_priv->card_type >= NV_50 &&
  348. dev_priv->gart_info.type == NOUVEAU_GART_SGDMA)) {
  349. ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
  350. offset + dev_priv->vm_gart_base,
  351. size, access, NV_DMA_TARGET_AGP,
  352. gpuobj);
  353. if (o_ret)
  354. *o_ret = 0;
  355. } else
  356. if (dev_priv->gart_info.type == NOUVEAU_GART_SGDMA) {
  357. nouveau_gpuobj_ref(dev_priv->gart_info.sg_ctxdma, gpuobj);
  358. if (offset & ~0xffffffffULL) {
  359. NV_ERROR(dev, "obj offset exceeds 32-bits\n");
  360. return -EINVAL;
  361. }
  362. if (o_ret)
  363. *o_ret = (uint32_t)offset;
  364. ret = (*gpuobj != NULL) ? 0 : -EINVAL;
  365. } else {
  366. NV_ERROR(dev, "Invalid GART type %d\n", dev_priv->gart_info.type);
  367. return -EINVAL;
  368. }
  369. return ret;
  370. }
  371. /* Context objects in the instance RAM have the following structure.
  372. * On NV40 they are 32 byte long, on NV30 and smaller 16 bytes.
  373. NV4 - NV30:
  374. entry[0]
  375. 11:0 class
  376. 12 chroma key enable
  377. 13 user clip enable
  378. 14 swizzle enable
  379. 17:15 patch config:
  380. scrcopy_and, rop_and, blend_and, scrcopy, srccopy_pre, blend_pre
  381. 18 synchronize enable
  382. 19 endian: 1 big, 0 little
  383. 21:20 dither mode
  384. 23 single step enable
  385. 24 patch status: 0 invalid, 1 valid
  386. 25 context_surface 0: 1 valid
  387. 26 context surface 1: 1 valid
  388. 27 context pattern: 1 valid
  389. 28 context rop: 1 valid
  390. 29,30 context beta, beta4
  391. entry[1]
  392. 7:0 mono format
  393. 15:8 color format
  394. 31:16 notify instance address
  395. entry[2]
  396. 15:0 dma 0 instance address
  397. 31:16 dma 1 instance address
  398. entry[3]
  399. dma method traps
  400. NV40:
  401. No idea what the exact format is. Here's what can be deducted:
  402. entry[0]:
  403. 11:0 class (maybe uses more bits here?)
  404. 17 user clip enable
  405. 21:19 patch config
  406. 25 patch status valid ?
  407. entry[1]:
  408. 15:0 DMA notifier (maybe 20:0)
  409. entry[2]:
  410. 15:0 DMA 0 instance (maybe 20:0)
  411. 24 big endian
  412. entry[3]:
  413. 15:0 DMA 1 instance (maybe 20:0)
  414. entry[4]:
  415. entry[5]:
  416. set to 0?
  417. */
  418. int
  419. nouveau_gpuobj_gr_new(struct nouveau_channel *chan, int class,
  420. struct nouveau_gpuobj **gpuobj)
  421. {
  422. struct drm_device *dev = chan->dev;
  423. struct drm_nouveau_private *dev_priv = dev->dev_private;
  424. int ret;
  425. NV_DEBUG(dev, "ch%d class=0x%04x\n", chan->id, class);
  426. ret = nouveau_gpuobj_new(dev, chan,
  427. nouveau_gpuobj_class_instmem_size(dev, class),
  428. 16,
  429. NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE,
  430. gpuobj);
  431. if (ret) {
  432. NV_ERROR(dev, "Error creating gpuobj: %d\n", ret);
  433. return ret;
  434. }
  435. if (dev_priv->card_type >= NV_50) {
  436. nv_wo32(*gpuobj, 0, class);
  437. nv_wo32(*gpuobj, 20, 0x00010000);
  438. } else {
  439. switch (class) {
  440. case NV_CLASS_NULL:
  441. nv_wo32(*gpuobj, 0, 0x00001030);
  442. nv_wo32(*gpuobj, 4, 0xFFFFFFFF);
  443. break;
  444. default:
  445. if (dev_priv->card_type >= NV_40) {
  446. nv_wo32(*gpuobj, 0, class);
  447. #ifdef __BIG_ENDIAN
  448. nv_wo32(*gpuobj, 8, 0x01000000);
  449. #endif
  450. } else {
  451. #ifdef __BIG_ENDIAN
  452. nv_wo32(*gpuobj, 0, class | 0x00080000);
  453. #else
  454. nv_wo32(*gpuobj, 0, class);
  455. #endif
  456. }
  457. }
  458. }
  459. dev_priv->engine.instmem.flush(dev);
  460. (*gpuobj)->engine = NVOBJ_ENGINE_GR;
  461. (*gpuobj)->class = class;
  462. return 0;
  463. }
  464. int
  465. nouveau_gpuobj_sw_new(struct nouveau_channel *chan, int class,
  466. struct nouveau_gpuobj **gpuobj_ret)
  467. {
  468. struct drm_nouveau_private *dev_priv;
  469. struct nouveau_gpuobj *gpuobj;
  470. if (!chan || !gpuobj_ret || *gpuobj_ret != NULL)
  471. return -EINVAL;
  472. dev_priv = chan->dev->dev_private;
  473. gpuobj = kzalloc(sizeof(*gpuobj), GFP_KERNEL);
  474. if (!gpuobj)
  475. return -ENOMEM;
  476. gpuobj->dev = chan->dev;
  477. gpuobj->engine = NVOBJ_ENGINE_SW;
  478. gpuobj->class = class;
  479. kref_init(&gpuobj->refcount);
  480. gpuobj->cinst = 0x40;
  481. spin_lock(&dev_priv->ramin_lock);
  482. list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list);
  483. spin_unlock(&dev_priv->ramin_lock);
  484. *gpuobj_ret = gpuobj;
  485. return 0;
  486. }
  487. static int
  488. nouveau_gpuobj_channel_init_pramin(struct nouveau_channel *chan)
  489. {
  490. struct drm_device *dev = chan->dev;
  491. struct drm_nouveau_private *dev_priv = dev->dev_private;
  492. uint32_t size;
  493. uint32_t base;
  494. int ret;
  495. NV_DEBUG(dev, "ch%d\n", chan->id);
  496. /* Base amount for object storage (4KiB enough?) */
  497. size = 0x1000;
  498. base = 0;
  499. /* PGRAPH context */
  500. size += dev_priv->engine.graph.grctx_size;
  501. if (dev_priv->card_type == NV_50) {
  502. /* Various fixed table thingos */
  503. size += 0x1400; /* mostly unknown stuff */
  504. size += 0x4000; /* vm pd */
  505. base = 0x6000;
  506. /* RAMHT, not sure about setting size yet, 32KiB to be safe */
  507. size += 0x8000;
  508. /* RAMFC */
  509. size += 0x1000;
  510. }
  511. ret = nouveau_gpuobj_new(dev, NULL, size, 0x1000, 0, &chan->ramin);
  512. if (ret) {
  513. NV_ERROR(dev, "Error allocating channel PRAMIN: %d\n", ret);
  514. return ret;
  515. }
  516. ret = drm_mm_init(&chan->ramin_heap, base, size);
  517. if (ret) {
  518. NV_ERROR(dev, "Error creating PRAMIN heap: %d\n", ret);
  519. nouveau_gpuobj_ref(NULL, &chan->ramin);
  520. return ret;
  521. }
  522. return 0;
  523. }
  524. int
  525. nouveau_gpuobj_channel_init(struct nouveau_channel *chan,
  526. uint32_t vram_h, uint32_t tt_h)
  527. {
  528. struct drm_device *dev = chan->dev;
  529. struct drm_nouveau_private *dev_priv = dev->dev_private;
  530. struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem;
  531. struct nouveau_gpuobj *vram = NULL, *tt = NULL;
  532. int ret, i;
  533. NV_DEBUG(dev, "ch%d vram=0x%08x tt=0x%08x\n", chan->id, vram_h, tt_h);
  534. /* Allocate a chunk of memory for per-channel object storage */
  535. ret = nouveau_gpuobj_channel_init_pramin(chan);
  536. if (ret) {
  537. NV_ERROR(dev, "init pramin\n");
  538. return ret;
  539. }
  540. /* NV50 VM
  541. * - Allocate per-channel page-directory
  542. * - Map GART and VRAM into the channel's address space at the
  543. * locations determined during init.
  544. */
  545. if (dev_priv->card_type >= NV_50) {
  546. u32 pgd_offs = (dev_priv->chipset == 0x50) ? 0x1400 : 0x0200;
  547. u64 vm_vinst = chan->ramin->vinst + pgd_offs;
  548. u32 vm_pinst = chan->ramin->pinst;
  549. u32 pde;
  550. if (vm_pinst != ~0)
  551. vm_pinst += pgd_offs;
  552. ret = nouveau_gpuobj_new_fake(dev, vm_pinst, vm_vinst, 0x4000,
  553. 0, &chan->vm_pd);
  554. if (ret)
  555. return ret;
  556. for (i = 0; i < 0x4000; i += 8) {
  557. nv_wo32(chan->vm_pd, i + 0, 0x00000000);
  558. nv_wo32(chan->vm_pd, i + 4, 0xdeadcafe);
  559. }
  560. nouveau_gpuobj_ref(dev_priv->gart_info.sg_ctxdma,
  561. &chan->vm_gart_pt);
  562. pde = (dev_priv->vm_gart_base / (512*1024*1024)) * 8;
  563. nv_wo32(chan->vm_pd, pde + 0, chan->vm_gart_pt->vinst | 3);
  564. nv_wo32(chan->vm_pd, pde + 4, 0x00000000);
  565. pde = (dev_priv->vm_vram_base / (512*1024*1024)) * 8;
  566. for (i = 0; i < dev_priv->vm_vram_pt_nr; i++) {
  567. nouveau_gpuobj_ref(dev_priv->vm_vram_pt[i],
  568. &chan->vm_vram_pt[i]);
  569. nv_wo32(chan->vm_pd, pde + 0,
  570. chan->vm_vram_pt[i]->vinst | 0x61);
  571. nv_wo32(chan->vm_pd, pde + 4, 0x00000000);
  572. pde += 8;
  573. }
  574. instmem->flush(dev);
  575. }
  576. /* RAMHT */
  577. if (dev_priv->card_type < NV_50) {
  578. nouveau_ramht_ref(dev_priv->ramht, &chan->ramht, NULL);
  579. } else {
  580. struct nouveau_gpuobj *ramht = NULL;
  581. ret = nouveau_gpuobj_new(dev, chan, 0x8000, 16,
  582. NVOBJ_FLAG_ZERO_ALLOC, &ramht);
  583. if (ret)
  584. return ret;
  585. ret = nouveau_ramht_new(dev, ramht, &chan->ramht);
  586. nouveau_gpuobj_ref(NULL, &ramht);
  587. if (ret)
  588. return ret;
  589. }
  590. /* VRAM ctxdma */
  591. if (dev_priv->card_type >= NV_50) {
  592. ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
  593. 0, dev_priv->vm_end,
  594. NV_DMA_ACCESS_RW,
  595. NV_DMA_TARGET_AGP, &vram);
  596. if (ret) {
  597. NV_ERROR(dev, "Error creating VRAM ctxdma: %d\n", ret);
  598. return ret;
  599. }
  600. } else {
  601. ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
  602. 0, dev_priv->fb_available_size,
  603. NV_DMA_ACCESS_RW,
  604. NV_DMA_TARGET_VIDMEM, &vram);
  605. if (ret) {
  606. NV_ERROR(dev, "Error creating VRAM ctxdma: %d\n", ret);
  607. return ret;
  608. }
  609. }
  610. ret = nouveau_ramht_insert(chan, vram_h, vram);
  611. nouveau_gpuobj_ref(NULL, &vram);
  612. if (ret) {
  613. NV_ERROR(dev, "Error adding VRAM ctxdma to RAMHT: %d\n", ret);
  614. return ret;
  615. }
  616. /* TT memory ctxdma */
  617. if (dev_priv->card_type >= NV_50) {
  618. ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
  619. 0, dev_priv->vm_end,
  620. NV_DMA_ACCESS_RW,
  621. NV_DMA_TARGET_AGP, &tt);
  622. if (ret) {
  623. NV_ERROR(dev, "Error creating VRAM ctxdma: %d\n", ret);
  624. return ret;
  625. }
  626. } else
  627. if (dev_priv->gart_info.type != NOUVEAU_GART_NONE) {
  628. ret = nouveau_gpuobj_gart_dma_new(chan, 0,
  629. dev_priv->gart_info.aper_size,
  630. NV_DMA_ACCESS_RW, &tt, NULL);
  631. } else {
  632. NV_ERROR(dev, "Invalid GART type %d\n", dev_priv->gart_info.type);
  633. ret = -EINVAL;
  634. }
  635. if (ret) {
  636. NV_ERROR(dev, "Error creating TT ctxdma: %d\n", ret);
  637. return ret;
  638. }
  639. ret = nouveau_ramht_insert(chan, tt_h, tt);
  640. nouveau_gpuobj_ref(NULL, &tt);
  641. if (ret) {
  642. NV_ERROR(dev, "Error adding TT ctxdma to RAMHT: %d\n", ret);
  643. return ret;
  644. }
  645. return 0;
  646. }
  647. void
  648. nouveau_gpuobj_channel_takedown(struct nouveau_channel *chan)
  649. {
  650. struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
  651. struct drm_device *dev = chan->dev;
  652. int i;
  653. NV_DEBUG(dev, "ch%d\n", chan->id);
  654. if (!chan->ramht)
  655. return;
  656. nouveau_ramht_ref(NULL, &chan->ramht, chan);
  657. nouveau_gpuobj_ref(NULL, &chan->vm_pd);
  658. nouveau_gpuobj_ref(NULL, &chan->vm_gart_pt);
  659. for (i = 0; i < dev_priv->vm_vram_pt_nr; i++)
  660. nouveau_gpuobj_ref(NULL, &chan->vm_vram_pt[i]);
  661. if (chan->ramin_heap.free_stack.next)
  662. drm_mm_takedown(&chan->ramin_heap);
  663. nouveau_gpuobj_ref(NULL, &chan->ramin);
  664. }
  665. int
  666. nouveau_gpuobj_suspend(struct drm_device *dev)
  667. {
  668. struct drm_nouveau_private *dev_priv = dev->dev_private;
  669. struct nouveau_gpuobj *gpuobj;
  670. int i;
  671. if (dev_priv->card_type < NV_50) {
  672. dev_priv->susres.ramin_copy = vmalloc(dev_priv->ramin_rsvd_vram);
  673. if (!dev_priv->susres.ramin_copy)
  674. return -ENOMEM;
  675. for (i = 0; i < dev_priv->ramin_rsvd_vram; i += 4)
  676. dev_priv->susres.ramin_copy[i/4] = nv_ri32(dev, i);
  677. return 0;
  678. }
  679. list_for_each_entry(gpuobj, &dev_priv->gpuobj_list, list) {
  680. if (!gpuobj->im_backing)
  681. continue;
  682. gpuobj->im_backing_suspend = vmalloc(gpuobj->size);
  683. if (!gpuobj->im_backing_suspend) {
  684. nouveau_gpuobj_resume(dev);
  685. return -ENOMEM;
  686. }
  687. for (i = 0; i < gpuobj->size; i += 4)
  688. gpuobj->im_backing_suspend[i/4] = nv_ro32(gpuobj, i);
  689. }
  690. return 0;
  691. }
  692. void
  693. nouveau_gpuobj_suspend_cleanup(struct drm_device *dev)
  694. {
  695. struct drm_nouveau_private *dev_priv = dev->dev_private;
  696. struct nouveau_gpuobj *gpuobj;
  697. if (dev_priv->card_type < NV_50) {
  698. vfree(dev_priv->susres.ramin_copy);
  699. dev_priv->susres.ramin_copy = NULL;
  700. return;
  701. }
  702. list_for_each_entry(gpuobj, &dev_priv->gpuobj_list, list) {
  703. if (!gpuobj->im_backing_suspend)
  704. continue;
  705. vfree(gpuobj->im_backing_suspend);
  706. gpuobj->im_backing_suspend = NULL;
  707. }
  708. }
  709. void
  710. nouveau_gpuobj_resume(struct drm_device *dev)
  711. {
  712. struct drm_nouveau_private *dev_priv = dev->dev_private;
  713. struct nouveau_gpuobj *gpuobj;
  714. int i;
  715. if (dev_priv->card_type < NV_50) {
  716. for (i = 0; i < dev_priv->ramin_rsvd_vram; i += 4)
  717. nv_wi32(dev, i, dev_priv->susres.ramin_copy[i/4]);
  718. nouveau_gpuobj_suspend_cleanup(dev);
  719. return;
  720. }
  721. list_for_each_entry(gpuobj, &dev_priv->gpuobj_list, list) {
  722. if (!gpuobj->im_backing_suspend)
  723. continue;
  724. for (i = 0; i < gpuobj->size; i += 4)
  725. nv_wo32(gpuobj, i, gpuobj->im_backing_suspend[i/4]);
  726. dev_priv->engine.instmem.flush(dev);
  727. }
  728. nouveau_gpuobj_suspend_cleanup(dev);
  729. }
  730. int nouveau_ioctl_grobj_alloc(struct drm_device *dev, void *data,
  731. struct drm_file *file_priv)
  732. {
  733. struct drm_nouveau_private *dev_priv = dev->dev_private;
  734. struct drm_nouveau_grobj_alloc *init = data;
  735. struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
  736. struct nouveau_pgraph_object_class *grc;
  737. struct nouveau_gpuobj *gr = NULL;
  738. struct nouveau_channel *chan;
  739. int ret;
  740. NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(init->channel, file_priv, chan);
  741. if (init->handle == ~0)
  742. return -EINVAL;
  743. grc = pgraph->grclass;
  744. while (grc->id) {
  745. if (grc->id == init->class)
  746. break;
  747. grc++;
  748. }
  749. if (!grc->id) {
  750. NV_ERROR(dev, "Illegal object class: 0x%x\n", init->class);
  751. return -EPERM;
  752. }
  753. if (nouveau_ramht_find(chan, init->handle))
  754. return -EEXIST;
  755. if (!grc->software)
  756. ret = nouveau_gpuobj_gr_new(chan, grc->id, &gr);
  757. else
  758. ret = nouveau_gpuobj_sw_new(chan, grc->id, &gr);
  759. if (ret) {
  760. NV_ERROR(dev, "Error creating object: %d (%d/0x%08x)\n",
  761. ret, init->channel, init->handle);
  762. return ret;
  763. }
  764. ret = nouveau_ramht_insert(chan, init->handle, gr);
  765. nouveau_gpuobj_ref(NULL, &gr);
  766. if (ret) {
  767. NV_ERROR(dev, "Error referencing object: %d (%d/0x%08x)\n",
  768. ret, init->channel, init->handle);
  769. return ret;
  770. }
  771. return 0;
  772. }
  773. int nouveau_ioctl_gpuobj_free(struct drm_device *dev, void *data,
  774. struct drm_file *file_priv)
  775. {
  776. struct drm_nouveau_gpuobj_free *objfree = data;
  777. struct nouveau_gpuobj *gpuobj;
  778. struct nouveau_channel *chan;
  779. NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(objfree->channel, file_priv, chan);
  780. gpuobj = nouveau_ramht_find(chan, objfree->handle);
  781. if (!gpuobj)
  782. return -ENOENT;
  783. nouveau_ramht_remove(chan, objfree->handle);
  784. return 0;
  785. }
  786. u32
  787. nv_ro32(struct nouveau_gpuobj *gpuobj, u32 offset)
  788. {
  789. struct drm_nouveau_private *dev_priv = gpuobj->dev->dev_private;
  790. struct drm_device *dev = gpuobj->dev;
  791. if (gpuobj->pinst == ~0 || !dev_priv->ramin_available) {
  792. u64 ptr = gpuobj->vinst + offset;
  793. u32 base = ptr >> 16;
  794. u32 val;
  795. spin_lock(&dev_priv->ramin_lock);
  796. if (dev_priv->ramin_base != base) {
  797. dev_priv->ramin_base = base;
  798. nv_wr32(dev, 0x001700, dev_priv->ramin_base);
  799. }
  800. val = nv_rd32(dev, 0x700000 + (ptr & 0xffff));
  801. spin_unlock(&dev_priv->ramin_lock);
  802. return val;
  803. }
  804. return nv_ri32(dev, gpuobj->pinst + offset);
  805. }
  806. void
  807. nv_wo32(struct nouveau_gpuobj *gpuobj, u32 offset, u32 val)
  808. {
  809. struct drm_nouveau_private *dev_priv = gpuobj->dev->dev_private;
  810. struct drm_device *dev = gpuobj->dev;
  811. if (gpuobj->pinst == ~0 || !dev_priv->ramin_available) {
  812. u64 ptr = gpuobj->vinst + offset;
  813. u32 base = ptr >> 16;
  814. spin_lock(&dev_priv->ramin_lock);
  815. if (dev_priv->ramin_base != base) {
  816. dev_priv->ramin_base = base;
  817. nv_wr32(dev, 0x001700, dev_priv->ramin_base);
  818. }
  819. nv_wr32(dev, 0x700000 + (ptr & 0xffff), val);
  820. spin_unlock(&dev_priv->ramin_lock);
  821. return;
  822. }
  823. nv_wi32(dev, gpuobj->pinst + offset, val);
  824. }