ux500_dma.c 12 KB

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  1. /*
  2. * drivers/usb/musb/ux500_dma.c
  3. *
  4. * U8500 and U5500 DMA support code
  5. *
  6. * Copyright (C) 2009 STMicroelectronics
  7. * Copyright (C) 2011 ST-Ericsson SA
  8. * Authors:
  9. * Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com>
  10. * Praveena Nadahally <praveen.nadahally@stericsson.com>
  11. * Rajaram Regupathy <ragupathy.rajaram@stericsson.com>
  12. *
  13. * This program is free software: you can redistribute it and/or modify
  14. * it under the terms of the GNU General Public License as published by
  15. * the Free Software Foundation, either version 2 of the License, or
  16. * (at your option) any later version.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. *
  23. * You should have received a copy of the GNU General Public License
  24. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  25. */
  26. #include <linux/device.h>
  27. #include <linux/interrupt.h>
  28. #include <linux/platform_device.h>
  29. #include <linux/dma-mapping.h>
  30. #include <linux/dmaengine.h>
  31. #include <linux/pfn.h>
  32. #include <mach/usb.h>
  33. #include "musb_core.h"
  34. struct ux500_dma_channel {
  35. struct dma_channel channel;
  36. struct ux500_dma_controller *controller;
  37. struct musb_hw_ep *hw_ep;
  38. struct work_struct channel_work;
  39. struct dma_chan *dma_chan;
  40. unsigned int cur_len;
  41. dma_cookie_t cookie;
  42. u8 ch_num;
  43. u8 is_tx;
  44. u8 is_allocated;
  45. };
  46. struct ux500_dma_controller {
  47. struct dma_controller controller;
  48. struct ux500_dma_channel rx_channel[UX500_MUSB_DMA_NUM_RX_CHANNELS];
  49. struct ux500_dma_channel tx_channel[UX500_MUSB_DMA_NUM_TX_CHANNELS];
  50. u32 num_rx_channels;
  51. u32 num_tx_channels;
  52. void *private_data;
  53. dma_addr_t phy_base;
  54. };
  55. /* Work function invoked from DMA callback to handle tx transfers. */
  56. static void ux500_tx_work(struct work_struct *data)
  57. {
  58. struct ux500_dma_channel *ux500_channel = container_of(data,
  59. struct ux500_dma_channel, channel_work);
  60. struct musb_hw_ep *hw_ep = ux500_channel->hw_ep;
  61. struct musb *musb = hw_ep->musb;
  62. unsigned long flags;
  63. dev_dbg(musb->controller, "DMA tx transfer done on hw_ep=%d\n",
  64. hw_ep->epnum);
  65. spin_lock_irqsave(&musb->lock, flags);
  66. ux500_channel->channel.actual_len = ux500_channel->cur_len;
  67. ux500_channel->channel.status = MUSB_DMA_STATUS_FREE;
  68. musb_dma_completion(musb, hw_ep->epnum,
  69. ux500_channel->is_tx);
  70. spin_unlock_irqrestore(&musb->lock, flags);
  71. }
  72. /* Work function invoked from DMA callback to handle rx transfers. */
  73. static void ux500_rx_work(struct work_struct *data)
  74. {
  75. struct ux500_dma_channel *ux500_channel = container_of(data,
  76. struct ux500_dma_channel, channel_work);
  77. struct musb_hw_ep *hw_ep = ux500_channel->hw_ep;
  78. struct musb *musb = hw_ep->musb;
  79. unsigned long flags;
  80. dev_dbg(musb->controller, "DMA rx transfer done on hw_ep=%d\n",
  81. hw_ep->epnum);
  82. spin_lock_irqsave(&musb->lock, flags);
  83. ux500_channel->channel.actual_len = ux500_channel->cur_len;
  84. ux500_channel->channel.status = MUSB_DMA_STATUS_FREE;
  85. musb_dma_completion(musb, hw_ep->epnum,
  86. ux500_channel->is_tx);
  87. spin_unlock_irqrestore(&musb->lock, flags);
  88. }
  89. void ux500_dma_callback(void *private_data)
  90. {
  91. struct dma_channel *channel = (struct dma_channel *)private_data;
  92. struct ux500_dma_channel *ux500_channel = channel->private_data;
  93. schedule_work(&ux500_channel->channel_work);
  94. }
  95. static bool ux500_configure_channel(struct dma_channel *channel,
  96. u16 packet_sz, u8 mode,
  97. dma_addr_t dma_addr, u32 len)
  98. {
  99. struct ux500_dma_channel *ux500_channel = channel->private_data;
  100. struct musb_hw_ep *hw_ep = ux500_channel->hw_ep;
  101. struct dma_chan *dma_chan = ux500_channel->dma_chan;
  102. struct dma_async_tx_descriptor *dma_desc;
  103. enum dma_data_direction direction;
  104. struct scatterlist sg;
  105. struct dma_slave_config slave_conf;
  106. enum dma_slave_buswidth addr_width;
  107. dma_addr_t usb_fifo_addr = (MUSB_FIFO_OFFSET(hw_ep->epnum) +
  108. ux500_channel->controller->phy_base);
  109. struct musb *musb = ux500_channel->controller->private_data;
  110. dev_dbg(musb->controller,
  111. "packet_sz=%d, mode=%d, dma_addr=0x%x, len=%d is_tx=%d\n",
  112. packet_sz, mode, dma_addr, len, ux500_channel->is_tx);
  113. ux500_channel->cur_len = len;
  114. sg_init_table(&sg, 1);
  115. sg_set_page(&sg, pfn_to_page(PFN_DOWN(dma_addr)), len,
  116. offset_in_page(dma_addr));
  117. sg_dma_address(&sg) = dma_addr;
  118. sg_dma_len(&sg) = len;
  119. direction = ux500_channel->is_tx ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
  120. addr_width = (len & 0x3) ? DMA_SLAVE_BUSWIDTH_1_BYTE :
  121. DMA_SLAVE_BUSWIDTH_4_BYTES;
  122. slave_conf.direction = direction;
  123. slave_conf.src_addr = usb_fifo_addr;
  124. slave_conf.src_addr_width = addr_width;
  125. slave_conf.src_maxburst = 16;
  126. slave_conf.dst_addr = usb_fifo_addr;
  127. slave_conf.dst_addr_width = addr_width;
  128. slave_conf.dst_maxburst = 16;
  129. dma_chan->device->device_control(dma_chan, DMA_SLAVE_CONFIG,
  130. (unsigned long) &slave_conf);
  131. dma_desc = dma_chan->device->
  132. device_prep_slave_sg(dma_chan, &sg, 1, direction,
  133. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  134. if (!dma_desc)
  135. return false;
  136. dma_desc->callback = ux500_dma_callback;
  137. dma_desc->callback_param = channel;
  138. ux500_channel->cookie = dma_desc->tx_submit(dma_desc);
  139. dma_async_issue_pending(dma_chan);
  140. return true;
  141. }
  142. static struct dma_channel *ux500_dma_channel_allocate(struct dma_controller *c,
  143. struct musb_hw_ep *hw_ep, u8 is_tx)
  144. {
  145. struct ux500_dma_controller *controller = container_of(c,
  146. struct ux500_dma_controller, controller);
  147. struct ux500_dma_channel *ux500_channel = NULL;
  148. struct musb *musb = controller->private_data;
  149. u8 ch_num = hw_ep->epnum - 1;
  150. u32 max_ch;
  151. /* Max 8 DMA channels (0 - 7). Each DMA channel can only be allocated
  152. * to specified hw_ep. For example DMA channel 0 can only be allocated
  153. * to hw_ep 1 and 9.
  154. */
  155. if (ch_num > 7)
  156. ch_num -= 8;
  157. max_ch = is_tx ? controller->num_tx_channels :
  158. controller->num_rx_channels;
  159. if (ch_num >= max_ch)
  160. return NULL;
  161. ux500_channel = is_tx ? &(controller->tx_channel[ch_num]) :
  162. &(controller->rx_channel[ch_num]) ;
  163. /* Check if channel is already used. */
  164. if (ux500_channel->is_allocated)
  165. return NULL;
  166. ux500_channel->hw_ep = hw_ep;
  167. ux500_channel->is_allocated = 1;
  168. dev_dbg(musb->controller, "hw_ep=%d, is_tx=0x%x, channel=%d\n",
  169. hw_ep->epnum, is_tx, ch_num);
  170. return &(ux500_channel->channel);
  171. }
  172. static void ux500_dma_channel_release(struct dma_channel *channel)
  173. {
  174. struct ux500_dma_channel *ux500_channel = channel->private_data;
  175. struct musb *musb = ux500_channel->controller->private_data;
  176. dev_dbg(musb->controller, "channel=%d\n", ux500_channel->ch_num);
  177. if (ux500_channel->is_allocated) {
  178. ux500_channel->is_allocated = 0;
  179. channel->status = MUSB_DMA_STATUS_FREE;
  180. channel->actual_len = 0;
  181. }
  182. }
  183. static int ux500_dma_is_compatible(struct dma_channel *channel,
  184. u16 maxpacket, void *buf, u32 length)
  185. {
  186. if ((maxpacket & 0x3) ||
  187. ((int)buf & 0x3) ||
  188. (length < 512) ||
  189. (length & 0x3))
  190. return false;
  191. else
  192. return true;
  193. }
  194. static int ux500_dma_channel_program(struct dma_channel *channel,
  195. u16 packet_sz, u8 mode,
  196. dma_addr_t dma_addr, u32 len)
  197. {
  198. int ret;
  199. BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
  200. channel->status == MUSB_DMA_STATUS_BUSY);
  201. if (!ux500_dma_is_compatible(channel, packet_sz, (void *)dma_addr, len))
  202. return false;
  203. channel->status = MUSB_DMA_STATUS_BUSY;
  204. channel->actual_len = 0;
  205. ret = ux500_configure_channel(channel, packet_sz, mode, dma_addr, len);
  206. if (!ret)
  207. channel->status = MUSB_DMA_STATUS_FREE;
  208. return ret;
  209. }
  210. static int ux500_dma_channel_abort(struct dma_channel *channel)
  211. {
  212. struct ux500_dma_channel *ux500_channel = channel->private_data;
  213. struct ux500_dma_controller *controller = ux500_channel->controller;
  214. struct musb *musb = controller->private_data;
  215. void __iomem *epio = musb->endpoints[ux500_channel->hw_ep->epnum].regs;
  216. u16 csr;
  217. dev_dbg(musb->controller, "channel=%d, is_tx=%d\n",
  218. ux500_channel->ch_num, ux500_channel->is_tx);
  219. if (channel->status == MUSB_DMA_STATUS_BUSY) {
  220. if (ux500_channel->is_tx) {
  221. csr = musb_readw(epio, MUSB_TXCSR);
  222. csr &= ~(MUSB_TXCSR_AUTOSET |
  223. MUSB_TXCSR_DMAENAB |
  224. MUSB_TXCSR_DMAMODE);
  225. musb_writew(epio, MUSB_TXCSR, csr);
  226. } else {
  227. csr = musb_readw(epio, MUSB_RXCSR);
  228. csr &= ~(MUSB_RXCSR_AUTOCLEAR |
  229. MUSB_RXCSR_DMAENAB |
  230. MUSB_RXCSR_DMAMODE);
  231. musb_writew(epio, MUSB_RXCSR, csr);
  232. }
  233. ux500_channel->dma_chan->device->
  234. device_control(ux500_channel->dma_chan,
  235. DMA_TERMINATE_ALL, 0);
  236. channel->status = MUSB_DMA_STATUS_FREE;
  237. }
  238. return 0;
  239. }
  240. static int ux500_dma_controller_stop(struct dma_controller *c)
  241. {
  242. struct ux500_dma_controller *controller = container_of(c,
  243. struct ux500_dma_controller, controller);
  244. struct ux500_dma_channel *ux500_channel;
  245. struct dma_channel *channel;
  246. u8 ch_num;
  247. for (ch_num = 0; ch_num < controller->num_rx_channels; ch_num++) {
  248. channel = &controller->rx_channel[ch_num].channel;
  249. ux500_channel = channel->private_data;
  250. ux500_dma_channel_release(channel);
  251. if (ux500_channel->dma_chan)
  252. dma_release_channel(ux500_channel->dma_chan);
  253. }
  254. for (ch_num = 0; ch_num < controller->num_tx_channels; ch_num++) {
  255. channel = &controller->tx_channel[ch_num].channel;
  256. ux500_channel = channel->private_data;
  257. ux500_dma_channel_release(channel);
  258. if (ux500_channel->dma_chan)
  259. dma_release_channel(ux500_channel->dma_chan);
  260. }
  261. return 0;
  262. }
  263. static int ux500_dma_controller_start(struct dma_controller *c)
  264. {
  265. struct ux500_dma_controller *controller = container_of(c,
  266. struct ux500_dma_controller, controller);
  267. struct ux500_dma_channel *ux500_channel = NULL;
  268. struct musb *musb = controller->private_data;
  269. struct device *dev = musb->controller;
  270. struct musb_hdrc_platform_data *plat = dev->platform_data;
  271. struct ux500_musb_board_data *data = plat->board_data;
  272. struct dma_channel *dma_channel = NULL;
  273. u32 ch_num;
  274. u8 dir;
  275. u8 is_tx = 0;
  276. void **param_array;
  277. struct ux500_dma_channel *channel_array;
  278. u32 ch_count;
  279. void (*musb_channel_work)(struct work_struct *);
  280. dma_cap_mask_t mask;
  281. if ((data->num_rx_channels > UX500_MUSB_DMA_NUM_RX_CHANNELS) ||
  282. (data->num_tx_channels > UX500_MUSB_DMA_NUM_TX_CHANNELS))
  283. return -EINVAL;
  284. controller->num_rx_channels = data->num_rx_channels;
  285. controller->num_tx_channels = data->num_tx_channels;
  286. dma_cap_zero(mask);
  287. dma_cap_set(DMA_SLAVE, mask);
  288. /* Prepare the loop for RX channels */
  289. channel_array = controller->rx_channel;
  290. ch_count = data->num_rx_channels;
  291. param_array = data->dma_rx_param_array;
  292. musb_channel_work = ux500_rx_work;
  293. for (dir = 0; dir < 2; dir++) {
  294. for (ch_num = 0; ch_num < ch_count; ch_num++) {
  295. ux500_channel = &channel_array[ch_num];
  296. ux500_channel->controller = controller;
  297. ux500_channel->ch_num = ch_num;
  298. ux500_channel->is_tx = is_tx;
  299. dma_channel = &(ux500_channel->channel);
  300. dma_channel->private_data = ux500_channel;
  301. dma_channel->status = MUSB_DMA_STATUS_FREE;
  302. dma_channel->max_len = SZ_16M;
  303. ux500_channel->dma_chan = dma_request_channel(mask,
  304. data->dma_filter,
  305. param_array[ch_num]);
  306. if (!ux500_channel->dma_chan) {
  307. ERR("Dma pipe allocation error dir=%d ch=%d\n",
  308. dir, ch_num);
  309. /* Release already allocated channels */
  310. ux500_dma_controller_stop(c);
  311. return -EBUSY;
  312. }
  313. INIT_WORK(&ux500_channel->channel_work,
  314. musb_channel_work);
  315. }
  316. /* Prepare the loop for TX channels */
  317. channel_array = controller->tx_channel;
  318. ch_count = data->num_tx_channels;
  319. param_array = data->dma_tx_param_array;
  320. musb_channel_work = ux500_tx_work;
  321. is_tx = 1;
  322. }
  323. return 0;
  324. }
  325. void dma_controller_destroy(struct dma_controller *c)
  326. {
  327. struct ux500_dma_controller *controller = container_of(c,
  328. struct ux500_dma_controller, controller);
  329. kfree(controller);
  330. }
  331. struct dma_controller *__init
  332. dma_controller_create(struct musb *musb, void __iomem *base)
  333. {
  334. struct ux500_dma_controller *controller;
  335. struct platform_device *pdev = to_platform_device(musb->controller);
  336. struct resource *iomem;
  337. controller = kzalloc(sizeof(*controller), GFP_KERNEL);
  338. if (!controller)
  339. return NULL;
  340. controller->private_data = musb;
  341. /* Save physical address for DMA controller. */
  342. iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  343. controller->phy_base = (dma_addr_t) iomem->start;
  344. controller->controller.start = ux500_dma_controller_start;
  345. controller->controller.stop = ux500_dma_controller_stop;
  346. controller->controller.channel_alloc = ux500_dma_channel_allocate;
  347. controller->controller.channel_release = ux500_dma_channel_release;
  348. controller->controller.channel_program = ux500_dma_channel_program;
  349. controller->controller.channel_abort = ux500_dma_channel_abort;
  350. controller->controller.is_compatible = ux500_dma_is_compatible;
  351. return &controller->controller;
  352. }