qla_mr.c 93 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2013 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include <linux/delay.h>
  9. #include <linux/pci.h>
  10. #include <linux/ratelimit.h>
  11. #include <linux/vmalloc.h>
  12. #include <scsi/scsi_tcq.h>
  13. #include <linux/utsname.h>
  14. /* QLAFX00 specific Mailbox implementation functions */
  15. /*
  16. * qlafx00_mailbox_command
  17. * Issue mailbox command and waits for completion.
  18. *
  19. * Input:
  20. * ha = adapter block pointer.
  21. * mcp = driver internal mbx struct pointer.
  22. *
  23. * Output:
  24. * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data.
  25. *
  26. * Returns:
  27. * 0 : QLA_SUCCESS = cmd performed success
  28. * 1 : QLA_FUNCTION_FAILED (error encountered)
  29. * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered)
  30. *
  31. * Context:
  32. * Kernel context.
  33. */
  34. static int
  35. qlafx00_mailbox_command(scsi_qla_host_t *vha, struct mbx_cmd_32 *mcp)
  36. {
  37. int rval;
  38. unsigned long flags = 0;
  39. device_reg_t __iomem *reg;
  40. uint8_t abort_active;
  41. uint8_t io_lock_on;
  42. uint16_t command = 0;
  43. uint32_t *iptr;
  44. uint32_t __iomem *optr;
  45. uint32_t cnt;
  46. uint32_t mboxes;
  47. unsigned long wait_time;
  48. struct qla_hw_data *ha = vha->hw;
  49. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  50. if (ha->pdev->error_state > pci_channel_io_frozen) {
  51. ql_log(ql_log_warn, vha, 0x115c,
  52. "error_state is greater than pci_channel_io_frozen, "
  53. "exiting.\n");
  54. return QLA_FUNCTION_TIMEOUT;
  55. }
  56. if (vha->device_flags & DFLG_DEV_FAILED) {
  57. ql_log(ql_log_warn, vha, 0x115f,
  58. "Device in failed state, exiting.\n");
  59. return QLA_FUNCTION_TIMEOUT;
  60. }
  61. reg = ha->iobase;
  62. io_lock_on = base_vha->flags.init_done;
  63. rval = QLA_SUCCESS;
  64. abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  65. if (ha->flags.pci_channel_io_perm_failure) {
  66. ql_log(ql_log_warn, vha, 0x1175,
  67. "Perm failure on EEH timeout MBX, exiting.\n");
  68. return QLA_FUNCTION_TIMEOUT;
  69. }
  70. if (ha->flags.isp82xx_fw_hung) {
  71. /* Setting Link-Down error */
  72. mcp->mb[0] = MBS_LINK_DOWN_ERROR;
  73. ql_log(ql_log_warn, vha, 0x1176,
  74. "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
  75. rval = QLA_FUNCTION_FAILED;
  76. goto premature_exit;
  77. }
  78. /*
  79. * Wait for active mailbox commands to finish by waiting at most tov
  80. * seconds. This is to serialize actual issuing of mailbox cmds during
  81. * non ISP abort time.
  82. */
  83. if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) {
  84. /* Timeout occurred. Return error. */
  85. ql_log(ql_log_warn, vha, 0x1177,
  86. "Cmd access timeout, cmd=0x%x, Exiting.\n",
  87. mcp->mb[0]);
  88. return QLA_FUNCTION_TIMEOUT;
  89. }
  90. ha->flags.mbox_busy = 1;
  91. /* Save mailbox command for debug */
  92. ha->mcp32 = mcp;
  93. ql_dbg(ql_dbg_mbx, vha, 0x1178,
  94. "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]);
  95. spin_lock_irqsave(&ha->hardware_lock, flags);
  96. /* Load mailbox registers. */
  97. optr = (uint32_t __iomem *)&reg->ispfx00.mailbox0;
  98. iptr = mcp->mb;
  99. command = mcp->mb[0];
  100. mboxes = mcp->out_mb;
  101. for (cnt = 0; cnt < ha->mbx_count; cnt++) {
  102. if (mboxes & BIT_0)
  103. WRT_REG_DWORD(optr, *iptr);
  104. mboxes >>= 1;
  105. optr++;
  106. iptr++;
  107. }
  108. /* Issue set host interrupt command to send cmd out. */
  109. ha->flags.mbox_int = 0;
  110. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  111. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1172,
  112. (uint8_t *)mcp->mb, 16);
  113. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1173,
  114. ((uint8_t *)mcp->mb + 0x10), 16);
  115. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1174,
  116. ((uint8_t *)mcp->mb + 0x20), 8);
  117. /* Unlock mbx registers and wait for interrupt */
  118. ql_dbg(ql_dbg_mbx, vha, 0x1179,
  119. "Going to unlock irq & waiting for interrupts. "
  120. "jiffies=%lx.\n", jiffies);
  121. /* Wait for mbx cmd completion until timeout */
  122. if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
  123. set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
  124. QLAFX00_SET_HST_INTR(ha, ha->mbx_intr_code);
  125. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  126. wait_for_completion_timeout(&ha->mbx_intr_comp, mcp->tov * HZ);
  127. } else {
  128. ql_dbg(ql_dbg_mbx, vha, 0x112c,
  129. "Cmd=%x Polling Mode.\n", command);
  130. QLAFX00_SET_HST_INTR(ha, ha->mbx_intr_code);
  131. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  132. wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */
  133. while (!ha->flags.mbox_int) {
  134. if (time_after(jiffies, wait_time))
  135. break;
  136. /* Check for pending interrupts. */
  137. qla2x00_poll(ha->rsp_q_map[0]);
  138. if (!ha->flags.mbox_int &&
  139. !(IS_QLA2200(ha) &&
  140. command == MBC_LOAD_RISC_RAM_EXTENDED))
  141. usleep_range(10000, 11000);
  142. } /* while */
  143. ql_dbg(ql_dbg_mbx, vha, 0x112d,
  144. "Waited %d sec.\n",
  145. (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
  146. }
  147. /* Check whether we timed out */
  148. if (ha->flags.mbox_int) {
  149. uint32_t *iptr2;
  150. ql_dbg(ql_dbg_mbx, vha, 0x112e,
  151. "Cmd=%x completed.\n", command);
  152. /* Got interrupt. Clear the flag. */
  153. ha->flags.mbox_int = 0;
  154. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  155. if (ha->mailbox_out32[0] != MBS_COMMAND_COMPLETE)
  156. rval = QLA_FUNCTION_FAILED;
  157. /* Load return mailbox registers. */
  158. iptr2 = mcp->mb;
  159. iptr = (uint32_t *)&ha->mailbox_out32[0];
  160. mboxes = mcp->in_mb;
  161. for (cnt = 0; cnt < ha->mbx_count; cnt++) {
  162. if (mboxes & BIT_0)
  163. *iptr2 = *iptr;
  164. mboxes >>= 1;
  165. iptr2++;
  166. iptr++;
  167. }
  168. } else {
  169. rval = QLA_FUNCTION_TIMEOUT;
  170. }
  171. ha->flags.mbox_busy = 0;
  172. /* Clean up */
  173. ha->mcp32 = NULL;
  174. if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) {
  175. ql_dbg(ql_dbg_mbx, vha, 0x113a,
  176. "checking for additional resp interrupt.\n");
  177. /* polling mode for non isp_abort commands. */
  178. qla2x00_poll(ha->rsp_q_map[0]);
  179. }
  180. if (rval == QLA_FUNCTION_TIMEOUT &&
  181. mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) {
  182. if (!io_lock_on || (mcp->flags & IOCTL_CMD) ||
  183. ha->flags.eeh_busy) {
  184. /* not in dpc. schedule it for dpc to take over. */
  185. ql_dbg(ql_dbg_mbx, vha, 0x115d,
  186. "Timeout, schedule isp_abort_needed.\n");
  187. if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
  188. !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
  189. !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  190. ql_log(ql_log_info, base_vha, 0x115e,
  191. "Mailbox cmd timeout occurred, cmd=0x%x, "
  192. "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP "
  193. "abort.\n", command, mcp->mb[0],
  194. ha->flags.eeh_busy);
  195. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  196. qla2xxx_wake_dpc(vha);
  197. }
  198. } else if (!abort_active) {
  199. /* call abort directly since we are in the DPC thread */
  200. ql_dbg(ql_dbg_mbx, vha, 0x1160,
  201. "Timeout, calling abort_isp.\n");
  202. if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
  203. !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
  204. !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  205. ql_log(ql_log_info, base_vha, 0x1161,
  206. "Mailbox cmd timeout occurred, cmd=0x%x, "
  207. "mb[0]=0x%x. Scheduling ISP abort ",
  208. command, mcp->mb[0]);
  209. set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
  210. clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  211. if (ha->isp_ops->abort_isp(vha)) {
  212. /* Failed. retry later. */
  213. set_bit(ISP_ABORT_NEEDED,
  214. &vha->dpc_flags);
  215. }
  216. clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
  217. ql_dbg(ql_dbg_mbx, vha, 0x1162,
  218. "Finished abort_isp.\n");
  219. }
  220. }
  221. }
  222. premature_exit:
  223. /* Allow next mbx cmd to come in. */
  224. complete(&ha->mbx_cmd_comp);
  225. if (rval) {
  226. ql_log(ql_log_warn, base_vha, 0x1163,
  227. "**** Failed mbx[0]=%x, mb[1]=%x, mb[2]=%x, "
  228. "mb[3]=%x, cmd=%x ****.\n",
  229. mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], command);
  230. } else {
  231. ql_dbg(ql_dbg_mbx, base_vha, 0x1164, "Done %s.\n", __func__);
  232. }
  233. return rval;
  234. }
  235. /*
  236. * qlafx00_driver_shutdown
  237. * Indicate a driver shutdown to firmware.
  238. *
  239. * Input:
  240. * ha = adapter block pointer.
  241. *
  242. * Returns:
  243. * local function return status code.
  244. *
  245. * Context:
  246. * Kernel context.
  247. */
  248. int
  249. qlafx00_driver_shutdown(scsi_qla_host_t *vha, int tmo)
  250. {
  251. int rval;
  252. struct mbx_cmd_32 mc;
  253. struct mbx_cmd_32 *mcp = &mc;
  254. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1166,
  255. "Entered %s.\n", __func__);
  256. mcp->mb[0] = MBC_MR_DRV_SHUTDOWN;
  257. mcp->out_mb = MBX_0;
  258. mcp->in_mb = MBX_0;
  259. if (tmo)
  260. mcp->tov = tmo;
  261. else
  262. mcp->tov = MBX_TOV_SECONDS;
  263. mcp->flags = 0;
  264. rval = qlafx00_mailbox_command(vha, mcp);
  265. if (rval != QLA_SUCCESS) {
  266. ql_dbg(ql_dbg_mbx, vha, 0x1167,
  267. "Failed=%x.\n", rval);
  268. } else {
  269. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1168,
  270. "Done %s.\n", __func__);
  271. }
  272. return rval;
  273. }
  274. /*
  275. * qlafx00_get_firmware_state
  276. * Get adapter firmware state.
  277. *
  278. * Input:
  279. * ha = adapter block pointer.
  280. * TARGET_QUEUE_LOCK must be released.
  281. * ADAPTER_STATE_LOCK must be released.
  282. *
  283. * Returns:
  284. * qla7xxx local function return status code.
  285. *
  286. * Context:
  287. * Kernel context.
  288. */
  289. static int
  290. qlafx00_get_firmware_state(scsi_qla_host_t *vha, uint32_t *states)
  291. {
  292. int rval;
  293. struct mbx_cmd_32 mc;
  294. struct mbx_cmd_32 *mcp = &mc;
  295. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1169,
  296. "Entered %s.\n", __func__);
  297. mcp->mb[0] = MBC_GET_FIRMWARE_STATE;
  298. mcp->out_mb = MBX_0;
  299. mcp->in_mb = MBX_1|MBX_0;
  300. mcp->tov = MBX_TOV_SECONDS;
  301. mcp->flags = 0;
  302. rval = qlafx00_mailbox_command(vha, mcp);
  303. /* Return firmware states. */
  304. states[0] = mcp->mb[1];
  305. if (rval != QLA_SUCCESS) {
  306. ql_dbg(ql_dbg_mbx, vha, 0x116a,
  307. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  308. } else {
  309. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116b,
  310. "Done %s.\n", __func__);
  311. }
  312. return rval;
  313. }
  314. /*
  315. * qlafx00_init_firmware
  316. * Initialize adapter firmware.
  317. *
  318. * Input:
  319. * ha = adapter block pointer.
  320. * dptr = Initialization control block pointer.
  321. * size = size of initialization control block.
  322. * TARGET_QUEUE_LOCK must be released.
  323. * ADAPTER_STATE_LOCK must be released.
  324. *
  325. * Returns:
  326. * qlafx00 local function return status code.
  327. *
  328. * Context:
  329. * Kernel context.
  330. */
  331. int
  332. qlafx00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
  333. {
  334. int rval;
  335. struct mbx_cmd_32 mc;
  336. struct mbx_cmd_32 *mcp = &mc;
  337. struct qla_hw_data *ha = vha->hw;
  338. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116c,
  339. "Entered %s.\n", __func__);
  340. mcp->mb[0] = MBC_INITIALIZE_FIRMWARE;
  341. mcp->mb[1] = 0;
  342. mcp->mb[2] = MSD(ha->init_cb_dma);
  343. mcp->mb[3] = LSD(ha->init_cb_dma);
  344. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  345. mcp->in_mb = MBX_0;
  346. mcp->buf_size = size;
  347. mcp->flags = MBX_DMA_OUT;
  348. mcp->tov = MBX_TOV_SECONDS;
  349. rval = qlafx00_mailbox_command(vha, mcp);
  350. if (rval != QLA_SUCCESS) {
  351. ql_dbg(ql_dbg_mbx, vha, 0x116d,
  352. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  353. } else {
  354. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116e,
  355. "Done %s.\n", __func__);
  356. }
  357. return rval;
  358. }
  359. /*
  360. * qlafx00_mbx_reg_test
  361. */
  362. static int
  363. qlafx00_mbx_reg_test(scsi_qla_host_t *vha)
  364. {
  365. int rval;
  366. struct mbx_cmd_32 mc;
  367. struct mbx_cmd_32 *mcp = &mc;
  368. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116f,
  369. "Entered %s.\n", __func__);
  370. mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST;
  371. mcp->mb[1] = 0xAAAA;
  372. mcp->mb[2] = 0x5555;
  373. mcp->mb[3] = 0xAA55;
  374. mcp->mb[4] = 0x55AA;
  375. mcp->mb[5] = 0xA5A5;
  376. mcp->mb[6] = 0x5A5A;
  377. mcp->mb[7] = 0x2525;
  378. mcp->mb[8] = 0xBBBB;
  379. mcp->mb[9] = 0x6666;
  380. mcp->mb[10] = 0xBB66;
  381. mcp->mb[11] = 0x66BB;
  382. mcp->mb[12] = 0xB6B6;
  383. mcp->mb[13] = 0x6B6B;
  384. mcp->mb[14] = 0x3636;
  385. mcp->mb[15] = 0xCCCC;
  386. mcp->out_mb = MBX_15|MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
  387. MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  388. mcp->in_mb = MBX_15|MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
  389. MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  390. mcp->buf_size = 0;
  391. mcp->flags = MBX_DMA_OUT;
  392. mcp->tov = MBX_TOV_SECONDS;
  393. rval = qlafx00_mailbox_command(vha, mcp);
  394. if (rval == QLA_SUCCESS) {
  395. if (mcp->mb[17] != 0xAAAA || mcp->mb[18] != 0x5555 ||
  396. mcp->mb[19] != 0xAA55 || mcp->mb[20] != 0x55AA)
  397. rval = QLA_FUNCTION_FAILED;
  398. if (mcp->mb[21] != 0xA5A5 || mcp->mb[22] != 0x5A5A ||
  399. mcp->mb[23] != 0x2525 || mcp->mb[24] != 0xBBBB)
  400. rval = QLA_FUNCTION_FAILED;
  401. if (mcp->mb[25] != 0x6666 || mcp->mb[26] != 0xBB66 ||
  402. mcp->mb[27] != 0x66BB || mcp->mb[28] != 0xB6B6)
  403. rval = QLA_FUNCTION_FAILED;
  404. if (mcp->mb[29] != 0x6B6B || mcp->mb[30] != 0x3636 ||
  405. mcp->mb[31] != 0xCCCC)
  406. rval = QLA_FUNCTION_FAILED;
  407. }
  408. if (rval != QLA_SUCCESS) {
  409. ql_dbg(ql_dbg_mbx, vha, 0x1170,
  410. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  411. } else {
  412. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1171,
  413. "Done %s.\n", __func__);
  414. }
  415. return rval;
  416. }
  417. /**
  418. * qlafx00_pci_config() - Setup ISPFx00 PCI configuration registers.
  419. * @ha: HA context
  420. *
  421. * Returns 0 on success.
  422. */
  423. int
  424. qlafx00_pci_config(scsi_qla_host_t *vha)
  425. {
  426. uint16_t w;
  427. struct qla_hw_data *ha = vha->hw;
  428. pci_set_master(ha->pdev);
  429. pci_try_set_mwi(ha->pdev);
  430. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  431. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  432. w &= ~PCI_COMMAND_INTX_DISABLE;
  433. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  434. /* PCIe -- adjust Maximum Read Request Size (2048). */
  435. if (pci_find_capability(ha->pdev, PCI_CAP_ID_EXP))
  436. pcie_set_readrq(ha->pdev, 2048);
  437. ha->chip_revision = ha->pdev->revision;
  438. return QLA_SUCCESS;
  439. }
  440. /**
  441. * qlafx00_warm_reset() - Perform warm reset of iSA(CPUs being reset on SOC).
  442. * @ha: HA context
  443. *
  444. */
  445. static inline void
  446. qlafx00_soc_cpu_reset(scsi_qla_host_t *vha)
  447. {
  448. unsigned long flags = 0;
  449. struct qla_hw_data *ha = vha->hw;
  450. int i, core;
  451. uint32_t cnt;
  452. /* Set all 4 cores in reset */
  453. for (i = 0; i < 4; i++) {
  454. QLAFX00_SET_HBA_SOC_REG(ha,
  455. (SOC_SW_RST_CONTROL_REG_CORE0 + 8*i), (0xF01));
  456. }
  457. /* Set all 4 core Clock gating control */
  458. for (i = 0; i < 4; i++) {
  459. QLAFX00_SET_HBA_SOC_REG(ha,
  460. (SOC_SW_RST_CONTROL_REG_CORE0 + 4 + 8*i), (0x01010101));
  461. }
  462. /* Reset all units in Fabric */
  463. QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_RST_CONTROL_REG, (0x11F0101));
  464. /* Reset all interrupt control registers */
  465. for (i = 0; i < 115; i++) {
  466. QLAFX00_SET_HBA_SOC_REG(ha,
  467. (SOC_INTERRUPT_SOURCE_I_CONTROL_REG + 4*i), (0x0));
  468. }
  469. /* Reset Timers control registers. per core */
  470. for (core = 0; core < 4; core++)
  471. for (i = 0; i < 8; i++)
  472. QLAFX00_SET_HBA_SOC_REG(ha,
  473. (SOC_CORE_TIMER_REG + 0x100*core + 4*i), (0x0));
  474. /* Reset per core IRQ ack register */
  475. for (core = 0; core < 4; core++)
  476. QLAFX00_SET_HBA_SOC_REG(ha,
  477. (SOC_IRQ_ACK_REG + 0x100*core), (0x3FF));
  478. /* Set Fabric control and config to defaults */
  479. QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_CONTROL_REG, (0x2));
  480. QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_CONFIG_REG, (0x3));
  481. spin_lock_irqsave(&ha->hardware_lock, flags);
  482. /* Kick in Fabric units */
  483. QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_RST_CONTROL_REG, (0x0));
  484. /* Kick in Core0 to start boot process */
  485. QLAFX00_SET_HBA_SOC_REG(ha, SOC_SW_RST_CONTROL_REG_CORE0, (0xF00));
  486. /* Wait 10secs for soft-reset to complete. */
  487. for (cnt = 10; cnt; cnt--) {
  488. msleep(1000);
  489. barrier();
  490. }
  491. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  492. }
  493. /**
  494. * qlafx00_soft_reset() - Soft Reset ISPFx00.
  495. * @ha: HA context
  496. *
  497. * Returns 0 on success.
  498. */
  499. void
  500. qlafx00_soft_reset(scsi_qla_host_t *vha)
  501. {
  502. struct qla_hw_data *ha = vha->hw;
  503. if (unlikely(pci_channel_offline(ha->pdev) &&
  504. ha->flags.pci_channel_io_perm_failure))
  505. return;
  506. ha->isp_ops->disable_intrs(ha);
  507. qlafx00_soc_cpu_reset(vha);
  508. ha->isp_ops->enable_intrs(ha);
  509. }
  510. /**
  511. * qlafx00_chip_diag() - Test ISPFx00 for proper operation.
  512. * @ha: HA context
  513. *
  514. * Returns 0 on success.
  515. */
  516. int
  517. qlafx00_chip_diag(scsi_qla_host_t *vha)
  518. {
  519. int rval = 0;
  520. struct qla_hw_data *ha = vha->hw;
  521. struct req_que *req = ha->req_q_map[0];
  522. ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
  523. rval = qlafx00_mbx_reg_test(vha);
  524. if (rval) {
  525. ql_log(ql_log_warn, vha, 0x1165,
  526. "Failed mailbox send register test\n");
  527. } else {
  528. /* Flag a successful rval */
  529. rval = QLA_SUCCESS;
  530. }
  531. return rval;
  532. }
  533. void
  534. qlafx00_config_rings(struct scsi_qla_host *vha)
  535. {
  536. struct qla_hw_data *ha = vha->hw;
  537. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  538. struct init_cb_fx *icb;
  539. struct req_que *req = ha->req_q_map[0];
  540. struct rsp_que *rsp = ha->rsp_q_map[0];
  541. /* Setup ring parameters in initialization control block. */
  542. icb = (struct init_cb_fx *)ha->init_cb;
  543. icb->request_q_outpointer = __constant_cpu_to_le16(0);
  544. icb->response_q_inpointer = __constant_cpu_to_le16(0);
  545. icb->request_q_length = cpu_to_le16(req->length);
  546. icb->response_q_length = cpu_to_le16(rsp->length);
  547. icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
  548. icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
  549. icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
  550. icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
  551. WRT_REG_DWORD(&reg->req_q_in, 0);
  552. WRT_REG_DWORD(&reg->req_q_out, 0);
  553. WRT_REG_DWORD(&reg->rsp_q_in, 0);
  554. WRT_REG_DWORD(&reg->rsp_q_out, 0);
  555. /* PCI posting */
  556. RD_REG_DWORD(&reg->rsp_q_out);
  557. }
  558. char *
  559. qlafx00_pci_info_str(struct scsi_qla_host *vha, char *str)
  560. {
  561. struct qla_hw_data *ha = vha->hw;
  562. int pcie_reg;
  563. pcie_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP);
  564. if (pcie_reg) {
  565. strcpy(str, "PCIe iSA");
  566. return str;
  567. }
  568. return str;
  569. }
  570. char *
  571. qlafx00_fw_version_str(struct scsi_qla_host *vha, char *str)
  572. {
  573. struct qla_hw_data *ha = vha->hw;
  574. sprintf(str, "%s", ha->mr.fw_version);
  575. return str;
  576. }
  577. void
  578. qlafx00_enable_intrs(struct qla_hw_data *ha)
  579. {
  580. unsigned long flags = 0;
  581. spin_lock_irqsave(&ha->hardware_lock, flags);
  582. ha->interrupts_on = 1;
  583. QLAFX00_ENABLE_ICNTRL_REG(ha);
  584. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  585. }
  586. void
  587. qlafx00_disable_intrs(struct qla_hw_data *ha)
  588. {
  589. unsigned long flags = 0;
  590. spin_lock_irqsave(&ha->hardware_lock, flags);
  591. ha->interrupts_on = 0;
  592. QLAFX00_DISABLE_ICNTRL_REG(ha);
  593. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  594. }
  595. static void
  596. qlafx00_tmf_iocb_timeout(void *data)
  597. {
  598. srb_t *sp = (srb_t *)data;
  599. struct srb_iocb *tmf = &sp->u.iocb_cmd;
  600. tmf->u.tmf.comp_status = cpu_to_le16((uint16_t)CS_TIMEOUT);
  601. complete(&tmf->u.tmf.comp);
  602. }
  603. static void
  604. qlafx00_tmf_sp_done(void *data, void *ptr, int res)
  605. {
  606. srb_t *sp = (srb_t *)ptr;
  607. struct srb_iocb *tmf = &sp->u.iocb_cmd;
  608. complete(&tmf->u.tmf.comp);
  609. }
  610. static int
  611. qlafx00_async_tm_cmd(fc_port_t *fcport, uint32_t flags,
  612. uint32_t lun, uint32_t tag)
  613. {
  614. scsi_qla_host_t *vha = fcport->vha;
  615. struct srb_iocb *tm_iocb;
  616. srb_t *sp;
  617. int rval = QLA_FUNCTION_FAILED;
  618. sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
  619. if (!sp)
  620. goto done;
  621. tm_iocb = &sp->u.iocb_cmd;
  622. sp->type = SRB_TM_CMD;
  623. sp->name = "tmf";
  624. qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
  625. tm_iocb->u.tmf.flags = flags;
  626. tm_iocb->u.tmf.lun = lun;
  627. tm_iocb->u.tmf.data = tag;
  628. sp->done = qlafx00_tmf_sp_done;
  629. tm_iocb->timeout = qlafx00_tmf_iocb_timeout;
  630. init_completion(&tm_iocb->u.tmf.comp);
  631. rval = qla2x00_start_sp(sp);
  632. if (rval != QLA_SUCCESS)
  633. goto done_free_sp;
  634. ql_dbg(ql_dbg_async, vha, 0x507b,
  635. "Task management command issued target_id=%x\n",
  636. fcport->tgt_id);
  637. wait_for_completion(&tm_iocb->u.tmf.comp);
  638. rval = tm_iocb->u.tmf.comp_status == CS_COMPLETE ?
  639. QLA_SUCCESS : QLA_FUNCTION_FAILED;
  640. done_free_sp:
  641. sp->free(vha, sp);
  642. done:
  643. return rval;
  644. }
  645. int
  646. qlafx00_abort_target(fc_port_t *fcport, unsigned int l, int tag)
  647. {
  648. return qlafx00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag);
  649. }
  650. int
  651. qlafx00_lun_reset(fc_port_t *fcport, unsigned int l, int tag)
  652. {
  653. return qlafx00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag);
  654. }
  655. int
  656. qlafx00_loop_reset(scsi_qla_host_t *vha)
  657. {
  658. int ret;
  659. struct fc_port *fcport;
  660. struct qla_hw_data *ha = vha->hw;
  661. if (ql2xtargetreset) {
  662. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  663. if (fcport->port_type != FCT_TARGET)
  664. continue;
  665. ret = ha->isp_ops->target_reset(fcport, 0, 0);
  666. if (ret != QLA_SUCCESS) {
  667. ql_dbg(ql_dbg_taskm, vha, 0x803d,
  668. "Bus Reset failed: Reset=%d "
  669. "d_id=%x.\n", ret, fcport->d_id.b24);
  670. }
  671. }
  672. }
  673. return QLA_SUCCESS;
  674. }
  675. int
  676. qlafx00_iospace_config(struct qla_hw_data *ha)
  677. {
  678. if (pci_request_selected_regions(ha->pdev, ha->bars,
  679. QLA2XXX_DRIVER_NAME)) {
  680. ql_log_pci(ql_log_fatal, ha->pdev, 0x014e,
  681. "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
  682. pci_name(ha->pdev));
  683. goto iospace_error_exit;
  684. }
  685. /* Use MMIO operations for all accesses. */
  686. if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
  687. ql_log_pci(ql_log_warn, ha->pdev, 0x014f,
  688. "Invalid pci I/O region size (%s).\n",
  689. pci_name(ha->pdev));
  690. goto iospace_error_exit;
  691. }
  692. if (pci_resource_len(ha->pdev, 0) < BAR0_LEN_FX00) {
  693. ql_log_pci(ql_log_warn, ha->pdev, 0x0127,
  694. "Invalid PCI mem BAR0 region size (%s), aborting\n",
  695. pci_name(ha->pdev));
  696. goto iospace_error_exit;
  697. }
  698. ha->cregbase =
  699. ioremap_nocache(pci_resource_start(ha->pdev, 0), BAR0_LEN_FX00);
  700. if (!ha->cregbase) {
  701. ql_log_pci(ql_log_fatal, ha->pdev, 0x0128,
  702. "cannot remap MMIO (%s), aborting\n", pci_name(ha->pdev));
  703. goto iospace_error_exit;
  704. }
  705. if (!(pci_resource_flags(ha->pdev, 2) & IORESOURCE_MEM)) {
  706. ql_log_pci(ql_log_warn, ha->pdev, 0x0129,
  707. "region #2 not an MMIO resource (%s), aborting\n",
  708. pci_name(ha->pdev));
  709. goto iospace_error_exit;
  710. }
  711. if (pci_resource_len(ha->pdev, 2) < BAR2_LEN_FX00) {
  712. ql_log_pci(ql_log_warn, ha->pdev, 0x012a,
  713. "Invalid PCI mem BAR2 region size (%s), aborting\n",
  714. pci_name(ha->pdev));
  715. goto iospace_error_exit;
  716. }
  717. ha->iobase =
  718. ioremap_nocache(pci_resource_start(ha->pdev, 2), BAR2_LEN_FX00);
  719. if (!ha->iobase) {
  720. ql_log_pci(ql_log_fatal, ha->pdev, 0x012b,
  721. "cannot remap MMIO (%s), aborting\n", pci_name(ha->pdev));
  722. goto iospace_error_exit;
  723. }
  724. /* Determine queue resources */
  725. ha->max_req_queues = ha->max_rsp_queues = 1;
  726. ql_log_pci(ql_log_info, ha->pdev, 0x012c,
  727. "Bars 0x%x, iobase0 0x%p, iobase2 0x%p\n",
  728. ha->bars, ha->cregbase, ha->iobase);
  729. return 0;
  730. iospace_error_exit:
  731. return -ENOMEM;
  732. }
  733. static void
  734. qlafx00_save_queue_ptrs(struct scsi_qla_host *vha)
  735. {
  736. struct qla_hw_data *ha = vha->hw;
  737. struct req_que *req = ha->req_q_map[0];
  738. struct rsp_que *rsp = ha->rsp_q_map[0];
  739. req->length_fx00 = req->length;
  740. req->ring_fx00 = req->ring;
  741. req->dma_fx00 = req->dma;
  742. rsp->length_fx00 = rsp->length;
  743. rsp->ring_fx00 = rsp->ring;
  744. rsp->dma_fx00 = rsp->dma;
  745. ql_dbg(ql_dbg_init, vha, 0x012d,
  746. "req: %p, ring_fx00: %p, length_fx00: 0x%x,"
  747. "req->dma_fx00: 0x%llx\n", req, req->ring_fx00,
  748. req->length_fx00, (u64)req->dma_fx00);
  749. ql_dbg(ql_dbg_init, vha, 0x012e,
  750. "rsp: %p, ring_fx00: %p, length_fx00: 0x%x,"
  751. "rsp->dma_fx00: 0x%llx\n", rsp, rsp->ring_fx00,
  752. rsp->length_fx00, (u64)rsp->dma_fx00);
  753. }
  754. static int
  755. qlafx00_config_queues(struct scsi_qla_host *vha)
  756. {
  757. struct qla_hw_data *ha = vha->hw;
  758. struct req_que *req = ha->req_q_map[0];
  759. struct rsp_que *rsp = ha->rsp_q_map[0];
  760. dma_addr_t bar2_hdl = pci_resource_start(ha->pdev, 2);
  761. req->length = ha->req_que_len;
  762. req->ring = (void *)ha->iobase + ha->req_que_off;
  763. req->dma = bar2_hdl + ha->req_que_off;
  764. if ((!req->ring) || (req->length == 0)) {
  765. ql_log_pci(ql_log_info, ha->pdev, 0x012f,
  766. "Unable to allocate memory for req_ring\n");
  767. return QLA_FUNCTION_FAILED;
  768. }
  769. ql_dbg(ql_dbg_init, vha, 0x0130,
  770. "req: %p req_ring pointer %p req len 0x%x "
  771. "req off 0x%x\n, req->dma: 0x%llx",
  772. req, req->ring, req->length,
  773. ha->req_que_off, (u64)req->dma);
  774. rsp->length = ha->rsp_que_len;
  775. rsp->ring = (void *)ha->iobase + ha->rsp_que_off;
  776. rsp->dma = bar2_hdl + ha->rsp_que_off;
  777. if ((!rsp->ring) || (rsp->length == 0)) {
  778. ql_log_pci(ql_log_info, ha->pdev, 0x0131,
  779. "Unable to allocate memory for rsp_ring\n");
  780. return QLA_FUNCTION_FAILED;
  781. }
  782. ql_dbg(ql_dbg_init, vha, 0x0132,
  783. "rsp: %p rsp_ring pointer %p rsp len 0x%x "
  784. "rsp off 0x%x, rsp->dma: 0x%llx\n",
  785. rsp, rsp->ring, rsp->length,
  786. ha->rsp_que_off, (u64)rsp->dma);
  787. return QLA_SUCCESS;
  788. }
  789. static int
  790. qlafx00_init_fw_ready(scsi_qla_host_t *vha)
  791. {
  792. int rval = 0;
  793. unsigned long wtime;
  794. uint16_t wait_time; /* Wait time */
  795. struct qla_hw_data *ha = vha->hw;
  796. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  797. uint32_t aenmbx, aenmbx7 = 0;
  798. uint32_t state[5];
  799. bool done = false;
  800. /* 30 seconds wait - Adjust if required */
  801. wait_time = 30;
  802. /* wait time before firmware ready */
  803. wtime = jiffies + (wait_time * HZ);
  804. do {
  805. aenmbx = RD_REG_DWORD(&reg->aenmailbox0);
  806. barrier();
  807. ql_dbg(ql_dbg_mbx, vha, 0x0133,
  808. "aenmbx: 0x%x\n", aenmbx);
  809. switch (aenmbx) {
  810. case MBA_FW_NOT_STARTED:
  811. case MBA_FW_STARTING:
  812. break;
  813. case MBA_SYSTEM_ERR:
  814. case MBA_REQ_TRANSFER_ERR:
  815. case MBA_RSP_TRANSFER_ERR:
  816. case MBA_FW_INIT_FAILURE:
  817. qlafx00_soft_reset(vha);
  818. break;
  819. case MBA_FW_RESTART_CMPLT:
  820. /* Set the mbx and rqstq intr code */
  821. aenmbx7 = RD_REG_DWORD(&reg->aenmailbox7);
  822. ha->mbx_intr_code = MSW(aenmbx7);
  823. ha->rqstq_intr_code = LSW(aenmbx7);
  824. ha->req_que_off = RD_REG_DWORD(&reg->aenmailbox1);
  825. ha->rsp_que_off = RD_REG_DWORD(&reg->aenmailbox3);
  826. ha->req_que_len = RD_REG_DWORD(&reg->aenmailbox5);
  827. ha->rsp_que_len = RD_REG_DWORD(&reg->aenmailbox6);
  828. WRT_REG_DWORD(&reg->aenmailbox0, 0);
  829. RD_REG_DWORD_RELAXED(&reg->aenmailbox0);
  830. ql_dbg(ql_dbg_init, vha, 0x0134,
  831. "f/w returned mbx_intr_code: 0x%x, "
  832. "rqstq_intr_code: 0x%x\n",
  833. ha->mbx_intr_code, ha->rqstq_intr_code);
  834. QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
  835. rval = QLA_SUCCESS;
  836. done = true;
  837. break;
  838. default:
  839. /* If fw is apparently not ready. In order to continue,
  840. * we might need to issue Mbox cmd, but the problem is
  841. * that the DoorBell vector values that come with the
  842. * 8060 AEN are most likely gone by now (and thus no
  843. * bell would be rung on the fw side when mbox cmd is
  844. * issued). We have to therefore grab the 8060 AEN
  845. * shadow regs (filled in by FW when the last 8060
  846. * AEN was being posted).
  847. * Do the following to determine what is needed in
  848. * order to get the FW ready:
  849. * 1. reload the 8060 AEN values from the shadow regs
  850. * 2. clear int status to get rid of possible pending
  851. * interrupts
  852. * 3. issue Get FW State Mbox cmd to determine fw state
  853. * Set the mbx and rqstq intr code from Shadow Regs
  854. */
  855. aenmbx7 = RD_REG_DWORD(&reg->initval7);
  856. ha->mbx_intr_code = MSW(aenmbx7);
  857. ha->rqstq_intr_code = LSW(aenmbx7);
  858. ha->req_que_off = RD_REG_DWORD(&reg->initval1);
  859. ha->rsp_que_off = RD_REG_DWORD(&reg->initval3);
  860. ha->req_que_len = RD_REG_DWORD(&reg->initval5);
  861. ha->rsp_que_len = RD_REG_DWORD(&reg->initval6);
  862. ql_dbg(ql_dbg_init, vha, 0x0135,
  863. "f/w returned mbx_intr_code: 0x%x, "
  864. "rqstq_intr_code: 0x%x\n",
  865. ha->mbx_intr_code, ha->rqstq_intr_code);
  866. QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
  867. /* Get the FW state */
  868. rval = qlafx00_get_firmware_state(vha, state);
  869. if (rval != QLA_SUCCESS) {
  870. /* Retry if timer has not expired */
  871. break;
  872. }
  873. if (state[0] == FSTATE_FX00_CONFIG_WAIT) {
  874. /* Firmware is waiting to be
  875. * initialized by driver
  876. */
  877. rval = QLA_SUCCESS;
  878. done = true;
  879. break;
  880. }
  881. /* Issue driver shutdown and wait until f/w recovers.
  882. * Driver should continue to poll until 8060 AEN is
  883. * received indicating firmware recovery.
  884. */
  885. ql_dbg(ql_dbg_init, vha, 0x0136,
  886. "Sending Driver shutdown fw_state 0x%x\n",
  887. state[0]);
  888. rval = qlafx00_driver_shutdown(vha, 10);
  889. if (rval != QLA_SUCCESS) {
  890. rval = QLA_FUNCTION_FAILED;
  891. break;
  892. }
  893. msleep(500);
  894. wtime = jiffies + (wait_time * HZ);
  895. break;
  896. }
  897. if (!done) {
  898. if (time_after_eq(jiffies, wtime)) {
  899. ql_dbg(ql_dbg_init, vha, 0x0137,
  900. "Init f/w failed: aen[7]: 0x%x\n",
  901. RD_REG_DWORD(&reg->aenmailbox7));
  902. rval = QLA_FUNCTION_FAILED;
  903. done = true;
  904. break;
  905. }
  906. /* Delay for a while */
  907. msleep(500);
  908. }
  909. } while (!done);
  910. if (rval)
  911. ql_dbg(ql_dbg_init, vha, 0x0138,
  912. "%s **** FAILED ****.\n", __func__);
  913. else
  914. ql_dbg(ql_dbg_init, vha, 0x0139,
  915. "%s **** SUCCESS ****.\n", __func__);
  916. return rval;
  917. }
  918. /*
  919. * qlafx00_fw_ready() - Waits for firmware ready.
  920. * @ha: HA context
  921. *
  922. * Returns 0 on success.
  923. */
  924. int
  925. qlafx00_fw_ready(scsi_qla_host_t *vha)
  926. {
  927. int rval;
  928. unsigned long wtime;
  929. uint16_t wait_time; /* Wait time if loop is coming ready */
  930. uint32_t state[5];
  931. rval = QLA_SUCCESS;
  932. wait_time = 10;
  933. /* wait time before firmware ready */
  934. wtime = jiffies + (wait_time * HZ);
  935. /* Wait for ISP to finish init */
  936. if (!vha->flags.init_done)
  937. ql_dbg(ql_dbg_init, vha, 0x013a,
  938. "Waiting for init to complete...\n");
  939. do {
  940. rval = qlafx00_get_firmware_state(vha, state);
  941. if (rval == QLA_SUCCESS) {
  942. if (state[0] == FSTATE_FX00_INITIALIZED) {
  943. ql_dbg(ql_dbg_init, vha, 0x013b,
  944. "fw_state=%x\n", state[0]);
  945. rval = QLA_SUCCESS;
  946. break;
  947. }
  948. }
  949. rval = QLA_FUNCTION_FAILED;
  950. if (time_after_eq(jiffies, wtime))
  951. break;
  952. /* Delay for a while */
  953. msleep(500);
  954. ql_dbg(ql_dbg_init, vha, 0x013c,
  955. "fw_state=%x curr time=%lx.\n", state[0], jiffies);
  956. } while (1);
  957. if (rval)
  958. ql_dbg(ql_dbg_init, vha, 0x013d,
  959. "Firmware ready **** FAILED ****.\n");
  960. else
  961. ql_dbg(ql_dbg_init, vha, 0x013e,
  962. "Firmware ready **** SUCCESS ****.\n");
  963. return rval;
  964. }
  965. static int
  966. qlafx00_find_all_targets(scsi_qla_host_t *vha,
  967. struct list_head *new_fcports)
  968. {
  969. int rval;
  970. uint16_t tgt_id;
  971. fc_port_t *fcport, *new_fcport;
  972. int found;
  973. struct qla_hw_data *ha = vha->hw;
  974. rval = QLA_SUCCESS;
  975. if (!test_bit(LOOP_RESYNC_ACTIVE, &vha->dpc_flags))
  976. return QLA_FUNCTION_FAILED;
  977. if ((atomic_read(&vha->loop_down_timer) ||
  978. STATE_TRANSITION(vha))) {
  979. atomic_set(&vha->loop_down_timer, 0);
  980. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  981. return QLA_FUNCTION_FAILED;
  982. }
  983. ql_dbg(ql_dbg_disc + ql_dbg_init, vha, 0x2088,
  984. "Listing Target bit map...\n");
  985. ql_dump_buffer(ql_dbg_disc + ql_dbg_init, vha,
  986. 0x2089, (uint8_t *)ha->gid_list, 32);
  987. /* Allocate temporary rmtport for any new rmtports discovered. */
  988. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  989. if (new_fcport == NULL)
  990. return QLA_MEMORY_ALLOC_FAILED;
  991. for_each_set_bit(tgt_id, (void *)ha->gid_list,
  992. QLAFX00_TGT_NODE_LIST_SIZE) {
  993. /* Send get target node info */
  994. new_fcport->tgt_id = tgt_id;
  995. rval = qlafx00_fx_disc(vha, new_fcport,
  996. FXDISC_GET_TGT_NODE_INFO);
  997. if (rval != QLA_SUCCESS) {
  998. ql_log(ql_log_warn, vha, 0x208a,
  999. "Target info scan failed -- assuming zero-entry "
  1000. "result...\n");
  1001. continue;
  1002. }
  1003. /* Locate matching device in database. */
  1004. found = 0;
  1005. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  1006. if (memcmp(new_fcport->port_name,
  1007. fcport->port_name, WWN_SIZE))
  1008. continue;
  1009. found++;
  1010. /*
  1011. * If tgt_id is same and state FCS_ONLINE, nothing
  1012. * changed.
  1013. */
  1014. if (fcport->tgt_id == new_fcport->tgt_id &&
  1015. atomic_read(&fcport->state) == FCS_ONLINE)
  1016. break;
  1017. /*
  1018. * Tgt ID changed or device was marked to be updated.
  1019. */
  1020. ql_dbg(ql_dbg_disc + ql_dbg_init, vha, 0x208b,
  1021. "TGT-ID Change(%s): Present tgt id: "
  1022. "0x%x state: 0x%x "
  1023. "wwnn = %llx wwpn = %llx.\n",
  1024. __func__, fcport->tgt_id,
  1025. atomic_read(&fcport->state),
  1026. (unsigned long long)wwn_to_u64(fcport->node_name),
  1027. (unsigned long long)wwn_to_u64(fcport->port_name));
  1028. ql_log(ql_log_info, vha, 0x208c,
  1029. "TGT-ID Announce(%s): Discovered tgt "
  1030. "id 0x%x wwnn = %llx "
  1031. "wwpn = %llx.\n", __func__, new_fcport->tgt_id,
  1032. (unsigned long long)
  1033. wwn_to_u64(new_fcport->node_name),
  1034. (unsigned long long)
  1035. wwn_to_u64(new_fcport->port_name));
  1036. if (atomic_read(&fcport->state) != FCS_ONLINE) {
  1037. fcport->old_tgt_id = fcport->tgt_id;
  1038. fcport->tgt_id = new_fcport->tgt_id;
  1039. ql_log(ql_log_info, vha, 0x208d,
  1040. "TGT-ID: New fcport Added: %p\n", fcport);
  1041. qla2x00_update_fcport(vha, fcport);
  1042. } else {
  1043. ql_log(ql_log_info, vha, 0x208e,
  1044. " Existing TGT-ID %x did not get "
  1045. " offline event from firmware.\n",
  1046. fcport->old_tgt_id);
  1047. qla2x00_mark_device_lost(vha, fcport, 0, 0);
  1048. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1049. kfree(new_fcport);
  1050. return rval;
  1051. }
  1052. break;
  1053. }
  1054. if (found)
  1055. continue;
  1056. /* If device was not in our fcports list, then add it. */
  1057. list_add_tail(&new_fcport->list, new_fcports);
  1058. /* Allocate a new replacement fcport. */
  1059. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  1060. if (new_fcport == NULL)
  1061. return QLA_MEMORY_ALLOC_FAILED;
  1062. }
  1063. kfree(new_fcport);
  1064. return rval;
  1065. }
  1066. /*
  1067. * qlafx00_configure_all_targets
  1068. * Setup target devices with node ID's.
  1069. *
  1070. * Input:
  1071. * ha = adapter block pointer.
  1072. *
  1073. * Returns:
  1074. * 0 = success.
  1075. * BIT_0 = error
  1076. */
  1077. static int
  1078. qlafx00_configure_all_targets(scsi_qla_host_t *vha)
  1079. {
  1080. int rval;
  1081. fc_port_t *fcport, *rmptemp;
  1082. LIST_HEAD(new_fcports);
  1083. rval = qlafx00_fx_disc(vha, &vha->hw->mr.fcport,
  1084. FXDISC_GET_TGT_NODE_LIST);
  1085. if (rval != QLA_SUCCESS) {
  1086. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1087. return rval;
  1088. }
  1089. rval = qlafx00_find_all_targets(vha, &new_fcports);
  1090. if (rval != QLA_SUCCESS) {
  1091. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1092. return rval;
  1093. }
  1094. /*
  1095. * Delete all previous devices marked lost.
  1096. */
  1097. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  1098. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  1099. break;
  1100. if (atomic_read(&fcport->state) == FCS_DEVICE_LOST) {
  1101. if (fcport->port_type != FCT_INITIATOR)
  1102. qla2x00_mark_device_lost(vha, fcport, 0, 0);
  1103. }
  1104. }
  1105. /*
  1106. * Add the new devices to our devices list.
  1107. */
  1108. list_for_each_entry_safe(fcport, rmptemp, &new_fcports, list) {
  1109. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  1110. break;
  1111. qla2x00_update_fcport(vha, fcport);
  1112. list_move_tail(&fcport->list, &vha->vp_fcports);
  1113. ql_log(ql_log_info, vha, 0x208f,
  1114. "Attach new target id 0x%x wwnn = %llx "
  1115. "wwpn = %llx.\n",
  1116. fcport->tgt_id,
  1117. (unsigned long long)wwn_to_u64(fcport->node_name),
  1118. (unsigned long long)wwn_to_u64(fcport->port_name));
  1119. }
  1120. /* Free all new device structures not processed. */
  1121. list_for_each_entry_safe(fcport, rmptemp, &new_fcports, list) {
  1122. list_del(&fcport->list);
  1123. kfree(fcport);
  1124. }
  1125. return rval;
  1126. }
  1127. /*
  1128. * qlafx00_configure_devices
  1129. * Updates Fibre Channel Device Database with what is actually on loop.
  1130. *
  1131. * Input:
  1132. * ha = adapter block pointer.
  1133. *
  1134. * Returns:
  1135. * 0 = success.
  1136. * 1 = error.
  1137. * 2 = database was full and device was not configured.
  1138. */
  1139. int
  1140. qlafx00_configure_devices(scsi_qla_host_t *vha)
  1141. {
  1142. int rval;
  1143. unsigned long flags, save_flags;
  1144. rval = QLA_SUCCESS;
  1145. save_flags = flags = vha->dpc_flags;
  1146. ql_dbg(ql_dbg_disc, vha, 0x2090,
  1147. "Configure devices -- dpc flags =0x%lx\n", flags);
  1148. rval = qlafx00_configure_all_targets(vha);
  1149. if (rval == QLA_SUCCESS) {
  1150. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
  1151. rval = QLA_FUNCTION_FAILED;
  1152. } else {
  1153. atomic_set(&vha->loop_state, LOOP_READY);
  1154. ql_log(ql_log_info, vha, 0x2091,
  1155. "Device Ready\n");
  1156. }
  1157. }
  1158. if (rval) {
  1159. ql_dbg(ql_dbg_disc, vha, 0x2092,
  1160. "%s *** FAILED ***.\n", __func__);
  1161. } else {
  1162. ql_dbg(ql_dbg_disc, vha, 0x2093,
  1163. "%s: exiting normally.\n", __func__);
  1164. }
  1165. return rval;
  1166. }
  1167. static void
  1168. qlafx00_abort_isp_cleanup(scsi_qla_host_t *vha, bool critemp)
  1169. {
  1170. struct qla_hw_data *ha = vha->hw;
  1171. fc_port_t *fcport;
  1172. vha->flags.online = 0;
  1173. ha->mr.fw_hbt_en = 0;
  1174. if (!critemp) {
  1175. ha->flags.chip_reset_done = 0;
  1176. clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1177. vha->qla_stats.total_isp_aborts++;
  1178. ql_log(ql_log_info, vha, 0x013f,
  1179. "Performing ISP error recovery - ha = %p.\n", ha);
  1180. ha->isp_ops->reset_chip(vha);
  1181. }
  1182. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  1183. atomic_set(&vha->loop_state, LOOP_DOWN);
  1184. atomic_set(&vha->loop_down_timer,
  1185. QLAFX00_LOOP_DOWN_TIME);
  1186. } else {
  1187. if (!atomic_read(&vha->loop_down_timer))
  1188. atomic_set(&vha->loop_down_timer,
  1189. QLAFX00_LOOP_DOWN_TIME);
  1190. }
  1191. /* Clear all async request states across all VPs. */
  1192. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  1193. fcport->flags = 0;
  1194. if (atomic_read(&fcport->state) == FCS_ONLINE)
  1195. qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
  1196. }
  1197. if (!ha->flags.eeh_busy) {
  1198. if (critemp) {
  1199. qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
  1200. } else {
  1201. /* Requeue all commands in outstanding command list. */
  1202. qla2x00_abort_all_cmds(vha, DID_RESET << 16);
  1203. }
  1204. }
  1205. qla2x00_free_irqs(vha);
  1206. if (critemp)
  1207. set_bit(FX00_CRITEMP_RECOVERY, &vha->dpc_flags);
  1208. else
  1209. set_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
  1210. /* Clear the Interrupts */
  1211. QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
  1212. ql_log(ql_log_info, vha, 0x0140,
  1213. "%s Done done - ha=%p.\n", __func__, ha);
  1214. }
  1215. /**
  1216. * qlafx00_init_response_q_entries() - Initializes response queue entries.
  1217. * @ha: HA context
  1218. *
  1219. * Beginning of request ring has initialization control block already built
  1220. * by nvram config routine.
  1221. *
  1222. * Returns 0 on success.
  1223. */
  1224. void
  1225. qlafx00_init_response_q_entries(struct rsp_que *rsp)
  1226. {
  1227. uint16_t cnt;
  1228. response_t *pkt;
  1229. rsp->ring_ptr = rsp->ring;
  1230. rsp->ring_index = 0;
  1231. rsp->status_srb = NULL;
  1232. pkt = rsp->ring_ptr;
  1233. for (cnt = 0; cnt < rsp->length; cnt++) {
  1234. pkt->signature = RESPONSE_PROCESSED;
  1235. WRT_REG_DWORD((void __iomem *)&pkt->signature,
  1236. RESPONSE_PROCESSED);
  1237. pkt++;
  1238. }
  1239. }
  1240. int
  1241. qlafx00_rescan_isp(scsi_qla_host_t *vha)
  1242. {
  1243. uint32_t status = QLA_FUNCTION_FAILED;
  1244. struct qla_hw_data *ha = vha->hw;
  1245. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  1246. uint32_t aenmbx7;
  1247. qla2x00_request_irqs(ha, ha->rsp_q_map[0]);
  1248. aenmbx7 = RD_REG_DWORD(&reg->aenmailbox7);
  1249. ha->mbx_intr_code = MSW(aenmbx7);
  1250. ha->rqstq_intr_code = LSW(aenmbx7);
  1251. ha->req_que_off = RD_REG_DWORD(&reg->aenmailbox1);
  1252. ha->rsp_que_off = RD_REG_DWORD(&reg->aenmailbox3);
  1253. ha->req_que_len = RD_REG_DWORD(&reg->aenmailbox5);
  1254. ha->rsp_que_len = RD_REG_DWORD(&reg->aenmailbox6);
  1255. ql_dbg(ql_dbg_disc, vha, 0x2094,
  1256. "fw returned mbx_intr_code: 0x%x, rqstq_intr_code: 0x%x "
  1257. " Req que offset 0x%x Rsp que offset 0x%x\n",
  1258. ha->mbx_intr_code, ha->rqstq_intr_code,
  1259. ha->req_que_off, ha->rsp_que_len);
  1260. /* Clear the Interrupts */
  1261. QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
  1262. status = qla2x00_init_rings(vha);
  1263. if (!status) {
  1264. vha->flags.online = 1;
  1265. /* if no cable then assume it's good */
  1266. if ((vha->device_flags & DFLG_NO_CABLE))
  1267. status = 0;
  1268. /* Register system information */
  1269. if (qlafx00_fx_disc(vha,
  1270. &vha->hw->mr.fcport, FXDISC_REG_HOST_INFO))
  1271. ql_dbg(ql_dbg_disc, vha, 0x2095,
  1272. "failed to register host info\n");
  1273. }
  1274. scsi_unblock_requests(vha->host);
  1275. return status;
  1276. }
  1277. void
  1278. qlafx00_timer_routine(scsi_qla_host_t *vha)
  1279. {
  1280. struct qla_hw_data *ha = vha->hw;
  1281. uint32_t fw_heart_beat;
  1282. uint32_t aenmbx0;
  1283. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  1284. uint32_t tempc;
  1285. /* Check firmware health */
  1286. if (ha->mr.fw_hbt_cnt)
  1287. ha->mr.fw_hbt_cnt--;
  1288. else {
  1289. if ((!ha->flags.mr_reset_hdlr_active) &&
  1290. (!test_bit(UNLOADING, &vha->dpc_flags)) &&
  1291. (!test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
  1292. (ha->mr.fw_hbt_en)) {
  1293. fw_heart_beat = RD_REG_DWORD(&reg->fwheartbeat);
  1294. if (fw_heart_beat != ha->mr.old_fw_hbt_cnt) {
  1295. ha->mr.old_fw_hbt_cnt = fw_heart_beat;
  1296. ha->mr.fw_hbt_miss_cnt = 0;
  1297. } else {
  1298. ha->mr.fw_hbt_miss_cnt++;
  1299. if (ha->mr.fw_hbt_miss_cnt ==
  1300. QLAFX00_HEARTBEAT_MISS_CNT) {
  1301. set_bit(ISP_ABORT_NEEDED,
  1302. &vha->dpc_flags);
  1303. qla2xxx_wake_dpc(vha);
  1304. ha->mr.fw_hbt_miss_cnt = 0;
  1305. }
  1306. }
  1307. }
  1308. ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
  1309. }
  1310. if (test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags)) {
  1311. /* Reset recovery to be performed in timer routine */
  1312. aenmbx0 = RD_REG_DWORD(&reg->aenmailbox0);
  1313. if (ha->mr.fw_reset_timer_exp) {
  1314. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1315. qla2xxx_wake_dpc(vha);
  1316. ha->mr.fw_reset_timer_exp = 0;
  1317. } else if (aenmbx0 == MBA_FW_RESTART_CMPLT) {
  1318. /* Wake up DPC to rescan the targets */
  1319. set_bit(FX00_TARGET_SCAN, &vha->dpc_flags);
  1320. clear_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
  1321. qla2xxx_wake_dpc(vha);
  1322. ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
  1323. } else if ((aenmbx0 == MBA_FW_STARTING) &&
  1324. (!ha->mr.fw_hbt_en)) {
  1325. ha->mr.fw_hbt_en = 1;
  1326. } else if (!ha->mr.fw_reset_timer_tick) {
  1327. if (aenmbx0 == ha->mr.old_aenmbx0_state)
  1328. ha->mr.fw_reset_timer_exp = 1;
  1329. ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
  1330. } else if (aenmbx0 == 0xFFFFFFFF) {
  1331. uint32_t data0, data1;
  1332. data0 = QLAFX00_RD_REG(ha,
  1333. QLAFX00_BAR1_BASE_ADDR_REG);
  1334. data1 = QLAFX00_RD_REG(ha,
  1335. QLAFX00_PEX0_WIN0_BASE_ADDR_REG);
  1336. data0 &= 0xffff0000;
  1337. data1 &= 0x0000ffff;
  1338. QLAFX00_WR_REG(ha,
  1339. QLAFX00_PEX0_WIN0_BASE_ADDR_REG,
  1340. (data0 | data1));
  1341. } else if ((aenmbx0 & 0xFF00) == MBA_FW_POLL_STATE) {
  1342. ha->mr.fw_reset_timer_tick =
  1343. QLAFX00_MAX_RESET_INTERVAL;
  1344. } else if (aenmbx0 == MBA_FW_RESET_FCT) {
  1345. ha->mr.fw_reset_timer_tick =
  1346. QLAFX00_MAX_RESET_INTERVAL;
  1347. }
  1348. ha->mr.old_aenmbx0_state = aenmbx0;
  1349. ha->mr.fw_reset_timer_tick--;
  1350. }
  1351. if (test_bit(FX00_CRITEMP_RECOVERY, &vha->dpc_flags)) {
  1352. /*
  1353. * Critical temperature recovery to be
  1354. * performed in timer routine
  1355. */
  1356. if (ha->mr.fw_critemp_timer_tick == 0) {
  1357. tempc = QLAFX00_GET_TEMPERATURE(ha);
  1358. ql_log(ql_dbg_timer, vha, 0x6012,
  1359. "ISPFx00(%s): Critical temp timer, "
  1360. "current SOC temperature: %d\n",
  1361. __func__, tempc);
  1362. if (tempc < ha->mr.critical_temperature) {
  1363. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1364. clear_bit(FX00_CRITEMP_RECOVERY,
  1365. &vha->dpc_flags);
  1366. qla2xxx_wake_dpc(vha);
  1367. }
  1368. ha->mr.fw_critemp_timer_tick =
  1369. QLAFX00_CRITEMP_INTERVAL;
  1370. } else {
  1371. ha->mr.fw_critemp_timer_tick--;
  1372. }
  1373. }
  1374. }
  1375. /*
  1376. * qlfx00a_reset_initialize
  1377. * Re-initialize after a iSA device reset.
  1378. *
  1379. * Input:
  1380. * ha = adapter block pointer.
  1381. *
  1382. * Returns:
  1383. * 0 = success
  1384. */
  1385. int
  1386. qlafx00_reset_initialize(scsi_qla_host_t *vha)
  1387. {
  1388. struct qla_hw_data *ha = vha->hw;
  1389. if (vha->device_flags & DFLG_DEV_FAILED) {
  1390. ql_dbg(ql_dbg_init, vha, 0x0142,
  1391. "Device in failed state\n");
  1392. return QLA_SUCCESS;
  1393. }
  1394. ha->flags.mr_reset_hdlr_active = 1;
  1395. if (vha->flags.online) {
  1396. scsi_block_requests(vha->host);
  1397. qlafx00_abort_isp_cleanup(vha, false);
  1398. }
  1399. ql_log(ql_log_info, vha, 0x0143,
  1400. "(%s): succeeded.\n", __func__);
  1401. ha->flags.mr_reset_hdlr_active = 0;
  1402. return QLA_SUCCESS;
  1403. }
  1404. /*
  1405. * qlafx00_abort_isp
  1406. * Resets ISP and aborts all outstanding commands.
  1407. *
  1408. * Input:
  1409. * ha = adapter block pointer.
  1410. *
  1411. * Returns:
  1412. * 0 = success
  1413. */
  1414. int
  1415. qlafx00_abort_isp(scsi_qla_host_t *vha)
  1416. {
  1417. struct qla_hw_data *ha = vha->hw;
  1418. if (vha->flags.online) {
  1419. if (unlikely(pci_channel_offline(ha->pdev) &&
  1420. ha->flags.pci_channel_io_perm_failure)) {
  1421. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  1422. return QLA_SUCCESS;
  1423. }
  1424. scsi_block_requests(vha->host);
  1425. qlafx00_abort_isp_cleanup(vha, false);
  1426. } else {
  1427. scsi_block_requests(vha->host);
  1428. clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1429. vha->qla_stats.total_isp_aborts++;
  1430. ha->isp_ops->reset_chip(vha);
  1431. set_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
  1432. /* Clear the Interrupts */
  1433. QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
  1434. }
  1435. ql_log(ql_log_info, vha, 0x0145,
  1436. "(%s): succeeded.\n", __func__);
  1437. return QLA_SUCCESS;
  1438. }
  1439. static inline fc_port_t*
  1440. qlafx00_get_fcport(struct scsi_qla_host *vha, int tgt_id)
  1441. {
  1442. fc_port_t *fcport;
  1443. /* Check for matching device in remote port list. */
  1444. fcport = NULL;
  1445. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  1446. if (fcport->tgt_id == tgt_id) {
  1447. ql_dbg(ql_dbg_async, vha, 0x5072,
  1448. "Matching fcport(%p) found with TGT-ID: 0x%x "
  1449. "and Remote TGT_ID: 0x%x\n",
  1450. fcport, fcport->tgt_id, tgt_id);
  1451. break;
  1452. }
  1453. }
  1454. return fcport;
  1455. }
  1456. static void
  1457. qlafx00_tgt_detach(struct scsi_qla_host *vha, int tgt_id)
  1458. {
  1459. fc_port_t *fcport;
  1460. ql_log(ql_log_info, vha, 0x5073,
  1461. "Detach TGT-ID: 0x%x\n", tgt_id);
  1462. fcport = qlafx00_get_fcport(vha, tgt_id);
  1463. if (!fcport)
  1464. return;
  1465. qla2x00_mark_device_lost(vha, fcport, 0, 0);
  1466. return;
  1467. }
  1468. int
  1469. qlafx00_process_aen(struct scsi_qla_host *vha, struct qla_work_evt *evt)
  1470. {
  1471. int rval = 0;
  1472. uint32_t aen_code, aen_data;
  1473. aen_code = FCH_EVT_VENDOR_UNIQUE;
  1474. aen_data = evt->u.aenfx.evtcode;
  1475. switch (evt->u.aenfx.evtcode) {
  1476. case QLAFX00_MBA_PORT_UPDATE: /* Port database update */
  1477. if (evt->u.aenfx.mbx[1] == 0) {
  1478. if (evt->u.aenfx.mbx[2] == 1) {
  1479. if (!vha->flags.fw_tgt_reported)
  1480. vha->flags.fw_tgt_reported = 1;
  1481. atomic_set(&vha->loop_down_timer, 0);
  1482. atomic_set(&vha->loop_state, LOOP_UP);
  1483. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1484. qla2xxx_wake_dpc(vha);
  1485. } else if (evt->u.aenfx.mbx[2] == 2) {
  1486. qlafx00_tgt_detach(vha, evt->u.aenfx.mbx[3]);
  1487. }
  1488. } else if (evt->u.aenfx.mbx[1] == 0xffff) {
  1489. if (evt->u.aenfx.mbx[2] == 1) {
  1490. if (!vha->flags.fw_tgt_reported)
  1491. vha->flags.fw_tgt_reported = 1;
  1492. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1493. } else if (evt->u.aenfx.mbx[2] == 2) {
  1494. vha->device_flags |= DFLG_NO_CABLE;
  1495. qla2x00_mark_all_devices_lost(vha, 1);
  1496. }
  1497. }
  1498. break;
  1499. case QLAFX00_MBA_LINK_UP:
  1500. aen_code = FCH_EVT_LINKUP;
  1501. aen_data = 0;
  1502. break;
  1503. case QLAFX00_MBA_LINK_DOWN:
  1504. aen_code = FCH_EVT_LINKDOWN;
  1505. aen_data = 0;
  1506. break;
  1507. case QLAFX00_MBA_TEMP_OVER:
  1508. case QLAFX00_MBA_TEMP_CRIT: /* Critical temperature event */
  1509. ql_log(ql_log_info, vha, 0x5082,
  1510. "Process critical temperature event "
  1511. "aenmb[0]: %x\n",
  1512. evt->u.aenfx.evtcode);
  1513. scsi_block_requests(vha->host);
  1514. qlafx00_abort_isp_cleanup(vha, true);
  1515. scsi_unblock_requests(vha->host);
  1516. break;
  1517. }
  1518. fc_host_post_event(vha->host, fc_get_event_number(),
  1519. aen_code, aen_data);
  1520. return rval;
  1521. }
  1522. static void
  1523. qlafx00_update_host_attr(scsi_qla_host_t *vha, struct port_info_data *pinfo)
  1524. {
  1525. u64 port_name = 0, node_name = 0;
  1526. port_name = (unsigned long long)wwn_to_u64(pinfo->port_name);
  1527. node_name = (unsigned long long)wwn_to_u64(pinfo->node_name);
  1528. fc_host_node_name(vha->host) = node_name;
  1529. fc_host_port_name(vha->host) = port_name;
  1530. if (!pinfo->port_type)
  1531. vha->hw->current_topology = ISP_CFG_F;
  1532. if (pinfo->link_status == QLAFX00_LINK_STATUS_UP)
  1533. atomic_set(&vha->loop_state, LOOP_READY);
  1534. else if (pinfo->link_status == QLAFX00_LINK_STATUS_DOWN)
  1535. atomic_set(&vha->loop_state, LOOP_DOWN);
  1536. vha->hw->link_data_rate = (uint16_t)pinfo->link_config;
  1537. }
  1538. static void
  1539. qla2x00_fxdisc_iocb_timeout(void *data)
  1540. {
  1541. srb_t *sp = (srb_t *)data;
  1542. struct srb_iocb *lio = &sp->u.iocb_cmd;
  1543. complete(&lio->u.fxiocb.fxiocb_comp);
  1544. }
  1545. static void
  1546. qla2x00_fxdisc_sp_done(void *data, void *ptr, int res)
  1547. {
  1548. srb_t *sp = (srb_t *)ptr;
  1549. struct srb_iocb *lio = &sp->u.iocb_cmd;
  1550. complete(&lio->u.fxiocb.fxiocb_comp);
  1551. }
  1552. int
  1553. qlafx00_fx_disc(scsi_qla_host_t *vha, fc_port_t *fcport, uint16_t fx_type)
  1554. {
  1555. srb_t *sp;
  1556. struct srb_iocb *fdisc;
  1557. int rval = QLA_FUNCTION_FAILED;
  1558. struct qla_hw_data *ha = vha->hw;
  1559. struct host_system_info *phost_info;
  1560. struct register_host_info *preg_hsi;
  1561. struct new_utsname *p_sysid = NULL;
  1562. struct timeval tv;
  1563. sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
  1564. if (!sp)
  1565. goto done;
  1566. fdisc = &sp->u.iocb_cmd;
  1567. switch (fx_type) {
  1568. case FXDISC_GET_CONFIG_INFO:
  1569. fdisc->u.fxiocb.flags =
  1570. SRB_FXDISC_RESP_DMA_VALID;
  1571. fdisc->u.fxiocb.rsp_len = sizeof(struct config_info_data);
  1572. break;
  1573. case FXDISC_GET_PORT_INFO:
  1574. fdisc->u.fxiocb.flags =
  1575. SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
  1576. fdisc->u.fxiocb.rsp_len = QLAFX00_PORT_DATA_INFO;
  1577. fdisc->u.fxiocb.req_data = cpu_to_le32(fcport->port_id);
  1578. break;
  1579. case FXDISC_GET_TGT_NODE_INFO:
  1580. fdisc->u.fxiocb.flags =
  1581. SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
  1582. fdisc->u.fxiocb.rsp_len = QLAFX00_TGT_NODE_INFO;
  1583. fdisc->u.fxiocb.req_data = cpu_to_le32(fcport->tgt_id);
  1584. break;
  1585. case FXDISC_GET_TGT_NODE_LIST:
  1586. fdisc->u.fxiocb.flags =
  1587. SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
  1588. fdisc->u.fxiocb.rsp_len = QLAFX00_TGT_NODE_LIST_SIZE;
  1589. break;
  1590. case FXDISC_REG_HOST_INFO:
  1591. fdisc->u.fxiocb.flags = SRB_FXDISC_REQ_DMA_VALID;
  1592. fdisc->u.fxiocb.req_len = sizeof(struct register_host_info);
  1593. p_sysid = utsname();
  1594. if (!p_sysid) {
  1595. ql_log(ql_log_warn, vha, 0x303c,
  1596. "Not able to get the system informtion\n");
  1597. goto done_free_sp;
  1598. }
  1599. break;
  1600. default:
  1601. break;
  1602. }
  1603. if (fdisc->u.fxiocb.flags & SRB_FXDISC_REQ_DMA_VALID) {
  1604. fdisc->u.fxiocb.req_addr = dma_alloc_coherent(&ha->pdev->dev,
  1605. fdisc->u.fxiocb.req_len,
  1606. &fdisc->u.fxiocb.req_dma_handle, GFP_KERNEL);
  1607. if (!fdisc->u.fxiocb.req_addr)
  1608. goto done_free_sp;
  1609. if (fx_type == FXDISC_REG_HOST_INFO) {
  1610. preg_hsi = (struct register_host_info *)
  1611. fdisc->u.fxiocb.req_addr;
  1612. phost_info = &preg_hsi->hsi;
  1613. memset(preg_hsi, 0, sizeof(struct register_host_info));
  1614. phost_info->os_type = OS_TYPE_LINUX;
  1615. strncpy(phost_info->sysname,
  1616. p_sysid->sysname, SYSNAME_LENGTH);
  1617. strncpy(phost_info->nodename,
  1618. p_sysid->nodename, NODENAME_LENGTH);
  1619. strncpy(phost_info->release,
  1620. p_sysid->release, RELEASE_LENGTH);
  1621. strncpy(phost_info->version,
  1622. p_sysid->version, VERSION_LENGTH);
  1623. strncpy(phost_info->machine,
  1624. p_sysid->machine, MACHINE_LENGTH);
  1625. strncpy(phost_info->domainname,
  1626. p_sysid->domainname, DOMNAME_LENGTH);
  1627. strncpy(phost_info->hostdriver,
  1628. QLA2XXX_VERSION, VERSION_LENGTH);
  1629. do_gettimeofday(&tv);
  1630. preg_hsi->utc = (uint64_t)tv.tv_sec;
  1631. ql_dbg(ql_dbg_init, vha, 0x0149,
  1632. "ISP%04X: Host registration with firmware\n",
  1633. ha->pdev->device);
  1634. ql_dbg(ql_dbg_init, vha, 0x014a,
  1635. "os_type = '%d', sysname = '%s', nodname = '%s'\n",
  1636. phost_info->os_type,
  1637. phost_info->sysname,
  1638. phost_info->nodename);
  1639. ql_dbg(ql_dbg_init, vha, 0x014b,
  1640. "release = '%s', version = '%s'\n",
  1641. phost_info->release,
  1642. phost_info->version);
  1643. ql_dbg(ql_dbg_init, vha, 0x014c,
  1644. "machine = '%s' "
  1645. "domainname = '%s', hostdriver = '%s'\n",
  1646. phost_info->machine,
  1647. phost_info->domainname,
  1648. phost_info->hostdriver);
  1649. ql_dump_buffer(ql_dbg_init + ql_dbg_disc, vha, 0x014d,
  1650. (uint8_t *)phost_info,
  1651. sizeof(struct host_system_info));
  1652. }
  1653. }
  1654. if (fdisc->u.fxiocb.flags & SRB_FXDISC_RESP_DMA_VALID) {
  1655. fdisc->u.fxiocb.rsp_addr = dma_alloc_coherent(&ha->pdev->dev,
  1656. fdisc->u.fxiocb.rsp_len,
  1657. &fdisc->u.fxiocb.rsp_dma_handle, GFP_KERNEL);
  1658. if (!fdisc->u.fxiocb.rsp_addr)
  1659. goto done_unmap_req;
  1660. }
  1661. sp->type = SRB_FXIOCB_DCMD;
  1662. sp->name = "fxdisc";
  1663. qla2x00_init_timer(sp, FXDISC_TIMEOUT);
  1664. fdisc->timeout = qla2x00_fxdisc_iocb_timeout;
  1665. fdisc->u.fxiocb.req_func_type = cpu_to_le16(fx_type);
  1666. sp->done = qla2x00_fxdisc_sp_done;
  1667. rval = qla2x00_start_sp(sp);
  1668. if (rval != QLA_SUCCESS)
  1669. goto done_unmap_dma;
  1670. wait_for_completion(&fdisc->u.fxiocb.fxiocb_comp);
  1671. if (fx_type == FXDISC_GET_CONFIG_INFO) {
  1672. struct config_info_data *pinfo =
  1673. (struct config_info_data *) fdisc->u.fxiocb.rsp_addr;
  1674. memcpy(&vha->hw->mr.product_name, pinfo->product_name,
  1675. sizeof(vha->hw->mr.product_name));
  1676. memcpy(&vha->hw->mr.symbolic_name, pinfo->symbolic_name,
  1677. sizeof(vha->hw->mr.symbolic_name));
  1678. memcpy(&vha->hw->mr.serial_num, pinfo->serial_num,
  1679. sizeof(vha->hw->mr.serial_num));
  1680. memcpy(&vha->hw->mr.hw_version, pinfo->hw_version,
  1681. sizeof(vha->hw->mr.hw_version));
  1682. memcpy(&vha->hw->mr.fw_version, pinfo->fw_version,
  1683. sizeof(vha->hw->mr.fw_version));
  1684. strim(vha->hw->mr.fw_version);
  1685. memcpy(&vha->hw->mr.uboot_version, pinfo->uboot_version,
  1686. sizeof(vha->hw->mr.uboot_version));
  1687. memcpy(&vha->hw->mr.fru_serial_num, pinfo->fru_serial_num,
  1688. sizeof(vha->hw->mr.fru_serial_num));
  1689. vha->hw->mr.critical_temperature = pinfo->nominal_temp_value;
  1690. ha->mr.extended_io_enabled = (pinfo->enabled_capabilities &
  1691. QLAFX00_EXTENDED_IO_EN_MASK) != 0;
  1692. } else if (fx_type == FXDISC_GET_PORT_INFO) {
  1693. struct port_info_data *pinfo =
  1694. (struct port_info_data *) fdisc->u.fxiocb.rsp_addr;
  1695. memcpy(vha->node_name, pinfo->node_name, WWN_SIZE);
  1696. memcpy(vha->port_name, pinfo->port_name, WWN_SIZE);
  1697. vha->d_id.b.domain = pinfo->port_id[0];
  1698. vha->d_id.b.area = pinfo->port_id[1];
  1699. vha->d_id.b.al_pa = pinfo->port_id[2];
  1700. qlafx00_update_host_attr(vha, pinfo);
  1701. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0141,
  1702. (uint8_t *)pinfo, 16);
  1703. } else if (fx_type == FXDISC_GET_TGT_NODE_INFO) {
  1704. struct qlafx00_tgt_node_info *pinfo =
  1705. (struct qlafx00_tgt_node_info *) fdisc->u.fxiocb.rsp_addr;
  1706. memcpy(fcport->node_name, pinfo->tgt_node_wwnn, WWN_SIZE);
  1707. memcpy(fcport->port_name, pinfo->tgt_node_wwpn, WWN_SIZE);
  1708. fcport->port_type = FCT_TARGET;
  1709. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0144,
  1710. (uint8_t *)pinfo, 16);
  1711. } else if (fx_type == FXDISC_GET_TGT_NODE_LIST) {
  1712. struct qlafx00_tgt_node_info *pinfo =
  1713. (struct qlafx00_tgt_node_info *) fdisc->u.fxiocb.rsp_addr;
  1714. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0146,
  1715. (uint8_t *)pinfo, 16);
  1716. memcpy(vha->hw->gid_list, pinfo, QLAFX00_TGT_NODE_LIST_SIZE);
  1717. }
  1718. rval = le32_to_cpu(fdisc->u.fxiocb.result);
  1719. done_unmap_dma:
  1720. if (fdisc->u.fxiocb.rsp_addr)
  1721. dma_free_coherent(&ha->pdev->dev, fdisc->u.fxiocb.rsp_len,
  1722. fdisc->u.fxiocb.rsp_addr, fdisc->u.fxiocb.rsp_dma_handle);
  1723. done_unmap_req:
  1724. if (fdisc->u.fxiocb.req_addr)
  1725. dma_free_coherent(&ha->pdev->dev, fdisc->u.fxiocb.req_len,
  1726. fdisc->u.fxiocb.req_addr, fdisc->u.fxiocb.req_dma_handle);
  1727. done_free_sp:
  1728. sp->free(vha, sp);
  1729. done:
  1730. return rval;
  1731. }
  1732. static void
  1733. qlafx00_abort_iocb_timeout(void *data)
  1734. {
  1735. srb_t *sp = (srb_t *)data;
  1736. struct srb_iocb *abt = &sp->u.iocb_cmd;
  1737. abt->u.abt.comp_status = cpu_to_le16((uint16_t)CS_TIMEOUT);
  1738. complete(&abt->u.abt.comp);
  1739. }
  1740. static void
  1741. qlafx00_abort_sp_done(void *data, void *ptr, int res)
  1742. {
  1743. srb_t *sp = (srb_t *)ptr;
  1744. struct srb_iocb *abt = &sp->u.iocb_cmd;
  1745. complete(&abt->u.abt.comp);
  1746. }
  1747. static int
  1748. qlafx00_async_abt_cmd(srb_t *cmd_sp)
  1749. {
  1750. scsi_qla_host_t *vha = cmd_sp->fcport->vha;
  1751. fc_port_t *fcport = cmd_sp->fcport;
  1752. struct srb_iocb *abt_iocb;
  1753. srb_t *sp;
  1754. int rval = QLA_FUNCTION_FAILED;
  1755. sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
  1756. if (!sp)
  1757. goto done;
  1758. abt_iocb = &sp->u.iocb_cmd;
  1759. sp->type = SRB_ABT_CMD;
  1760. sp->name = "abort";
  1761. qla2x00_init_timer(sp, FXDISC_TIMEOUT);
  1762. abt_iocb->u.abt.cmd_hndl = cmd_sp->handle;
  1763. sp->done = qlafx00_abort_sp_done;
  1764. abt_iocb->timeout = qlafx00_abort_iocb_timeout;
  1765. init_completion(&abt_iocb->u.abt.comp);
  1766. rval = qla2x00_start_sp(sp);
  1767. if (rval != QLA_SUCCESS)
  1768. goto done_free_sp;
  1769. ql_dbg(ql_dbg_async, vha, 0x507c,
  1770. "Abort command issued - hdl=%x, target_id=%x\n",
  1771. cmd_sp->handle, fcport->tgt_id);
  1772. wait_for_completion(&abt_iocb->u.abt.comp);
  1773. rval = abt_iocb->u.abt.comp_status == CS_COMPLETE ?
  1774. QLA_SUCCESS : QLA_FUNCTION_FAILED;
  1775. done_free_sp:
  1776. sp->free(vha, sp);
  1777. done:
  1778. return rval;
  1779. }
  1780. int
  1781. qlafx00_abort_command(srb_t *sp)
  1782. {
  1783. unsigned long flags = 0;
  1784. uint32_t handle;
  1785. fc_port_t *fcport = sp->fcport;
  1786. struct scsi_qla_host *vha = fcport->vha;
  1787. struct qla_hw_data *ha = vha->hw;
  1788. struct req_que *req = vha->req;
  1789. spin_lock_irqsave(&ha->hardware_lock, flags);
  1790. for (handle = 1; handle < DEFAULT_OUTSTANDING_COMMANDS; handle++) {
  1791. if (req->outstanding_cmds[handle] == sp)
  1792. break;
  1793. }
  1794. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1795. if (handle == DEFAULT_OUTSTANDING_COMMANDS) {
  1796. /* Command not found. */
  1797. return QLA_FUNCTION_FAILED;
  1798. }
  1799. return qlafx00_async_abt_cmd(sp);
  1800. }
  1801. /*
  1802. * qlafx00_initialize_adapter
  1803. * Initialize board.
  1804. *
  1805. * Input:
  1806. * ha = adapter block pointer.
  1807. *
  1808. * Returns:
  1809. * 0 = success
  1810. */
  1811. int
  1812. qlafx00_initialize_adapter(scsi_qla_host_t *vha)
  1813. {
  1814. int rval;
  1815. struct qla_hw_data *ha = vha->hw;
  1816. uint32_t tempc;
  1817. /* Clear adapter flags. */
  1818. vha->flags.online = 0;
  1819. ha->flags.chip_reset_done = 0;
  1820. vha->flags.reset_active = 0;
  1821. ha->flags.pci_channel_io_perm_failure = 0;
  1822. ha->flags.eeh_busy = 0;
  1823. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  1824. atomic_set(&vha->loop_state, LOOP_DOWN);
  1825. vha->device_flags = DFLG_NO_CABLE;
  1826. vha->dpc_flags = 0;
  1827. vha->flags.management_server_logged_in = 0;
  1828. vha->marker_needed = 0;
  1829. ha->isp_abort_cnt = 0;
  1830. ha->beacon_blink_led = 0;
  1831. set_bit(0, ha->req_qid_map);
  1832. set_bit(0, ha->rsp_qid_map);
  1833. ql_dbg(ql_dbg_init, vha, 0x0147,
  1834. "Configuring PCI space...\n");
  1835. rval = ha->isp_ops->pci_config(vha);
  1836. if (rval) {
  1837. ql_log(ql_log_warn, vha, 0x0148,
  1838. "Unable to configure PCI space.\n");
  1839. return rval;
  1840. }
  1841. rval = qlafx00_init_fw_ready(vha);
  1842. if (rval != QLA_SUCCESS)
  1843. return rval;
  1844. qlafx00_save_queue_ptrs(vha);
  1845. rval = qlafx00_config_queues(vha);
  1846. if (rval != QLA_SUCCESS)
  1847. return rval;
  1848. /*
  1849. * Allocate the array of outstanding commands
  1850. * now that we know the firmware resources.
  1851. */
  1852. rval = qla2x00_alloc_outstanding_cmds(ha, vha->req);
  1853. if (rval != QLA_SUCCESS)
  1854. return rval;
  1855. rval = qla2x00_init_rings(vha);
  1856. ha->flags.chip_reset_done = 1;
  1857. tempc = QLAFX00_GET_TEMPERATURE(ha);
  1858. ql_dbg(ql_dbg_init, vha, 0x0152,
  1859. "ISPFx00(%s): Critical temp timer, current SOC temperature: 0x%x\n",
  1860. __func__, tempc);
  1861. return rval;
  1862. }
  1863. uint32_t
  1864. qlafx00_fw_state_show(struct device *dev, struct device_attribute *attr,
  1865. char *buf)
  1866. {
  1867. scsi_qla_host_t *vha = shost_priv(class_to_shost(dev));
  1868. int rval = QLA_FUNCTION_FAILED;
  1869. uint32_t state[1];
  1870. if (qla2x00_reset_active(vha))
  1871. ql_log(ql_log_warn, vha, 0x70ce,
  1872. "ISP reset active.\n");
  1873. else if (!vha->hw->flags.eeh_busy) {
  1874. rval = qlafx00_get_firmware_state(vha, state);
  1875. }
  1876. if (rval != QLA_SUCCESS)
  1877. memset(state, -1, sizeof(state));
  1878. return state[0];
  1879. }
  1880. void
  1881. qlafx00_get_host_speed(struct Scsi_Host *shost)
  1882. {
  1883. struct qla_hw_data *ha = ((struct scsi_qla_host *)
  1884. (shost_priv(shost)))->hw;
  1885. u32 speed = FC_PORTSPEED_UNKNOWN;
  1886. switch (ha->link_data_rate) {
  1887. case QLAFX00_PORT_SPEED_2G:
  1888. speed = FC_PORTSPEED_2GBIT;
  1889. break;
  1890. case QLAFX00_PORT_SPEED_4G:
  1891. speed = FC_PORTSPEED_4GBIT;
  1892. break;
  1893. case QLAFX00_PORT_SPEED_8G:
  1894. speed = FC_PORTSPEED_8GBIT;
  1895. break;
  1896. case QLAFX00_PORT_SPEED_10G:
  1897. speed = FC_PORTSPEED_10GBIT;
  1898. break;
  1899. }
  1900. fc_host_speed(shost) = speed;
  1901. }
  1902. /** QLAFX00 specific ISR implementation functions */
  1903. static inline void
  1904. qlafx00_handle_sense(srb_t *sp, uint8_t *sense_data, uint32_t par_sense_len,
  1905. uint32_t sense_len, struct rsp_que *rsp, int res)
  1906. {
  1907. struct scsi_qla_host *vha = sp->fcport->vha;
  1908. struct scsi_cmnd *cp = GET_CMD_SP(sp);
  1909. uint32_t track_sense_len;
  1910. SET_FW_SENSE_LEN(sp, sense_len);
  1911. if (sense_len >= SCSI_SENSE_BUFFERSIZE)
  1912. sense_len = SCSI_SENSE_BUFFERSIZE;
  1913. SET_CMD_SENSE_LEN(sp, sense_len);
  1914. SET_CMD_SENSE_PTR(sp, cp->sense_buffer);
  1915. track_sense_len = sense_len;
  1916. if (sense_len > par_sense_len)
  1917. sense_len = par_sense_len;
  1918. memcpy(cp->sense_buffer, sense_data, sense_len);
  1919. SET_FW_SENSE_LEN(sp, GET_FW_SENSE_LEN(sp) - sense_len);
  1920. SET_CMD_SENSE_PTR(sp, cp->sense_buffer + sense_len);
  1921. track_sense_len -= sense_len;
  1922. SET_CMD_SENSE_LEN(sp, track_sense_len);
  1923. ql_dbg(ql_dbg_io, vha, 0x304d,
  1924. "sense_len=0x%x par_sense_len=0x%x track_sense_len=0x%x.\n",
  1925. sense_len, par_sense_len, track_sense_len);
  1926. if (GET_FW_SENSE_LEN(sp) > 0) {
  1927. rsp->status_srb = sp;
  1928. cp->result = res;
  1929. }
  1930. if (sense_len) {
  1931. ql_dbg(ql_dbg_io + ql_dbg_buffer, vha, 0x3039,
  1932. "Check condition Sense data, nexus%ld:%d:%d cmd=%p.\n",
  1933. sp->fcport->vha->host_no, cp->device->id, cp->device->lun,
  1934. cp);
  1935. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x3049,
  1936. cp->sense_buffer, sense_len);
  1937. }
  1938. }
  1939. static void
  1940. qlafx00_tm_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1941. struct tsk_mgmt_entry_fx00 *pkt, srb_t *sp,
  1942. __le16 sstatus, __le16 cpstatus)
  1943. {
  1944. struct srb_iocb *tmf;
  1945. tmf = &sp->u.iocb_cmd;
  1946. if (cpstatus != cpu_to_le16((uint16_t)CS_COMPLETE) ||
  1947. (sstatus & cpu_to_le16((uint16_t)SS_RESPONSE_INFO_LEN_VALID)))
  1948. cpstatus = cpu_to_le16((uint16_t)CS_INCOMPLETE);
  1949. tmf->u.tmf.comp_status = cpstatus;
  1950. sp->done(vha, sp, 0);
  1951. }
  1952. static void
  1953. qlafx00_abort_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1954. struct abort_iocb_entry_fx00 *pkt)
  1955. {
  1956. const char func[] = "ABT_IOCB";
  1957. srb_t *sp;
  1958. struct srb_iocb *abt;
  1959. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1960. if (!sp)
  1961. return;
  1962. abt = &sp->u.iocb_cmd;
  1963. abt->u.abt.comp_status = pkt->tgt_id_sts;
  1964. sp->done(vha, sp, 0);
  1965. }
  1966. static void
  1967. qlafx00_ioctl_iosb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1968. struct ioctl_iocb_entry_fx00 *pkt)
  1969. {
  1970. const char func[] = "IOSB_IOCB";
  1971. srb_t *sp;
  1972. struct fc_bsg_job *bsg_job;
  1973. struct srb_iocb *iocb_job;
  1974. int res;
  1975. struct qla_mt_iocb_rsp_fx00 fstatus;
  1976. uint8_t *fw_sts_ptr;
  1977. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1978. if (!sp)
  1979. return;
  1980. if (sp->type == SRB_FXIOCB_DCMD) {
  1981. iocb_job = &sp->u.iocb_cmd;
  1982. iocb_job->u.fxiocb.seq_number = pkt->seq_no;
  1983. iocb_job->u.fxiocb.fw_flags = pkt->fw_iotcl_flags;
  1984. iocb_job->u.fxiocb.result = pkt->status;
  1985. if (iocb_job->u.fxiocb.flags & SRB_FXDISC_RSP_DWRD_VALID)
  1986. iocb_job->u.fxiocb.req_data =
  1987. pkt->dataword_r;
  1988. } else {
  1989. bsg_job = sp->u.bsg_job;
  1990. memset(&fstatus, 0, sizeof(struct qla_mt_iocb_rsp_fx00));
  1991. fstatus.reserved_1 = pkt->reserved_0;
  1992. fstatus.func_type = pkt->comp_func_num;
  1993. fstatus.ioctl_flags = pkt->fw_iotcl_flags;
  1994. fstatus.ioctl_data = pkt->dataword_r;
  1995. fstatus.adapid = pkt->adapid;
  1996. fstatus.adapid_hi = pkt->adapid_hi;
  1997. fstatus.reserved_2 = pkt->reserved_1;
  1998. fstatus.res_count = pkt->residuallen;
  1999. fstatus.status = pkt->status;
  2000. fstatus.seq_number = pkt->seq_no;
  2001. memcpy(fstatus.reserved_3,
  2002. pkt->reserved_2, 20 * sizeof(uint8_t));
  2003. fw_sts_ptr = ((uint8_t *)bsg_job->req->sense) +
  2004. sizeof(struct fc_bsg_reply);
  2005. memcpy(fw_sts_ptr, (uint8_t *)&fstatus,
  2006. sizeof(struct qla_mt_iocb_rsp_fx00));
  2007. bsg_job->reply_len = sizeof(struct fc_bsg_reply) +
  2008. sizeof(struct qla_mt_iocb_rsp_fx00) + sizeof(uint8_t);
  2009. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  2010. sp->fcport->vha, 0x5080,
  2011. (uint8_t *)pkt, sizeof(struct ioctl_iocb_entry_fx00));
  2012. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  2013. sp->fcport->vha, 0x5074,
  2014. (uint8_t *)fw_sts_ptr, sizeof(struct qla_mt_iocb_rsp_fx00));
  2015. res = bsg_job->reply->result = DID_OK << 16;
  2016. bsg_job->reply->reply_payload_rcv_len =
  2017. bsg_job->reply_payload.payload_len;
  2018. }
  2019. sp->done(vha, sp, res);
  2020. }
  2021. /**
  2022. * qlafx00_status_entry() - Process a Status IOCB entry.
  2023. * @ha: SCSI driver HA context
  2024. * @pkt: Entry pointer
  2025. */
  2026. static void
  2027. qlafx00_status_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, void *pkt)
  2028. {
  2029. srb_t *sp;
  2030. fc_port_t *fcport;
  2031. struct scsi_cmnd *cp;
  2032. struct sts_entry_fx00 *sts;
  2033. __le16 comp_status;
  2034. __le16 scsi_status;
  2035. uint16_t ox_id;
  2036. __le16 lscsi_status;
  2037. int32_t resid;
  2038. uint32_t sense_len, par_sense_len, rsp_info_len, resid_len,
  2039. fw_resid_len;
  2040. uint8_t *rsp_info = NULL, *sense_data = NULL;
  2041. struct qla_hw_data *ha = vha->hw;
  2042. uint32_t hindex, handle;
  2043. uint16_t que;
  2044. struct req_que *req;
  2045. int logit = 1;
  2046. int res = 0;
  2047. sts = (struct sts_entry_fx00 *) pkt;
  2048. comp_status = sts->comp_status;
  2049. scsi_status = sts->scsi_status & cpu_to_le16((uint16_t)SS_MASK);
  2050. hindex = sts->handle;
  2051. handle = LSW(hindex);
  2052. que = MSW(hindex);
  2053. req = ha->req_q_map[que];
  2054. /* Validate handle. */
  2055. if (handle < req->num_outstanding_cmds)
  2056. sp = req->outstanding_cmds[handle];
  2057. else
  2058. sp = NULL;
  2059. if (sp == NULL) {
  2060. ql_dbg(ql_dbg_io, vha, 0x3034,
  2061. "Invalid status handle (0x%x).\n", handle);
  2062. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2063. qla2xxx_wake_dpc(vha);
  2064. return;
  2065. }
  2066. if (sp->type == SRB_TM_CMD) {
  2067. req->outstanding_cmds[handle] = NULL;
  2068. qlafx00_tm_iocb_entry(vha, req, pkt, sp,
  2069. scsi_status, comp_status);
  2070. return;
  2071. }
  2072. /* Fast path completion. */
  2073. if (comp_status == CS_COMPLETE && scsi_status == 0) {
  2074. qla2x00_do_host_ramp_up(vha);
  2075. qla2x00_process_completed_request(vha, req, handle);
  2076. return;
  2077. }
  2078. req->outstanding_cmds[handle] = NULL;
  2079. cp = GET_CMD_SP(sp);
  2080. if (cp == NULL) {
  2081. ql_dbg(ql_dbg_io, vha, 0x3048,
  2082. "Command already returned (0x%x/%p).\n",
  2083. handle, sp);
  2084. return;
  2085. }
  2086. lscsi_status = scsi_status & cpu_to_le16((uint16_t)STATUS_MASK);
  2087. fcport = sp->fcport;
  2088. ox_id = 0;
  2089. sense_len = par_sense_len = rsp_info_len = resid_len =
  2090. fw_resid_len = 0;
  2091. if (scsi_status & cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID))
  2092. sense_len = sts->sense_len;
  2093. if (scsi_status & cpu_to_le16(((uint16_t)SS_RESIDUAL_UNDER
  2094. | (uint16_t)SS_RESIDUAL_OVER)))
  2095. resid_len = le32_to_cpu(sts->residual_len);
  2096. if (comp_status == cpu_to_le16((uint16_t)CS_DATA_UNDERRUN))
  2097. fw_resid_len = le32_to_cpu(sts->residual_len);
  2098. rsp_info = sense_data = sts->data;
  2099. par_sense_len = sizeof(sts->data);
  2100. /* Check for overrun. */
  2101. if (comp_status == CS_COMPLETE &&
  2102. scsi_status & cpu_to_le16((uint16_t)SS_RESIDUAL_OVER))
  2103. comp_status = cpu_to_le16((uint16_t)CS_DATA_OVERRUN);
  2104. /*
  2105. * Based on Host and scsi status generate status code for Linux
  2106. */
  2107. switch (le16_to_cpu(comp_status)) {
  2108. case CS_COMPLETE:
  2109. case CS_QUEUE_FULL:
  2110. if (scsi_status == 0) {
  2111. res = DID_OK << 16;
  2112. break;
  2113. }
  2114. if (scsi_status & cpu_to_le16(((uint16_t)SS_RESIDUAL_UNDER
  2115. | (uint16_t)SS_RESIDUAL_OVER))) {
  2116. resid = resid_len;
  2117. scsi_set_resid(cp, resid);
  2118. if (!lscsi_status &&
  2119. ((unsigned)(scsi_bufflen(cp) - resid) <
  2120. cp->underflow)) {
  2121. ql_dbg(ql_dbg_io, fcport->vha, 0x3050,
  2122. "Mid-layer underflow "
  2123. "detected (0x%x of 0x%x bytes).\n",
  2124. resid, scsi_bufflen(cp));
  2125. res = DID_ERROR << 16;
  2126. break;
  2127. }
  2128. }
  2129. res = DID_OK << 16 | le16_to_cpu(lscsi_status);
  2130. if (lscsi_status ==
  2131. cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL)) {
  2132. ql_dbg(ql_dbg_io, fcport->vha, 0x3051,
  2133. "QUEUE FULL detected.\n");
  2134. break;
  2135. }
  2136. logit = 0;
  2137. if (lscsi_status != cpu_to_le16((uint16_t)SS_CHECK_CONDITION))
  2138. break;
  2139. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  2140. if (!(scsi_status & cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID)))
  2141. break;
  2142. qlafx00_handle_sense(sp, sense_data, par_sense_len, sense_len,
  2143. rsp, res);
  2144. break;
  2145. case CS_DATA_UNDERRUN:
  2146. /* Use F/W calculated residual length. */
  2147. if (IS_FWI2_CAPABLE(ha) || IS_QLAFX00(ha))
  2148. resid = fw_resid_len;
  2149. else
  2150. resid = resid_len;
  2151. scsi_set_resid(cp, resid);
  2152. if (scsi_status & cpu_to_le16((uint16_t)SS_RESIDUAL_UNDER)) {
  2153. if ((IS_FWI2_CAPABLE(ha) || IS_QLAFX00(ha))
  2154. && fw_resid_len != resid_len) {
  2155. ql_dbg(ql_dbg_io, fcport->vha, 0x3052,
  2156. "Dropped frame(s) detected "
  2157. "(0x%x of 0x%x bytes).\n",
  2158. resid, scsi_bufflen(cp));
  2159. res = DID_ERROR << 16 |
  2160. le16_to_cpu(lscsi_status);
  2161. goto check_scsi_status;
  2162. }
  2163. if (!lscsi_status &&
  2164. ((unsigned)(scsi_bufflen(cp) - resid) <
  2165. cp->underflow)) {
  2166. ql_dbg(ql_dbg_io, fcport->vha, 0x3053,
  2167. "Mid-layer underflow "
  2168. "detected (0x%x of 0x%x bytes, "
  2169. "cp->underflow: 0x%x).\n",
  2170. resid, scsi_bufflen(cp), cp->underflow);
  2171. res = DID_ERROR << 16;
  2172. break;
  2173. }
  2174. } else if (lscsi_status !=
  2175. cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL) &&
  2176. lscsi_status != cpu_to_le16((uint16_t)SAM_STAT_BUSY)) {
  2177. /*
  2178. * scsi status of task set and busy are considered
  2179. * to be task not completed.
  2180. */
  2181. ql_dbg(ql_dbg_io, fcport->vha, 0x3054,
  2182. "Dropped frame(s) detected (0x%x "
  2183. "of 0x%x bytes).\n", resid,
  2184. scsi_bufflen(cp));
  2185. res = DID_ERROR << 16 | le16_to_cpu(lscsi_status);
  2186. goto check_scsi_status;
  2187. } else {
  2188. ql_dbg(ql_dbg_io, fcport->vha, 0x3055,
  2189. "scsi_status: 0x%x, lscsi_status: 0x%x\n",
  2190. scsi_status, lscsi_status);
  2191. }
  2192. res = DID_OK << 16 | le16_to_cpu(lscsi_status);
  2193. logit = 0;
  2194. check_scsi_status:
  2195. /*
  2196. * Check to see if SCSI Status is non zero. If so report SCSI
  2197. * Status.
  2198. */
  2199. if (lscsi_status != 0) {
  2200. if (lscsi_status ==
  2201. cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL)) {
  2202. ql_dbg(ql_dbg_io, fcport->vha, 0x3056,
  2203. "QUEUE FULL detected.\n");
  2204. logit = 1;
  2205. break;
  2206. }
  2207. if (lscsi_status !=
  2208. cpu_to_le16((uint16_t)SS_CHECK_CONDITION))
  2209. break;
  2210. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  2211. if (!(scsi_status &
  2212. cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID)))
  2213. break;
  2214. qlafx00_handle_sense(sp, sense_data, par_sense_len,
  2215. sense_len, rsp, res);
  2216. }
  2217. break;
  2218. case CS_PORT_LOGGED_OUT:
  2219. case CS_PORT_CONFIG_CHG:
  2220. case CS_PORT_BUSY:
  2221. case CS_INCOMPLETE:
  2222. case CS_PORT_UNAVAILABLE:
  2223. case CS_TIMEOUT:
  2224. case CS_RESET:
  2225. /*
  2226. * We are going to have the fc class block the rport
  2227. * while we try to recover so instruct the mid layer
  2228. * to requeue until the class decides how to handle this.
  2229. */
  2230. res = DID_TRANSPORT_DISRUPTED << 16;
  2231. ql_dbg(ql_dbg_io, fcport->vha, 0x3057,
  2232. "Port down status: port-state=0x%x.\n",
  2233. atomic_read(&fcport->state));
  2234. if (atomic_read(&fcport->state) == FCS_ONLINE)
  2235. qla2x00_mark_device_lost(fcport->vha, fcport, 1, 1);
  2236. break;
  2237. case CS_ABORTED:
  2238. res = DID_RESET << 16;
  2239. break;
  2240. default:
  2241. res = DID_ERROR << 16;
  2242. break;
  2243. }
  2244. if (logit)
  2245. ql_dbg(ql_dbg_io, fcport->vha, 0x3058,
  2246. "FCP command status: 0x%x-0x%x (0x%x) nexus=%ld:%d:%d "
  2247. "tgt_id: 0x%x lscsi_status: 0x%x cdb=%10phN len=0x%x "
  2248. "rsp_info=0x%x resid=0x%x fw_resid=0x%x sense_len=0x%x, "
  2249. "par_sense_len=0x%x, rsp_info_len=0x%x\n",
  2250. comp_status, scsi_status, res, vha->host_no,
  2251. cp->device->id, cp->device->lun, fcport->tgt_id,
  2252. lscsi_status, cp->cmnd, scsi_bufflen(cp),
  2253. rsp_info_len, resid_len, fw_resid_len, sense_len,
  2254. par_sense_len, rsp_info_len);
  2255. if (!res)
  2256. qla2x00_do_host_ramp_up(vha);
  2257. if (rsp->status_srb == NULL)
  2258. sp->done(ha, sp, res);
  2259. }
  2260. /**
  2261. * qlafx00_status_cont_entry() - Process a Status Continuations entry.
  2262. * @ha: SCSI driver HA context
  2263. * @pkt: Entry pointer
  2264. *
  2265. * Extended sense data.
  2266. */
  2267. static void
  2268. qlafx00_status_cont_entry(struct rsp_que *rsp, sts_cont_entry_t *pkt)
  2269. {
  2270. uint8_t sense_sz = 0;
  2271. struct qla_hw_data *ha = rsp->hw;
  2272. struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev);
  2273. srb_t *sp = rsp->status_srb;
  2274. struct scsi_cmnd *cp;
  2275. uint32_t sense_len;
  2276. uint8_t *sense_ptr;
  2277. if (!sp) {
  2278. ql_dbg(ql_dbg_io, vha, 0x3037,
  2279. "no SP, sp = %p\n", sp);
  2280. return;
  2281. }
  2282. if (!GET_FW_SENSE_LEN(sp)) {
  2283. ql_dbg(ql_dbg_io, vha, 0x304b,
  2284. "no fw sense data, sp = %p\n", sp);
  2285. return;
  2286. }
  2287. cp = GET_CMD_SP(sp);
  2288. if (cp == NULL) {
  2289. ql_log(ql_log_warn, vha, 0x303b,
  2290. "cmd is NULL: already returned to OS (sp=%p).\n", sp);
  2291. rsp->status_srb = NULL;
  2292. return;
  2293. }
  2294. if (!GET_CMD_SENSE_LEN(sp)) {
  2295. ql_dbg(ql_dbg_io, vha, 0x304c,
  2296. "no sense data, sp = %p\n", sp);
  2297. } else {
  2298. sense_len = GET_CMD_SENSE_LEN(sp);
  2299. sense_ptr = GET_CMD_SENSE_PTR(sp);
  2300. ql_dbg(ql_dbg_io, vha, 0x304f,
  2301. "sp=%p sense_len=0x%x sense_ptr=%p.\n",
  2302. sp, sense_len, sense_ptr);
  2303. if (sense_len > sizeof(pkt->data))
  2304. sense_sz = sizeof(pkt->data);
  2305. else
  2306. sense_sz = sense_len;
  2307. /* Move sense data. */
  2308. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x304e,
  2309. (uint8_t *)pkt, sizeof(sts_cont_entry_t));
  2310. memcpy(sense_ptr, pkt->data, sense_sz);
  2311. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x304a,
  2312. sense_ptr, sense_sz);
  2313. sense_len -= sense_sz;
  2314. sense_ptr += sense_sz;
  2315. SET_CMD_SENSE_PTR(sp, sense_ptr);
  2316. SET_CMD_SENSE_LEN(sp, sense_len);
  2317. }
  2318. sense_len = GET_FW_SENSE_LEN(sp);
  2319. sense_len = (sense_len > sizeof(pkt->data)) ?
  2320. (sense_len - sizeof(pkt->data)) : 0;
  2321. SET_FW_SENSE_LEN(sp, sense_len);
  2322. /* Place command on done queue. */
  2323. if (sense_len == 0) {
  2324. rsp->status_srb = NULL;
  2325. sp->done(ha, sp, cp->result);
  2326. }
  2327. }
  2328. /**
  2329. * qlafx00_multistatus_entry() - Process Multi response queue entries.
  2330. * @ha: SCSI driver HA context
  2331. */
  2332. static void
  2333. qlafx00_multistatus_entry(struct scsi_qla_host *vha,
  2334. struct rsp_que *rsp, void *pkt)
  2335. {
  2336. srb_t *sp;
  2337. struct multi_sts_entry_fx00 *stsmfx;
  2338. struct qla_hw_data *ha = vha->hw;
  2339. uint32_t handle, hindex, handle_count, i;
  2340. uint16_t que;
  2341. struct req_que *req;
  2342. __le32 *handle_ptr;
  2343. stsmfx = (struct multi_sts_entry_fx00 *) pkt;
  2344. handle_count = stsmfx->handle_count;
  2345. if (handle_count > MAX_HANDLE_COUNT) {
  2346. ql_dbg(ql_dbg_io, vha, 0x3035,
  2347. "Invalid handle count (0x%x).\n", handle_count);
  2348. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2349. qla2xxx_wake_dpc(vha);
  2350. return;
  2351. }
  2352. handle_ptr = &stsmfx->handles[0];
  2353. for (i = 0; i < handle_count; i++) {
  2354. hindex = le32_to_cpu(*handle_ptr);
  2355. handle = LSW(hindex);
  2356. que = MSW(hindex);
  2357. req = ha->req_q_map[que];
  2358. /* Validate handle. */
  2359. if (handle < req->num_outstanding_cmds)
  2360. sp = req->outstanding_cmds[handle];
  2361. else
  2362. sp = NULL;
  2363. if (sp == NULL) {
  2364. ql_dbg(ql_dbg_io, vha, 0x3044,
  2365. "Invalid status handle (0x%x).\n", handle);
  2366. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2367. qla2xxx_wake_dpc(vha);
  2368. return;
  2369. }
  2370. qla2x00_process_completed_request(vha, req, handle);
  2371. handle_ptr++;
  2372. }
  2373. }
  2374. /**
  2375. * qlafx00_error_entry() - Process an error entry.
  2376. * @ha: SCSI driver HA context
  2377. * @pkt: Entry pointer
  2378. */
  2379. static void
  2380. qlafx00_error_entry(scsi_qla_host_t *vha, struct rsp_que *rsp,
  2381. struct sts_entry_fx00 *pkt, uint8_t estatus, uint8_t etype)
  2382. {
  2383. srb_t *sp;
  2384. struct qla_hw_data *ha = vha->hw;
  2385. const char func[] = "ERROR-IOCB";
  2386. uint16_t que = MSW(pkt->handle);
  2387. struct req_que *req = NULL;
  2388. int res = DID_ERROR << 16;
  2389. ql_dbg(ql_dbg_async, vha, 0x507f,
  2390. "type of error status in response: 0x%x\n", estatus);
  2391. req = ha->req_q_map[que];
  2392. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  2393. if (sp) {
  2394. sp->done(ha, sp, res);
  2395. return;
  2396. }
  2397. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2398. qla2xxx_wake_dpc(vha);
  2399. }
  2400. /**
  2401. * qlafx00_process_response_queue() - Process response queue entries.
  2402. * @ha: SCSI driver HA context
  2403. */
  2404. static void
  2405. qlafx00_process_response_queue(struct scsi_qla_host *vha,
  2406. struct rsp_que *rsp)
  2407. {
  2408. struct sts_entry_fx00 *pkt;
  2409. response_t *lptr;
  2410. while (RD_REG_DWORD((void __iomem *)&(rsp->ring_ptr->signature)) !=
  2411. RESPONSE_PROCESSED) {
  2412. lptr = rsp->ring_ptr;
  2413. memcpy_fromio(rsp->rsp_pkt, (void __iomem *)lptr,
  2414. sizeof(rsp->rsp_pkt));
  2415. pkt = (struct sts_entry_fx00 *)rsp->rsp_pkt;
  2416. rsp->ring_index++;
  2417. if (rsp->ring_index == rsp->length) {
  2418. rsp->ring_index = 0;
  2419. rsp->ring_ptr = rsp->ring;
  2420. } else {
  2421. rsp->ring_ptr++;
  2422. }
  2423. if (pkt->entry_status != 0 &&
  2424. pkt->entry_type != IOCTL_IOSB_TYPE_FX00) {
  2425. qlafx00_error_entry(vha, rsp,
  2426. (struct sts_entry_fx00 *)pkt, pkt->entry_status,
  2427. pkt->entry_type);
  2428. goto next_iter;
  2429. continue;
  2430. }
  2431. switch (pkt->entry_type) {
  2432. case STATUS_TYPE_FX00:
  2433. qlafx00_status_entry(vha, rsp, pkt);
  2434. break;
  2435. case STATUS_CONT_TYPE_FX00:
  2436. qlafx00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
  2437. break;
  2438. case MULTI_STATUS_TYPE_FX00:
  2439. qlafx00_multistatus_entry(vha, rsp, pkt);
  2440. break;
  2441. case ABORT_IOCB_TYPE_FX00:
  2442. qlafx00_abort_iocb_entry(vha, rsp->req,
  2443. (struct abort_iocb_entry_fx00 *)pkt);
  2444. break;
  2445. case IOCTL_IOSB_TYPE_FX00:
  2446. qlafx00_ioctl_iosb_entry(vha, rsp->req,
  2447. (struct ioctl_iocb_entry_fx00 *)pkt);
  2448. break;
  2449. default:
  2450. /* Type Not Supported. */
  2451. ql_dbg(ql_dbg_async, vha, 0x5081,
  2452. "Received unknown response pkt type %x "
  2453. "entry status=%x.\n",
  2454. pkt->entry_type, pkt->entry_status);
  2455. break;
  2456. }
  2457. next_iter:
  2458. WRT_REG_DWORD((void __iomem *)&lptr->signature,
  2459. RESPONSE_PROCESSED);
  2460. wmb();
  2461. }
  2462. /* Adjust ring index */
  2463. WRT_REG_DWORD(rsp->rsp_q_out, rsp->ring_index);
  2464. }
  2465. /**
  2466. * qlafx00_async_event() - Process aynchronous events.
  2467. * @ha: SCSI driver HA context
  2468. */
  2469. static void
  2470. qlafx00_async_event(scsi_qla_host_t *vha)
  2471. {
  2472. struct qla_hw_data *ha = vha->hw;
  2473. struct device_reg_fx00 __iomem *reg;
  2474. int data_size = 1;
  2475. reg = &ha->iobase->ispfx00;
  2476. /* Setup to process RIO completion. */
  2477. switch (ha->aenmb[0]) {
  2478. case QLAFX00_MBA_SYSTEM_ERR: /* System Error */
  2479. ql_log(ql_log_warn, vha, 0x5079,
  2480. "ISP System Error - mbx1=%x\n", ha->aenmb[0]);
  2481. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2482. break;
  2483. case QLAFX00_MBA_SHUTDOWN_RQSTD: /* Shutdown requested */
  2484. ql_dbg(ql_dbg_async, vha, 0x5076,
  2485. "Asynchronous FW shutdown requested.\n");
  2486. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2487. qla2xxx_wake_dpc(vha);
  2488. break;
  2489. case QLAFX00_MBA_PORT_UPDATE: /* Port database update */
  2490. ha->aenmb[1] = RD_REG_WORD(&reg->aenmailbox1);
  2491. ha->aenmb[2] = RD_REG_WORD(&reg->aenmailbox2);
  2492. ha->aenmb[3] = RD_REG_WORD(&reg->aenmailbox3);
  2493. ql_dbg(ql_dbg_async, vha, 0x5077,
  2494. "Asynchronous port Update received "
  2495. "aenmb[0]: %x, aenmb[1]: %x, aenmb[2]: %x, aenmb[3]: %x\n",
  2496. ha->aenmb[0], ha->aenmb[1], ha->aenmb[2], ha->aenmb[3]);
  2497. data_size = 4;
  2498. break;
  2499. case QLAFX00_MBA_TEMP_OVER: /* Over temperature event */
  2500. case QLAFX00_MBA_TEMP_CRIT: /* Critical temperature event */
  2501. ql_log(ql_log_info, vha, 0x5083,
  2502. "Asynchronous critical temperature event received "
  2503. "aenmb[0]: %x\n",
  2504. ha->aenmb[0]);
  2505. qlafx00_post_aenfx_work(vha, ha->aenmb[0],
  2506. (uint32_t *)ha->aenmb, 1);
  2507. break;
  2508. default:
  2509. ha->aenmb[1] = RD_REG_WORD(&reg->aenmailbox1);
  2510. ha->aenmb[2] = RD_REG_WORD(&reg->aenmailbox2);
  2511. ha->aenmb[3] = RD_REG_WORD(&reg->aenmailbox3);
  2512. ha->aenmb[4] = RD_REG_WORD(&reg->aenmailbox4);
  2513. ha->aenmb[5] = RD_REG_WORD(&reg->aenmailbox5);
  2514. ha->aenmb[6] = RD_REG_WORD(&reg->aenmailbox6);
  2515. ha->aenmb[7] = RD_REG_WORD(&reg->aenmailbox7);
  2516. ql_dbg(ql_dbg_async, vha, 0x5078,
  2517. "AEN:%04x %04x %04x %04x :%04x %04x %04x %04x\n",
  2518. ha->aenmb[0], ha->aenmb[1], ha->aenmb[2], ha->aenmb[3],
  2519. ha->aenmb[4], ha->aenmb[5], ha->aenmb[6], ha->aenmb[7]);
  2520. break;
  2521. }
  2522. qlafx00_post_aenfx_work(vha, ha->aenmb[0],
  2523. (uint32_t *)ha->aenmb, data_size);
  2524. }
  2525. /**
  2526. *
  2527. * qlafx00x_mbx_completion() - Process mailbox command completions.
  2528. * @ha: SCSI driver HA context
  2529. * @mb16: Mailbox16 register
  2530. */
  2531. static void
  2532. qlafx00_mbx_completion(scsi_qla_host_t *vha, uint32_t mb0)
  2533. {
  2534. uint16_t cnt;
  2535. uint16_t __iomem *wptr;
  2536. struct qla_hw_data *ha = vha->hw;
  2537. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  2538. if (!ha->mcp32)
  2539. ql_dbg(ql_dbg_async, vha, 0x507e, "MBX pointer ERROR.\n");
  2540. /* Load return mailbox registers. */
  2541. ha->flags.mbox_int = 1;
  2542. ha->mailbox_out32[0] = mb0;
  2543. wptr = (uint16_t __iomem *)&reg->mailbox17;
  2544. for (cnt = 1; cnt < ha->mbx_count; cnt++) {
  2545. ha->mailbox_out32[cnt] = RD_REG_WORD(wptr);
  2546. wptr++;
  2547. }
  2548. }
  2549. /**
  2550. * qlafx00_intr_handler() - Process interrupts for the ISPFX00.
  2551. * @irq:
  2552. * @dev_id: SCSI driver HA context
  2553. *
  2554. * Called by system whenever the host adapter generates an interrupt.
  2555. *
  2556. * Returns handled flag.
  2557. */
  2558. irqreturn_t
  2559. qlafx00_intr_handler(int irq, void *dev_id)
  2560. {
  2561. scsi_qla_host_t *vha;
  2562. struct qla_hw_data *ha;
  2563. struct device_reg_fx00 __iomem *reg;
  2564. int status;
  2565. unsigned long iter;
  2566. uint32_t stat;
  2567. uint32_t mb[8];
  2568. struct rsp_que *rsp;
  2569. unsigned long flags;
  2570. uint32_t clr_intr = 0;
  2571. rsp = (struct rsp_que *) dev_id;
  2572. if (!rsp) {
  2573. ql_log(ql_log_info, NULL, 0x507d,
  2574. "%s: NULL response queue pointer.\n", __func__);
  2575. return IRQ_NONE;
  2576. }
  2577. ha = rsp->hw;
  2578. reg = &ha->iobase->ispfx00;
  2579. status = 0;
  2580. if (unlikely(pci_channel_offline(ha->pdev)))
  2581. return IRQ_HANDLED;
  2582. spin_lock_irqsave(&ha->hardware_lock, flags);
  2583. vha = pci_get_drvdata(ha->pdev);
  2584. for (iter = 50; iter--; clr_intr = 0) {
  2585. stat = QLAFX00_RD_INTR_REG(ha);
  2586. if ((stat & QLAFX00_HST_INT_STS_BITS) == 0)
  2587. break;
  2588. switch (stat & QLAFX00_HST_INT_STS_BITS) {
  2589. case QLAFX00_INTR_MB_CMPLT:
  2590. case QLAFX00_INTR_MB_RSP_CMPLT:
  2591. case QLAFX00_INTR_MB_ASYNC_CMPLT:
  2592. case QLAFX00_INTR_ALL_CMPLT:
  2593. mb[0] = RD_REG_WORD(&reg->mailbox16);
  2594. qlafx00_mbx_completion(vha, mb[0]);
  2595. status |= MBX_INTERRUPT;
  2596. clr_intr |= QLAFX00_INTR_MB_CMPLT;
  2597. break;
  2598. case QLAFX00_INTR_ASYNC_CMPLT:
  2599. case QLAFX00_INTR_RSP_ASYNC_CMPLT:
  2600. ha->aenmb[0] = RD_REG_WORD(&reg->aenmailbox0);
  2601. qlafx00_async_event(vha);
  2602. clr_intr |= QLAFX00_INTR_ASYNC_CMPLT;
  2603. break;
  2604. case QLAFX00_INTR_RSP_CMPLT:
  2605. qlafx00_process_response_queue(vha, rsp);
  2606. clr_intr |= QLAFX00_INTR_RSP_CMPLT;
  2607. break;
  2608. default:
  2609. ql_dbg(ql_dbg_async, vha, 0x507a,
  2610. "Unrecognized interrupt type (%d).\n", stat);
  2611. break;
  2612. }
  2613. QLAFX00_CLR_INTR_REG(ha, clr_intr);
  2614. QLAFX00_RD_INTR_REG(ha);
  2615. }
  2616. qla2x00_handle_mbx_completion(ha, status);
  2617. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2618. return IRQ_HANDLED;
  2619. }
  2620. /** QLAFX00 specific IOCB implementation functions */
  2621. static inline cont_a64_entry_t *
  2622. qlafx00_prep_cont_type1_iocb(struct req_que *req,
  2623. cont_a64_entry_t *lcont_pkt)
  2624. {
  2625. cont_a64_entry_t *cont_pkt;
  2626. /* Adjust ring index. */
  2627. req->ring_index++;
  2628. if (req->ring_index == req->length) {
  2629. req->ring_index = 0;
  2630. req->ring_ptr = req->ring;
  2631. } else {
  2632. req->ring_ptr++;
  2633. }
  2634. cont_pkt = (cont_a64_entry_t *)req->ring_ptr;
  2635. /* Load packet defaults. */
  2636. lcont_pkt->entry_type = CONTINUE_A64_TYPE_FX00;
  2637. return cont_pkt;
  2638. }
  2639. static inline void
  2640. qlafx00_build_scsi_iocbs(srb_t *sp, struct cmd_type_7_fx00 *cmd_pkt,
  2641. uint16_t tot_dsds, struct cmd_type_7_fx00 *lcmd_pkt)
  2642. {
  2643. uint16_t avail_dsds;
  2644. __le32 *cur_dsd;
  2645. scsi_qla_host_t *vha;
  2646. struct scsi_cmnd *cmd;
  2647. struct scatterlist *sg;
  2648. int i, cont;
  2649. struct req_que *req;
  2650. cont_a64_entry_t lcont_pkt;
  2651. cont_a64_entry_t *cont_pkt;
  2652. vha = sp->fcport->vha;
  2653. req = vha->req;
  2654. cmd = GET_CMD_SP(sp);
  2655. cont = 0;
  2656. cont_pkt = NULL;
  2657. /* Update entry type to indicate Command Type 3 IOCB */
  2658. lcmd_pkt->entry_type = FX00_COMMAND_TYPE_7;
  2659. /* No data transfer */
  2660. if (!scsi_bufflen(cmd) || cmd->sc_data_direction == DMA_NONE) {
  2661. lcmd_pkt->byte_count = __constant_cpu_to_le32(0);
  2662. return;
  2663. }
  2664. /* Set transfer direction */
  2665. if (cmd->sc_data_direction == DMA_TO_DEVICE) {
  2666. lcmd_pkt->cntrl_flags = TMF_WRITE_DATA;
  2667. vha->qla_stats.output_bytes += scsi_bufflen(cmd);
  2668. } else if (cmd->sc_data_direction == DMA_FROM_DEVICE) {
  2669. lcmd_pkt->cntrl_flags = TMF_READ_DATA;
  2670. vha->qla_stats.input_bytes += scsi_bufflen(cmd);
  2671. }
  2672. /* One DSD is available in the Command Type 3 IOCB */
  2673. avail_dsds = 1;
  2674. cur_dsd = (__le32 *)&lcmd_pkt->dseg_0_address;
  2675. /* Load data segments */
  2676. scsi_for_each_sg(cmd, sg, tot_dsds, i) {
  2677. dma_addr_t sle_dma;
  2678. /* Allocate additional continuation packets? */
  2679. if (avail_dsds == 0) {
  2680. /*
  2681. * Five DSDs are available in the Continuation
  2682. * Type 1 IOCB.
  2683. */
  2684. memset(&lcont_pkt, 0, REQUEST_ENTRY_SIZE);
  2685. cont_pkt =
  2686. qlafx00_prep_cont_type1_iocb(req, &lcont_pkt);
  2687. cur_dsd = (__le32 *)lcont_pkt.dseg_0_address;
  2688. avail_dsds = 5;
  2689. cont = 1;
  2690. }
  2691. sle_dma = sg_dma_address(sg);
  2692. *cur_dsd++ = cpu_to_le32(LSD(sle_dma));
  2693. *cur_dsd++ = cpu_to_le32(MSD(sle_dma));
  2694. *cur_dsd++ = cpu_to_le32(sg_dma_len(sg));
  2695. avail_dsds--;
  2696. if (avail_dsds == 0 && cont == 1) {
  2697. cont = 0;
  2698. memcpy_toio((void __iomem *)cont_pkt, &lcont_pkt,
  2699. REQUEST_ENTRY_SIZE);
  2700. }
  2701. }
  2702. if (avail_dsds != 0 && cont == 1) {
  2703. memcpy_toio((void __iomem *)cont_pkt, &lcont_pkt,
  2704. REQUEST_ENTRY_SIZE);
  2705. }
  2706. }
  2707. /**
  2708. * qlafx00_start_scsi() - Send a SCSI command to the ISP
  2709. * @sp: command to send to the ISP
  2710. *
  2711. * Returns non-zero if a failure occurred, else zero.
  2712. */
  2713. int
  2714. qlafx00_start_scsi(srb_t *sp)
  2715. {
  2716. int ret, nseg;
  2717. unsigned long flags;
  2718. uint32_t index;
  2719. uint32_t handle;
  2720. uint16_t cnt;
  2721. uint16_t req_cnt;
  2722. uint16_t tot_dsds;
  2723. struct req_que *req = NULL;
  2724. struct rsp_que *rsp = NULL;
  2725. struct scsi_cmnd *cmd = GET_CMD_SP(sp);
  2726. struct scsi_qla_host *vha = sp->fcport->vha;
  2727. struct qla_hw_data *ha = vha->hw;
  2728. struct cmd_type_7_fx00 *cmd_pkt;
  2729. struct cmd_type_7_fx00 lcmd_pkt;
  2730. struct scsi_lun llun;
  2731. char tag[2];
  2732. /* Setup device pointers. */
  2733. ret = 0;
  2734. rsp = ha->rsp_q_map[0];
  2735. req = vha->req;
  2736. /* So we know we haven't pci_map'ed anything yet */
  2737. tot_dsds = 0;
  2738. /* Forcing marker needed for now */
  2739. vha->marker_needed = 0;
  2740. /* Send marker if required */
  2741. if (vha->marker_needed != 0) {
  2742. if (qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL) !=
  2743. QLA_SUCCESS)
  2744. return QLA_FUNCTION_FAILED;
  2745. vha->marker_needed = 0;
  2746. }
  2747. /* Acquire ring specific lock */
  2748. spin_lock_irqsave(&ha->hardware_lock, flags);
  2749. /* Check for room in outstanding command list. */
  2750. handle = req->current_outstanding_cmd;
  2751. for (index = 1; index < req->num_outstanding_cmds; index++) {
  2752. handle++;
  2753. if (handle == req->num_outstanding_cmds)
  2754. handle = 1;
  2755. if (!req->outstanding_cmds[handle])
  2756. break;
  2757. }
  2758. if (index == req->num_outstanding_cmds)
  2759. goto queuing_error;
  2760. /* Map the sg table so we have an accurate count of sg entries needed */
  2761. if (scsi_sg_count(cmd)) {
  2762. nseg = dma_map_sg(&ha->pdev->dev, scsi_sglist(cmd),
  2763. scsi_sg_count(cmd), cmd->sc_data_direction);
  2764. if (unlikely(!nseg))
  2765. goto queuing_error;
  2766. } else
  2767. nseg = 0;
  2768. tot_dsds = nseg;
  2769. req_cnt = qla24xx_calc_iocbs(vha, tot_dsds);
  2770. if (req->cnt < (req_cnt + 2)) {
  2771. cnt = RD_REG_DWORD_RELAXED(req->req_q_out);
  2772. if (req->ring_index < cnt)
  2773. req->cnt = cnt - req->ring_index;
  2774. else
  2775. req->cnt = req->length -
  2776. (req->ring_index - cnt);
  2777. if (req->cnt < (req_cnt + 2))
  2778. goto queuing_error;
  2779. }
  2780. /* Build command packet. */
  2781. req->current_outstanding_cmd = handle;
  2782. req->outstanding_cmds[handle] = sp;
  2783. sp->handle = handle;
  2784. cmd->host_scribble = (unsigned char *)(unsigned long)handle;
  2785. req->cnt -= req_cnt;
  2786. cmd_pkt = (struct cmd_type_7_fx00 *)req->ring_ptr;
  2787. memset(&lcmd_pkt, 0, REQUEST_ENTRY_SIZE);
  2788. lcmd_pkt.handle = MAKE_HANDLE(req->id, sp->handle);
  2789. lcmd_pkt.handle_hi = 0;
  2790. lcmd_pkt.dseg_count = cpu_to_le16(tot_dsds);
  2791. lcmd_pkt.tgt_idx = cpu_to_le16(sp->fcport->tgt_id);
  2792. int_to_scsilun(cmd->device->lun, &llun);
  2793. host_to_adap((uint8_t *)&llun, (uint8_t *)&lcmd_pkt.lun,
  2794. sizeof(lcmd_pkt.lun));
  2795. /* Update tagged queuing modifier -- default is TSK_SIMPLE (0). */
  2796. if (scsi_populate_tag_msg(cmd, tag)) {
  2797. switch (tag[0]) {
  2798. case HEAD_OF_QUEUE_TAG:
  2799. lcmd_pkt.task = TSK_HEAD_OF_QUEUE;
  2800. break;
  2801. case ORDERED_QUEUE_TAG:
  2802. lcmd_pkt.task = TSK_ORDERED;
  2803. break;
  2804. }
  2805. }
  2806. /* Load SCSI command packet. */
  2807. host_to_adap(cmd->cmnd, lcmd_pkt.fcp_cdb, sizeof(lcmd_pkt.fcp_cdb));
  2808. lcmd_pkt.byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd));
  2809. /* Build IOCB segments */
  2810. qlafx00_build_scsi_iocbs(sp, cmd_pkt, tot_dsds, &lcmd_pkt);
  2811. /* Set total data segment count. */
  2812. lcmd_pkt.entry_count = (uint8_t)req_cnt;
  2813. /* Specify response queue number where completion should happen */
  2814. lcmd_pkt.entry_status = (uint8_t) rsp->id;
  2815. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302e,
  2816. (uint8_t *)cmd->cmnd, cmd->cmd_len);
  2817. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x3032,
  2818. (uint8_t *)&lcmd_pkt, REQUEST_ENTRY_SIZE);
  2819. memcpy_toio((void __iomem *)cmd_pkt, &lcmd_pkt, REQUEST_ENTRY_SIZE);
  2820. wmb();
  2821. /* Adjust ring index. */
  2822. req->ring_index++;
  2823. if (req->ring_index == req->length) {
  2824. req->ring_index = 0;
  2825. req->ring_ptr = req->ring;
  2826. } else
  2827. req->ring_ptr++;
  2828. sp->flags |= SRB_DMA_VALID;
  2829. /* Set chip new ring index. */
  2830. WRT_REG_DWORD(req->req_q_in, req->ring_index);
  2831. QLAFX00_SET_HST_INTR(ha, ha->rqstq_intr_code);
  2832. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2833. return QLA_SUCCESS;
  2834. queuing_error:
  2835. if (tot_dsds)
  2836. scsi_dma_unmap(cmd);
  2837. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2838. return QLA_FUNCTION_FAILED;
  2839. }
  2840. void
  2841. qlafx00_tm_iocb(srb_t *sp, struct tsk_mgmt_entry_fx00 *ptm_iocb)
  2842. {
  2843. struct srb_iocb *fxio = &sp->u.iocb_cmd;
  2844. scsi_qla_host_t *vha = sp->fcport->vha;
  2845. struct req_que *req = vha->req;
  2846. struct tsk_mgmt_entry_fx00 tm_iocb;
  2847. struct scsi_lun llun;
  2848. memset(&tm_iocb, 0, sizeof(struct tsk_mgmt_entry_fx00));
  2849. tm_iocb.entry_type = TSK_MGMT_IOCB_TYPE_FX00;
  2850. tm_iocb.entry_count = 1;
  2851. tm_iocb.handle = cpu_to_le32(MAKE_HANDLE(req->id, sp->handle));
  2852. tm_iocb.handle_hi = 0;
  2853. tm_iocb.timeout = cpu_to_le16(qla2x00_get_async_timeout(vha) + 2);
  2854. tm_iocb.tgt_id = cpu_to_le16(sp->fcport->tgt_id);
  2855. tm_iocb.control_flags = cpu_to_le32(fxio->u.tmf.flags);
  2856. if (tm_iocb.control_flags == cpu_to_le32((uint32_t)TCF_LUN_RESET)) {
  2857. int_to_scsilun(fxio->u.tmf.lun, &llun);
  2858. host_to_adap((uint8_t *)&llun, (uint8_t *)&tm_iocb.lun,
  2859. sizeof(struct scsi_lun));
  2860. }
  2861. memcpy((void *)ptm_iocb, &tm_iocb,
  2862. sizeof(struct tsk_mgmt_entry_fx00));
  2863. wmb();
  2864. }
  2865. void
  2866. qlafx00_abort_iocb(srb_t *sp, struct abort_iocb_entry_fx00 *pabt_iocb)
  2867. {
  2868. struct srb_iocb *fxio = &sp->u.iocb_cmd;
  2869. scsi_qla_host_t *vha = sp->fcport->vha;
  2870. struct req_que *req = vha->req;
  2871. struct abort_iocb_entry_fx00 abt_iocb;
  2872. memset(&abt_iocb, 0, sizeof(struct abort_iocb_entry_fx00));
  2873. abt_iocb.entry_type = ABORT_IOCB_TYPE_FX00;
  2874. abt_iocb.entry_count = 1;
  2875. abt_iocb.handle = cpu_to_le32(MAKE_HANDLE(req->id, sp->handle));
  2876. abt_iocb.abort_handle =
  2877. cpu_to_le32(MAKE_HANDLE(req->id, fxio->u.abt.cmd_hndl));
  2878. abt_iocb.tgt_id_sts = cpu_to_le16(sp->fcport->tgt_id);
  2879. abt_iocb.req_que_no = cpu_to_le16(req->id);
  2880. memcpy((void *)pabt_iocb, &abt_iocb,
  2881. sizeof(struct abort_iocb_entry_fx00));
  2882. wmb();
  2883. }
  2884. void
  2885. qlafx00_fxdisc_iocb(srb_t *sp, struct fxdisc_entry_fx00 *pfxiocb)
  2886. {
  2887. struct srb_iocb *fxio = &sp->u.iocb_cmd;
  2888. struct qla_mt_iocb_rqst_fx00 *piocb_rqst;
  2889. struct fc_bsg_job *bsg_job;
  2890. struct fxdisc_entry_fx00 fx_iocb;
  2891. uint8_t entry_cnt = 1;
  2892. memset(&fx_iocb, 0, sizeof(struct fxdisc_entry_fx00));
  2893. fx_iocb.entry_type = FX00_IOCB_TYPE;
  2894. fx_iocb.handle = cpu_to_le32(sp->handle);
  2895. fx_iocb.entry_count = entry_cnt;
  2896. if (sp->type == SRB_FXIOCB_DCMD) {
  2897. fx_iocb.func_num =
  2898. sp->u.iocb_cmd.u.fxiocb.req_func_type;
  2899. fx_iocb.adapid = fxio->u.fxiocb.adapter_id;
  2900. fx_iocb.adapid_hi = fxio->u.fxiocb.adapter_id_hi;
  2901. fx_iocb.reserved_0 = fxio->u.fxiocb.reserved_0;
  2902. fx_iocb.reserved_1 = fxio->u.fxiocb.reserved_1;
  2903. fx_iocb.dataword_extra = fxio->u.fxiocb.req_data_extra;
  2904. if (fxio->u.fxiocb.flags & SRB_FXDISC_REQ_DMA_VALID) {
  2905. fx_iocb.req_dsdcnt = cpu_to_le16(1);
  2906. fx_iocb.req_xfrcnt =
  2907. cpu_to_le16(fxio->u.fxiocb.req_len);
  2908. fx_iocb.dseg_rq_address[0] =
  2909. cpu_to_le32(LSD(fxio->u.fxiocb.req_dma_handle));
  2910. fx_iocb.dseg_rq_address[1] =
  2911. cpu_to_le32(MSD(fxio->u.fxiocb.req_dma_handle));
  2912. fx_iocb.dseg_rq_len =
  2913. cpu_to_le32(fxio->u.fxiocb.req_len);
  2914. }
  2915. if (fxio->u.fxiocb.flags & SRB_FXDISC_RESP_DMA_VALID) {
  2916. fx_iocb.rsp_dsdcnt = cpu_to_le16(1);
  2917. fx_iocb.rsp_xfrcnt =
  2918. cpu_to_le16(fxio->u.fxiocb.rsp_len);
  2919. fx_iocb.dseg_rsp_address[0] =
  2920. cpu_to_le32(LSD(fxio->u.fxiocb.rsp_dma_handle));
  2921. fx_iocb.dseg_rsp_address[1] =
  2922. cpu_to_le32(MSD(fxio->u.fxiocb.rsp_dma_handle));
  2923. fx_iocb.dseg_rsp_len =
  2924. cpu_to_le32(fxio->u.fxiocb.rsp_len);
  2925. }
  2926. if (fxio->u.fxiocb.flags & SRB_FXDISC_REQ_DWRD_VALID) {
  2927. fx_iocb.dataword = fxio->u.fxiocb.req_data;
  2928. }
  2929. fx_iocb.flags = fxio->u.fxiocb.flags;
  2930. } else {
  2931. struct scatterlist *sg;
  2932. bsg_job = sp->u.bsg_job;
  2933. piocb_rqst = (struct qla_mt_iocb_rqst_fx00 *)
  2934. &bsg_job->request->rqst_data.h_vendor.vendor_cmd[1];
  2935. fx_iocb.func_num = piocb_rqst->func_type;
  2936. fx_iocb.adapid = piocb_rqst->adapid;
  2937. fx_iocb.adapid_hi = piocb_rqst->adapid_hi;
  2938. fx_iocb.reserved_0 = piocb_rqst->reserved_0;
  2939. fx_iocb.reserved_1 = piocb_rqst->reserved_1;
  2940. fx_iocb.dataword_extra = piocb_rqst->dataword_extra;
  2941. fx_iocb.dataword = piocb_rqst->dataword;
  2942. fx_iocb.req_xfrcnt = piocb_rqst->req_len;
  2943. fx_iocb.rsp_xfrcnt = piocb_rqst->rsp_len;
  2944. if (piocb_rqst->flags & SRB_FXDISC_REQ_DMA_VALID) {
  2945. int avail_dsds, tot_dsds;
  2946. cont_a64_entry_t lcont_pkt;
  2947. cont_a64_entry_t *cont_pkt = NULL;
  2948. __le32 *cur_dsd;
  2949. int index = 0, cont = 0;
  2950. fx_iocb.req_dsdcnt =
  2951. cpu_to_le16(bsg_job->request_payload.sg_cnt);
  2952. tot_dsds =
  2953. bsg_job->request_payload.sg_cnt;
  2954. cur_dsd = (__le32 *)&fx_iocb.dseg_rq_address[0];
  2955. avail_dsds = 1;
  2956. for_each_sg(bsg_job->request_payload.sg_list, sg,
  2957. tot_dsds, index) {
  2958. dma_addr_t sle_dma;
  2959. /* Allocate additional continuation packets? */
  2960. if (avail_dsds == 0) {
  2961. /*
  2962. * Five DSDs are available in the Cont.
  2963. * Type 1 IOCB.
  2964. */
  2965. memset(&lcont_pkt, 0,
  2966. REQUEST_ENTRY_SIZE);
  2967. cont_pkt =
  2968. qlafx00_prep_cont_type1_iocb(
  2969. sp->fcport->vha->req,
  2970. &lcont_pkt);
  2971. cur_dsd = (__le32 *)
  2972. lcont_pkt.dseg_0_address;
  2973. avail_dsds = 5;
  2974. cont = 1;
  2975. entry_cnt++;
  2976. }
  2977. sle_dma = sg_dma_address(sg);
  2978. *cur_dsd++ = cpu_to_le32(LSD(sle_dma));
  2979. *cur_dsd++ = cpu_to_le32(MSD(sle_dma));
  2980. *cur_dsd++ = cpu_to_le32(sg_dma_len(sg));
  2981. avail_dsds--;
  2982. if (avail_dsds == 0 && cont == 1) {
  2983. cont = 0;
  2984. memcpy_toio(
  2985. (void __iomem *)cont_pkt,
  2986. &lcont_pkt, REQUEST_ENTRY_SIZE);
  2987. ql_dump_buffer(
  2988. ql_dbg_user + ql_dbg_verbose,
  2989. sp->fcport->vha, 0x3042,
  2990. (uint8_t *)&lcont_pkt,
  2991. REQUEST_ENTRY_SIZE);
  2992. }
  2993. }
  2994. if (avail_dsds != 0 && cont == 1) {
  2995. memcpy_toio((void __iomem *)cont_pkt,
  2996. &lcont_pkt, REQUEST_ENTRY_SIZE);
  2997. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  2998. sp->fcport->vha, 0x3043,
  2999. (uint8_t *)&lcont_pkt, REQUEST_ENTRY_SIZE);
  3000. }
  3001. }
  3002. if (piocb_rqst->flags & SRB_FXDISC_RESP_DMA_VALID) {
  3003. int avail_dsds, tot_dsds;
  3004. cont_a64_entry_t lcont_pkt;
  3005. cont_a64_entry_t *cont_pkt = NULL;
  3006. __le32 *cur_dsd;
  3007. int index = 0, cont = 0;
  3008. fx_iocb.rsp_dsdcnt =
  3009. cpu_to_le16(bsg_job->reply_payload.sg_cnt);
  3010. tot_dsds = bsg_job->reply_payload.sg_cnt;
  3011. cur_dsd = (__le32 *)&fx_iocb.dseg_rsp_address[0];
  3012. avail_dsds = 1;
  3013. for_each_sg(bsg_job->reply_payload.sg_list, sg,
  3014. tot_dsds, index) {
  3015. dma_addr_t sle_dma;
  3016. /* Allocate additional continuation packets? */
  3017. if (avail_dsds == 0) {
  3018. /*
  3019. * Five DSDs are available in the Cont.
  3020. * Type 1 IOCB.
  3021. */
  3022. memset(&lcont_pkt, 0,
  3023. REQUEST_ENTRY_SIZE);
  3024. cont_pkt =
  3025. qlafx00_prep_cont_type1_iocb(
  3026. sp->fcport->vha->req,
  3027. &lcont_pkt);
  3028. cur_dsd = (__le32 *)
  3029. lcont_pkt.dseg_0_address;
  3030. avail_dsds = 5;
  3031. cont = 1;
  3032. entry_cnt++;
  3033. }
  3034. sle_dma = sg_dma_address(sg);
  3035. *cur_dsd++ = cpu_to_le32(LSD(sle_dma));
  3036. *cur_dsd++ = cpu_to_le32(MSD(sle_dma));
  3037. *cur_dsd++ = cpu_to_le32(sg_dma_len(sg));
  3038. avail_dsds--;
  3039. if (avail_dsds == 0 && cont == 1) {
  3040. cont = 0;
  3041. memcpy_toio((void __iomem *)cont_pkt,
  3042. &lcont_pkt,
  3043. REQUEST_ENTRY_SIZE);
  3044. ql_dump_buffer(
  3045. ql_dbg_user + ql_dbg_verbose,
  3046. sp->fcport->vha, 0x3045,
  3047. (uint8_t *)&lcont_pkt,
  3048. REQUEST_ENTRY_SIZE);
  3049. }
  3050. }
  3051. if (avail_dsds != 0 && cont == 1) {
  3052. memcpy_toio((void __iomem *)cont_pkt,
  3053. &lcont_pkt, REQUEST_ENTRY_SIZE);
  3054. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  3055. sp->fcport->vha, 0x3046,
  3056. (uint8_t *)&lcont_pkt, REQUEST_ENTRY_SIZE);
  3057. }
  3058. }
  3059. if (piocb_rqst->flags & SRB_FXDISC_REQ_DWRD_VALID)
  3060. fx_iocb.dataword = piocb_rqst->dataword;
  3061. fx_iocb.flags = piocb_rqst->flags;
  3062. fx_iocb.entry_count = entry_cnt;
  3063. }
  3064. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  3065. sp->fcport->vha, 0x3047,
  3066. (uint8_t *)&fx_iocb, sizeof(struct fxdisc_entry_fx00));
  3067. memcpy((void *)pfxiocb, &fx_iocb,
  3068. sizeof(struct fxdisc_entry_fx00));
  3069. wmb();
  3070. }