radeon_device.c 26 KB

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  1. /*
  2. * Copyright 2008 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. * Copyright 2009 Jerome Glisse.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors: Dave Airlie
  25. * Alex Deucher
  26. * Jerome Glisse
  27. */
  28. #include <linux/console.h>
  29. #include <linux/slab.h>
  30. #include <drm/drmP.h>
  31. #include <drm/drm_crtc_helper.h>
  32. #include <drm/radeon_drm.h>
  33. #include <linux/vgaarb.h>
  34. #include <linux/vga_switcheroo.h>
  35. #include "radeon_reg.h"
  36. #include "radeon.h"
  37. #include "atom.h"
  38. static const char radeon_family_name[][16] = {
  39. "R100",
  40. "RV100",
  41. "RS100",
  42. "RV200",
  43. "RS200",
  44. "R200",
  45. "RV250",
  46. "RS300",
  47. "RV280",
  48. "R300",
  49. "R350",
  50. "RV350",
  51. "RV380",
  52. "R420",
  53. "R423",
  54. "RV410",
  55. "RS400",
  56. "RS480",
  57. "RS600",
  58. "RS690",
  59. "RS740",
  60. "RV515",
  61. "R520",
  62. "RV530",
  63. "RV560",
  64. "RV570",
  65. "R580",
  66. "R600",
  67. "RV610",
  68. "RV630",
  69. "RV670",
  70. "RV620",
  71. "RV635",
  72. "RS780",
  73. "RS880",
  74. "RV770",
  75. "RV730",
  76. "RV710",
  77. "RV740",
  78. "CEDAR",
  79. "REDWOOD",
  80. "JUNIPER",
  81. "CYPRESS",
  82. "HEMLOCK",
  83. "PALM",
  84. "BARTS",
  85. "TURKS",
  86. "CAICOS",
  87. "LAST",
  88. };
  89. /*
  90. * Clear GPU surface registers.
  91. */
  92. void radeon_surface_init(struct radeon_device *rdev)
  93. {
  94. /* FIXME: check this out */
  95. if (rdev->family < CHIP_R600) {
  96. int i;
  97. for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
  98. if (rdev->surface_regs[i].bo)
  99. radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
  100. else
  101. radeon_clear_surface_reg(rdev, i);
  102. }
  103. /* enable surfaces */
  104. WREG32(RADEON_SURFACE_CNTL, 0);
  105. }
  106. }
  107. /*
  108. * GPU scratch registers helpers function.
  109. */
  110. void radeon_scratch_init(struct radeon_device *rdev)
  111. {
  112. int i;
  113. /* FIXME: check this out */
  114. if (rdev->family < CHIP_R300) {
  115. rdev->scratch.num_reg = 5;
  116. } else {
  117. rdev->scratch.num_reg = 7;
  118. }
  119. rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
  120. for (i = 0; i < rdev->scratch.num_reg; i++) {
  121. rdev->scratch.free[i] = true;
  122. rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
  123. }
  124. }
  125. int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
  126. {
  127. int i;
  128. for (i = 0; i < rdev->scratch.num_reg; i++) {
  129. if (rdev->scratch.free[i]) {
  130. rdev->scratch.free[i] = false;
  131. *reg = rdev->scratch.reg[i];
  132. return 0;
  133. }
  134. }
  135. return -EINVAL;
  136. }
  137. void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
  138. {
  139. int i;
  140. for (i = 0; i < rdev->scratch.num_reg; i++) {
  141. if (rdev->scratch.reg[i] == reg) {
  142. rdev->scratch.free[i] = true;
  143. return;
  144. }
  145. }
  146. }
  147. void radeon_wb_disable(struct radeon_device *rdev)
  148. {
  149. int r;
  150. if (rdev->wb.wb_obj) {
  151. r = radeon_bo_reserve(rdev->wb.wb_obj, false);
  152. if (unlikely(r != 0))
  153. return;
  154. radeon_bo_kunmap(rdev->wb.wb_obj);
  155. radeon_bo_unpin(rdev->wb.wb_obj);
  156. radeon_bo_unreserve(rdev->wb.wb_obj);
  157. }
  158. rdev->wb.enabled = false;
  159. }
  160. void radeon_wb_fini(struct radeon_device *rdev)
  161. {
  162. radeon_wb_disable(rdev);
  163. if (rdev->wb.wb_obj) {
  164. radeon_bo_unref(&rdev->wb.wb_obj);
  165. rdev->wb.wb = NULL;
  166. rdev->wb.wb_obj = NULL;
  167. }
  168. }
  169. int radeon_wb_init(struct radeon_device *rdev)
  170. {
  171. int r;
  172. if (rdev->wb.wb_obj == NULL) {
  173. r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
  174. RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
  175. if (r) {
  176. dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
  177. return r;
  178. }
  179. }
  180. r = radeon_bo_reserve(rdev->wb.wb_obj, false);
  181. if (unlikely(r != 0)) {
  182. radeon_wb_fini(rdev);
  183. return r;
  184. }
  185. r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
  186. &rdev->wb.gpu_addr);
  187. if (r) {
  188. radeon_bo_unreserve(rdev->wb.wb_obj);
  189. dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
  190. radeon_wb_fini(rdev);
  191. return r;
  192. }
  193. r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
  194. radeon_bo_unreserve(rdev->wb.wb_obj);
  195. if (r) {
  196. dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
  197. radeon_wb_fini(rdev);
  198. return r;
  199. }
  200. /* disable event_write fences */
  201. rdev->wb.use_event = false;
  202. /* disabled via module param */
  203. if (radeon_no_wb == 1)
  204. rdev->wb.enabled = false;
  205. else {
  206. /* often unreliable on AGP */
  207. if (rdev->flags & RADEON_IS_AGP) {
  208. rdev->wb.enabled = false;
  209. } else {
  210. rdev->wb.enabled = true;
  211. /* event_write fences are only available on r600+ */
  212. if (rdev->family >= CHIP_R600)
  213. rdev->wb.use_event = true;
  214. }
  215. }
  216. dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
  217. return 0;
  218. }
  219. /**
  220. * radeon_vram_location - try to find VRAM location
  221. * @rdev: radeon device structure holding all necessary informations
  222. * @mc: memory controller structure holding memory informations
  223. * @base: base address at which to put VRAM
  224. *
  225. * Function will place try to place VRAM at base address provided
  226. * as parameter (which is so far either PCI aperture address or
  227. * for IGP TOM base address).
  228. *
  229. * If there is not enough space to fit the unvisible VRAM in the 32bits
  230. * address space then we limit the VRAM size to the aperture.
  231. *
  232. * If we are using AGP and if the AGP aperture doesn't allow us to have
  233. * room for all the VRAM than we restrict the VRAM to the PCI aperture
  234. * size and print a warning.
  235. *
  236. * This function will never fails, worst case are limiting VRAM.
  237. *
  238. * Note: GTT start, end, size should be initialized before calling this
  239. * function on AGP platform.
  240. *
  241. * Note: We don't explictly enforce VRAM start to be aligned on VRAM size,
  242. * this shouldn't be a problem as we are using the PCI aperture as a reference.
  243. * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
  244. * not IGP.
  245. *
  246. * Note: we use mc_vram_size as on some board we need to program the mc to
  247. * cover the whole aperture even if VRAM size is inferior to aperture size
  248. * Novell bug 204882 + along with lots of ubuntu ones
  249. *
  250. * Note: when limiting vram it's safe to overwritte real_vram_size because
  251. * we are not in case where real_vram_size is inferior to mc_vram_size (ie
  252. * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
  253. * ones)
  254. *
  255. * Note: IGP TOM addr should be the same as the aperture addr, we don't
  256. * explicitly check for that thought.
  257. *
  258. * FIXME: when reducing VRAM size align new size on power of 2.
  259. */
  260. void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
  261. {
  262. mc->vram_start = base;
  263. if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) {
  264. dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
  265. mc->real_vram_size = mc->aper_size;
  266. mc->mc_vram_size = mc->aper_size;
  267. }
  268. mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
  269. if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
  270. dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
  271. mc->real_vram_size = mc->aper_size;
  272. mc->mc_vram_size = mc->aper_size;
  273. }
  274. mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
  275. dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
  276. mc->mc_vram_size >> 20, mc->vram_start,
  277. mc->vram_end, mc->real_vram_size >> 20);
  278. }
  279. /**
  280. * radeon_gtt_location - try to find GTT location
  281. * @rdev: radeon device structure holding all necessary informations
  282. * @mc: memory controller structure holding memory informations
  283. *
  284. * Function will place try to place GTT before or after VRAM.
  285. *
  286. * If GTT size is bigger than space left then we ajust GTT size.
  287. * Thus function will never fails.
  288. *
  289. * FIXME: when reducing GTT size align new size on power of 2.
  290. */
  291. void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
  292. {
  293. u64 size_af, size_bf;
  294. size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
  295. size_bf = mc->vram_start & ~mc->gtt_base_align;
  296. if (size_bf > size_af) {
  297. if (mc->gtt_size > size_bf) {
  298. dev_warn(rdev->dev, "limiting GTT\n");
  299. mc->gtt_size = size_bf;
  300. }
  301. mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
  302. } else {
  303. if (mc->gtt_size > size_af) {
  304. dev_warn(rdev->dev, "limiting GTT\n");
  305. mc->gtt_size = size_af;
  306. }
  307. mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
  308. }
  309. mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
  310. dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
  311. mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
  312. }
  313. /*
  314. * GPU helpers function.
  315. */
  316. bool radeon_card_posted(struct radeon_device *rdev)
  317. {
  318. uint32_t reg;
  319. /* first check CRTCs */
  320. if (ASIC_IS_DCE41(rdev)) {
  321. reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
  322. RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
  323. if (reg & EVERGREEN_CRTC_MASTER_EN)
  324. return true;
  325. } else if (ASIC_IS_DCE4(rdev)) {
  326. reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
  327. RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
  328. RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
  329. RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
  330. RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
  331. RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
  332. if (reg & EVERGREEN_CRTC_MASTER_EN)
  333. return true;
  334. } else if (ASIC_IS_AVIVO(rdev)) {
  335. reg = RREG32(AVIVO_D1CRTC_CONTROL) |
  336. RREG32(AVIVO_D2CRTC_CONTROL);
  337. if (reg & AVIVO_CRTC_EN) {
  338. return true;
  339. }
  340. } else {
  341. reg = RREG32(RADEON_CRTC_GEN_CNTL) |
  342. RREG32(RADEON_CRTC2_GEN_CNTL);
  343. if (reg & RADEON_CRTC_EN) {
  344. return true;
  345. }
  346. }
  347. /* then check MEM_SIZE, in case the crtcs are off */
  348. if (rdev->family >= CHIP_R600)
  349. reg = RREG32(R600_CONFIG_MEMSIZE);
  350. else
  351. reg = RREG32(RADEON_CONFIG_MEMSIZE);
  352. if (reg)
  353. return true;
  354. return false;
  355. }
  356. void radeon_update_bandwidth_info(struct radeon_device *rdev)
  357. {
  358. fixed20_12 a;
  359. u32 sclk = rdev->pm.current_sclk;
  360. u32 mclk = rdev->pm.current_mclk;
  361. /* sclk/mclk in Mhz */
  362. a.full = dfixed_const(100);
  363. rdev->pm.sclk.full = dfixed_const(sclk);
  364. rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
  365. rdev->pm.mclk.full = dfixed_const(mclk);
  366. rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
  367. if (rdev->flags & RADEON_IS_IGP) {
  368. a.full = dfixed_const(16);
  369. /* core_bandwidth = sclk(Mhz) * 16 */
  370. rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
  371. }
  372. }
  373. bool radeon_boot_test_post_card(struct radeon_device *rdev)
  374. {
  375. if (radeon_card_posted(rdev))
  376. return true;
  377. if (rdev->bios) {
  378. DRM_INFO("GPU not posted. posting now...\n");
  379. if (rdev->is_atom_bios)
  380. atom_asic_init(rdev->mode_info.atom_context);
  381. else
  382. radeon_combios_asic_init(rdev->ddev);
  383. return true;
  384. } else {
  385. dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
  386. return false;
  387. }
  388. }
  389. int radeon_dummy_page_init(struct radeon_device *rdev)
  390. {
  391. if (rdev->dummy_page.page)
  392. return 0;
  393. rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
  394. if (rdev->dummy_page.page == NULL)
  395. return -ENOMEM;
  396. rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
  397. 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
  398. if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) {
  399. dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n");
  400. __free_page(rdev->dummy_page.page);
  401. rdev->dummy_page.page = NULL;
  402. return -ENOMEM;
  403. }
  404. return 0;
  405. }
  406. void radeon_dummy_page_fini(struct radeon_device *rdev)
  407. {
  408. if (rdev->dummy_page.page == NULL)
  409. return;
  410. pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
  411. PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
  412. __free_page(rdev->dummy_page.page);
  413. rdev->dummy_page.page = NULL;
  414. }
  415. /* ATOM accessor methods */
  416. static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
  417. {
  418. struct radeon_device *rdev = info->dev->dev_private;
  419. uint32_t r;
  420. r = rdev->pll_rreg(rdev, reg);
  421. return r;
  422. }
  423. static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
  424. {
  425. struct radeon_device *rdev = info->dev->dev_private;
  426. rdev->pll_wreg(rdev, reg, val);
  427. }
  428. static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
  429. {
  430. struct radeon_device *rdev = info->dev->dev_private;
  431. uint32_t r;
  432. r = rdev->mc_rreg(rdev, reg);
  433. return r;
  434. }
  435. static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
  436. {
  437. struct radeon_device *rdev = info->dev->dev_private;
  438. rdev->mc_wreg(rdev, reg, val);
  439. }
  440. static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
  441. {
  442. struct radeon_device *rdev = info->dev->dev_private;
  443. WREG32(reg*4, val);
  444. }
  445. static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
  446. {
  447. struct radeon_device *rdev = info->dev->dev_private;
  448. uint32_t r;
  449. r = RREG32(reg*4);
  450. return r;
  451. }
  452. static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
  453. {
  454. struct radeon_device *rdev = info->dev->dev_private;
  455. WREG32_IO(reg*4, val);
  456. }
  457. static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
  458. {
  459. struct radeon_device *rdev = info->dev->dev_private;
  460. uint32_t r;
  461. r = RREG32_IO(reg*4);
  462. return r;
  463. }
  464. int radeon_atombios_init(struct radeon_device *rdev)
  465. {
  466. struct card_info *atom_card_info =
  467. kzalloc(sizeof(struct card_info), GFP_KERNEL);
  468. if (!atom_card_info)
  469. return -ENOMEM;
  470. rdev->mode_info.atom_card_info = atom_card_info;
  471. atom_card_info->dev = rdev->ddev;
  472. atom_card_info->reg_read = cail_reg_read;
  473. atom_card_info->reg_write = cail_reg_write;
  474. /* needed for iio ops */
  475. if (rdev->rio_mem) {
  476. atom_card_info->ioreg_read = cail_ioreg_read;
  477. atom_card_info->ioreg_write = cail_ioreg_write;
  478. } else {
  479. DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
  480. atom_card_info->ioreg_read = cail_reg_read;
  481. atom_card_info->ioreg_write = cail_reg_write;
  482. }
  483. atom_card_info->mc_read = cail_mc_read;
  484. atom_card_info->mc_write = cail_mc_write;
  485. atom_card_info->pll_read = cail_pll_read;
  486. atom_card_info->pll_write = cail_pll_write;
  487. rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
  488. mutex_init(&rdev->mode_info.atom_context->mutex);
  489. radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
  490. atom_allocate_fb_scratch(rdev->mode_info.atom_context);
  491. return 0;
  492. }
  493. void radeon_atombios_fini(struct radeon_device *rdev)
  494. {
  495. if (rdev->mode_info.atom_context) {
  496. kfree(rdev->mode_info.atom_context->scratch);
  497. kfree(rdev->mode_info.atom_context);
  498. }
  499. kfree(rdev->mode_info.atom_card_info);
  500. }
  501. int radeon_combios_init(struct radeon_device *rdev)
  502. {
  503. radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
  504. return 0;
  505. }
  506. void radeon_combios_fini(struct radeon_device *rdev)
  507. {
  508. }
  509. /* if we get transitioned to only one device, tak VGA back */
  510. static unsigned int radeon_vga_set_decode(void *cookie, bool state)
  511. {
  512. struct radeon_device *rdev = cookie;
  513. radeon_vga_set_state(rdev, state);
  514. if (state)
  515. return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
  516. VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
  517. else
  518. return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
  519. }
  520. void radeon_check_arguments(struct radeon_device *rdev)
  521. {
  522. /* vramlimit must be a power of two */
  523. switch (radeon_vram_limit) {
  524. case 0:
  525. case 4:
  526. case 8:
  527. case 16:
  528. case 32:
  529. case 64:
  530. case 128:
  531. case 256:
  532. case 512:
  533. case 1024:
  534. case 2048:
  535. case 4096:
  536. break;
  537. default:
  538. dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
  539. radeon_vram_limit);
  540. radeon_vram_limit = 0;
  541. break;
  542. }
  543. radeon_vram_limit = radeon_vram_limit << 20;
  544. /* gtt size must be power of two and greater or equal to 32M */
  545. switch (radeon_gart_size) {
  546. case 4:
  547. case 8:
  548. case 16:
  549. dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n",
  550. radeon_gart_size);
  551. radeon_gart_size = 512;
  552. break;
  553. case 32:
  554. case 64:
  555. case 128:
  556. case 256:
  557. case 512:
  558. case 1024:
  559. case 2048:
  560. case 4096:
  561. break;
  562. default:
  563. dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
  564. radeon_gart_size);
  565. radeon_gart_size = 512;
  566. break;
  567. }
  568. rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
  569. /* AGP mode can only be -1, 1, 2, 4, 8 */
  570. switch (radeon_agpmode) {
  571. case -1:
  572. case 0:
  573. case 1:
  574. case 2:
  575. case 4:
  576. case 8:
  577. break;
  578. default:
  579. dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
  580. "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
  581. radeon_agpmode = 0;
  582. break;
  583. }
  584. }
  585. static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
  586. {
  587. struct drm_device *dev = pci_get_drvdata(pdev);
  588. pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
  589. if (state == VGA_SWITCHEROO_ON) {
  590. printk(KERN_INFO "radeon: switched on\n");
  591. /* don't suspend or resume card normally */
  592. dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
  593. radeon_resume_kms(dev);
  594. dev->switch_power_state = DRM_SWITCH_POWER_ON;
  595. drm_kms_helper_poll_enable(dev);
  596. } else {
  597. printk(KERN_INFO "radeon: switched off\n");
  598. drm_kms_helper_poll_disable(dev);
  599. dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
  600. radeon_suspend_kms(dev, pmm);
  601. dev->switch_power_state = DRM_SWITCH_POWER_OFF;
  602. }
  603. }
  604. static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
  605. {
  606. struct drm_device *dev = pci_get_drvdata(pdev);
  607. bool can_switch;
  608. spin_lock(&dev->count_lock);
  609. can_switch = (dev->open_count == 0);
  610. spin_unlock(&dev->count_lock);
  611. return can_switch;
  612. }
  613. int radeon_device_init(struct radeon_device *rdev,
  614. struct drm_device *ddev,
  615. struct pci_dev *pdev,
  616. uint32_t flags)
  617. {
  618. int r, i;
  619. int dma_bits;
  620. rdev->shutdown = false;
  621. rdev->dev = &pdev->dev;
  622. rdev->ddev = ddev;
  623. rdev->pdev = pdev;
  624. rdev->flags = flags;
  625. rdev->family = flags & RADEON_FAMILY_MASK;
  626. rdev->is_atom_bios = false;
  627. rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
  628. rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
  629. rdev->gpu_lockup = false;
  630. rdev->accel_working = false;
  631. DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X).\n",
  632. radeon_family_name[rdev->family], pdev->vendor, pdev->device);
  633. /* mutex initialization are all done here so we
  634. * can recall function without having locking issues */
  635. mutex_init(&rdev->cs_mutex);
  636. mutex_init(&rdev->ib_pool.mutex);
  637. mutex_init(&rdev->cp.mutex);
  638. mutex_init(&rdev->dc_hw_i2c_mutex);
  639. if (rdev->family >= CHIP_R600)
  640. spin_lock_init(&rdev->ih.lock);
  641. mutex_init(&rdev->gem.mutex);
  642. mutex_init(&rdev->pm.mutex);
  643. mutex_init(&rdev->vram_mutex);
  644. rwlock_init(&rdev->fence_drv.lock);
  645. INIT_LIST_HEAD(&rdev->gem.objects);
  646. init_waitqueue_head(&rdev->irq.vblank_queue);
  647. init_waitqueue_head(&rdev->irq.idle_queue);
  648. /* Set asic functions */
  649. r = radeon_asic_init(rdev);
  650. if (r)
  651. return r;
  652. radeon_check_arguments(rdev);
  653. /* all of the newer IGP chips have an internal gart
  654. * However some rs4xx report as AGP, so remove that here.
  655. */
  656. if ((rdev->family >= CHIP_RS400) &&
  657. (rdev->flags & RADEON_IS_IGP)) {
  658. rdev->flags &= ~RADEON_IS_AGP;
  659. }
  660. if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
  661. radeon_agp_disable(rdev);
  662. }
  663. /* set DMA mask + need_dma32 flags.
  664. * PCIE - can handle 40-bits.
  665. * IGP - can handle 40-bits (in theory)
  666. * AGP - generally dma32 is safest
  667. * PCI - only dma32
  668. */
  669. rdev->need_dma32 = false;
  670. if (rdev->flags & RADEON_IS_AGP)
  671. rdev->need_dma32 = true;
  672. if (rdev->flags & RADEON_IS_PCI)
  673. rdev->need_dma32 = true;
  674. dma_bits = rdev->need_dma32 ? 32 : 40;
  675. r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
  676. if (r) {
  677. printk(KERN_WARNING "radeon: No suitable DMA available.\n");
  678. }
  679. /* Registers mapping */
  680. /* TODO: block userspace mapping of io register */
  681. rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
  682. rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
  683. rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
  684. if (rdev->rmmio == NULL) {
  685. return -ENOMEM;
  686. }
  687. DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
  688. DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
  689. /* io port mapping */
  690. for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
  691. if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
  692. rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
  693. rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
  694. break;
  695. }
  696. }
  697. if (rdev->rio_mem == NULL)
  698. DRM_ERROR("Unable to find PCI I/O BAR\n");
  699. /* if we have > 1 VGA cards, then disable the radeon VGA resources */
  700. /* this will fail for cards that aren't VGA class devices, just
  701. * ignore it */
  702. vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
  703. vga_switcheroo_register_client(rdev->pdev,
  704. radeon_switcheroo_set_state,
  705. NULL,
  706. radeon_switcheroo_can_switch);
  707. r = radeon_init(rdev);
  708. if (r)
  709. return r;
  710. if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
  711. /* Acceleration not working on AGP card try again
  712. * with fallback to PCI or PCIE GART
  713. */
  714. radeon_asic_reset(rdev);
  715. radeon_fini(rdev);
  716. radeon_agp_disable(rdev);
  717. r = radeon_init(rdev);
  718. if (r)
  719. return r;
  720. }
  721. if (radeon_testing) {
  722. radeon_test_moves(rdev);
  723. }
  724. if (radeon_benchmarking) {
  725. radeon_benchmark(rdev);
  726. }
  727. return 0;
  728. }
  729. void radeon_device_fini(struct radeon_device *rdev)
  730. {
  731. DRM_INFO("radeon: finishing device.\n");
  732. rdev->shutdown = true;
  733. /* evict vram memory */
  734. radeon_bo_evict_vram(rdev);
  735. radeon_fini(rdev);
  736. vga_switcheroo_unregister_client(rdev->pdev);
  737. vga_client_register(rdev->pdev, NULL, NULL, NULL);
  738. if (rdev->rio_mem)
  739. pci_iounmap(rdev->pdev, rdev->rio_mem);
  740. rdev->rio_mem = NULL;
  741. iounmap(rdev->rmmio);
  742. rdev->rmmio = NULL;
  743. }
  744. /*
  745. * Suspend & resume.
  746. */
  747. int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
  748. {
  749. struct radeon_device *rdev;
  750. struct drm_crtc *crtc;
  751. struct drm_connector *connector;
  752. int r;
  753. if (dev == NULL || dev->dev_private == NULL) {
  754. return -ENODEV;
  755. }
  756. if (state.event == PM_EVENT_PRETHAW) {
  757. return 0;
  758. }
  759. rdev = dev->dev_private;
  760. if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
  761. return 0;
  762. /* turn off display hw */
  763. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  764. drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
  765. }
  766. /* unpin the front buffers */
  767. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  768. struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
  769. struct radeon_bo *robj;
  770. if (rfb == NULL || rfb->obj == NULL) {
  771. continue;
  772. }
  773. robj = rfb->obj->driver_private;
  774. /* don't unpin kernel fb objects */
  775. if (!radeon_fbdev_robj_is_fb(rdev, robj)) {
  776. r = radeon_bo_reserve(robj, false);
  777. if (r == 0) {
  778. radeon_bo_unpin(robj);
  779. radeon_bo_unreserve(robj);
  780. }
  781. }
  782. }
  783. /* evict vram memory */
  784. radeon_bo_evict_vram(rdev);
  785. /* wait for gpu to finish processing current batch */
  786. radeon_fence_wait_last(rdev);
  787. radeon_save_bios_scratch_regs(rdev);
  788. radeon_pm_suspend(rdev);
  789. radeon_suspend(rdev);
  790. radeon_hpd_fini(rdev);
  791. /* evict remaining vram memory */
  792. radeon_bo_evict_vram(rdev);
  793. radeon_agp_suspend(rdev);
  794. pci_save_state(dev->pdev);
  795. if (state.event == PM_EVENT_SUSPEND) {
  796. /* Shut down the device */
  797. pci_disable_device(dev->pdev);
  798. pci_set_power_state(dev->pdev, PCI_D3hot);
  799. }
  800. acquire_console_sem();
  801. radeon_fbdev_set_suspend(rdev, 1);
  802. release_console_sem();
  803. return 0;
  804. }
  805. int radeon_resume_kms(struct drm_device *dev)
  806. {
  807. struct drm_connector *connector;
  808. struct radeon_device *rdev = dev->dev_private;
  809. if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
  810. return 0;
  811. acquire_console_sem();
  812. pci_set_power_state(dev->pdev, PCI_D0);
  813. pci_restore_state(dev->pdev);
  814. if (pci_enable_device(dev->pdev)) {
  815. release_console_sem();
  816. return -1;
  817. }
  818. pci_set_master(dev->pdev);
  819. /* resume AGP if in use */
  820. radeon_agp_resume(rdev);
  821. radeon_resume(rdev);
  822. radeon_pm_resume(rdev);
  823. radeon_restore_bios_scratch_regs(rdev);
  824. radeon_fbdev_set_suspend(rdev, 0);
  825. release_console_sem();
  826. /* reset hpd state */
  827. radeon_hpd_init(rdev);
  828. /* blat the mode back in */
  829. drm_helper_resume_force_mode(dev);
  830. /* turn on display hw */
  831. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  832. drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
  833. }
  834. return 0;
  835. }
  836. int radeon_gpu_reset(struct radeon_device *rdev)
  837. {
  838. int r;
  839. radeon_save_bios_scratch_regs(rdev);
  840. radeon_suspend(rdev);
  841. r = radeon_asic_reset(rdev);
  842. if (!r) {
  843. dev_info(rdev->dev, "GPU reset succeed\n");
  844. radeon_resume(rdev);
  845. radeon_restore_bios_scratch_regs(rdev);
  846. drm_helper_resume_force_mode(rdev->ddev);
  847. return 0;
  848. }
  849. /* bad news, how to tell it to userspace ? */
  850. dev_info(rdev->dev, "GPU reset failed\n");
  851. return r;
  852. }
  853. /*
  854. * Debugfs
  855. */
  856. struct radeon_debugfs {
  857. struct drm_info_list *files;
  858. unsigned num_files;
  859. };
  860. static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES];
  861. static unsigned _radeon_debugfs_count = 0;
  862. int radeon_debugfs_add_files(struct radeon_device *rdev,
  863. struct drm_info_list *files,
  864. unsigned nfiles)
  865. {
  866. unsigned i;
  867. for (i = 0; i < _radeon_debugfs_count; i++) {
  868. if (_radeon_debugfs[i].files == files) {
  869. /* Already registered */
  870. return 0;
  871. }
  872. }
  873. if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) {
  874. DRM_ERROR("Reached maximum number of debugfs files.\n");
  875. DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n");
  876. return -EINVAL;
  877. }
  878. _radeon_debugfs[_radeon_debugfs_count].files = files;
  879. _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles;
  880. _radeon_debugfs_count++;
  881. #if defined(CONFIG_DEBUG_FS)
  882. drm_debugfs_create_files(files, nfiles,
  883. rdev->ddev->control->debugfs_root,
  884. rdev->ddev->control);
  885. drm_debugfs_create_files(files, nfiles,
  886. rdev->ddev->primary->debugfs_root,
  887. rdev->ddev->primary);
  888. #endif
  889. return 0;
  890. }
  891. #if defined(CONFIG_DEBUG_FS)
  892. int radeon_debugfs_init(struct drm_minor *minor)
  893. {
  894. return 0;
  895. }
  896. void radeon_debugfs_cleanup(struct drm_minor *minor)
  897. {
  898. unsigned i;
  899. for (i = 0; i < _radeon_debugfs_count; i++) {
  900. drm_debugfs_remove_files(_radeon_debugfs[i].files,
  901. _radeon_debugfs[i].num_files, minor);
  902. }
  903. }
  904. #endif