board-bockw.c 7.3 KB

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  1. /*
  2. * Bock-W board support
  3. *
  4. * Copyright (C) 2013 Renesas Solutions Corp.
  5. * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; version 2 of the License.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  19. */
  20. #include <linux/mfd/tmio.h>
  21. #include <linux/mmc/host.h>
  22. #include <linux/mmc/sh_mobile_sdhi.h>
  23. #include <linux/mmc/sh_mmcif.h>
  24. #include <linux/mtd/partitions.h>
  25. #include <linux/pinctrl/machine.h>
  26. #include <linux/platform_data/usb-rcar-phy.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/regulator/fixed.h>
  29. #include <linux/regulator/machine.h>
  30. #include <linux/smsc911x.h>
  31. #include <linux/spi/spi.h>
  32. #include <linux/spi/flash.h>
  33. #include <mach/common.h>
  34. #include <mach/irqs.h>
  35. #include <mach/r8a7778.h>
  36. #include <asm/mach/arch.h>
  37. /*
  38. * CN9(Upper side) SCIF/RCAN selection
  39. *
  40. * 1,4 3,6
  41. * SW40 SCIF RCAN
  42. * SW41 SCIF RCAN
  43. */
  44. /*
  45. * MMC (CN26) pin
  46. *
  47. * SW6 (D2) 3 pin
  48. * SW7 (D5) ON
  49. * SW8 (D3) 3 pin
  50. * SW10 (D4) 1 pin
  51. * SW12 (CLK) 1 pin
  52. * SW13 (D6) 3 pin
  53. * SW14 (CMD) ON
  54. * SW15 (D6) 1 pin
  55. * SW16 (D0) ON
  56. * SW17 (D1) ON
  57. * SW18 (D7) 3 pin
  58. * SW19 (MMC) 1 pin
  59. */
  60. /* Dummy supplies, where voltage doesn't matter */
  61. static struct regulator_consumer_supply dummy_supplies[] = {
  62. REGULATOR_SUPPLY("vddvario", "smsc911x"),
  63. REGULATOR_SUPPLY("vdd33a", "smsc911x"),
  64. };
  65. static struct smsc911x_platform_config smsc911x_data = {
  66. .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
  67. .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
  68. .flags = SMSC911X_USE_32BIT,
  69. .phy_interface = PHY_INTERFACE_MODE_MII,
  70. };
  71. static struct resource smsc911x_resources[] = {
  72. DEFINE_RES_MEM(0x18300000, 0x1000),
  73. DEFINE_RES_IRQ(irq_pin(0)), /* IRQ 0 */
  74. };
  75. /* USB */
  76. static struct resource usb_phy_resources[] __initdata = {
  77. DEFINE_RES_MEM(0xffe70800, 0x100),
  78. DEFINE_RES_MEM(0xffe76000, 0x100),
  79. };
  80. static struct rcar_phy_platform_data usb_phy_platform_data __initdata;
  81. /* SDHI */
  82. static struct sh_mobile_sdhi_info sdhi0_info = {
  83. .tmio_caps = MMC_CAP_SD_HIGHSPEED,
  84. .tmio_ocr_mask = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
  85. .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT,
  86. };
  87. static struct resource sdhi0_resources[] __initdata = {
  88. DEFINE_RES_MEM(0xFFE4C000, 0x100),
  89. DEFINE_RES_IRQ(gic_iid(0x77)),
  90. };
  91. static struct sh_eth_plat_data ether_platform_data __initdata = {
  92. .phy = 0x01,
  93. .edmac_endian = EDMAC_LITTLE_ENDIAN,
  94. .register_type = SH_ETH_REG_FAST_RCAR,
  95. .phy_interface = PHY_INTERFACE_MODE_RMII,
  96. /*
  97. * Although the LINK signal is available on the board, it's connected to
  98. * the link/activity LED output of the PHY, thus the link disappears and
  99. * reappears after each packet. We'd be better off ignoring such signal
  100. * and getting the link state from the PHY indirectly.
  101. */
  102. .no_ether_link = 1,
  103. };
  104. /* I2C */
  105. static struct i2c_board_info i2c0_devices[] = {
  106. {
  107. I2C_BOARD_INFO("rx8581", 0x51),
  108. },
  109. };
  110. /* HSPI*/
  111. static struct mtd_partition m25p80_spi_flash_partitions[] = {
  112. {
  113. .name = "data(spi)",
  114. .size = 0x0100000,
  115. .offset = 0,
  116. },
  117. };
  118. static struct flash_platform_data spi_flash_data = {
  119. .name = "m25p80",
  120. .type = "s25fl008k",
  121. .parts = m25p80_spi_flash_partitions,
  122. .nr_parts = ARRAY_SIZE(m25p80_spi_flash_partitions),
  123. };
  124. static struct spi_board_info spi_board_info[] __initdata = {
  125. {
  126. .modalias = "m25p80",
  127. .max_speed_hz = 104000000,
  128. .chip_select = 0,
  129. .bus_num = 0,
  130. .mode = SPI_MODE_0,
  131. .platform_data = &spi_flash_data,
  132. },
  133. };
  134. /* MMC */
  135. static struct resource mmc_resources[] __initdata = {
  136. DEFINE_RES_MEM(0xffe4e000, 0x100),
  137. DEFINE_RES_IRQ(gic_iid(0x5d)),
  138. };
  139. static struct sh_mmcif_plat_data sh_mmcif_plat = {
  140. .sup_pclk = 0,
  141. .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
  142. .caps = MMC_CAP_4_BIT_DATA |
  143. MMC_CAP_8_BIT_DATA |
  144. MMC_CAP_NEEDS_POLL,
  145. };
  146. static const struct pinctrl_map bockw_pinctrl_map[] = {
  147. /* Ether */
  148. PIN_MAP_MUX_GROUP_DEFAULT("r8a777x-ether", "pfc-r8a7778",
  149. "ether_rmii", "ether"),
  150. /* HSPI0 */
  151. PIN_MAP_MUX_GROUP_DEFAULT("sh-hspi.0", "pfc-r8a7778",
  152. "hspi0_a", "hspi0"),
  153. /* MMC */
  154. PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif", "pfc-r8a7778",
  155. "mmc_data8", "mmc"),
  156. PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif", "pfc-r8a7778",
  157. "mmc_ctrl", "mmc"),
  158. /* SCIF0 */
  159. PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
  160. "scif0_data_a", "scif0"),
  161. PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
  162. "scif0_ctrl", "scif0"),
  163. /* USB */
  164. PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform", "pfc-r8a7778",
  165. "usb0", "usb0"),
  166. PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform", "pfc-r8a7778",
  167. "usb1", "usb1"),
  168. /* SDHI0 */
  169. PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7778",
  170. "sdhi0", "sdhi0"),
  171. };
  172. #define FPGA 0x18200000
  173. #define IRQ0MR 0x30
  174. #define PFC 0xfffc0000
  175. #define PUPR4 0x110
  176. static void __init bockw_init(void)
  177. {
  178. void __iomem *base;
  179. r8a7778_clock_init();
  180. r8a7778_init_irq_extpin(1);
  181. r8a7778_add_standard_devices();
  182. r8a7778_add_ether_device(&ether_platform_data);
  183. r8a7778_add_hspi_device(0);
  184. i2c_register_board_info(0, i2c0_devices,
  185. ARRAY_SIZE(i2c0_devices));
  186. spi_register_board_info(spi_board_info,
  187. ARRAY_SIZE(spi_board_info));
  188. pinctrl_register_mappings(bockw_pinctrl_map,
  189. ARRAY_SIZE(bockw_pinctrl_map));
  190. r8a7778_pinmux_init();
  191. platform_device_register_resndata(
  192. &platform_bus, "sh_mmcif", -1,
  193. mmc_resources, ARRAY_SIZE(mmc_resources),
  194. &sh_mmcif_plat, sizeof(struct sh_mmcif_plat_data));
  195. platform_device_register_resndata(
  196. &platform_bus, "rcar_usb_phy", -1,
  197. usb_phy_resources,
  198. ARRAY_SIZE(usb_phy_resources),
  199. &usb_phy_platform_data,
  200. sizeof(struct rcar_phy_platform_data));
  201. /* for SMSC */
  202. base = ioremap_nocache(FPGA, SZ_1M);
  203. if (base) {
  204. /*
  205. * CAUTION
  206. *
  207. * IRQ0/1 is cascaded interrupt from FPGA.
  208. * it should be cared in the future
  209. * Now, it is assuming IRQ0 was used only from SMSC.
  210. */
  211. u16 val = ioread16(base + IRQ0MR);
  212. val &= ~(1 << 4); /* enable SMSC911x */
  213. iowrite16(val, base + IRQ0MR);
  214. iounmap(base);
  215. regulator_register_fixed(0, dummy_supplies,
  216. ARRAY_SIZE(dummy_supplies));
  217. platform_device_register_resndata(
  218. &platform_bus, "smsc911x", -1,
  219. smsc911x_resources, ARRAY_SIZE(smsc911x_resources),
  220. &smsc911x_data, sizeof(smsc911x_data));
  221. }
  222. /* for SDHI */
  223. base = ioremap_nocache(PFC, 0x200);
  224. if (base) {
  225. /*
  226. * FIXME
  227. *
  228. * SDHI CD/WP pin needs pull-up
  229. */
  230. iowrite32(ioread32(base + PUPR4) | (3 << 26), base + PUPR4);
  231. iounmap(base);
  232. platform_device_register_resndata(
  233. &platform_bus, "sh_mobile_sdhi", 0,
  234. sdhi0_resources, ARRAY_SIZE(sdhi0_resources),
  235. &sdhi0_info, sizeof(struct sh_mobile_sdhi_info));
  236. }
  237. }
  238. static const char *bockw_boards_compat_dt[] __initdata = {
  239. "renesas,bockw",
  240. NULL,
  241. };
  242. DT_MACHINE_START(BOCKW_DT, "bockw")
  243. .init_early = r8a7778_init_delay,
  244. .init_irq = r8a7778_init_irq_dt,
  245. .init_machine = bockw_init,
  246. .init_time = shmobile_timer_init,
  247. .dt_compat = bockw_boards_compat_dt,
  248. .init_late = r8a7778_init_late,
  249. MACHINE_END