Kconfig 28 KB

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  1. #
  2. # For a description of the syntax of this configuration file,
  3. # see Documentation/kbuild/kconfig-language.txt.
  4. #
  5. mainmenu "Blackfin Kernel Configuration"
  6. config MMU
  7. bool
  8. default n
  9. config FPU
  10. bool
  11. default n
  12. config RWSEM_GENERIC_SPINLOCK
  13. bool
  14. default y
  15. config RWSEM_XCHGADD_ALGORITHM
  16. bool
  17. default n
  18. config BLACKFIN
  19. bool
  20. default y
  21. select HAVE_IDE
  22. select HAVE_OPROFILE
  23. select ARCH_WANT_OPTIONAL_GPIOLIB
  24. config ZONE_DMA
  25. bool
  26. default y
  27. config GENERIC_FIND_NEXT_BIT
  28. bool
  29. default y
  30. config GENERIC_HWEIGHT
  31. bool
  32. default y
  33. config GENERIC_HARDIRQS
  34. bool
  35. default y
  36. config GENERIC_IRQ_PROBE
  37. bool
  38. default y
  39. config GENERIC_GPIO
  40. bool
  41. default y
  42. config FORCE_MAX_ZONEORDER
  43. int
  44. default "14"
  45. config GENERIC_CALIBRATE_DELAY
  46. bool
  47. default y
  48. source "init/Kconfig"
  49. source "kernel/Kconfig.preempt"
  50. source "kernel/Kconfig.freezer"
  51. menu "Blackfin Processor Options"
  52. comment "Processor and Board Settings"
  53. choice
  54. prompt "CPU"
  55. default BF533
  56. config BF512
  57. bool "BF512"
  58. help
  59. BF512 Processor Support.
  60. config BF514
  61. bool "BF514"
  62. help
  63. BF514 Processor Support.
  64. config BF516
  65. bool "BF516"
  66. help
  67. BF516 Processor Support.
  68. config BF518
  69. bool "BF518"
  70. help
  71. BF518 Processor Support.
  72. config BF522
  73. bool "BF522"
  74. help
  75. BF522 Processor Support.
  76. config BF523
  77. bool "BF523"
  78. help
  79. BF523 Processor Support.
  80. config BF524
  81. bool "BF524"
  82. help
  83. BF524 Processor Support.
  84. config BF525
  85. bool "BF525"
  86. help
  87. BF525 Processor Support.
  88. config BF526
  89. bool "BF526"
  90. help
  91. BF526 Processor Support.
  92. config BF527
  93. bool "BF527"
  94. help
  95. BF527 Processor Support.
  96. config BF531
  97. bool "BF531"
  98. help
  99. BF531 Processor Support.
  100. config BF532
  101. bool "BF532"
  102. help
  103. BF532 Processor Support.
  104. config BF533
  105. bool "BF533"
  106. help
  107. BF533 Processor Support.
  108. config BF534
  109. bool "BF534"
  110. help
  111. BF534 Processor Support.
  112. config BF536
  113. bool "BF536"
  114. help
  115. BF536 Processor Support.
  116. config BF537
  117. bool "BF537"
  118. help
  119. BF537 Processor Support.
  120. config BF538
  121. bool "BF538"
  122. help
  123. BF538 Processor Support.
  124. config BF539
  125. bool "BF539"
  126. help
  127. BF539 Processor Support.
  128. config BF542
  129. bool "BF542"
  130. help
  131. BF542 Processor Support.
  132. config BF542M
  133. bool "BF542m"
  134. help
  135. BF542 Processor Support.
  136. config BF544
  137. bool "BF544"
  138. help
  139. BF544 Processor Support.
  140. config BF544M
  141. bool "BF544m"
  142. help
  143. BF544 Processor Support.
  144. config BF547
  145. bool "BF547"
  146. help
  147. BF547 Processor Support.
  148. config BF547M
  149. bool "BF547m"
  150. help
  151. BF547 Processor Support.
  152. config BF548
  153. bool "BF548"
  154. help
  155. BF548 Processor Support.
  156. config BF548M
  157. bool "BF548m"
  158. help
  159. BF548 Processor Support.
  160. config BF549
  161. bool "BF549"
  162. help
  163. BF549 Processor Support.
  164. config BF549M
  165. bool "BF549m"
  166. help
  167. BF549 Processor Support.
  168. config BF561
  169. bool "BF561"
  170. help
  171. BF561 Processor Support.
  172. endchoice
  173. config SMP
  174. depends on BF561
  175. bool "Symmetric multi-processing support"
  176. ---help---
  177. This enables support for systems with more than one CPU,
  178. like the dual core BF561. If you have a system with only one
  179. CPU, say N. If you have a system with more than one CPU, say Y.
  180. If you don't know what to do here, say N.
  181. config NR_CPUS
  182. int
  183. depends on SMP
  184. default 2 if BF561
  185. config IRQ_PER_CPU
  186. bool
  187. depends on SMP
  188. default y
  189. config BF_REV_MIN
  190. int
  191. default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
  192. default 2 if (BF537 || BF536 || BF534)
  193. default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
  194. default 4 if (BF538 || BF539)
  195. config BF_REV_MAX
  196. int
  197. default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
  198. default 3 if (BF537 || BF536 || BF534 || BF54xM)
  199. default 5 if (BF561 || BF538 || BF539)
  200. default 6 if (BF533 || BF532 || BF531)
  201. choice
  202. prompt "Silicon Rev"
  203. default BF_REV_0_0 if (BF51x || BF52x)
  204. default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
  205. default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
  206. config BF_REV_0_0
  207. bool "0.0"
  208. depends on (BF51x || BF52x || (BF54x && !BF54xM))
  209. config BF_REV_0_1
  210. bool "0.1"
  211. depends on (BF52x || (BF54x && !BF54xM))
  212. config BF_REV_0_2
  213. bool "0.2"
  214. depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
  215. config BF_REV_0_3
  216. bool "0.3"
  217. depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
  218. config BF_REV_0_4
  219. bool "0.4"
  220. depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
  221. config BF_REV_0_5
  222. bool "0.5"
  223. depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
  224. config BF_REV_0_6
  225. bool "0.6"
  226. depends on (BF533 || BF532 || BF531)
  227. config BF_REV_ANY
  228. bool "any"
  229. config BF_REV_NONE
  230. bool "none"
  231. endchoice
  232. config BF51x
  233. bool
  234. depends on (BF512 || BF514 || BF516 || BF518)
  235. default y
  236. config BF52x
  237. bool
  238. depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
  239. default y
  240. config BF53x
  241. bool
  242. depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
  243. default y
  244. config BF54xM
  245. bool
  246. depends on (BF542M || BF544M || BF547M || BF548M || BF549M)
  247. default y
  248. config BF54x
  249. bool
  250. depends on (BF542 || BF544 || BF547 || BF548 || BF549 || BF54xM)
  251. default y
  252. config MEM_GENERIC_BOARD
  253. bool
  254. depends on GENERIC_BOARD
  255. default y
  256. config MEM_MT48LC64M4A2FB_7E
  257. bool
  258. depends on (BFIN533_STAMP)
  259. default y
  260. config MEM_MT48LC16M16A2TG_75
  261. bool
  262. depends on (BFIN533_EZKIT || BFIN561_EZKIT \
  263. || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
  264. || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM)
  265. default y
  266. config MEM_MT48LC32M8A2_75
  267. bool
  268. depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
  269. default y
  270. config MEM_MT48LC8M32B2B5_7
  271. bool
  272. depends on (BFIN561_BLUETECHNIX_CM)
  273. default y
  274. config MEM_MT48LC32M16A2TG_75
  275. bool
  276. depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
  277. default y
  278. config MEM_MT48LC32M8A2_75
  279. bool
  280. depends on (BFIN518F_EZBRD)
  281. default y
  282. source "arch/blackfin/mach-bf518/Kconfig"
  283. source "arch/blackfin/mach-bf527/Kconfig"
  284. source "arch/blackfin/mach-bf533/Kconfig"
  285. source "arch/blackfin/mach-bf561/Kconfig"
  286. source "arch/blackfin/mach-bf537/Kconfig"
  287. source "arch/blackfin/mach-bf538/Kconfig"
  288. source "arch/blackfin/mach-bf548/Kconfig"
  289. menu "Board customizations"
  290. config CMDLINE_BOOL
  291. bool "Default bootloader kernel arguments"
  292. config CMDLINE
  293. string "Initial kernel command string"
  294. depends on CMDLINE_BOOL
  295. default "console=ttyBF0,57600"
  296. help
  297. If you don't have a boot loader capable of passing a command line string
  298. to the kernel, you may specify one here. As a minimum, you should specify
  299. the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
  300. config BOOT_LOAD
  301. hex "Kernel load address for booting"
  302. default "0x1000"
  303. range 0x1000 0x20000000
  304. help
  305. This option allows you to set the load address of the kernel.
  306. This can be useful if you are on a board which has a small amount
  307. of memory or you wish to reserve some memory at the beginning of
  308. the address space.
  309. Note that you need to keep this value above 4k (0x1000) as this
  310. memory region is used to capture NULL pointer references as well
  311. as some core kernel functions.
  312. config ROM_BASE
  313. hex "Kernel ROM Base"
  314. depends on ROMKERNEL
  315. default "0x20040000"
  316. range 0x20000000 0x20400000 if !(BF54x || BF561)
  317. range 0x20000000 0x30000000 if (BF54x || BF561)
  318. help
  319. comment "Clock/PLL Setup"
  320. config CLKIN_HZ
  321. int "Frequency of the crystal on the board in Hz"
  322. default "11059200" if BFIN533_STAMP
  323. default "27000000" if BFIN533_EZKIT
  324. default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN538_EZKIT || BFIN518F-EZBRD)
  325. default "30000000" if BFIN561_EZKIT
  326. default "24576000" if PNAV10
  327. default "10000000" if BFIN532_IP0X
  328. help
  329. The frequency of CLKIN crystal oscillator on the board in Hz.
  330. Warning: This value should match the crystal on the board. Otherwise,
  331. peripherals won't work properly.
  332. config BFIN_KERNEL_CLOCK
  333. bool "Re-program Clocks while Kernel boots?"
  334. default n
  335. help
  336. This option decides if kernel clocks are re-programed from the
  337. bootloader settings. If the clocks are not set, the SDRAM settings
  338. are also not changed, and the Bootloader does 100% of the hardware
  339. configuration.
  340. config PLL_BYPASS
  341. bool "Bypass PLL"
  342. depends on BFIN_KERNEL_CLOCK
  343. default n
  344. config CLKIN_HALF
  345. bool "Half Clock In"
  346. depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
  347. default n
  348. help
  349. If this is set the clock will be divided by 2, before it goes to the PLL.
  350. config VCO_MULT
  351. int "VCO Multiplier"
  352. depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
  353. range 1 64
  354. default "22" if BFIN533_EZKIT
  355. default "45" if BFIN533_STAMP
  356. default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
  357. default "22" if BFIN533_BLUETECHNIX_CM
  358. default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
  359. default "20" if BFIN561_EZKIT
  360. default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
  361. help
  362. This controls the frequency of the on-chip PLL. This can be between 1 and 64.
  363. PLL Frequency = (Crystal Frequency) * (this setting)
  364. choice
  365. prompt "Core Clock Divider"
  366. depends on BFIN_KERNEL_CLOCK
  367. default CCLK_DIV_1
  368. help
  369. This sets the frequency of the core. It can be 1, 2, 4 or 8
  370. Core Frequency = (PLL frequency) / (this setting)
  371. config CCLK_DIV_1
  372. bool "1"
  373. config CCLK_DIV_2
  374. bool "2"
  375. config CCLK_DIV_4
  376. bool "4"
  377. config CCLK_DIV_8
  378. bool "8"
  379. endchoice
  380. config SCLK_DIV
  381. int "System Clock Divider"
  382. depends on BFIN_KERNEL_CLOCK
  383. range 1 15
  384. default 5
  385. help
  386. This sets the frequency of the system clock (including SDRAM or DDR).
  387. This can be between 1 and 15
  388. System Clock = (PLL frequency) / (this setting)
  389. choice
  390. prompt "DDR SDRAM Chip Type"
  391. depends on BFIN_KERNEL_CLOCK
  392. depends on BF54x
  393. default MEM_MT46V32M16_5B
  394. config MEM_MT46V32M16_6T
  395. bool "MT46V32M16_6T"
  396. config MEM_MT46V32M16_5B
  397. bool "MT46V32M16_5B"
  398. endchoice
  399. choice
  400. prompt "DDR/SDRAM Timing"
  401. depends on BFIN_KERNEL_CLOCK
  402. default BFIN_KERNEL_CLOCK_MEMINIT_CALC
  403. help
  404. This option allows you to specify Blackfin SDRAM/DDR Timing parameters
  405. The calculated SDRAM timing parameters may not be 100%
  406. accurate - This option is therefore marked experimental.
  407. config BFIN_KERNEL_CLOCK_MEMINIT_CALC
  408. bool "Calculate Timings (EXPERIMENTAL)"
  409. depends on EXPERIMENTAL
  410. config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
  411. bool "Provide accurate Timings based on target SCLK"
  412. help
  413. Please consult the Blackfin Hardware Reference Manuals as well
  414. as the memory device datasheet.
  415. http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
  416. endchoice
  417. menu "Memory Init Control"
  418. depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
  419. config MEM_DDRCTL0
  420. depends on BF54x
  421. hex "DDRCTL0"
  422. default 0x0
  423. config MEM_DDRCTL1
  424. depends on BF54x
  425. hex "DDRCTL1"
  426. default 0x0
  427. config MEM_DDRCTL2
  428. depends on BF54x
  429. hex "DDRCTL2"
  430. default 0x0
  431. config MEM_EBIU_DDRQUE
  432. depends on BF54x
  433. hex "DDRQUE"
  434. default 0x0
  435. config MEM_SDRRC
  436. depends on !BF54x
  437. hex "SDRRC"
  438. default 0x0
  439. config MEM_SDGCTL
  440. depends on !BF54x
  441. hex "SDGCTL"
  442. default 0x0
  443. endmenu
  444. #
  445. # Max & Min Speeds for various Chips
  446. #
  447. config MAX_VCO_HZ
  448. int
  449. default 400000000 if BF512
  450. default 400000000 if BF514
  451. default 400000000 if BF516
  452. default 400000000 if BF518
  453. default 600000000 if BF522
  454. default 400000000 if BF523
  455. default 400000000 if BF524
  456. default 600000000 if BF525
  457. default 400000000 if BF526
  458. default 600000000 if BF527
  459. default 400000000 if BF531
  460. default 400000000 if BF532
  461. default 750000000 if BF533
  462. default 500000000 if BF534
  463. default 400000000 if BF536
  464. default 600000000 if BF537
  465. default 533333333 if BF538
  466. default 533333333 if BF539
  467. default 600000000 if BF542
  468. default 533333333 if BF544
  469. default 600000000 if BF547
  470. default 600000000 if BF548
  471. default 533333333 if BF549
  472. default 600000000 if BF561
  473. config MIN_VCO_HZ
  474. int
  475. default 50000000
  476. config MAX_SCLK_HZ
  477. int
  478. default 133333333
  479. config MIN_SCLK_HZ
  480. int
  481. default 27000000
  482. comment "Kernel Timer/Scheduler"
  483. source kernel/Kconfig.hz
  484. config GENERIC_TIME
  485. bool "Generic time"
  486. default y
  487. config GENERIC_CLOCKEVENTS
  488. bool "Generic clock events"
  489. depends on GENERIC_TIME
  490. default y
  491. choice
  492. prompt "Kernel Tick Source"
  493. depends on GENERIC_CLOCKEVENTS
  494. default TICKSOURCE_CORETMR
  495. config TICKSOURCE_GPTMR0
  496. bool "Gptimer0 (SCLK domain)"
  497. select BFIN_GPTIMERS
  498. depends on !IPIPE
  499. config TICKSOURCE_CORETMR
  500. bool "Core timer (CCLK domain)"
  501. endchoice
  502. config CYCLES_CLOCKSOURCE
  503. bool "Use 'CYCLES' as a clocksource"
  504. depends on GENERIC_CLOCKEVENTS
  505. depends on !BFIN_SCRATCH_REG_CYCLES
  506. depends on !SMP
  507. help
  508. If you say Y here, you will enable support for using the 'cycles'
  509. registers as a clock source. Doing so means you will be unable to
  510. safely write to the 'cycles' register during runtime. You will
  511. still be able to read it (such as for performance monitoring), but
  512. writing the registers will most likely crash the kernel.
  513. config GPTMR0_CLOCKSOURCE
  514. bool "Use GPTimer0 as a clocksource (higher rating)"
  515. depends on GENERIC_CLOCKEVENTS
  516. depends on !TICKSOURCE_GPTMR0
  517. source kernel/time/Kconfig
  518. comment "Misc"
  519. choice
  520. prompt "Blackfin Exception Scratch Register"
  521. default BFIN_SCRATCH_REG_RETN
  522. help
  523. Select the resource to reserve for the Exception handler:
  524. - RETN: Non-Maskable Interrupt (NMI)
  525. - RETE: Exception Return (JTAG/ICE)
  526. - CYCLES: Performance counter
  527. If you are unsure, please select "RETN".
  528. config BFIN_SCRATCH_REG_RETN
  529. bool "RETN"
  530. help
  531. Use the RETN register in the Blackfin exception handler
  532. as a stack scratch register. This means you cannot
  533. safely use NMI on the Blackfin while running Linux, but
  534. you can debug the system with a JTAG ICE and use the
  535. CYCLES performance registers.
  536. If you are unsure, please select "RETN".
  537. config BFIN_SCRATCH_REG_RETE
  538. bool "RETE"
  539. help
  540. Use the RETE register in the Blackfin exception handler
  541. as a stack scratch register. This means you cannot
  542. safely use a JTAG ICE while debugging a Blackfin board,
  543. but you can safely use the CYCLES performance registers
  544. and the NMI.
  545. If you are unsure, please select "RETN".
  546. config BFIN_SCRATCH_REG_CYCLES
  547. bool "CYCLES"
  548. help
  549. Use the CYCLES register in the Blackfin exception handler
  550. as a stack scratch register. This means you cannot
  551. safely use the CYCLES performance registers on a Blackfin
  552. board at anytime, but you can debug the system with a JTAG
  553. ICE and use the NMI.
  554. If you are unsure, please select "RETN".
  555. endchoice
  556. endmenu
  557. menu "Blackfin Kernel Optimizations"
  558. depends on !SMP
  559. comment "Memory Optimizations"
  560. config I_ENTRY_L1
  561. bool "Locate interrupt entry code in L1 Memory"
  562. default y
  563. help
  564. If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
  565. into L1 instruction memory. (less latency)
  566. config EXCPT_IRQ_SYSC_L1
  567. bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
  568. default y
  569. help
  570. If enabled, the entire ASM lowlevel exception and interrupt entry code
  571. (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
  572. (less latency)
  573. config DO_IRQ_L1
  574. bool "Locate frequently called do_irq dispatcher function in L1 Memory"
  575. default y
  576. help
  577. If enabled, the frequently called do_irq dispatcher function is linked
  578. into L1 instruction memory. (less latency)
  579. config CORE_TIMER_IRQ_L1
  580. bool "Locate frequently called timer_interrupt() function in L1 Memory"
  581. default y
  582. help
  583. If enabled, the frequently called timer_interrupt() function is linked
  584. into L1 instruction memory. (less latency)
  585. config IDLE_L1
  586. bool "Locate frequently idle function in L1 Memory"
  587. default y
  588. help
  589. If enabled, the frequently called idle function is linked
  590. into L1 instruction memory. (less latency)
  591. config SCHEDULE_L1
  592. bool "Locate kernel schedule function in L1 Memory"
  593. default y
  594. help
  595. If enabled, the frequently called kernel schedule is linked
  596. into L1 instruction memory. (less latency)
  597. config ARITHMETIC_OPS_L1
  598. bool "Locate kernel owned arithmetic functions in L1 Memory"
  599. default y
  600. help
  601. If enabled, arithmetic functions are linked
  602. into L1 instruction memory. (less latency)
  603. config ACCESS_OK_L1
  604. bool "Locate access_ok function in L1 Memory"
  605. default y
  606. help
  607. If enabled, the access_ok function is linked
  608. into L1 instruction memory. (less latency)
  609. config MEMSET_L1
  610. bool "Locate memset function in L1 Memory"
  611. default y
  612. help
  613. If enabled, the memset function is linked
  614. into L1 instruction memory. (less latency)
  615. config MEMCPY_L1
  616. bool "Locate memcpy function in L1 Memory"
  617. default y
  618. help
  619. If enabled, the memcpy function is linked
  620. into L1 instruction memory. (less latency)
  621. config SYS_BFIN_SPINLOCK_L1
  622. bool "Locate sys_bfin_spinlock function in L1 Memory"
  623. default y
  624. help
  625. If enabled, sys_bfin_spinlock function is linked
  626. into L1 instruction memory. (less latency)
  627. config IP_CHECKSUM_L1
  628. bool "Locate IP Checksum function in L1 Memory"
  629. default n
  630. help
  631. If enabled, the IP Checksum function is linked
  632. into L1 instruction memory. (less latency)
  633. config CACHELINE_ALIGNED_L1
  634. bool "Locate cacheline_aligned data to L1 Data Memory"
  635. default y if !BF54x
  636. default n if BF54x
  637. depends on !BF531
  638. help
  639. If enabled, cacheline_aligned data is linked
  640. into L1 data memory. (less latency)
  641. config SYSCALL_TAB_L1
  642. bool "Locate Syscall Table L1 Data Memory"
  643. default n
  644. depends on !BF531
  645. help
  646. If enabled, the Syscall LUT is linked
  647. into L1 data memory. (less latency)
  648. config CPLB_SWITCH_TAB_L1
  649. bool "Locate CPLB Switch Tables L1 Data Memory"
  650. default n
  651. depends on !BF531
  652. help
  653. If enabled, the CPLB Switch Tables are linked
  654. into L1 data memory. (less latency)
  655. config APP_STACK_L1
  656. bool "Support locating application stack in L1 Scratch Memory"
  657. default y
  658. help
  659. If enabled the application stack can be located in L1
  660. scratch memory (less latency).
  661. Currently only works with FLAT binaries.
  662. config EXCEPTION_L1_SCRATCH
  663. bool "Locate exception stack in L1 Scratch Memory"
  664. default n
  665. depends on !APP_STACK_L1
  666. help
  667. Whenever an exception occurs, use the L1 Scratch memory for
  668. stack storage. You cannot place the stacks of FLAT binaries
  669. in L1 when using this option.
  670. If you don't use L1 Scratch, then you should say Y here.
  671. comment "Speed Optimizations"
  672. config BFIN_INS_LOWOVERHEAD
  673. bool "ins[bwl] low overhead, higher interrupt latency"
  674. default y
  675. help
  676. Reads on the Blackfin are speculative. In Blackfin terms, this means
  677. they can be interrupted at any time (even after they have been issued
  678. on to the external bus), and re-issued after the interrupt occurs.
  679. For memory - this is not a big deal, since memory does not change if
  680. it sees a read.
  681. If a FIFO is sitting on the end of the read, it will see two reads,
  682. when the core only sees one since the FIFO receives both the read
  683. which is cancelled (and not delivered to the core) and the one which
  684. is re-issued (which is delivered to the core).
  685. To solve this, interrupts are turned off before reads occur to
  686. I/O space. This option controls which the overhead/latency of
  687. controlling interrupts during this time
  688. "n" turns interrupts off every read
  689. (higher overhead, but lower interrupt latency)
  690. "y" turns interrupts off every loop
  691. (low overhead, but longer interrupt latency)
  692. default behavior is to leave this set to on (type "Y"). If you are experiencing
  693. interrupt latency issues, it is safe and OK to turn this off.
  694. endmenu
  695. choice
  696. prompt "Kernel executes from"
  697. help
  698. Choose the memory type that the kernel will be running in.
  699. config RAMKERNEL
  700. bool "RAM"
  701. help
  702. The kernel will be resident in RAM when running.
  703. config ROMKERNEL
  704. bool "ROM"
  705. help
  706. The kernel will be resident in FLASH/ROM when running.
  707. endchoice
  708. source "mm/Kconfig"
  709. config BFIN_GPTIMERS
  710. tristate "Enable Blackfin General Purpose Timers API"
  711. default n
  712. help
  713. Enable support for the General Purpose Timers API. If you
  714. are unsure, say N.
  715. To compile this driver as a module, choose M here: the module
  716. will be called gptimers.ko.
  717. choice
  718. prompt "Uncached DMA region"
  719. default DMA_UNCACHED_1M
  720. config DMA_UNCACHED_4M
  721. bool "Enable 4M DMA region"
  722. config DMA_UNCACHED_2M
  723. bool "Enable 2M DMA region"
  724. config DMA_UNCACHED_1M
  725. bool "Enable 1M DMA region"
  726. config DMA_UNCACHED_NONE
  727. bool "Disable DMA region"
  728. endchoice
  729. comment "Cache Support"
  730. config BFIN_ICACHE
  731. bool "Enable ICACHE"
  732. config BFIN_DCACHE
  733. bool "Enable DCACHE"
  734. config BFIN_DCACHE_BANKA
  735. bool "Enable only 16k BankA DCACHE - BankB is SRAM"
  736. depends on BFIN_DCACHE && !BF531
  737. default n
  738. config BFIN_ICACHE_LOCK
  739. bool "Enable Instruction Cache Locking"
  740. choice
  741. prompt "Policy"
  742. depends on BFIN_DCACHE
  743. default BFIN_WB if !SMP
  744. default BFIN_WT if SMP
  745. config BFIN_WB
  746. bool "Write back"
  747. depends on !SMP
  748. help
  749. Write Back Policy:
  750. Cached data will be written back to SDRAM only when needed.
  751. This can give a nice increase in performance, but beware of
  752. broken drivers that do not properly invalidate/flush their
  753. cache.
  754. Write Through Policy:
  755. Cached data will always be written back to SDRAM when the
  756. cache is updated. This is a completely safe setting, but
  757. performance is worse than Write Back.
  758. If you are unsure of the options and you want to be safe,
  759. then go with Write Through.
  760. config BFIN_WT
  761. bool "Write through"
  762. help
  763. Write Back Policy:
  764. Cached data will be written back to SDRAM only when needed.
  765. This can give a nice increase in performance, but beware of
  766. broken drivers that do not properly invalidate/flush their
  767. cache.
  768. Write Through Policy:
  769. Cached data will always be written back to SDRAM when the
  770. cache is updated. This is a completely safe setting, but
  771. performance is worse than Write Back.
  772. If you are unsure of the options and you want to be safe,
  773. then go with Write Through.
  774. endchoice
  775. config BFIN_L2_CACHEABLE
  776. bool "Cache L2 SRAM"
  777. depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || (BF561 && !SMP))
  778. default n
  779. help
  780. Select to make L2 SRAM cacheable in L1 data and instruction cache.
  781. config MPU
  782. bool "Enable the memory protection unit (EXPERIMENTAL)"
  783. default n
  784. help
  785. Use the processor's MPU to protect applications from accessing
  786. memory they do not own. This comes at a performance penalty
  787. and is recommended only for debugging.
  788. comment "Asynchronous Memory Configuration"
  789. menu "EBIU_AMGCTL Global Control"
  790. config C_AMCKEN
  791. bool "Enable CLKOUT"
  792. default y
  793. config C_CDPRIO
  794. bool "DMA has priority over core for ext. accesses"
  795. default n
  796. config C_B0PEN
  797. depends on BF561
  798. bool "Bank 0 16 bit packing enable"
  799. default y
  800. config C_B1PEN
  801. depends on BF561
  802. bool "Bank 1 16 bit packing enable"
  803. default y
  804. config C_B2PEN
  805. depends on BF561
  806. bool "Bank 2 16 bit packing enable"
  807. default y
  808. config C_B3PEN
  809. depends on BF561
  810. bool "Bank 3 16 bit packing enable"
  811. default n
  812. choice
  813. prompt "Enable Asynchronous Memory Banks"
  814. default C_AMBEN_ALL
  815. config C_AMBEN
  816. bool "Disable All Banks"
  817. config C_AMBEN_B0
  818. bool "Enable Bank 0"
  819. config C_AMBEN_B0_B1
  820. bool "Enable Bank 0 & 1"
  821. config C_AMBEN_B0_B1_B2
  822. bool "Enable Bank 0 & 1 & 2"
  823. config C_AMBEN_ALL
  824. bool "Enable All Banks"
  825. endchoice
  826. endmenu
  827. menu "EBIU_AMBCTL Control"
  828. config BANK_0
  829. hex "Bank 0 (AMBCTL0.L)"
  830. default 0x7BB0
  831. help
  832. These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
  833. used to control the Asynchronous Memory Bank 0 settings.
  834. config BANK_1
  835. hex "Bank 1 (AMBCTL0.H)"
  836. default 0x7BB0
  837. default 0x5558 if BF54x
  838. help
  839. These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
  840. used to control the Asynchronous Memory Bank 1 settings.
  841. config BANK_2
  842. hex "Bank 2 (AMBCTL1.L)"
  843. default 0x7BB0
  844. help
  845. These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
  846. used to control the Asynchronous Memory Bank 2 settings.
  847. config BANK_3
  848. hex "Bank 3 (AMBCTL1.H)"
  849. default 0x99B3
  850. help
  851. These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
  852. used to control the Asynchronous Memory Bank 3 settings.
  853. endmenu
  854. config EBIU_MBSCTLVAL
  855. hex "EBIU Bank Select Control Register"
  856. depends on BF54x
  857. default 0
  858. config EBIU_MODEVAL
  859. hex "Flash Memory Mode Control Register"
  860. depends on BF54x
  861. default 1
  862. config EBIU_FCTLVAL
  863. hex "Flash Memory Bank Control Register"
  864. depends on BF54x
  865. default 6
  866. endmenu
  867. #############################################################################
  868. menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
  869. config PCI
  870. bool "PCI support"
  871. depends on BROKEN
  872. help
  873. Support for PCI bus.
  874. source "drivers/pci/Kconfig"
  875. config HOTPLUG
  876. bool "Support for hot-pluggable device"
  877. help
  878. Say Y here if you want to plug devices into your computer while
  879. the system is running, and be able to use them quickly. In many
  880. cases, the devices can likewise be unplugged at any time too.
  881. One well known example of this is PCMCIA- or PC-cards, credit-card
  882. size devices such as network cards, modems or hard drives which are
  883. plugged into slots found on all modern laptop computers. Another
  884. example, used on modern desktops as well as laptops, is USB.
  885. Enable HOTPLUG and build a modular kernel. Get agent software
  886. (from <http://linux-hotplug.sourceforge.net/>) and install it.
  887. Then your kernel will automatically call out to a user mode "policy
  888. agent" (/sbin/hotplug) to load modules and set up software needed
  889. to use devices as you hotplug them.
  890. source "drivers/pcmcia/Kconfig"
  891. source "drivers/pci/hotplug/Kconfig"
  892. endmenu
  893. menu "Executable file formats"
  894. source "fs/Kconfig.binfmt"
  895. endmenu
  896. menu "Power management options"
  897. source "kernel/power/Kconfig"
  898. config ARCH_SUSPEND_POSSIBLE
  899. def_bool y
  900. depends on !SMP
  901. choice
  902. prompt "Standby Power Saving Mode"
  903. depends on PM
  904. default PM_BFIN_SLEEP_DEEPER
  905. config PM_BFIN_SLEEP_DEEPER
  906. bool "Sleep Deeper"
  907. help
  908. Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
  909. power dissipation by disabling the clock to the processor core (CCLK).
  910. Furthermore, Standby sets the internal power supply voltage (VDDINT)
  911. to 0.85 V to provide the greatest power savings, while preserving the
  912. processor state.
  913. The PLL and system clock (SCLK) continue to operate at a very low
  914. frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
  915. the SDRAM is put into Self Refresh Mode. Typically an external event
  916. such as GPIO interrupt or RTC activity wakes up the processor.
  917. Various Peripherals such as UART, SPORT, PPI may not function as
  918. normal during Sleep Deeper, due to the reduced SCLK frequency.
  919. When in the sleep mode, system DMA access to L1 memory is not supported.
  920. If unsure, select "Sleep Deeper".
  921. config PM_BFIN_SLEEP
  922. bool "Sleep"
  923. help
  924. Sleep Mode (High Power Savings) - The sleep mode reduces power
  925. dissipation by disabling the clock to the processor core (CCLK).
  926. The PLL and system clock (SCLK), however, continue to operate in
  927. this mode. Typically an external event or RTC activity will wake
  928. up the processor. When in the sleep mode, system DMA access to L1
  929. memory is not supported.
  930. If unsure, select "Sleep Deeper".
  931. endchoice
  932. config PM_WAKEUP_BY_GPIO
  933. bool "Allow Wakeup from Standby by GPIO"
  934. depends on PM && !BF54x
  935. config PM_WAKEUP_GPIO_NUMBER
  936. int "GPIO number"
  937. range 0 47
  938. depends on PM_WAKEUP_BY_GPIO
  939. default 2
  940. choice
  941. prompt "GPIO Polarity"
  942. depends on PM_WAKEUP_BY_GPIO
  943. default PM_WAKEUP_GPIO_POLAR_H
  944. config PM_WAKEUP_GPIO_POLAR_H
  945. bool "Active High"
  946. config PM_WAKEUP_GPIO_POLAR_L
  947. bool "Active Low"
  948. config PM_WAKEUP_GPIO_POLAR_EDGE_F
  949. bool "Falling EDGE"
  950. config PM_WAKEUP_GPIO_POLAR_EDGE_R
  951. bool "Rising EDGE"
  952. config PM_WAKEUP_GPIO_POLAR_EDGE_B
  953. bool "Both EDGE"
  954. endchoice
  955. comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
  956. depends on PM
  957. config PM_BFIN_WAKE_PH6
  958. bool "Allow Wake-Up from on-chip PHY or PH6 GP"
  959. depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
  960. default n
  961. help
  962. Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
  963. config PM_BFIN_WAKE_GP
  964. bool "Allow Wake-Up from GPIOs"
  965. depends on PM && BF54x
  966. default n
  967. help
  968. Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
  969. (all processors, except ADSP-BF549). This option sets
  970. the general-purpose wake-up enable (GPWE) control bit to enable
  971. wake-up upon detection of an active low signal on the /GPW (PH7) pin.
  972. On ADSP-BF549 this option enables the the same functionality on the
  973. /MRXON pin also PH7.
  974. endmenu
  975. menu "CPU Frequency scaling"
  976. source "drivers/cpufreq/Kconfig"
  977. config BFIN_CPU_FREQ
  978. bool
  979. depends on CPU_FREQ
  980. select CPU_FREQ_TABLE
  981. default y
  982. config CPU_VOLTAGE
  983. bool "CPU Voltage scaling"
  984. depends on EXPERIMENTAL
  985. depends on CPU_FREQ
  986. default n
  987. help
  988. Say Y here if you want CPU voltage scaling according to the CPU frequency.
  989. This option violates the PLL BYPASS recommendation in the Blackfin Processor
  990. manuals. There is a theoretical risk that during VDDINT transitions
  991. the PLL may unlock.
  992. endmenu
  993. source "net/Kconfig"
  994. source "drivers/Kconfig"
  995. source "fs/Kconfig"
  996. source "arch/blackfin/Kconfig.debug"
  997. source "security/Kconfig"
  998. source "crypto/Kconfig"
  999. source "lib/Kconfig"