nv50_display.c 25 KB

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  1. /*
  2. * Copyright (C) 2008 Maarten Maathuis.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining
  6. * a copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sublicense, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * The above copyright notice and this permission notice (including the
  14. * next paragraph) shall be included in all copies or substantial
  15. * portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20. * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21. * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22. * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23. * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24. *
  25. */
  26. #include "nv50_display.h"
  27. #include "nouveau_crtc.h"
  28. #include "nouveau_encoder.h"
  29. #include "nouveau_connector.h"
  30. #include "nouveau_fb.h"
  31. #include "nouveau_fbcon.h"
  32. #include "nouveau_ramht.h"
  33. #include "drm_crtc_helper.h"
  34. static inline int
  35. nv50_sor_nr(struct drm_device *dev)
  36. {
  37. struct drm_nouveau_private *dev_priv = dev->dev_private;
  38. if (dev_priv->chipset < 0x90 ||
  39. dev_priv->chipset == 0x92 ||
  40. dev_priv->chipset == 0xa0)
  41. return 2;
  42. return 4;
  43. }
  44. int
  45. nv50_display_early_init(struct drm_device *dev)
  46. {
  47. return 0;
  48. }
  49. void
  50. nv50_display_late_takedown(struct drm_device *dev)
  51. {
  52. }
  53. int
  54. nv50_display_init(struct drm_device *dev)
  55. {
  56. struct drm_nouveau_private *dev_priv = dev->dev_private;
  57. struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
  58. struct drm_connector *connector;
  59. struct nouveau_channel *evo;
  60. int ret, i;
  61. u32 val;
  62. NV_DEBUG_KMS(dev, "\n");
  63. nv_wr32(dev, 0x00610184, nv_rd32(dev, 0x00614004));
  64. /*
  65. * I think the 0x006101XX range is some kind of main control area
  66. * that enables things.
  67. */
  68. /* CRTC? */
  69. for (i = 0; i < 2; i++) {
  70. val = nv_rd32(dev, 0x00616100 + (i * 0x800));
  71. nv_wr32(dev, 0x00610190 + (i * 0x10), val);
  72. val = nv_rd32(dev, 0x00616104 + (i * 0x800));
  73. nv_wr32(dev, 0x00610194 + (i * 0x10), val);
  74. val = nv_rd32(dev, 0x00616108 + (i * 0x800));
  75. nv_wr32(dev, 0x00610198 + (i * 0x10), val);
  76. val = nv_rd32(dev, 0x0061610c + (i * 0x800));
  77. nv_wr32(dev, 0x0061019c + (i * 0x10), val);
  78. }
  79. /* DAC */
  80. for (i = 0; i < 3; i++) {
  81. val = nv_rd32(dev, 0x0061a000 + (i * 0x800));
  82. nv_wr32(dev, 0x006101d0 + (i * 0x04), val);
  83. }
  84. /* SOR */
  85. for (i = 0; i < nv50_sor_nr(dev); i++) {
  86. val = nv_rd32(dev, 0x0061c000 + (i * 0x800));
  87. nv_wr32(dev, 0x006101e0 + (i * 0x04), val);
  88. }
  89. /* EXT */
  90. for (i = 0; i < 3; i++) {
  91. val = nv_rd32(dev, 0x0061e000 + (i * 0x800));
  92. nv_wr32(dev, 0x006101f0 + (i * 0x04), val);
  93. }
  94. for (i = 0; i < 3; i++) {
  95. nv_wr32(dev, NV50_PDISPLAY_DAC_DPMS_CTRL(i), 0x00550000 |
  96. NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING);
  97. nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL1(i), 0x00000001);
  98. }
  99. /* The precise purpose is unknown, i suspect it has something to do
  100. * with text mode.
  101. */
  102. if (nv_rd32(dev, NV50_PDISPLAY_INTR_1) & 0x100) {
  103. nv_wr32(dev, NV50_PDISPLAY_INTR_1, 0x100);
  104. nv_wr32(dev, 0x006194e8, nv_rd32(dev, 0x006194e8) & ~1);
  105. if (!nv_wait(dev, 0x006194e8, 2, 0)) {
  106. NV_ERROR(dev, "timeout: (0x6194e8 & 2) != 0\n");
  107. NV_ERROR(dev, "0x6194e8 = 0x%08x\n",
  108. nv_rd32(dev, 0x6194e8));
  109. return -EBUSY;
  110. }
  111. }
  112. for (i = 0; i < 2; i++) {
  113. nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0x2000);
  114. if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
  115. NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) {
  116. NV_ERROR(dev, "timeout: CURSOR_CTRL2_STATUS == 0\n");
  117. NV_ERROR(dev, "CURSOR_CTRL2 = 0x%08x\n",
  118. nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
  119. return -EBUSY;
  120. }
  121. nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
  122. NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON);
  123. if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
  124. NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS,
  125. NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE)) {
  126. NV_ERROR(dev, "timeout: "
  127. "CURSOR_CTRL2_STATUS_ACTIVE(%d)\n", i);
  128. NV_ERROR(dev, "CURSOR_CTRL2(%d) = 0x%08x\n", i,
  129. nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
  130. return -EBUSY;
  131. }
  132. }
  133. nv_wr32(dev, NV50_PDISPLAY_PIO_CTRL, 0x00000000);
  134. nv_mask(dev, NV50_PDISPLAY_INTR_0, 0x00000000, 0x00000000);
  135. nv_wr32(dev, NV50_PDISPLAY_INTR_EN_0, 0x00000000);
  136. nv_mask(dev, NV50_PDISPLAY_INTR_1, 0x00000000, 0x00000000);
  137. nv_wr32(dev, NV50_PDISPLAY_INTR_EN_1,
  138. NV50_PDISPLAY_INTR_EN_1_CLK_UNK10 |
  139. NV50_PDISPLAY_INTR_EN_1_CLK_UNK20 |
  140. NV50_PDISPLAY_INTR_EN_1_CLK_UNK40);
  141. /* enable hotplug interrupts */
  142. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  143. struct nouveau_connector *conn = nouveau_connector(connector);
  144. if (conn->dcb->gpio_tag == 0xff)
  145. continue;
  146. pgpio->irq_enable(dev, conn->dcb->gpio_tag, true);
  147. }
  148. ret = nv50_evo_init(dev);
  149. if (ret)
  150. return ret;
  151. evo = dev_priv->evo;
  152. nv_wr32(dev, NV50_PDISPLAY_OBJECTS, (evo->ramin->vinst >> 8) | 9);
  153. ret = RING_SPACE(evo, 11);
  154. if (ret)
  155. return ret;
  156. BEGIN_RING(evo, 0, NV50_EVO_UNK84, 2);
  157. OUT_RING(evo, NV50_EVO_UNK84_NOTIFY_DISABLED);
  158. OUT_RING(evo, NV50_EVO_DMA_NOTIFY_HANDLE_NONE);
  159. BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, FB_DMA), 1);
  160. OUT_RING(evo, NV50_EVO_CRTC_FB_DMA_HANDLE_NONE);
  161. BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK0800), 1);
  162. OUT_RING(evo, 0);
  163. BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, DISPLAY_START), 1);
  164. OUT_RING(evo, 0);
  165. BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK082C), 1);
  166. OUT_RING(evo, 0);
  167. FIRE_RING(evo);
  168. if (!nv_wait(dev, 0x640004, 0xffffffff, evo->dma.put << 2))
  169. NV_ERROR(dev, "evo pushbuf stalled\n");
  170. return 0;
  171. }
  172. static int nv50_display_disable(struct drm_device *dev)
  173. {
  174. struct drm_nouveau_private *dev_priv = dev->dev_private;
  175. struct drm_crtc *drm_crtc;
  176. int ret, i;
  177. NV_DEBUG_KMS(dev, "\n");
  178. list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
  179. struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
  180. nv50_crtc_blank(crtc, true);
  181. }
  182. ret = RING_SPACE(dev_priv->evo, 2);
  183. if (ret == 0) {
  184. BEGIN_RING(dev_priv->evo, 0, NV50_EVO_UPDATE, 1);
  185. OUT_RING(dev_priv->evo, 0);
  186. }
  187. FIRE_RING(dev_priv->evo);
  188. /* Almost like ack'ing a vblank interrupt, maybe in the spirit of
  189. * cleaning up?
  190. */
  191. list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
  192. struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
  193. uint32_t mask = NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(crtc->index);
  194. if (!crtc->base.enabled)
  195. continue;
  196. nv_wr32(dev, NV50_PDISPLAY_INTR_1, mask);
  197. if (!nv_wait(dev, NV50_PDISPLAY_INTR_1, mask, mask)) {
  198. NV_ERROR(dev, "timeout: (0x610024 & 0x%08x) == "
  199. "0x%08x\n", mask, mask);
  200. NV_ERROR(dev, "0x610024 = 0x%08x\n",
  201. nv_rd32(dev, NV50_PDISPLAY_INTR_1));
  202. }
  203. }
  204. nv50_evo_fini(dev);
  205. for (i = 0; i < 3; i++) {
  206. if (!nv_wait(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i),
  207. NV50_PDISPLAY_SOR_DPMS_STATE_WAIT, 0)) {
  208. NV_ERROR(dev, "timeout: SOR_DPMS_STATE_WAIT(%d) == 0\n", i);
  209. NV_ERROR(dev, "SOR_DPMS_STATE(%d) = 0x%08x\n", i,
  210. nv_rd32(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i)));
  211. }
  212. }
  213. /* disable interrupts. */
  214. nv_wr32(dev, NV50_PDISPLAY_INTR_EN_1, 0x00000000);
  215. /* disable hotplug interrupts */
  216. nv_wr32(dev, 0xe054, 0xffffffff);
  217. nv_wr32(dev, 0xe050, 0x00000000);
  218. if (dev_priv->chipset >= 0x90) {
  219. nv_wr32(dev, 0xe074, 0xffffffff);
  220. nv_wr32(dev, 0xe070, 0x00000000);
  221. }
  222. return 0;
  223. }
  224. int nv50_display_create(struct drm_device *dev)
  225. {
  226. struct drm_nouveau_private *dev_priv = dev->dev_private;
  227. struct dcb_table *dcb = &dev_priv->vbios.dcb;
  228. struct drm_connector *connector, *ct;
  229. int ret, i;
  230. NV_DEBUG_KMS(dev, "\n");
  231. /* init basic kernel modesetting */
  232. drm_mode_config_init(dev);
  233. /* Initialise some optional connector properties. */
  234. drm_mode_create_scaling_mode_property(dev);
  235. drm_mode_create_dithering_property(dev);
  236. dev->mode_config.min_width = 0;
  237. dev->mode_config.min_height = 0;
  238. dev->mode_config.funcs = (void *)&nouveau_mode_config_funcs;
  239. dev->mode_config.max_width = 8192;
  240. dev->mode_config.max_height = 8192;
  241. dev->mode_config.fb_base = dev_priv->fb_phys;
  242. /* Create CRTC objects */
  243. for (i = 0; i < 2; i++)
  244. nv50_crtc_create(dev, i);
  245. /* We setup the encoders from the BIOS table */
  246. for (i = 0 ; i < dcb->entries; i++) {
  247. struct dcb_entry *entry = &dcb->entry[i];
  248. if (entry->location != DCB_LOC_ON_CHIP) {
  249. NV_WARN(dev, "Off-chip encoder %d/%d unsupported\n",
  250. entry->type, ffs(entry->or) - 1);
  251. continue;
  252. }
  253. connector = nouveau_connector_create(dev, entry->connector);
  254. if (IS_ERR(connector))
  255. continue;
  256. switch (entry->type) {
  257. case OUTPUT_TMDS:
  258. case OUTPUT_LVDS:
  259. case OUTPUT_DP:
  260. nv50_sor_create(connector, entry);
  261. break;
  262. case OUTPUT_ANALOG:
  263. nv50_dac_create(connector, entry);
  264. break;
  265. default:
  266. NV_WARN(dev, "DCB encoder %d unknown\n", entry->type);
  267. continue;
  268. }
  269. }
  270. list_for_each_entry_safe(connector, ct,
  271. &dev->mode_config.connector_list, head) {
  272. if (!connector->encoder_ids[0]) {
  273. NV_WARN(dev, "%s has no encoders, removing\n",
  274. drm_get_connector_name(connector));
  275. connector->funcs->destroy(connector);
  276. }
  277. }
  278. ret = nv50_display_init(dev);
  279. if (ret) {
  280. nv50_display_destroy(dev);
  281. return ret;
  282. }
  283. return 0;
  284. }
  285. void
  286. nv50_display_destroy(struct drm_device *dev)
  287. {
  288. NV_DEBUG_KMS(dev, "\n");
  289. drm_mode_config_cleanup(dev);
  290. nv50_display_disable(dev);
  291. }
  292. static u16
  293. nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcb,
  294. u32 mc, int pxclk)
  295. {
  296. struct drm_nouveau_private *dev_priv = dev->dev_private;
  297. struct nouveau_connector *nv_connector = NULL;
  298. struct drm_encoder *encoder;
  299. struct nvbios *bios = &dev_priv->vbios;
  300. u32 script = 0, or;
  301. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  302. struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
  303. if (nv_encoder->dcb != dcb)
  304. continue;
  305. nv_connector = nouveau_encoder_connector_get(nv_encoder);
  306. break;
  307. }
  308. or = ffs(dcb->or) - 1;
  309. switch (dcb->type) {
  310. case OUTPUT_LVDS:
  311. script = (mc >> 8) & 0xf;
  312. if (bios->fp_no_ddc) {
  313. if (bios->fp.dual_link)
  314. script |= 0x0100;
  315. if (bios->fp.if_is_24bit)
  316. script |= 0x0200;
  317. } else {
  318. if (pxclk >= bios->fp.duallink_transition_clk) {
  319. script |= 0x0100;
  320. if (bios->fp.strapless_is_24bit & 2)
  321. script |= 0x0200;
  322. } else
  323. if (bios->fp.strapless_is_24bit & 1)
  324. script |= 0x0200;
  325. if (nv_connector && nv_connector->edid &&
  326. (nv_connector->edid->revision >= 4) &&
  327. (nv_connector->edid->input & 0x70) >= 0x20)
  328. script |= 0x0200;
  329. }
  330. if (nouveau_uscript_lvds >= 0) {
  331. NV_INFO(dev, "override script 0x%04x with 0x%04x "
  332. "for output LVDS-%d\n", script,
  333. nouveau_uscript_lvds, or);
  334. script = nouveau_uscript_lvds;
  335. }
  336. break;
  337. case OUTPUT_TMDS:
  338. script = (mc >> 8) & 0xf;
  339. if (pxclk >= 165000)
  340. script |= 0x0100;
  341. if (nouveau_uscript_tmds >= 0) {
  342. NV_INFO(dev, "override script 0x%04x with 0x%04x "
  343. "for output TMDS-%d\n", script,
  344. nouveau_uscript_tmds, or);
  345. script = nouveau_uscript_tmds;
  346. }
  347. break;
  348. case OUTPUT_DP:
  349. script = (mc >> 8) & 0xf;
  350. break;
  351. case OUTPUT_ANALOG:
  352. script = 0xff;
  353. break;
  354. default:
  355. NV_ERROR(dev, "modeset on unsupported output type!\n");
  356. break;
  357. }
  358. return script;
  359. }
  360. static void
  361. nv50_display_vblank_crtc_handler(struct drm_device *dev, int crtc)
  362. {
  363. struct drm_nouveau_private *dev_priv = dev->dev_private;
  364. struct nouveau_channel *chan, *tmp;
  365. list_for_each_entry_safe(chan, tmp, &dev_priv->vbl_waiting,
  366. nvsw.vbl_wait) {
  367. if (chan->nvsw.vblsem_head != crtc)
  368. continue;
  369. nouveau_bo_wr32(chan->notifier_bo, chan->nvsw.vblsem_offset,
  370. chan->nvsw.vblsem_rval);
  371. list_del(&chan->nvsw.vbl_wait);
  372. drm_vblank_put(dev, crtc);
  373. }
  374. drm_handle_vblank(dev, crtc);
  375. }
  376. static void
  377. nv50_display_vblank_handler(struct drm_device *dev, uint32_t intr)
  378. {
  379. if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_0)
  380. nv50_display_vblank_crtc_handler(dev, 0);
  381. if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_1)
  382. nv50_display_vblank_crtc_handler(dev, 1);
  383. nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_VBLANK_CRTC);
  384. }
  385. static void
  386. nv50_display_unk10_handler(struct drm_device *dev)
  387. {
  388. struct drm_nouveau_private *dev_priv = dev->dev_private;
  389. u32 unk30 = nv_rd32(dev, 0x610030), mc;
  390. int i, crtc, or, type = OUTPUT_ANY;
  391. NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
  392. dev_priv->evo_irq.dcb = NULL;
  393. nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) & ~8);
  394. /* Determine which CRTC we're dealing with, only 1 ever will be
  395. * signalled at the same time with the current nouveau code.
  396. */
  397. crtc = ffs((unk30 & 0x00000060) >> 5) - 1;
  398. if (crtc < 0)
  399. goto ack;
  400. /* Nothing needs to be done for the encoder */
  401. crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
  402. if (crtc < 0)
  403. goto ack;
  404. /* Find which encoder was connected to the CRTC */
  405. for (i = 0; type == OUTPUT_ANY && i < 3; i++) {
  406. mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_C(i));
  407. NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
  408. if (!(mc & (1 << crtc)))
  409. continue;
  410. switch ((mc & 0x00000f00) >> 8) {
  411. case 0: type = OUTPUT_ANALOG; break;
  412. case 1: type = OUTPUT_TV; break;
  413. default:
  414. NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
  415. goto ack;
  416. }
  417. or = i;
  418. }
  419. for (i = 0; type == OUTPUT_ANY && i < nv50_sor_nr(dev); i++) {
  420. if (dev_priv->chipset < 0x90 ||
  421. dev_priv->chipset == 0x92 ||
  422. dev_priv->chipset == 0xa0)
  423. mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(i));
  424. else
  425. mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(i));
  426. NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
  427. if (!(mc & (1 << crtc)))
  428. continue;
  429. switch ((mc & 0x00000f00) >> 8) {
  430. case 0: type = OUTPUT_LVDS; break;
  431. case 1: type = OUTPUT_TMDS; break;
  432. case 2: type = OUTPUT_TMDS; break;
  433. case 5: type = OUTPUT_TMDS; break;
  434. case 8: type = OUTPUT_DP; break;
  435. case 9: type = OUTPUT_DP; break;
  436. default:
  437. NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
  438. goto ack;
  439. }
  440. or = i;
  441. }
  442. /* There was no encoder to disable */
  443. if (type == OUTPUT_ANY)
  444. goto ack;
  445. /* Disable the encoder */
  446. for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
  447. struct dcb_entry *dcb = &dev_priv->vbios.dcb.entry[i];
  448. if (dcb->type == type && (dcb->or & (1 << or))) {
  449. nouveau_bios_run_display_table(dev, dcb, 0, -1);
  450. dev_priv->evo_irq.dcb = dcb;
  451. goto ack;
  452. }
  453. }
  454. NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
  455. ack:
  456. nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK10);
  457. nv_wr32(dev, 0x610030, 0x80000000);
  458. }
  459. static void
  460. nv50_display_unk20_dp_hack(struct drm_device *dev, struct dcb_entry *dcb)
  461. {
  462. int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1);
  463. struct drm_encoder *encoder;
  464. uint32_t tmp, unk0 = 0, unk1 = 0;
  465. if (dcb->type != OUTPUT_DP)
  466. return;
  467. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  468. struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
  469. if (nv_encoder->dcb == dcb) {
  470. unk0 = nv_encoder->dp.unk0;
  471. unk1 = nv_encoder->dp.unk1;
  472. break;
  473. }
  474. }
  475. if (unk0 || unk1) {
  476. tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
  477. tmp &= 0xfffffe03;
  478. nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp | unk0);
  479. tmp = nv_rd32(dev, NV50_SOR_DP_UNK128(or, link));
  480. tmp &= 0xfef080c0;
  481. nv_wr32(dev, NV50_SOR_DP_UNK128(or, link), tmp | unk1);
  482. }
  483. }
  484. static void
  485. nv50_display_unk20_handler(struct drm_device *dev)
  486. {
  487. struct drm_nouveau_private *dev_priv = dev->dev_private;
  488. u32 unk30 = nv_rd32(dev, 0x610030), tmp, pclk, script, mc;
  489. struct dcb_entry *dcb;
  490. int i, crtc, or, type = OUTPUT_ANY;
  491. NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
  492. dcb = dev_priv->evo_irq.dcb;
  493. if (dcb) {
  494. nouveau_bios_run_display_table(dev, dcb, 0, -2);
  495. dev_priv->evo_irq.dcb = NULL;
  496. }
  497. /* CRTC clock change requested? */
  498. crtc = ffs((unk30 & 0x00000600) >> 9) - 1;
  499. if (crtc >= 0) {
  500. pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK));
  501. pclk &= 0x003fffff;
  502. nv50_crtc_set_clock(dev, crtc, pclk);
  503. tmp = nv_rd32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc));
  504. tmp &= ~0x000000f;
  505. nv_wr32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc), tmp);
  506. }
  507. /* Nothing needs to be done for the encoder */
  508. crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
  509. if (crtc < 0)
  510. goto ack;
  511. pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK)) & 0x003fffff;
  512. /* Find which encoder is connected to the CRTC */
  513. for (i = 0; type == OUTPUT_ANY && i < 3; i++) {
  514. mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_P(i));
  515. NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
  516. if (!(mc & (1 << crtc)))
  517. continue;
  518. switch ((mc & 0x00000f00) >> 8) {
  519. case 0: type = OUTPUT_ANALOG; break;
  520. case 1: type = OUTPUT_TV; break;
  521. default:
  522. NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
  523. goto ack;
  524. }
  525. or = i;
  526. }
  527. for (i = 0; type == OUTPUT_ANY && i < nv50_sor_nr(dev); i++) {
  528. if (dev_priv->chipset < 0x90 ||
  529. dev_priv->chipset == 0x92 ||
  530. dev_priv->chipset == 0xa0)
  531. mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_P(i));
  532. else
  533. mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_P(i));
  534. NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
  535. if (!(mc & (1 << crtc)))
  536. continue;
  537. switch ((mc & 0x00000f00) >> 8) {
  538. case 0: type = OUTPUT_LVDS; break;
  539. case 1: type = OUTPUT_TMDS; break;
  540. case 2: type = OUTPUT_TMDS; break;
  541. case 5: type = OUTPUT_TMDS; break;
  542. case 8: type = OUTPUT_DP; break;
  543. case 9: type = OUTPUT_DP; break;
  544. default:
  545. NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
  546. goto ack;
  547. }
  548. or = i;
  549. }
  550. if (type == OUTPUT_ANY)
  551. goto ack;
  552. /* Enable the encoder */
  553. for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
  554. dcb = &dev_priv->vbios.dcb.entry[i];
  555. if (dcb->type == type && (dcb->or & (1 << or)))
  556. break;
  557. }
  558. if (i == dev_priv->vbios.dcb.entries) {
  559. NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
  560. goto ack;
  561. }
  562. script = nv50_display_script_select(dev, dcb, mc, pclk);
  563. nouveau_bios_run_display_table(dev, dcb, script, pclk);
  564. nv50_display_unk20_dp_hack(dev, dcb);
  565. if (dcb->type != OUTPUT_ANALOG) {
  566. tmp = nv_rd32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or));
  567. tmp &= ~0x00000f0f;
  568. if (script & 0x0100)
  569. tmp |= 0x00000101;
  570. nv_wr32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or), tmp);
  571. } else {
  572. nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL2(or), 0);
  573. }
  574. dev_priv->evo_irq.dcb = dcb;
  575. dev_priv->evo_irq.pclk = pclk;
  576. dev_priv->evo_irq.script = script;
  577. ack:
  578. nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK20);
  579. nv_wr32(dev, 0x610030, 0x80000000);
  580. }
  581. /* If programming a TMDS output on a SOR that can also be configured for
  582. * DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off.
  583. *
  584. * It looks like the VBIOS TMDS scripts make an attempt at this, however,
  585. * the VBIOS scripts on at least one board I have only switch it off on
  586. * link 0, causing a blank display if the output has previously been
  587. * programmed for DisplayPort.
  588. */
  589. static void
  590. nv50_display_unk40_dp_set_tmds(struct drm_device *dev, struct dcb_entry *dcb)
  591. {
  592. int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1);
  593. struct drm_encoder *encoder;
  594. u32 tmp;
  595. if (dcb->type != OUTPUT_TMDS)
  596. return;
  597. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  598. struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
  599. if (nv_encoder->dcb->type == OUTPUT_DP &&
  600. nv_encoder->dcb->or & (1 << or)) {
  601. tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
  602. tmp &= ~NV50_SOR_DP_CTRL_ENABLED;
  603. nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp);
  604. break;
  605. }
  606. }
  607. }
  608. static void
  609. nv50_display_unk40_handler(struct drm_device *dev)
  610. {
  611. struct drm_nouveau_private *dev_priv = dev->dev_private;
  612. struct dcb_entry *dcb = dev_priv->evo_irq.dcb;
  613. u16 script = dev_priv->evo_irq.script;
  614. u32 unk30 = nv_rd32(dev, 0x610030), pclk = dev_priv->evo_irq.pclk;
  615. NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
  616. dev_priv->evo_irq.dcb = NULL;
  617. if (!dcb)
  618. goto ack;
  619. nouveau_bios_run_display_table(dev, dcb, script, -pclk);
  620. nv50_display_unk40_dp_set_tmds(dev, dcb);
  621. ack:
  622. nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK40);
  623. nv_wr32(dev, 0x610030, 0x80000000);
  624. nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) | 8);
  625. }
  626. void
  627. nv50_display_irq_handler_bh(struct work_struct *work)
  628. {
  629. struct drm_nouveau_private *dev_priv =
  630. container_of(work, struct drm_nouveau_private, irq_work);
  631. struct drm_device *dev = dev_priv->dev;
  632. for (;;) {
  633. uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
  634. uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
  635. NV_DEBUG_KMS(dev, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0, intr1);
  636. if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK10)
  637. nv50_display_unk10_handler(dev);
  638. else
  639. if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK20)
  640. nv50_display_unk20_handler(dev);
  641. else
  642. if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK40)
  643. nv50_display_unk40_handler(dev);
  644. else
  645. break;
  646. }
  647. nv_wr32(dev, NV03_PMC_INTR_EN_0, 1);
  648. }
  649. static void
  650. nv50_display_error_handler(struct drm_device *dev)
  651. {
  652. u32 channels = (nv_rd32(dev, NV50_PDISPLAY_INTR_0) & 0x001f0000) >> 16;
  653. u32 addr, data;
  654. int chid;
  655. for (chid = 0; chid < 5; chid++) {
  656. if (!(channels & (1 << chid)))
  657. continue;
  658. nv_wr32(dev, NV50_PDISPLAY_INTR_0, 0x00010000 << chid);
  659. addr = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_ADDR(chid));
  660. data = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_DATA(chid));
  661. NV_ERROR(dev, "EvoCh %d Mthd 0x%04x Data 0x%08x "
  662. "(0x%04x 0x%02x)\n", chid,
  663. addr & 0xffc, data, addr >> 16, (addr >> 12) & 0xf);
  664. nv_wr32(dev, NV50_PDISPLAY_TRAPPED_ADDR(chid), 0x90000000);
  665. }
  666. }
  667. void
  668. nv50_display_irq_hotplug_bh(struct work_struct *work)
  669. {
  670. struct drm_nouveau_private *dev_priv =
  671. container_of(work, struct drm_nouveau_private, hpd_work);
  672. struct drm_device *dev = dev_priv->dev;
  673. struct drm_connector *connector;
  674. const uint32_t gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 };
  675. uint32_t unplug_mask, plug_mask, change_mask;
  676. uint32_t hpd0, hpd1;
  677. spin_lock_irq(&dev_priv->hpd_state.lock);
  678. hpd0 = dev_priv->hpd_state.hpd0_bits;
  679. dev_priv->hpd_state.hpd0_bits = 0;
  680. hpd1 = dev_priv->hpd_state.hpd1_bits;
  681. dev_priv->hpd_state.hpd1_bits = 0;
  682. spin_unlock_irq(&dev_priv->hpd_state.lock);
  683. hpd0 &= nv_rd32(dev, 0xe050);
  684. if (dev_priv->chipset >= 0x90)
  685. hpd1 &= nv_rd32(dev, 0xe070);
  686. plug_mask = (hpd0 & 0x0000ffff) | (hpd1 << 16);
  687. unplug_mask = (hpd0 >> 16) | (hpd1 & 0xffff0000);
  688. change_mask = plug_mask | unplug_mask;
  689. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  690. struct drm_encoder_helper_funcs *helper;
  691. struct nouveau_connector *nv_connector =
  692. nouveau_connector(connector);
  693. struct nouveau_encoder *nv_encoder;
  694. struct dcb_gpio_entry *gpio;
  695. uint32_t reg;
  696. bool plugged;
  697. if (!nv_connector->dcb)
  698. continue;
  699. gpio = nouveau_bios_gpio_entry(dev, nv_connector->dcb->gpio_tag);
  700. if (!gpio || !(change_mask & (1 << gpio->line)))
  701. continue;
  702. reg = nv_rd32(dev, gpio_reg[gpio->line >> 3]);
  703. plugged = !!(reg & (4 << ((gpio->line & 7) << 2)));
  704. NV_INFO(dev, "%splugged %s\n", plugged ? "" : "un",
  705. drm_get_connector_name(connector)) ;
  706. if (!connector->encoder || !connector->encoder->crtc ||
  707. !connector->encoder->crtc->enabled)
  708. continue;
  709. nv_encoder = nouveau_encoder(connector->encoder);
  710. helper = connector->encoder->helper_private;
  711. if (nv_encoder->dcb->type != OUTPUT_DP)
  712. continue;
  713. if (plugged)
  714. helper->dpms(connector->encoder, DRM_MODE_DPMS_ON);
  715. else
  716. helper->dpms(connector->encoder, DRM_MODE_DPMS_OFF);
  717. }
  718. drm_helper_hpd_irq_event(dev);
  719. }
  720. void
  721. nv50_display_irq_handler(struct drm_device *dev)
  722. {
  723. struct drm_nouveau_private *dev_priv = dev->dev_private;
  724. uint32_t delayed = 0;
  725. if (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_HOTPLUG) {
  726. uint32_t hpd0_bits, hpd1_bits = 0;
  727. hpd0_bits = nv_rd32(dev, 0xe054);
  728. nv_wr32(dev, 0xe054, hpd0_bits);
  729. if (dev_priv->chipset >= 0x90) {
  730. hpd1_bits = nv_rd32(dev, 0xe074);
  731. nv_wr32(dev, 0xe074, hpd1_bits);
  732. }
  733. spin_lock(&dev_priv->hpd_state.lock);
  734. dev_priv->hpd_state.hpd0_bits |= hpd0_bits;
  735. dev_priv->hpd_state.hpd1_bits |= hpd1_bits;
  736. spin_unlock(&dev_priv->hpd_state.lock);
  737. queue_work(dev_priv->wq, &dev_priv->hpd_work);
  738. }
  739. while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_DISPLAY) {
  740. uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
  741. uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
  742. uint32_t clock;
  743. NV_DEBUG_KMS(dev, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0, intr1);
  744. if (!intr0 && !(intr1 & ~delayed))
  745. break;
  746. if (intr0 & 0x001f0000) {
  747. nv50_display_error_handler(dev);
  748. intr0 &= ~0x001f0000;
  749. }
  750. if (intr1 & NV50_PDISPLAY_INTR_1_VBLANK_CRTC) {
  751. nv50_display_vblank_handler(dev, intr1);
  752. intr1 &= ~NV50_PDISPLAY_INTR_1_VBLANK_CRTC;
  753. }
  754. clock = (intr1 & (NV50_PDISPLAY_INTR_1_CLK_UNK10 |
  755. NV50_PDISPLAY_INTR_1_CLK_UNK20 |
  756. NV50_PDISPLAY_INTR_1_CLK_UNK40));
  757. if (clock) {
  758. nv_wr32(dev, NV03_PMC_INTR_EN_0, 0);
  759. if (!work_pending(&dev_priv->irq_work))
  760. queue_work(dev_priv->wq, &dev_priv->irq_work);
  761. delayed |= clock;
  762. intr1 &= ~clock;
  763. }
  764. if (intr0) {
  765. NV_ERROR(dev, "unknown PDISPLAY_INTR_0: 0x%08x\n", intr0);
  766. nv_wr32(dev, NV50_PDISPLAY_INTR_0, intr0);
  767. }
  768. if (intr1) {
  769. NV_ERROR(dev,
  770. "unknown PDISPLAY_INTR_1: 0x%08x\n", intr1);
  771. nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr1);
  772. }
  773. }
  774. }