mpc8349emitx.dts 7.0 KB

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  1. /*
  2. * MPC8349E-mITX Device Tree Source
  3. *
  4. * Copyright 2006 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. /dts-v1/;
  12. / {
  13. model = "MPC8349EMITX";
  14. compatible = "MPC8349EMITX", "MPC834xMITX", "MPC83xxMITX";
  15. #address-cells = <1>;
  16. #size-cells = <1>;
  17. aliases {
  18. ethernet0 = &enet0;
  19. ethernet1 = &enet1;
  20. serial0 = &serial0;
  21. serial1 = &serial1;
  22. pci0 = &pci0;
  23. pci1 = &pci1;
  24. };
  25. cpus {
  26. #address-cells = <1>;
  27. #size-cells = <0>;
  28. PowerPC,8349@0 {
  29. device_type = "cpu";
  30. reg = <0x0>;
  31. d-cache-line-size = <32>;
  32. i-cache-line-size = <32>;
  33. d-cache-size = <32768>;
  34. i-cache-size = <32768>;
  35. timebase-frequency = <0>; // from bootloader
  36. bus-frequency = <0>; // from bootloader
  37. clock-frequency = <0>; // from bootloader
  38. };
  39. };
  40. memory {
  41. device_type = "memory";
  42. reg = <0x00000000 0x10000000>;
  43. };
  44. soc8349@e0000000 {
  45. #address-cells = <1>;
  46. #size-cells = <1>;
  47. device_type = "soc";
  48. compatible = "simple-bus";
  49. ranges = <0x0 0xe0000000 0x00100000>;
  50. reg = <0xe0000000 0x00000200>;
  51. bus-frequency = <0>; // from bootloader
  52. wdt@200 {
  53. device_type = "watchdog";
  54. compatible = "mpc83xx_wdt";
  55. reg = <0x200 0x100>;
  56. };
  57. i2c@3000 {
  58. #address-cells = <1>;
  59. #size-cells = <0>;
  60. cell-index = <0>;
  61. compatible = "fsl-i2c";
  62. reg = <0x3000 0x100>;
  63. interrupts = <14 0x8>;
  64. interrupt-parent = <&ipic>;
  65. dfsrr;
  66. };
  67. i2c@3100 {
  68. #address-cells = <1>;
  69. #size-cells = <0>;
  70. cell-index = <1>;
  71. compatible = "fsl-i2c";
  72. reg = <0x3100 0x100>;
  73. interrupts = <15 0x8>;
  74. interrupt-parent = <&ipic>;
  75. dfsrr;
  76. };
  77. spi@7000 {
  78. cell-index = <0>;
  79. compatible = "fsl,spi";
  80. reg = <0x7000 0x1000>;
  81. interrupts = <16 0x8>;
  82. interrupt-parent = <&ipic>;
  83. mode = "cpu";
  84. };
  85. dma@82a8 {
  86. #address-cells = <1>;
  87. #size-cells = <1>;
  88. compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
  89. reg = <0x82a8 4>;
  90. ranges = <0 0x8100 0x1a8>;
  91. interrupt-parent = <&ipic>;
  92. interrupts = <71 8>;
  93. cell-index = <0>;
  94. dma-channel@0 {
  95. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  96. reg = <0 0x80>;
  97. interrupt-parent = <&ipic>;
  98. interrupts = <71 8>;
  99. };
  100. dma-channel@80 {
  101. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  102. reg = <0x80 0x80>;
  103. interrupt-parent = <&ipic>;
  104. interrupts = <71 8>;
  105. };
  106. dma-channel@100 {
  107. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  108. reg = <0x100 0x80>;
  109. interrupt-parent = <&ipic>;
  110. interrupts = <71 8>;
  111. };
  112. dma-channel@180 {
  113. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  114. reg = <0x180 0x28>;
  115. interrupt-parent = <&ipic>;
  116. interrupts = <71 8>;
  117. };
  118. };
  119. usb@22000 {
  120. compatible = "fsl-usb2-mph";
  121. reg = <0x22000 0x1000>;
  122. #address-cells = <1>;
  123. #size-cells = <0>;
  124. interrupt-parent = <&ipic>;
  125. interrupts = <39 0x8>;
  126. phy_type = "ulpi";
  127. port1;
  128. };
  129. usb@23000 {
  130. compatible = "fsl-usb2-dr";
  131. reg = <0x23000 0x1000>;
  132. #address-cells = <1>;
  133. #size-cells = <0>;
  134. interrupt-parent = <&ipic>;
  135. interrupts = <38 0x8>;
  136. dr_mode = "peripheral";
  137. phy_type = "ulpi";
  138. };
  139. mdio@24520 {
  140. #address-cells = <1>;
  141. #size-cells = <0>;
  142. compatible = "fsl,gianfar-mdio";
  143. reg = <0x24520 0x20>;
  144. /* Vitesse 8201 */
  145. phy1c: ethernet-phy@1c {
  146. interrupt-parent = <&ipic>;
  147. interrupts = <18 0x8>;
  148. reg = <0x1c>;
  149. device_type = "ethernet-phy";
  150. };
  151. };
  152. enet0: ethernet@24000 {
  153. cell-index = <0>;
  154. device_type = "network";
  155. model = "TSEC";
  156. compatible = "gianfar";
  157. reg = <0x24000 0x1000>;
  158. local-mac-address = [ 00 00 00 00 00 00 ];
  159. interrupts = <32 0x8 33 0x8 34 0x8>;
  160. interrupt-parent = <&ipic>;
  161. phy-handle = <&phy1c>;
  162. linux,network-index = <0>;
  163. };
  164. enet1: ethernet@25000 {
  165. cell-index = <1>;
  166. device_type = "network";
  167. model = "TSEC";
  168. compatible = "gianfar";
  169. reg = <0x25000 0x1000>;
  170. local-mac-address = [ 00 00 00 00 00 00 ];
  171. interrupts = <35 0x8 36 0x8 37 0x8>;
  172. interrupt-parent = <&ipic>;
  173. /* Vitesse 7385 isn't on the MDIO bus */
  174. fixed-link = <1 1 1000 0 0>;
  175. linux,network-index = <1>;
  176. };
  177. serial0: serial@4500 {
  178. cell-index = <0>;
  179. device_type = "serial";
  180. compatible = "ns16550";
  181. reg = <0x4500 0x100>;
  182. clock-frequency = <0>; // from bootloader
  183. interrupts = <9 0x8>;
  184. interrupt-parent = <&ipic>;
  185. };
  186. serial1: serial@4600 {
  187. cell-index = <1>;
  188. device_type = "serial";
  189. compatible = "ns16550";
  190. reg = <0x4600 0x100>;
  191. clock-frequency = <0>; // from bootloader
  192. interrupts = <10 0x8>;
  193. interrupt-parent = <&ipic>;
  194. };
  195. crypto@30000 {
  196. compatible = "fsl,sec2.0";
  197. reg = <0x30000 0x10000>;
  198. interrupts = <11 0x8>;
  199. interrupt-parent = <&ipic>;
  200. fsl,num-channels = <4>;
  201. fsl,channel-fifo-len = <24>;
  202. fsl,exec-units-mask = <0x7e>;
  203. fsl,descriptor-types-mask = <0x01010ebf>;
  204. };
  205. ipic: pic@700 {
  206. interrupt-controller;
  207. #address-cells = <0>;
  208. #interrupt-cells = <2>;
  209. reg = <0x700 0x100>;
  210. device_type = "ipic";
  211. };
  212. };
  213. pci0: pci@e0008500 {
  214. cell-index = <1>;
  215. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  216. interrupt-map = <
  217. /* IDSEL 0x10 - SATA */
  218. 0x8000 0x0 0x0 0x1 &ipic 22 0x8 /* SATA_INTA */
  219. >;
  220. interrupt-parent = <&ipic>;
  221. interrupts = <66 0x8>;
  222. bus-range = <0x0 0x0>;
  223. ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
  224. 0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
  225. 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x01000000>;
  226. clock-frequency = <66666666>;
  227. #interrupt-cells = <1>;
  228. #size-cells = <2>;
  229. #address-cells = <3>;
  230. reg = <0xe0008500 0x100>;
  231. compatible = "fsl,mpc8349-pci";
  232. device_type = "pci";
  233. };
  234. pci1: pci@e0008600 {
  235. cell-index = <2>;
  236. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  237. interrupt-map = <
  238. /* IDSEL 0x0E - MiniPCI Slot */
  239. 0x7000 0x0 0x0 0x1 &ipic 21 0x8 /* PCI_INTA */
  240. /* IDSEL 0x0F - PCI Slot */
  241. 0x7800 0x0 0x0 0x1 &ipic 20 0x8 /* PCI_INTA */
  242. 0x7800 0x0 0x0 0x2 &ipic 21 0x8 /* PCI_INTB */
  243. >;
  244. interrupt-parent = <&ipic>;
  245. interrupts = <67 0x8>;
  246. bus-range = <0x0 0x0>;
  247. ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
  248. 0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
  249. 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x01000000>;
  250. clock-frequency = <66666666>;
  251. #interrupt-cells = <1>;
  252. #size-cells = <2>;
  253. #address-cells = <3>;
  254. reg = <0xe0008600 0x100>;
  255. compatible = "fsl,mpc8349-pci";
  256. device_type = "pci";
  257. };
  258. localbus@e0005000 {
  259. #address-cells = <2>;
  260. #size-cells = <1>;
  261. compatible = "fsl,mpc8349e-localbus",
  262. "fsl,pq2pro-localbus";
  263. reg = <0xe0005000 0xd8>;
  264. ranges = <0x3 0x0 0xf0000000 0x210>;
  265. pata@3,0 {
  266. compatible = "fsl,mpc8349emitx-pata", "ata-generic";
  267. reg = <0x3 0x0 0x10 0x3 0x20c 0x4>;
  268. reg-shift = <1>;
  269. pio-mode = <6>;
  270. interrupts = <23 0x8>;
  271. interrupt-parent = <&ipic>;
  272. };
  273. };
  274. };