omap_crtc.c 18 KB

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  1. /*
  2. * drivers/gpu/drm/omapdrm/omap_crtc.c
  3. *
  4. * Copyright (C) 2011 Texas Instruments
  5. * Author: Rob Clark <rob@ti.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #include "omap_drv.h"
  20. #include <drm/drm_mode.h>
  21. #include "drm_crtc.h"
  22. #include "drm_crtc_helper.h"
  23. #define to_omap_crtc(x) container_of(x, struct omap_crtc, base)
  24. struct omap_crtc {
  25. struct drm_crtc base;
  26. struct drm_plane *plane;
  27. const char *name;
  28. int pipe;
  29. enum omap_channel channel;
  30. struct omap_overlay_manager_info info;
  31. /*
  32. * Temporary: eventually this will go away, but it is needed
  33. * for now to keep the output's happy. (They only need
  34. * mgr->id.) Eventually this will be replaced w/ something
  35. * more common-panel-framework-y
  36. */
  37. struct omap_overlay_manager *mgr;
  38. struct omap_video_timings timings;
  39. bool enabled;
  40. bool full_update;
  41. struct omap_drm_apply apply;
  42. struct omap_drm_irq apply_irq;
  43. struct omap_drm_irq error_irq;
  44. /* list of in-progress apply's: */
  45. struct list_head pending_applies;
  46. /* list of queued apply's: */
  47. struct list_head queued_applies;
  48. /* for handling queued and in-progress applies: */
  49. struct work_struct apply_work;
  50. /* if there is a pending flip, these will be non-null: */
  51. struct drm_pending_vblank_event *event;
  52. struct drm_framebuffer *old_fb;
  53. /* for handling page flips without caring about what
  54. * the callback is called from. Possibly we should just
  55. * make omap_gem always call the cb from the worker so
  56. * we don't have to care about this..
  57. *
  58. * XXX maybe fold into apply_work??
  59. */
  60. struct work_struct page_flip_work;
  61. };
  62. uint32_t pipe2vbl(struct drm_crtc *crtc)
  63. {
  64. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  65. return dispc_mgr_get_vsync_irq(omap_crtc->channel);
  66. }
  67. /*
  68. * Manager-ops, callbacks from output when they need to configure
  69. * the upstream part of the video pipe.
  70. *
  71. * Most of these we can ignore until we add support for command-mode
  72. * panels.. for video-mode the crtc-helpers already do an adequate
  73. * job of sequencing the setup of the video pipe in the proper order
  74. */
  75. /* ovl-mgr-id -> crtc */
  76. static struct omap_crtc *omap_crtcs[8];
  77. /* we can probably ignore these until we support command-mode panels: */
  78. static int omap_crtc_connect(struct omap_overlay_manager *mgr,
  79. struct omap_dss_device *dst)
  80. {
  81. if (mgr->output)
  82. return -EINVAL;
  83. if ((mgr->supported_outputs & dst->id) == 0)
  84. return -EINVAL;
  85. dst->manager = mgr;
  86. mgr->output = dst;
  87. return 0;
  88. }
  89. static void omap_crtc_disconnect(struct omap_overlay_manager *mgr,
  90. struct omap_dss_device *dst)
  91. {
  92. mgr->output->manager = NULL;
  93. mgr->output = NULL;
  94. }
  95. static void omap_crtc_start_update(struct omap_overlay_manager *mgr)
  96. {
  97. }
  98. static int omap_crtc_enable(struct omap_overlay_manager *mgr)
  99. {
  100. return 0;
  101. }
  102. static void omap_crtc_disable(struct omap_overlay_manager *mgr)
  103. {
  104. }
  105. static void omap_crtc_set_timings(struct omap_overlay_manager *mgr,
  106. const struct omap_video_timings *timings)
  107. {
  108. struct omap_crtc *omap_crtc = omap_crtcs[mgr->id];
  109. DBG("%s", omap_crtc->name);
  110. omap_crtc->timings = *timings;
  111. omap_crtc->full_update = true;
  112. }
  113. static void omap_crtc_set_lcd_config(struct omap_overlay_manager *mgr,
  114. const struct dss_lcd_mgr_config *config)
  115. {
  116. struct omap_crtc *omap_crtc = omap_crtcs[mgr->id];
  117. DBG("%s", omap_crtc->name);
  118. dispc_mgr_set_lcd_config(omap_crtc->channel, config);
  119. }
  120. static int omap_crtc_register_framedone_handler(
  121. struct omap_overlay_manager *mgr,
  122. void (*handler)(void *), void *data)
  123. {
  124. return 0;
  125. }
  126. static void omap_crtc_unregister_framedone_handler(
  127. struct omap_overlay_manager *mgr,
  128. void (*handler)(void *), void *data)
  129. {
  130. }
  131. static const struct dss_mgr_ops mgr_ops = {
  132. .connect = omap_crtc_connect,
  133. .disconnect = omap_crtc_disconnect,
  134. .start_update = omap_crtc_start_update,
  135. .enable = omap_crtc_enable,
  136. .disable = omap_crtc_disable,
  137. .set_timings = omap_crtc_set_timings,
  138. .set_lcd_config = omap_crtc_set_lcd_config,
  139. .register_framedone_handler = omap_crtc_register_framedone_handler,
  140. .unregister_framedone_handler = omap_crtc_unregister_framedone_handler,
  141. };
  142. /*
  143. * CRTC funcs:
  144. */
  145. static void omap_crtc_destroy(struct drm_crtc *crtc)
  146. {
  147. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  148. DBG("%s", omap_crtc->name);
  149. WARN_ON(omap_crtc->apply_irq.registered);
  150. omap_irq_unregister(crtc->dev, &omap_crtc->error_irq);
  151. omap_crtc->plane->funcs->destroy(omap_crtc->plane);
  152. drm_crtc_cleanup(crtc);
  153. kfree(omap_crtc);
  154. }
  155. static void omap_crtc_dpms(struct drm_crtc *crtc, int mode)
  156. {
  157. struct omap_drm_private *priv = crtc->dev->dev_private;
  158. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  159. bool enabled = (mode == DRM_MODE_DPMS_ON);
  160. int i;
  161. DBG("%s: %d", omap_crtc->name, mode);
  162. if (enabled != omap_crtc->enabled) {
  163. omap_crtc->enabled = enabled;
  164. omap_crtc->full_update = true;
  165. omap_crtc_apply(crtc, &omap_crtc->apply);
  166. /* also enable our private plane: */
  167. WARN_ON(omap_plane_dpms(omap_crtc->plane, mode));
  168. /* and any attached overlay planes: */
  169. for (i = 0; i < priv->num_planes; i++) {
  170. struct drm_plane *plane = priv->planes[i];
  171. if (plane->crtc == crtc)
  172. WARN_ON(omap_plane_dpms(plane, mode));
  173. }
  174. }
  175. }
  176. static bool omap_crtc_mode_fixup(struct drm_crtc *crtc,
  177. const struct drm_display_mode *mode,
  178. struct drm_display_mode *adjusted_mode)
  179. {
  180. return true;
  181. }
  182. static int omap_crtc_mode_set(struct drm_crtc *crtc,
  183. struct drm_display_mode *mode,
  184. struct drm_display_mode *adjusted_mode,
  185. int x, int y,
  186. struct drm_framebuffer *old_fb)
  187. {
  188. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  189. mode = adjusted_mode;
  190. DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
  191. omap_crtc->name, mode->base.id, mode->name,
  192. mode->vrefresh, mode->clock,
  193. mode->hdisplay, mode->hsync_start,
  194. mode->hsync_end, mode->htotal,
  195. mode->vdisplay, mode->vsync_start,
  196. mode->vsync_end, mode->vtotal,
  197. mode->type, mode->flags);
  198. copy_timings_drm_to_omap(&omap_crtc->timings, mode);
  199. omap_crtc->full_update = true;
  200. return omap_plane_mode_set(omap_crtc->plane, crtc, crtc->fb,
  201. 0, 0, mode->hdisplay, mode->vdisplay,
  202. x << 16, y << 16,
  203. mode->hdisplay << 16, mode->vdisplay << 16,
  204. NULL, NULL);
  205. }
  206. static void omap_crtc_prepare(struct drm_crtc *crtc)
  207. {
  208. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  209. DBG("%s", omap_crtc->name);
  210. omap_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
  211. }
  212. static void omap_crtc_commit(struct drm_crtc *crtc)
  213. {
  214. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  215. DBG("%s", omap_crtc->name);
  216. omap_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
  217. }
  218. static int omap_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
  219. struct drm_framebuffer *old_fb)
  220. {
  221. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  222. struct drm_plane *plane = omap_crtc->plane;
  223. struct drm_display_mode *mode = &crtc->mode;
  224. return omap_plane_mode_set(plane, crtc, crtc->fb,
  225. 0, 0, mode->hdisplay, mode->vdisplay,
  226. x << 16, y << 16,
  227. mode->hdisplay << 16, mode->vdisplay << 16,
  228. NULL, NULL);
  229. }
  230. static void omap_crtc_load_lut(struct drm_crtc *crtc)
  231. {
  232. }
  233. static void vblank_cb(void *arg)
  234. {
  235. struct drm_crtc *crtc = arg;
  236. struct drm_device *dev = crtc->dev;
  237. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  238. unsigned long flags;
  239. spin_lock_irqsave(&dev->event_lock, flags);
  240. /* wakeup userspace */
  241. if (omap_crtc->event)
  242. drm_send_vblank_event(dev, omap_crtc->pipe, omap_crtc->event);
  243. omap_crtc->event = NULL;
  244. omap_crtc->old_fb = NULL;
  245. spin_unlock_irqrestore(&dev->event_lock, flags);
  246. }
  247. static void page_flip_worker(struct work_struct *work)
  248. {
  249. struct omap_crtc *omap_crtc =
  250. container_of(work, struct omap_crtc, page_flip_work);
  251. struct drm_crtc *crtc = &omap_crtc->base;
  252. struct drm_display_mode *mode = &crtc->mode;
  253. struct drm_gem_object *bo;
  254. mutex_lock(&crtc->mutex);
  255. omap_plane_mode_set(omap_crtc->plane, crtc, crtc->fb,
  256. 0, 0, mode->hdisplay, mode->vdisplay,
  257. crtc->x << 16, crtc->y << 16,
  258. mode->hdisplay << 16, mode->vdisplay << 16,
  259. vblank_cb, crtc);
  260. mutex_unlock(&crtc->mutex);
  261. bo = omap_framebuffer_bo(crtc->fb, 0);
  262. drm_gem_object_unreference_unlocked(bo);
  263. }
  264. static void page_flip_cb(void *arg)
  265. {
  266. struct drm_crtc *crtc = arg;
  267. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  268. struct omap_drm_private *priv = crtc->dev->dev_private;
  269. /* avoid assumptions about what ctxt we are called from: */
  270. queue_work(priv->wq, &omap_crtc->page_flip_work);
  271. }
  272. static int omap_crtc_page_flip_locked(struct drm_crtc *crtc,
  273. struct drm_framebuffer *fb,
  274. struct drm_pending_vblank_event *event)
  275. {
  276. struct drm_device *dev = crtc->dev;
  277. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  278. struct drm_gem_object *bo;
  279. DBG("%d -> %d (event=%p)", crtc->fb ? crtc->fb->base.id : -1,
  280. fb->base.id, event);
  281. if (omap_crtc->old_fb) {
  282. dev_err(dev->dev, "already a pending flip\n");
  283. return -EINVAL;
  284. }
  285. omap_crtc->event = event;
  286. crtc->fb = fb;
  287. /*
  288. * Hold a reference temporarily until the crtc is updated
  289. * and takes the reference to the bo. This avoids it
  290. * getting freed from under us:
  291. */
  292. bo = omap_framebuffer_bo(fb, 0);
  293. drm_gem_object_reference(bo);
  294. omap_gem_op_async(bo, OMAP_GEM_READ, page_flip_cb, crtc);
  295. return 0;
  296. }
  297. static int omap_crtc_set_property(struct drm_crtc *crtc,
  298. struct drm_property *property, uint64_t val)
  299. {
  300. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  301. struct omap_drm_private *priv = crtc->dev->dev_private;
  302. if (property == priv->rotation_prop) {
  303. crtc->invert_dimensions =
  304. !!(val & ((1LL << DRM_ROTATE_90) | (1LL << DRM_ROTATE_270)));
  305. }
  306. return omap_plane_set_property(omap_crtc->plane, property, val);
  307. }
  308. static const struct drm_crtc_funcs omap_crtc_funcs = {
  309. .set_config = drm_crtc_helper_set_config,
  310. .destroy = omap_crtc_destroy,
  311. .page_flip = omap_crtc_page_flip_locked,
  312. .set_property = omap_crtc_set_property,
  313. };
  314. static const struct drm_crtc_helper_funcs omap_crtc_helper_funcs = {
  315. .dpms = omap_crtc_dpms,
  316. .mode_fixup = omap_crtc_mode_fixup,
  317. .mode_set = omap_crtc_mode_set,
  318. .prepare = omap_crtc_prepare,
  319. .commit = omap_crtc_commit,
  320. .mode_set_base = omap_crtc_mode_set_base,
  321. .load_lut = omap_crtc_load_lut,
  322. };
  323. const struct omap_video_timings *omap_crtc_timings(struct drm_crtc *crtc)
  324. {
  325. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  326. return &omap_crtc->timings;
  327. }
  328. enum omap_channel omap_crtc_channel(struct drm_crtc *crtc)
  329. {
  330. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  331. return omap_crtc->channel;
  332. }
  333. static void omap_crtc_error_irq(struct omap_drm_irq *irq, uint32_t irqstatus)
  334. {
  335. struct omap_crtc *omap_crtc =
  336. container_of(irq, struct omap_crtc, error_irq);
  337. struct drm_crtc *crtc = &omap_crtc->base;
  338. DRM_ERROR("%s: errors: %08x\n", omap_crtc->name, irqstatus);
  339. /* avoid getting in a flood, unregister the irq until next vblank */
  340. omap_irq_unregister(crtc->dev, &omap_crtc->error_irq);
  341. }
  342. static void omap_crtc_apply_irq(struct omap_drm_irq *irq, uint32_t irqstatus)
  343. {
  344. struct omap_crtc *omap_crtc =
  345. container_of(irq, struct omap_crtc, apply_irq);
  346. struct drm_crtc *crtc = &omap_crtc->base;
  347. if (!omap_crtc->error_irq.registered)
  348. omap_irq_register(crtc->dev, &omap_crtc->error_irq);
  349. if (!dispc_mgr_go_busy(omap_crtc->channel)) {
  350. struct omap_drm_private *priv =
  351. crtc->dev->dev_private;
  352. DBG("%s: apply done", omap_crtc->name);
  353. omap_irq_unregister(crtc->dev, &omap_crtc->apply_irq);
  354. queue_work(priv->wq, &omap_crtc->apply_work);
  355. }
  356. }
  357. static void apply_worker(struct work_struct *work)
  358. {
  359. struct omap_crtc *omap_crtc =
  360. container_of(work, struct omap_crtc, apply_work);
  361. struct drm_crtc *crtc = &omap_crtc->base;
  362. struct drm_device *dev = crtc->dev;
  363. struct omap_drm_apply *apply, *n;
  364. bool need_apply;
  365. /*
  366. * Synchronize everything on mode_config.mutex, to keep
  367. * the callbacks and list modification all serialized
  368. * with respect to modesetting ioctls from userspace.
  369. */
  370. mutex_lock(&crtc->mutex);
  371. dispc_runtime_get();
  372. /*
  373. * If we are still pending a previous update, wait.. when the
  374. * pending update completes, we get kicked again.
  375. */
  376. if (omap_crtc->apply_irq.registered)
  377. goto out;
  378. /* finish up previous apply's: */
  379. list_for_each_entry_safe(apply, n,
  380. &omap_crtc->pending_applies, pending_node) {
  381. apply->post_apply(apply);
  382. list_del(&apply->pending_node);
  383. }
  384. need_apply = !list_empty(&omap_crtc->queued_applies);
  385. /* then handle the next round of of queued apply's: */
  386. list_for_each_entry_safe(apply, n,
  387. &omap_crtc->queued_applies, queued_node) {
  388. apply->pre_apply(apply);
  389. list_del(&apply->queued_node);
  390. apply->queued = false;
  391. list_add_tail(&apply->pending_node,
  392. &omap_crtc->pending_applies);
  393. }
  394. if (need_apply) {
  395. enum omap_channel channel = omap_crtc->channel;
  396. DBG("%s: GO", omap_crtc->name);
  397. if (dispc_mgr_is_enabled(channel)) {
  398. omap_irq_register(dev, &omap_crtc->apply_irq);
  399. dispc_mgr_go(channel);
  400. } else {
  401. struct omap_drm_private *priv = dev->dev_private;
  402. queue_work(priv->wq, &omap_crtc->apply_work);
  403. }
  404. }
  405. out:
  406. dispc_runtime_put();
  407. mutex_unlock(&crtc->mutex);
  408. }
  409. int omap_crtc_apply(struct drm_crtc *crtc,
  410. struct omap_drm_apply *apply)
  411. {
  412. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  413. WARN_ON(!mutex_is_locked(&crtc->mutex));
  414. /* no need to queue it again if it is already queued: */
  415. if (apply->queued)
  416. return 0;
  417. apply->queued = true;
  418. list_add_tail(&apply->queued_node, &omap_crtc->queued_applies);
  419. /*
  420. * If there are no currently pending updates, then go ahead and
  421. * kick the worker immediately, otherwise it will run again when
  422. * the current update finishes.
  423. */
  424. if (list_empty(&omap_crtc->pending_applies)) {
  425. struct omap_drm_private *priv = crtc->dev->dev_private;
  426. queue_work(priv->wq, &omap_crtc->apply_work);
  427. }
  428. return 0;
  429. }
  430. /* called only from apply */
  431. static void set_enabled(struct drm_crtc *crtc, bool enable)
  432. {
  433. struct drm_device *dev = crtc->dev;
  434. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  435. enum omap_channel channel = omap_crtc->channel;
  436. struct omap_irq_wait *wait = NULL;
  437. if (dispc_mgr_is_enabled(channel) == enable)
  438. return;
  439. /* ignore sync-lost irqs during enable/disable */
  440. omap_irq_unregister(crtc->dev, &omap_crtc->error_irq);
  441. if (dispc_mgr_get_framedone_irq(channel)) {
  442. if (!enable) {
  443. wait = omap_irq_wait_init(dev,
  444. dispc_mgr_get_framedone_irq(channel), 1);
  445. }
  446. } else {
  447. /*
  448. * When we disable digit output, we need to wait until fields
  449. * are done. Otherwise the DSS is still working, and turning
  450. * off the clocks prevents DSS from going to OFF mode. And when
  451. * enabling, we need to wait for the extra sync losts
  452. */
  453. wait = omap_irq_wait_init(dev,
  454. dispc_mgr_get_vsync_irq(channel), 2);
  455. }
  456. dispc_mgr_enable(channel, enable);
  457. if (wait) {
  458. int ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100));
  459. if (ret) {
  460. dev_err(dev->dev, "%s: timeout waiting for %s\n",
  461. omap_crtc->name, enable ? "enable" : "disable");
  462. }
  463. }
  464. omap_irq_register(crtc->dev, &omap_crtc->error_irq);
  465. }
  466. static void omap_crtc_pre_apply(struct omap_drm_apply *apply)
  467. {
  468. struct omap_crtc *omap_crtc =
  469. container_of(apply, struct omap_crtc, apply);
  470. struct drm_crtc *crtc = &omap_crtc->base;
  471. struct drm_encoder *encoder = NULL;
  472. DBG("%s: enabled=%d, full=%d", omap_crtc->name,
  473. omap_crtc->enabled, omap_crtc->full_update);
  474. if (omap_crtc->full_update) {
  475. struct omap_drm_private *priv = crtc->dev->dev_private;
  476. int i;
  477. for (i = 0; i < priv->num_encoders; i++) {
  478. if (priv->encoders[i]->crtc == crtc) {
  479. encoder = priv->encoders[i];
  480. break;
  481. }
  482. }
  483. }
  484. if (!omap_crtc->enabled) {
  485. set_enabled(&omap_crtc->base, false);
  486. if (encoder)
  487. omap_encoder_set_enabled(encoder, false);
  488. } else {
  489. if (encoder) {
  490. omap_encoder_set_enabled(encoder, false);
  491. omap_encoder_update(encoder, omap_crtc->mgr,
  492. &omap_crtc->timings);
  493. omap_encoder_set_enabled(encoder, true);
  494. omap_crtc->full_update = false;
  495. }
  496. dispc_mgr_setup(omap_crtc->channel, &omap_crtc->info);
  497. dispc_mgr_set_timings(omap_crtc->channel,
  498. &omap_crtc->timings);
  499. set_enabled(&omap_crtc->base, true);
  500. }
  501. omap_crtc->full_update = false;
  502. }
  503. static void omap_crtc_post_apply(struct omap_drm_apply *apply)
  504. {
  505. /* nothing needed for post-apply */
  506. }
  507. static const char *channel_names[] = {
  508. [OMAP_DSS_CHANNEL_LCD] = "lcd",
  509. [OMAP_DSS_CHANNEL_DIGIT] = "tv",
  510. [OMAP_DSS_CHANNEL_LCD2] = "lcd2",
  511. };
  512. void omap_crtc_pre_init(void)
  513. {
  514. dss_install_mgr_ops(&mgr_ops);
  515. }
  516. /* initialize crtc */
  517. struct drm_crtc *omap_crtc_init(struct drm_device *dev,
  518. struct drm_plane *plane, enum omap_channel channel, int id)
  519. {
  520. struct drm_crtc *crtc = NULL;
  521. struct omap_crtc *omap_crtc;
  522. struct omap_overlay_manager_info *info;
  523. DBG("%s", channel_names[channel]);
  524. omap_crtc = kzalloc(sizeof(*omap_crtc), GFP_KERNEL);
  525. if (!omap_crtc)
  526. goto fail;
  527. crtc = &omap_crtc->base;
  528. INIT_WORK(&omap_crtc->page_flip_work, page_flip_worker);
  529. INIT_WORK(&omap_crtc->apply_work, apply_worker);
  530. INIT_LIST_HEAD(&omap_crtc->pending_applies);
  531. INIT_LIST_HEAD(&omap_crtc->queued_applies);
  532. omap_crtc->apply.pre_apply = omap_crtc_pre_apply;
  533. omap_crtc->apply.post_apply = omap_crtc_post_apply;
  534. omap_crtc->channel = channel;
  535. omap_crtc->plane = plane;
  536. omap_crtc->plane->crtc = crtc;
  537. omap_crtc->name = channel_names[channel];
  538. omap_crtc->pipe = id;
  539. omap_crtc->apply_irq.irqmask = pipe2vbl(crtc);
  540. omap_crtc->apply_irq.irq = omap_crtc_apply_irq;
  541. omap_crtc->error_irq.irqmask =
  542. dispc_mgr_get_sync_lost_irq(channel);
  543. omap_crtc->error_irq.irq = omap_crtc_error_irq;
  544. omap_irq_register(dev, &omap_crtc->error_irq);
  545. /* temporary: */
  546. omap_crtc->mgr = omap_dss_get_overlay_manager(channel);
  547. /* TODO: fix hard-coded setup.. add properties! */
  548. info = &omap_crtc->info;
  549. info->default_color = 0x00000000;
  550. info->trans_key = 0x00000000;
  551. info->trans_key_type = OMAP_DSS_COLOR_KEY_GFX_DST;
  552. info->trans_enabled = false;
  553. drm_crtc_init(dev, crtc, &omap_crtc_funcs);
  554. drm_crtc_helper_add(crtc, &omap_crtc_helper_funcs);
  555. omap_plane_install_properties(omap_crtc->plane, &crtc->base);
  556. omap_crtcs[channel] = omap_crtc;
  557. return crtc;
  558. fail:
  559. if (crtc)
  560. omap_crtc_destroy(crtc);
  561. return NULL;
  562. }