xonar_cs43xx.c 13 KB

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  1. /*
  2. * card driver for models with CS4398/CS4362A DACs (Xonar D1/DX)
  3. *
  4. * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
  5. *
  6. *
  7. * This driver is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License, version 2.
  9. *
  10. * This driver is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this driver; if not, see <http://www.gnu.org/licenses/>.
  17. */
  18. /*
  19. * Xonar D1/DX
  20. * -----------
  21. *
  22. * CMI8788:
  23. *
  24. * I²C <-> CS4398 (addr 1001111) (front)
  25. * <-> CS4362A (addr 0011000) (surround, center/LFE, back)
  26. *
  27. * GPI 0 <- external power present (DX only)
  28. *
  29. * GPIO 0 -> enable output to speakers
  30. * GPIO 1 -> route output to front panel
  31. * GPIO 2 -> M0 of CS5361
  32. * GPIO 3 -> M1 of CS5361
  33. * GPIO 6 -> ?
  34. * GPIO 7 -> ?
  35. * GPIO 8 -> route input jack to line-in (0) or mic-in (1)
  36. *
  37. * CM9780:
  38. *
  39. * LINE_OUT -> input of ADC
  40. *
  41. * AUX_IN <- aux
  42. * MIC_IN <- mic
  43. * FMIC_IN <- front mic
  44. *
  45. * GPO 0 -> route line-in (0) or AC97 output (1) to CS5361 input
  46. */
  47. #include <linux/pci.h>
  48. #include <linux/delay.h>
  49. #include <sound/ac97_codec.h>
  50. #include <sound/control.h>
  51. #include <sound/core.h>
  52. #include <sound/pcm.h>
  53. #include <sound/pcm_params.h>
  54. #include <sound/tlv.h>
  55. #include "xonar.h"
  56. #include "cm9780.h"
  57. #include "cs4398.h"
  58. #include "cs4362a.h"
  59. #define GPI_EXT_POWER 0x01
  60. #define GPIO_D1_OUTPUT_ENABLE 0x0001
  61. #define GPIO_D1_FRONT_PANEL 0x0002
  62. #define GPIO_D1_MAGIC 0x00c0
  63. #define GPIO_D1_INPUT_ROUTE 0x0100
  64. #define I2C_DEVICE_CS4398 0x9e /* 10011, AD1=1, AD0=1, /W=0 */
  65. #define I2C_DEVICE_CS4362A 0x30 /* 001100, AD0=0, /W=0 */
  66. struct xonar_cs43xx {
  67. struct xonar_generic generic;
  68. u8 cs4398_regs[8];
  69. u8 cs4362a_regs[15];
  70. };
  71. static void cs4398_write(struct oxygen *chip, u8 reg, u8 value)
  72. {
  73. struct xonar_cs43xx *data = chip->model_data;
  74. oxygen_write_i2c(chip, I2C_DEVICE_CS4398, reg, value);
  75. if (reg < ARRAY_SIZE(data->cs4398_regs))
  76. data->cs4398_regs[reg] = value;
  77. }
  78. static void cs4398_write_cached(struct oxygen *chip, u8 reg, u8 value)
  79. {
  80. struct xonar_cs43xx *data = chip->model_data;
  81. if (value != data->cs4398_regs[reg])
  82. cs4398_write(chip, reg, value);
  83. }
  84. static void cs4362a_write(struct oxygen *chip, u8 reg, u8 value)
  85. {
  86. struct xonar_cs43xx *data = chip->model_data;
  87. oxygen_write_i2c(chip, I2C_DEVICE_CS4362A, reg, value);
  88. if (reg < ARRAY_SIZE(data->cs4362a_regs))
  89. data->cs4362a_regs[reg] = value;
  90. }
  91. static void cs4362a_write_cached(struct oxygen *chip, u8 reg, u8 value)
  92. {
  93. struct xonar_cs43xx *data = chip->model_data;
  94. if (value != data->cs4362a_regs[reg])
  95. cs4362a_write(chip, reg, value);
  96. }
  97. static void cs43xx_registers_init(struct oxygen *chip)
  98. {
  99. struct xonar_cs43xx *data = chip->model_data;
  100. unsigned int i;
  101. /* set CPEN (control port mode) and power down */
  102. cs4398_write(chip, 8, CS4398_CPEN | CS4398_PDN);
  103. cs4362a_write(chip, 0x01, CS4362A_PDN | CS4362A_CPEN);
  104. /* configure */
  105. cs4398_write(chip, 2, data->cs4398_regs[2]);
  106. cs4398_write(chip, 3, CS4398_ATAPI_B_R | CS4398_ATAPI_A_L);
  107. cs4398_write(chip, 4, data->cs4398_regs[4]);
  108. cs4398_write(chip, 5, data->cs4398_regs[5]);
  109. cs4398_write(chip, 6, data->cs4398_regs[6]);
  110. cs4398_write(chip, 7, data->cs4398_regs[7]);
  111. cs4362a_write(chip, 0x02, CS4362A_DIF_LJUST);
  112. cs4362a_write(chip, 0x03, CS4362A_MUTEC_6 | CS4362A_AMUTE |
  113. CS4362A_RMP_UP | CS4362A_ZERO_CROSS | CS4362A_SOFT_RAMP);
  114. cs4362a_write(chip, 0x04, data->cs4362a_regs[0x04]);
  115. cs4362a_write(chip, 0x05, 0);
  116. for (i = 6; i <= 14; ++i)
  117. cs4362a_write(chip, i, data->cs4362a_regs[i]);
  118. /* clear power down */
  119. cs4398_write(chip, 8, CS4398_CPEN);
  120. cs4362a_write(chip, 0x01, CS4362A_CPEN);
  121. }
  122. static void xonar_d1_init(struct oxygen *chip)
  123. {
  124. struct xonar_cs43xx *data = chip->model_data;
  125. data->generic.anti_pop_delay = 800;
  126. data->generic.output_enable_bit = GPIO_D1_OUTPUT_ENABLE;
  127. data->cs4398_regs[2] =
  128. CS4398_FM_SINGLE | CS4398_DEM_NONE | CS4398_DIF_LJUST;
  129. data->cs4398_regs[4] = CS4398_MUTEP_LOW |
  130. CS4398_MUTE_B | CS4398_MUTE_A | CS4398_PAMUTE;
  131. data->cs4398_regs[5] = 60 * 2;
  132. data->cs4398_regs[6] = 60 * 2;
  133. data->cs4398_regs[7] = CS4398_RMP_DN | CS4398_RMP_UP |
  134. CS4398_ZERO_CROSS | CS4398_SOFT_RAMP;
  135. data->cs4362a_regs[4] = CS4362A_RMP_DN | CS4362A_DEM_NONE;
  136. data->cs4362a_regs[6] = CS4362A_FM_SINGLE |
  137. CS4362A_ATAPI_B_R | CS4362A_ATAPI_A_L;
  138. data->cs4362a_regs[7] = 60 | CS4362A_MUTE;
  139. data->cs4362a_regs[8] = 60 | CS4362A_MUTE;
  140. data->cs4362a_regs[9] = data->cs4362a_regs[6];
  141. data->cs4362a_regs[10] = 60 | CS4362A_MUTE;
  142. data->cs4362a_regs[11] = 60 | CS4362A_MUTE;
  143. data->cs4362a_regs[12] = data->cs4362a_regs[6];
  144. data->cs4362a_regs[13] = 60 | CS4362A_MUTE;
  145. data->cs4362a_regs[14] = 60 | CS4362A_MUTE;
  146. oxygen_write16(chip, OXYGEN_2WIRE_BUS_STATUS,
  147. OXYGEN_2WIRE_LENGTH_8 |
  148. OXYGEN_2WIRE_INTERRUPT_MASK |
  149. OXYGEN_2WIRE_SPEED_FAST);
  150. cs43xx_registers_init(chip);
  151. oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL,
  152. GPIO_D1_FRONT_PANEL |
  153. GPIO_D1_MAGIC |
  154. GPIO_D1_INPUT_ROUTE);
  155. oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA,
  156. GPIO_D1_FRONT_PANEL | GPIO_D1_INPUT_ROUTE);
  157. xonar_init_cs53x1(chip);
  158. xonar_enable_output(chip);
  159. snd_component_add(chip->card, "CS4398");
  160. snd_component_add(chip->card, "CS4362A");
  161. snd_component_add(chip->card, "CS5361");
  162. }
  163. static void xonar_dx_init(struct oxygen *chip)
  164. {
  165. struct xonar_cs43xx *data = chip->model_data;
  166. data->generic.ext_power_reg = OXYGEN_GPI_DATA;
  167. data->generic.ext_power_int_reg = OXYGEN_GPI_INTERRUPT_MASK;
  168. data->generic.ext_power_bit = GPI_EXT_POWER;
  169. xonar_init_ext_power(chip);
  170. xonar_d1_init(chip);
  171. }
  172. static void xonar_d1_cleanup(struct oxygen *chip)
  173. {
  174. xonar_disable_output(chip);
  175. cs4362a_write(chip, 0x01, CS4362A_PDN | CS4362A_CPEN);
  176. oxygen_clear_bits8(chip, OXYGEN_FUNCTION, OXYGEN_FUNCTION_RESET_CODEC);
  177. }
  178. static void xonar_d1_suspend(struct oxygen *chip)
  179. {
  180. xonar_d1_cleanup(chip);
  181. }
  182. static void xonar_d1_resume(struct oxygen *chip)
  183. {
  184. oxygen_set_bits8(chip, OXYGEN_FUNCTION, OXYGEN_FUNCTION_RESET_CODEC);
  185. msleep(1);
  186. cs43xx_registers_init(chip);
  187. xonar_enable_output(chip);
  188. }
  189. static void set_cs43xx_params(struct oxygen *chip,
  190. struct snd_pcm_hw_params *params)
  191. {
  192. struct xonar_cs43xx *data = chip->model_data;
  193. u8 cs4398_fm, cs4362a_fm;
  194. if (params_rate(params) <= 50000) {
  195. cs4398_fm = CS4398_FM_SINGLE;
  196. cs4362a_fm = CS4362A_FM_SINGLE;
  197. } else if (params_rate(params) <= 100000) {
  198. cs4398_fm = CS4398_FM_DOUBLE;
  199. cs4362a_fm = CS4362A_FM_DOUBLE;
  200. } else {
  201. cs4398_fm = CS4398_FM_QUAD;
  202. cs4362a_fm = CS4362A_FM_QUAD;
  203. }
  204. cs4398_fm |= CS4398_DEM_NONE | CS4398_DIF_LJUST;
  205. cs4398_write_cached(chip, 2, cs4398_fm);
  206. cs4362a_fm |= data->cs4362a_regs[6] & ~CS4362A_FM_MASK;
  207. cs4362a_write_cached(chip, 6, cs4362a_fm);
  208. cs4362a_write_cached(chip, 12, cs4362a_fm);
  209. cs4362a_fm &= CS4362A_FM_MASK;
  210. cs4362a_fm |= data->cs4362a_regs[9] & ~CS4362A_FM_MASK;
  211. cs4362a_write_cached(chip, 9, cs4362a_fm);
  212. }
  213. static void update_cs4362a_volumes(struct oxygen *chip)
  214. {
  215. unsigned int i;
  216. u8 mute;
  217. mute = chip->dac_mute ? CS4362A_MUTE : 0;
  218. for (i = 0; i < 6; ++i)
  219. cs4362a_write_cached(chip, 7 + i + i / 2,
  220. (127 - chip->dac_volume[2 + i]) | mute);
  221. }
  222. static void update_cs43xx_volume(struct oxygen *chip)
  223. {
  224. cs4398_write_cached(chip, 5, (127 - chip->dac_volume[0]) * 2);
  225. cs4398_write_cached(chip, 6, (127 - chip->dac_volume[1]) * 2);
  226. update_cs4362a_volumes(chip);
  227. }
  228. static void update_cs43xx_mute(struct oxygen *chip)
  229. {
  230. u8 reg;
  231. reg = CS4398_MUTEP_LOW | CS4398_PAMUTE;
  232. if (chip->dac_mute)
  233. reg |= CS4398_MUTE_B | CS4398_MUTE_A;
  234. cs4398_write_cached(chip, 4, reg);
  235. update_cs4362a_volumes(chip);
  236. }
  237. static void update_cs43xx_center_lfe_mix(struct oxygen *chip, bool mixed)
  238. {
  239. struct xonar_cs43xx *data = chip->model_data;
  240. u8 reg;
  241. reg = data->cs4362a_regs[9] & ~CS4362A_ATAPI_MASK;
  242. if (mixed)
  243. reg |= CS4362A_ATAPI_B_LR | CS4362A_ATAPI_A_LR;
  244. else
  245. reg |= CS4362A_ATAPI_B_R | CS4362A_ATAPI_A_L;
  246. cs4362a_write_cached(chip, 9, reg);
  247. }
  248. static const struct snd_kcontrol_new front_panel_switch = {
  249. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  250. .name = "Front Panel Playback Switch",
  251. .info = snd_ctl_boolean_mono_info,
  252. .get = xonar_gpio_bit_switch_get,
  253. .put = xonar_gpio_bit_switch_put,
  254. .private_value = GPIO_D1_FRONT_PANEL,
  255. };
  256. static int rolloff_info(struct snd_kcontrol *ctl,
  257. struct snd_ctl_elem_info *info)
  258. {
  259. static const char *const names[2] = {
  260. "Fast Roll-off", "Slow Roll-off"
  261. };
  262. info->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  263. info->count = 1;
  264. info->value.enumerated.items = 2;
  265. if (info->value.enumerated.item >= 2)
  266. info->value.enumerated.item = 1;
  267. strcpy(info->value.enumerated.name, names[info->value.enumerated.item]);
  268. return 0;
  269. }
  270. static int rolloff_get(struct snd_kcontrol *ctl,
  271. struct snd_ctl_elem_value *value)
  272. {
  273. struct oxygen *chip = ctl->private_data;
  274. struct xonar_cs43xx *data = chip->model_data;
  275. value->value.enumerated.item[0] =
  276. (data->cs4398_regs[7] & CS4398_FILT_SEL) != 0;
  277. return 0;
  278. }
  279. static int rolloff_put(struct snd_kcontrol *ctl,
  280. struct snd_ctl_elem_value *value)
  281. {
  282. struct oxygen *chip = ctl->private_data;
  283. struct xonar_cs43xx *data = chip->model_data;
  284. int changed;
  285. u8 reg;
  286. mutex_lock(&chip->mutex);
  287. reg = data->cs4398_regs[7];
  288. if (value->value.enumerated.item[0])
  289. reg |= CS4398_FILT_SEL;
  290. else
  291. reg &= ~CS4398_FILT_SEL;
  292. changed = reg != data->cs4398_regs[7];
  293. if (changed) {
  294. cs4398_write(chip, 7, reg);
  295. if (reg & CS4398_FILT_SEL)
  296. reg = data->cs4362a_regs[0x04] | CS4362A_FILT_SEL;
  297. else
  298. reg = data->cs4362a_regs[0x04] & ~CS4362A_FILT_SEL;
  299. cs4362a_write(chip, 0x04, reg);
  300. }
  301. mutex_unlock(&chip->mutex);
  302. return changed;
  303. }
  304. static const struct snd_kcontrol_new rolloff_control = {
  305. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  306. .name = "DAC Filter Playback Enum",
  307. .info = rolloff_info,
  308. .get = rolloff_get,
  309. .put = rolloff_put,
  310. };
  311. static void xonar_d1_line_mic_ac97_switch(struct oxygen *chip,
  312. unsigned int reg, unsigned int mute)
  313. {
  314. if (reg == AC97_LINE) {
  315. spin_lock_irq(&chip->reg_lock);
  316. oxygen_write16_masked(chip, OXYGEN_GPIO_DATA,
  317. mute ? GPIO_D1_INPUT_ROUTE : 0,
  318. GPIO_D1_INPUT_ROUTE);
  319. spin_unlock_irq(&chip->reg_lock);
  320. }
  321. }
  322. static const DECLARE_TLV_DB_SCALE(cs4362a_db_scale, -6000, 100, 0);
  323. static int xonar_d1_mixer_init(struct oxygen *chip)
  324. {
  325. int err;
  326. err = snd_ctl_add(chip->card, snd_ctl_new1(&front_panel_switch, chip));
  327. if (err < 0)
  328. return err;
  329. err = snd_ctl_add(chip->card, snd_ctl_new1(&rolloff_control, chip));
  330. if (err < 0)
  331. return err;
  332. return 0;
  333. }
  334. static void dump_cs4362a_registers(struct xonar_cs43xx *data,
  335. struct snd_info_buffer *buffer)
  336. {
  337. unsigned int i;
  338. snd_iprintf(buffer, "\nCS4362A:");
  339. for (i = 1; i <= 14; ++i)
  340. snd_iprintf(buffer, " %02x", data->cs4362a_regs[i]);
  341. snd_iprintf(buffer, "\n");
  342. }
  343. static void dump_d1_registers(struct oxygen *chip,
  344. struct snd_info_buffer *buffer)
  345. {
  346. struct xonar_cs43xx *data = chip->model_data;
  347. unsigned int i;
  348. snd_iprintf(buffer, "\nCS4398: 7?");
  349. for (i = 2; i <= 8; ++i)
  350. snd_iprintf(buffer, " %02x", data->cs4398_regs[i]);
  351. snd_iprintf(buffer, "\n");
  352. dump_cs4362a_registers(data, buffer);
  353. }
  354. static const struct oxygen_model model_xonar_d1 = {
  355. .longname = "Asus Virtuoso 100",
  356. .chip = "AV200",
  357. .init = xonar_d1_init,
  358. .mixer_init = xonar_d1_mixer_init,
  359. .cleanup = xonar_d1_cleanup,
  360. .suspend = xonar_d1_suspend,
  361. .resume = xonar_d1_resume,
  362. .get_i2s_mclk = oxygen_default_i2s_mclk,
  363. .set_dac_params = set_cs43xx_params,
  364. .set_adc_params = xonar_set_cs53x1_params,
  365. .update_dac_volume = update_cs43xx_volume,
  366. .update_dac_mute = update_cs43xx_mute,
  367. .update_center_lfe_mix = update_cs43xx_center_lfe_mix,
  368. .ac97_switch = xonar_d1_line_mic_ac97_switch,
  369. .dump_registers = dump_d1_registers,
  370. .dac_tlv = cs4362a_db_scale,
  371. .model_data_size = sizeof(struct xonar_cs43xx),
  372. .device_config = PLAYBACK_0_TO_I2S |
  373. PLAYBACK_1_TO_SPDIF |
  374. CAPTURE_0_FROM_I2S_2 |
  375. AC97_FMIC_SWITCH,
  376. .dac_channels_pcm = 8,
  377. .dac_channels_mixer = 8,
  378. .dac_volume_min = 127 - 60,
  379. .dac_volume_max = 127,
  380. .function_flags = OXYGEN_FUNCTION_2WIRE,
  381. .dac_i2s_format = OXYGEN_I2S_FORMAT_LJUST,
  382. .adc_i2s_format = OXYGEN_I2S_FORMAT_LJUST,
  383. };
  384. int __devinit get_xonar_cs43xx_model(struct oxygen *chip,
  385. const struct pci_device_id *id)
  386. {
  387. switch (id->subdevice) {
  388. case 0x834f:
  389. chip->model = model_xonar_d1;
  390. chip->model.shortname = "Xonar D1";
  391. break;
  392. case 0x8275:
  393. case 0x8327:
  394. chip->model = model_xonar_d1;
  395. chip->model.shortname = "Xonar DX";
  396. chip->model.init = xonar_dx_init;
  397. break;
  398. default:
  399. return -EINVAL;
  400. }
  401. return 0;
  402. }