main.c 60 KB

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  1. /*
  2. * Copyright (c) 2008-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/nl80211.h>
  17. #include <linux/delay.h>
  18. #include "ath9k.h"
  19. #include "btcoex.h"
  20. u8 ath9k_parse_mpdudensity(u8 mpdudensity)
  21. {
  22. /*
  23. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  24. * 0 for no restriction
  25. * 1 for 1/4 us
  26. * 2 for 1/2 us
  27. * 3 for 1 us
  28. * 4 for 2 us
  29. * 5 for 4 us
  30. * 6 for 8 us
  31. * 7 for 16 us
  32. */
  33. switch (mpdudensity) {
  34. case 0:
  35. return 0;
  36. case 1:
  37. case 2:
  38. case 3:
  39. /* Our lower layer calculations limit our precision to
  40. 1 microsecond */
  41. return 1;
  42. case 4:
  43. return 2;
  44. case 5:
  45. return 4;
  46. case 6:
  47. return 8;
  48. case 7:
  49. return 16;
  50. default:
  51. return 0;
  52. }
  53. }
  54. static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
  55. {
  56. bool pending = false;
  57. spin_lock_bh(&txq->axq_lock);
  58. if (txq->axq_depth || !list_empty(&txq->axq_acq))
  59. pending = true;
  60. spin_unlock_bh(&txq->axq_lock);
  61. return pending;
  62. }
  63. static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
  64. {
  65. unsigned long flags;
  66. bool ret;
  67. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  68. ret = ath9k_hw_setpower(sc->sc_ah, mode);
  69. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  70. return ret;
  71. }
  72. void ath9k_ps_wakeup(struct ath_softc *sc)
  73. {
  74. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  75. unsigned long flags;
  76. enum ath9k_power_mode power_mode;
  77. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  78. if (++sc->ps_usecount != 1)
  79. goto unlock;
  80. power_mode = sc->sc_ah->power_mode;
  81. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  82. /*
  83. * While the hardware is asleep, the cycle counters contain no
  84. * useful data. Better clear them now so that they don't mess up
  85. * survey data results.
  86. */
  87. if (power_mode != ATH9K_PM_AWAKE) {
  88. spin_lock(&common->cc_lock);
  89. ath_hw_cycle_counters_update(common);
  90. memset(&common->cc_survey, 0, sizeof(common->cc_survey));
  91. memset(&common->cc_ani, 0, sizeof(common->cc_ani));
  92. spin_unlock(&common->cc_lock);
  93. }
  94. unlock:
  95. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  96. }
  97. void ath9k_ps_restore(struct ath_softc *sc)
  98. {
  99. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  100. enum ath9k_power_mode mode;
  101. unsigned long flags;
  102. bool reset;
  103. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  104. if (--sc->ps_usecount != 0)
  105. goto unlock;
  106. if (sc->ps_idle) {
  107. ath9k_hw_setrxabort(sc->sc_ah, 1);
  108. ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
  109. mode = ATH9K_PM_FULL_SLEEP;
  110. } else if (sc->ps_enabled &&
  111. !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
  112. PS_WAIT_FOR_CAB |
  113. PS_WAIT_FOR_PSPOLL_DATA |
  114. PS_WAIT_FOR_TX_ACK))) {
  115. mode = ATH9K_PM_NETWORK_SLEEP;
  116. if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
  117. ath9k_btcoex_stop_gen_timer(sc);
  118. } else {
  119. goto unlock;
  120. }
  121. spin_lock(&common->cc_lock);
  122. ath_hw_cycle_counters_update(common);
  123. spin_unlock(&common->cc_lock);
  124. ath9k_hw_setpower(sc->sc_ah, mode);
  125. unlock:
  126. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  127. }
  128. static void __ath_cancel_work(struct ath_softc *sc)
  129. {
  130. cancel_work_sync(&sc->paprd_work);
  131. cancel_work_sync(&sc->hw_check_work);
  132. cancel_delayed_work_sync(&sc->tx_complete_work);
  133. cancel_delayed_work_sync(&sc->hw_pll_work);
  134. #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
  135. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  136. cancel_work_sync(&sc->mci_work);
  137. #endif
  138. }
  139. static void ath_cancel_work(struct ath_softc *sc)
  140. {
  141. __ath_cancel_work(sc);
  142. cancel_work_sync(&sc->hw_reset_work);
  143. }
  144. static void ath_restart_work(struct ath_softc *sc)
  145. {
  146. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  147. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  148. if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9485(sc->sc_ah) ||
  149. AR_SREV_9550(sc->sc_ah))
  150. ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
  151. msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
  152. ath_start_rx_poll(sc, 3);
  153. if (!common->disable_ani)
  154. ath_start_ani(common);
  155. }
  156. static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush)
  157. {
  158. struct ath_hw *ah = sc->sc_ah;
  159. struct ath_common *common = ath9k_hw_common(ah);
  160. bool ret = true;
  161. ieee80211_stop_queues(sc->hw);
  162. sc->hw_busy_count = 0;
  163. del_timer_sync(&common->ani.timer);
  164. del_timer_sync(&sc->rx_poll_timer);
  165. ath9k_debug_samp_bb_mac(sc);
  166. ath9k_hw_disable_interrupts(ah);
  167. if (!ath_stoprecv(sc))
  168. ret = false;
  169. if (!ath_drain_all_txq(sc, retry_tx))
  170. ret = false;
  171. if (!flush) {
  172. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  173. ath_rx_tasklet(sc, 1, true);
  174. ath_rx_tasklet(sc, 1, false);
  175. } else {
  176. ath_flushrecv(sc);
  177. }
  178. return ret;
  179. }
  180. static bool ath_complete_reset(struct ath_softc *sc, bool start)
  181. {
  182. struct ath_hw *ah = sc->sc_ah;
  183. struct ath_common *common = ath9k_hw_common(ah);
  184. unsigned long flags;
  185. if (ath_startrecv(sc) != 0) {
  186. ath_err(common, "Unable to restart recv logic\n");
  187. return false;
  188. }
  189. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  190. sc->config.txpowlimit, &sc->curtxpow);
  191. clear_bit(SC_OP_HW_RESET, &sc->sc_flags);
  192. ath9k_hw_set_interrupts(ah);
  193. ath9k_hw_enable_interrupts(ah);
  194. if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) {
  195. if (!test_bit(SC_OP_BEACONS, &sc->sc_flags))
  196. goto work;
  197. ath_set_beacon(sc);
  198. if (ah->opmode == NL80211_IFTYPE_STATION &&
  199. test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  200. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  201. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  202. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  203. }
  204. work:
  205. ath_restart_work(sc);
  206. }
  207. if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3)
  208. ath_ant_comb_update(sc);
  209. ieee80211_wake_queues(sc->hw);
  210. return true;
  211. }
  212. static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan,
  213. bool retry_tx)
  214. {
  215. struct ath_hw *ah = sc->sc_ah;
  216. struct ath_common *common = ath9k_hw_common(ah);
  217. struct ath9k_hw_cal_data *caldata = NULL;
  218. bool fastcc = true;
  219. bool flush = false;
  220. int r;
  221. __ath_cancel_work(sc);
  222. spin_lock_bh(&sc->sc_pcu_lock);
  223. if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) {
  224. fastcc = false;
  225. caldata = &sc->caldata;
  226. }
  227. if (!hchan) {
  228. fastcc = false;
  229. flush = true;
  230. hchan = ah->curchan;
  231. }
  232. if (!ath_prepare_reset(sc, retry_tx, flush))
  233. fastcc = false;
  234. ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
  235. hchan->channel, IS_CHAN_HT40(hchan), fastcc);
  236. r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
  237. if (r) {
  238. ath_err(common,
  239. "Unable to reset channel, reset status %d\n", r);
  240. goto out;
  241. }
  242. if (!ath_complete_reset(sc, true))
  243. r = -EIO;
  244. out:
  245. spin_unlock_bh(&sc->sc_pcu_lock);
  246. return r;
  247. }
  248. /*
  249. * Set/change channels. If the channel is really being changed, it's done
  250. * by reseting the chip. To accomplish this we must first cleanup any pending
  251. * DMA, then restart stuff.
  252. */
  253. static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
  254. struct ath9k_channel *hchan)
  255. {
  256. int r;
  257. if (test_bit(SC_OP_INVALID, &sc->sc_flags))
  258. return -EIO;
  259. r = ath_reset_internal(sc, hchan, false);
  260. return r;
  261. }
  262. static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
  263. struct ieee80211_vif *vif)
  264. {
  265. struct ath_node *an;
  266. u8 density;
  267. an = (struct ath_node *)sta->drv_priv;
  268. #ifdef CONFIG_ATH9K_DEBUGFS
  269. spin_lock(&sc->nodes_lock);
  270. list_add(&an->list, &sc->nodes);
  271. spin_unlock(&sc->nodes_lock);
  272. #endif
  273. an->sta = sta;
  274. an->vif = vif;
  275. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
  276. ath_tx_node_init(sc, an);
  277. an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
  278. sta->ht_cap.ampdu_factor);
  279. density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
  280. an->mpdudensity = density;
  281. }
  282. }
  283. static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
  284. {
  285. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  286. #ifdef CONFIG_ATH9K_DEBUGFS
  287. spin_lock(&sc->nodes_lock);
  288. list_del(&an->list);
  289. spin_unlock(&sc->nodes_lock);
  290. an->sta = NULL;
  291. #endif
  292. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  293. ath_tx_node_cleanup(sc, an);
  294. }
  295. void ath9k_tasklet(unsigned long data)
  296. {
  297. struct ath_softc *sc = (struct ath_softc *)data;
  298. struct ath_hw *ah = sc->sc_ah;
  299. struct ath_common *common = ath9k_hw_common(ah);
  300. unsigned long flags;
  301. u32 status = sc->intrstatus;
  302. u32 rxmask;
  303. ath9k_ps_wakeup(sc);
  304. spin_lock(&sc->sc_pcu_lock);
  305. if ((status & ATH9K_INT_FATAL) ||
  306. (status & ATH9K_INT_BB_WATCHDOG)) {
  307. #ifdef CONFIG_ATH9K_DEBUGFS
  308. enum ath_reset_type type;
  309. if (status & ATH9K_INT_FATAL)
  310. type = RESET_TYPE_FATAL_INT;
  311. else
  312. type = RESET_TYPE_BB_WATCHDOG;
  313. RESET_STAT_INC(sc, type);
  314. #endif
  315. set_bit(SC_OP_HW_RESET, &sc->sc_flags);
  316. ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
  317. goto out;
  318. }
  319. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  320. if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
  321. /*
  322. * TSF sync does not look correct; remain awake to sync with
  323. * the next Beacon.
  324. */
  325. ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
  326. sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
  327. }
  328. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  329. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  330. rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
  331. ATH9K_INT_RXORN);
  332. else
  333. rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  334. if (status & rxmask) {
  335. /* Check for high priority Rx first */
  336. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  337. (status & ATH9K_INT_RXHP))
  338. ath_rx_tasklet(sc, 0, true);
  339. ath_rx_tasklet(sc, 0, false);
  340. }
  341. if (status & ATH9K_INT_TX) {
  342. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  343. ath_tx_edma_tasklet(sc);
  344. else
  345. ath_tx_tasklet(sc);
  346. }
  347. ath9k_btcoex_handle_interrupt(sc, status);
  348. out:
  349. /* re-enable hardware interrupt */
  350. ath9k_hw_enable_interrupts(ah);
  351. spin_unlock(&sc->sc_pcu_lock);
  352. ath9k_ps_restore(sc);
  353. }
  354. irqreturn_t ath_isr(int irq, void *dev)
  355. {
  356. #define SCHED_INTR ( \
  357. ATH9K_INT_FATAL | \
  358. ATH9K_INT_BB_WATCHDOG | \
  359. ATH9K_INT_RXORN | \
  360. ATH9K_INT_RXEOL | \
  361. ATH9K_INT_RX | \
  362. ATH9K_INT_RXLP | \
  363. ATH9K_INT_RXHP | \
  364. ATH9K_INT_TX | \
  365. ATH9K_INT_BMISS | \
  366. ATH9K_INT_CST | \
  367. ATH9K_INT_TSFOOR | \
  368. ATH9K_INT_GENTIMER | \
  369. ATH9K_INT_MCI)
  370. struct ath_softc *sc = dev;
  371. struct ath_hw *ah = sc->sc_ah;
  372. struct ath_common *common = ath9k_hw_common(ah);
  373. enum ath9k_int status;
  374. bool sched = false;
  375. /*
  376. * The hardware is not ready/present, don't
  377. * touch anything. Note this can happen early
  378. * on if the IRQ is shared.
  379. */
  380. if (test_bit(SC_OP_INVALID, &sc->sc_flags))
  381. return IRQ_NONE;
  382. /* shared irq, not for us */
  383. if (!ath9k_hw_intrpend(ah))
  384. return IRQ_NONE;
  385. if(test_bit(SC_OP_HW_RESET, &sc->sc_flags))
  386. return IRQ_HANDLED;
  387. /*
  388. * Figure out the reason(s) for the interrupt. Note
  389. * that the hal returns a pseudo-ISR that may include
  390. * bits we haven't explicitly enabled so we mask the
  391. * value to insure we only process bits we requested.
  392. */
  393. ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
  394. status &= ah->imask; /* discard unasked-for bits */
  395. /*
  396. * If there are no status bits set, then this interrupt was not
  397. * for me (should have been caught above).
  398. */
  399. if (!status)
  400. return IRQ_NONE;
  401. /* Cache the status */
  402. sc->intrstatus = status;
  403. if (status & SCHED_INTR)
  404. sched = true;
  405. #ifdef CONFIG_PM_SLEEP
  406. if (status & ATH9K_INT_BMISS) {
  407. if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
  408. ath_dbg(common, ANY, "during WoW we got a BMISS\n");
  409. atomic_inc(&sc->wow_got_bmiss_intr);
  410. atomic_dec(&sc->wow_sleep_proc_intr);
  411. }
  412. ath_dbg(common, INTERRUPT, "beacon miss interrupt\n");
  413. }
  414. #endif
  415. /*
  416. * If a FATAL or RXORN interrupt is received, we have to reset the
  417. * chip immediately.
  418. */
  419. if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
  420. !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
  421. goto chip_reset;
  422. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  423. (status & ATH9K_INT_BB_WATCHDOG)) {
  424. spin_lock(&common->cc_lock);
  425. ath_hw_cycle_counters_update(common);
  426. ar9003_hw_bb_watchdog_dbg_info(ah);
  427. spin_unlock(&common->cc_lock);
  428. goto chip_reset;
  429. }
  430. if (status & ATH9K_INT_SWBA)
  431. tasklet_schedule(&sc->bcon_tasklet);
  432. if (status & ATH9K_INT_TXURN)
  433. ath9k_hw_updatetxtriglevel(ah, true);
  434. if (status & ATH9K_INT_RXEOL) {
  435. ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  436. ath9k_hw_set_interrupts(ah);
  437. }
  438. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  439. if (status & ATH9K_INT_TIM_TIMER) {
  440. if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
  441. goto chip_reset;
  442. /* Clear RxAbort bit so that we can
  443. * receive frames */
  444. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  445. spin_lock(&sc->sc_pm_lock);
  446. ath9k_hw_setrxabort(sc->sc_ah, 0);
  447. sc->ps_flags |= PS_WAIT_FOR_BEACON;
  448. spin_unlock(&sc->sc_pm_lock);
  449. }
  450. chip_reset:
  451. ath_debug_stat_interrupt(sc, status);
  452. if (sched) {
  453. /* turn off every interrupt */
  454. ath9k_hw_disable_interrupts(ah);
  455. tasklet_schedule(&sc->intr_tq);
  456. }
  457. return IRQ_HANDLED;
  458. #undef SCHED_INTR
  459. }
  460. static int ath_reset(struct ath_softc *sc, bool retry_tx)
  461. {
  462. int r;
  463. ath9k_ps_wakeup(sc);
  464. r = ath_reset_internal(sc, NULL, retry_tx);
  465. if (retry_tx) {
  466. int i;
  467. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  468. if (ATH_TXQ_SETUP(sc, i)) {
  469. spin_lock_bh(&sc->tx.txq[i].axq_lock);
  470. ath_txq_schedule(sc, &sc->tx.txq[i]);
  471. spin_unlock_bh(&sc->tx.txq[i].axq_lock);
  472. }
  473. }
  474. }
  475. ath9k_ps_restore(sc);
  476. return r;
  477. }
  478. void ath_reset_work(struct work_struct *work)
  479. {
  480. struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
  481. ath_reset(sc, true);
  482. }
  483. /**********************/
  484. /* mac80211 callbacks */
  485. /**********************/
  486. static int ath9k_start(struct ieee80211_hw *hw)
  487. {
  488. struct ath_softc *sc = hw->priv;
  489. struct ath_hw *ah = sc->sc_ah;
  490. struct ath_common *common = ath9k_hw_common(ah);
  491. struct ieee80211_channel *curchan = hw->conf.channel;
  492. struct ath9k_channel *init_channel;
  493. int r;
  494. ath_dbg(common, CONFIG,
  495. "Starting driver with initial channel: %d MHz\n",
  496. curchan->center_freq);
  497. ath9k_ps_wakeup(sc);
  498. mutex_lock(&sc->mutex);
  499. init_channel = ath9k_cmn_get_curchannel(hw, ah);
  500. /* Reset SERDES registers */
  501. ath9k_hw_configpcipowersave(ah, false);
  502. /*
  503. * The basic interface to setting the hardware in a good
  504. * state is ``reset''. On return the hardware is known to
  505. * be powered up and with interrupts disabled. This must
  506. * be followed by initialization of the appropriate bits
  507. * and then setup of the interrupt mask.
  508. */
  509. spin_lock_bh(&sc->sc_pcu_lock);
  510. atomic_set(&ah->intr_ref_cnt, -1);
  511. r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
  512. if (r) {
  513. ath_err(common,
  514. "Unable to reset hardware; reset status %d (freq %u MHz)\n",
  515. r, curchan->center_freq);
  516. spin_unlock_bh(&sc->sc_pcu_lock);
  517. goto mutex_unlock;
  518. }
  519. /* Setup our intr mask. */
  520. ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
  521. ATH9K_INT_RXORN | ATH9K_INT_FATAL |
  522. ATH9K_INT_GLOBAL;
  523. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  524. ah->imask |= ATH9K_INT_RXHP |
  525. ATH9K_INT_RXLP |
  526. ATH9K_INT_BB_WATCHDOG;
  527. else
  528. ah->imask |= ATH9K_INT_RX;
  529. ah->imask |= ATH9K_INT_GTT;
  530. if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  531. ah->imask |= ATH9K_INT_CST;
  532. ath_mci_enable(sc);
  533. clear_bit(SC_OP_INVALID, &sc->sc_flags);
  534. sc->sc_ah->is_monitoring = false;
  535. if (!ath_complete_reset(sc, false)) {
  536. r = -EIO;
  537. spin_unlock_bh(&sc->sc_pcu_lock);
  538. goto mutex_unlock;
  539. }
  540. if (ah->led_pin >= 0) {
  541. ath9k_hw_cfg_output(ah, ah->led_pin,
  542. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  543. ath9k_hw_set_gpio(ah, ah->led_pin, 0);
  544. }
  545. /*
  546. * Reset key cache to sane defaults (all entries cleared) instead of
  547. * semi-random values after suspend/resume.
  548. */
  549. ath9k_cmn_init_crypto(sc->sc_ah);
  550. spin_unlock_bh(&sc->sc_pcu_lock);
  551. if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
  552. common->bus_ops->extn_synch_en(common);
  553. mutex_unlock:
  554. mutex_unlock(&sc->mutex);
  555. ath9k_ps_restore(sc);
  556. return r;
  557. }
  558. static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  559. {
  560. struct ath_softc *sc = hw->priv;
  561. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  562. struct ath_tx_control txctl;
  563. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  564. unsigned long flags;
  565. if (sc->ps_enabled) {
  566. /*
  567. * mac80211 does not set PM field for normal data frames, so we
  568. * need to update that based on the current PS mode.
  569. */
  570. if (ieee80211_is_data(hdr->frame_control) &&
  571. !ieee80211_is_nullfunc(hdr->frame_control) &&
  572. !ieee80211_has_pm(hdr->frame_control)) {
  573. ath_dbg(common, PS,
  574. "Add PM=1 for a TX frame while in PS mode\n");
  575. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
  576. }
  577. }
  578. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
  579. /*
  580. * We are using PS-Poll and mac80211 can request TX while in
  581. * power save mode. Need to wake up hardware for the TX to be
  582. * completed and if needed, also for RX of buffered frames.
  583. */
  584. ath9k_ps_wakeup(sc);
  585. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  586. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  587. ath9k_hw_setrxabort(sc->sc_ah, 0);
  588. if (ieee80211_is_pspoll(hdr->frame_control)) {
  589. ath_dbg(common, PS,
  590. "Sending PS-Poll to pick a buffered frame\n");
  591. sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
  592. } else {
  593. ath_dbg(common, PS, "Wake up to complete TX\n");
  594. sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
  595. }
  596. /*
  597. * The actual restore operation will happen only after
  598. * the ps_flags bit is cleared. We are just dropping
  599. * the ps_usecount here.
  600. */
  601. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  602. ath9k_ps_restore(sc);
  603. }
  604. /*
  605. * Cannot tx while the hardware is in full sleep, it first needs a full
  606. * chip reset to recover from that
  607. */
  608. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
  609. ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
  610. goto exit;
  611. }
  612. memset(&txctl, 0, sizeof(struct ath_tx_control));
  613. txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
  614. ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
  615. if (ath_tx_start(hw, skb, &txctl) != 0) {
  616. ath_dbg(common, XMIT, "TX failed\n");
  617. TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
  618. goto exit;
  619. }
  620. return;
  621. exit:
  622. dev_kfree_skb_any(skb);
  623. }
  624. static void ath9k_stop(struct ieee80211_hw *hw)
  625. {
  626. struct ath_softc *sc = hw->priv;
  627. struct ath_hw *ah = sc->sc_ah;
  628. struct ath_common *common = ath9k_hw_common(ah);
  629. bool prev_idle;
  630. mutex_lock(&sc->mutex);
  631. ath_cancel_work(sc);
  632. del_timer_sync(&sc->rx_poll_timer);
  633. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  634. ath_dbg(common, ANY, "Device not present\n");
  635. mutex_unlock(&sc->mutex);
  636. return;
  637. }
  638. /* Ensure HW is awake when we try to shut it down. */
  639. ath9k_ps_wakeup(sc);
  640. spin_lock_bh(&sc->sc_pcu_lock);
  641. /* prevent tasklets to enable interrupts once we disable them */
  642. ah->imask &= ~ATH9K_INT_GLOBAL;
  643. /* make sure h/w will not generate any interrupt
  644. * before setting the invalid flag. */
  645. ath9k_hw_disable_interrupts(ah);
  646. spin_unlock_bh(&sc->sc_pcu_lock);
  647. /* we can now sync irq and kill any running tasklets, since we already
  648. * disabled interrupts and not holding a spin lock */
  649. synchronize_irq(sc->irq);
  650. tasklet_kill(&sc->intr_tq);
  651. tasklet_kill(&sc->bcon_tasklet);
  652. prev_idle = sc->ps_idle;
  653. sc->ps_idle = true;
  654. spin_lock_bh(&sc->sc_pcu_lock);
  655. if (ah->led_pin >= 0) {
  656. ath9k_hw_set_gpio(ah, ah->led_pin, 1);
  657. ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
  658. }
  659. ath_prepare_reset(sc, false, true);
  660. if (sc->rx.frag) {
  661. dev_kfree_skb_any(sc->rx.frag);
  662. sc->rx.frag = NULL;
  663. }
  664. if (!ah->curchan)
  665. ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
  666. ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
  667. ath9k_hw_phy_disable(ah);
  668. ath9k_hw_configpcipowersave(ah, true);
  669. spin_unlock_bh(&sc->sc_pcu_lock);
  670. ath9k_ps_restore(sc);
  671. set_bit(SC_OP_INVALID, &sc->sc_flags);
  672. sc->ps_idle = prev_idle;
  673. mutex_unlock(&sc->mutex);
  674. ath_dbg(common, CONFIG, "Driver halt\n");
  675. }
  676. bool ath9k_uses_beacons(int type)
  677. {
  678. switch (type) {
  679. case NL80211_IFTYPE_AP:
  680. case NL80211_IFTYPE_ADHOC:
  681. case NL80211_IFTYPE_MESH_POINT:
  682. return true;
  683. default:
  684. return false;
  685. }
  686. }
  687. static void ath9k_reclaim_beacon(struct ath_softc *sc,
  688. struct ieee80211_vif *vif)
  689. {
  690. struct ath_vif *avp = (void *)vif->drv_priv;
  691. ath9k_set_beaconing_status(sc, false);
  692. ath_beacon_return(sc, avp);
  693. ath9k_set_beaconing_status(sc, true);
  694. }
  695. static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  696. {
  697. struct ath9k_vif_iter_data *iter_data = data;
  698. int i;
  699. if (iter_data->hw_macaddr)
  700. for (i = 0; i < ETH_ALEN; i++)
  701. iter_data->mask[i] &=
  702. ~(iter_data->hw_macaddr[i] ^ mac[i]);
  703. switch (vif->type) {
  704. case NL80211_IFTYPE_AP:
  705. iter_data->naps++;
  706. break;
  707. case NL80211_IFTYPE_STATION:
  708. iter_data->nstations++;
  709. break;
  710. case NL80211_IFTYPE_ADHOC:
  711. iter_data->nadhocs++;
  712. break;
  713. case NL80211_IFTYPE_MESH_POINT:
  714. iter_data->nmeshes++;
  715. break;
  716. case NL80211_IFTYPE_WDS:
  717. iter_data->nwds++;
  718. break;
  719. default:
  720. break;
  721. }
  722. }
  723. /* Called with sc->mutex held. */
  724. void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
  725. struct ieee80211_vif *vif,
  726. struct ath9k_vif_iter_data *iter_data)
  727. {
  728. struct ath_softc *sc = hw->priv;
  729. struct ath_hw *ah = sc->sc_ah;
  730. struct ath_common *common = ath9k_hw_common(ah);
  731. /*
  732. * Use the hardware MAC address as reference, the hardware uses it
  733. * together with the BSSID mask when matching addresses.
  734. */
  735. memset(iter_data, 0, sizeof(*iter_data));
  736. iter_data->hw_macaddr = common->macaddr;
  737. memset(&iter_data->mask, 0xff, ETH_ALEN);
  738. if (vif)
  739. ath9k_vif_iter(iter_data, vif->addr, vif);
  740. /* Get list of all active MAC addresses */
  741. ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
  742. iter_data);
  743. }
  744. /* Called with sc->mutex held. */
  745. static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
  746. struct ieee80211_vif *vif)
  747. {
  748. struct ath_softc *sc = hw->priv;
  749. struct ath_hw *ah = sc->sc_ah;
  750. struct ath_common *common = ath9k_hw_common(ah);
  751. struct ath9k_vif_iter_data iter_data;
  752. ath9k_calculate_iter_data(hw, vif, &iter_data);
  753. /* Set BSSID mask. */
  754. memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
  755. ath_hw_setbssidmask(common);
  756. /* Set op-mode & TSF */
  757. if (iter_data.naps > 0) {
  758. ath9k_hw_set_tsfadjust(ah, 1);
  759. set_bit(SC_OP_TSF_RESET, &sc->sc_flags);
  760. ah->opmode = NL80211_IFTYPE_AP;
  761. } else {
  762. ath9k_hw_set_tsfadjust(ah, 0);
  763. clear_bit(SC_OP_TSF_RESET, &sc->sc_flags);
  764. if (iter_data.nmeshes)
  765. ah->opmode = NL80211_IFTYPE_MESH_POINT;
  766. else if (iter_data.nwds)
  767. ah->opmode = NL80211_IFTYPE_AP;
  768. else if (iter_data.nadhocs)
  769. ah->opmode = NL80211_IFTYPE_ADHOC;
  770. else
  771. ah->opmode = NL80211_IFTYPE_STATION;
  772. }
  773. /*
  774. * Enable MIB interrupts when there are hardware phy counters.
  775. */
  776. if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
  777. ah->imask |= ATH9K_INT_TSFOOR;
  778. else
  779. ah->imask &= ~ATH9K_INT_TSFOOR;
  780. ath9k_hw_set_interrupts(ah);
  781. /* Set up ANI */
  782. if (iter_data.naps > 0) {
  783. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  784. if (!common->disable_ani) {
  785. set_bit(SC_OP_ANI_RUN, &sc->sc_flags);
  786. ath_start_ani(common);
  787. }
  788. } else {
  789. clear_bit(SC_OP_ANI_RUN, &sc->sc_flags);
  790. del_timer_sync(&common->ani.timer);
  791. }
  792. }
  793. /* Called with sc->mutex held, vif counts set up properly. */
  794. static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw,
  795. struct ieee80211_vif *vif)
  796. {
  797. struct ath_softc *sc = hw->priv;
  798. ath9k_calculate_summary_state(hw, vif);
  799. if (ath9k_uses_beacons(vif->type)) {
  800. /* Reserve a beacon slot for the vif */
  801. ath9k_set_beaconing_status(sc, false);
  802. ath_beacon_alloc(sc, vif);
  803. ath9k_set_beaconing_status(sc, true);
  804. }
  805. }
  806. static int ath9k_add_interface(struct ieee80211_hw *hw,
  807. struct ieee80211_vif *vif)
  808. {
  809. struct ath_softc *sc = hw->priv;
  810. struct ath_hw *ah = sc->sc_ah;
  811. struct ath_common *common = ath9k_hw_common(ah);
  812. int ret = 0;
  813. ath9k_ps_wakeup(sc);
  814. mutex_lock(&sc->mutex);
  815. switch (vif->type) {
  816. case NL80211_IFTYPE_STATION:
  817. case NL80211_IFTYPE_WDS:
  818. case NL80211_IFTYPE_ADHOC:
  819. case NL80211_IFTYPE_AP:
  820. case NL80211_IFTYPE_MESH_POINT:
  821. break;
  822. default:
  823. ath_err(common, "Interface type %d not yet supported\n",
  824. vif->type);
  825. ret = -EOPNOTSUPP;
  826. goto out;
  827. }
  828. if (ath9k_uses_beacons(vif->type)) {
  829. if (sc->nbcnvifs >= ATH_BCBUF) {
  830. ath_err(common, "Not enough beacon buffers when adding"
  831. " new interface of type: %i\n",
  832. vif->type);
  833. ret = -ENOBUFS;
  834. goto out;
  835. }
  836. }
  837. ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
  838. sc->nvifs++;
  839. ath9k_do_vif_add_setup(hw, vif);
  840. out:
  841. mutex_unlock(&sc->mutex);
  842. ath9k_ps_restore(sc);
  843. return ret;
  844. }
  845. static int ath9k_change_interface(struct ieee80211_hw *hw,
  846. struct ieee80211_vif *vif,
  847. enum nl80211_iftype new_type,
  848. bool p2p)
  849. {
  850. struct ath_softc *sc = hw->priv;
  851. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  852. int ret = 0;
  853. ath_dbg(common, CONFIG, "Change Interface\n");
  854. mutex_lock(&sc->mutex);
  855. ath9k_ps_wakeup(sc);
  856. if (ath9k_uses_beacons(new_type) &&
  857. !ath9k_uses_beacons(vif->type)) {
  858. if (sc->nbcnvifs >= ATH_BCBUF) {
  859. ath_err(common, "No beacon slot available\n");
  860. ret = -ENOBUFS;
  861. goto out;
  862. }
  863. }
  864. /* Clean up old vif stuff */
  865. if (ath9k_uses_beacons(vif->type))
  866. ath9k_reclaim_beacon(sc, vif);
  867. /* Add new settings */
  868. vif->type = new_type;
  869. vif->p2p = p2p;
  870. ath9k_do_vif_add_setup(hw, vif);
  871. out:
  872. ath9k_ps_restore(sc);
  873. mutex_unlock(&sc->mutex);
  874. return ret;
  875. }
  876. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  877. struct ieee80211_vif *vif)
  878. {
  879. struct ath_softc *sc = hw->priv;
  880. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  881. ath_dbg(common, CONFIG, "Detach Interface\n");
  882. ath9k_ps_wakeup(sc);
  883. mutex_lock(&sc->mutex);
  884. sc->nvifs--;
  885. /* Reclaim beacon resources */
  886. if (ath9k_uses_beacons(vif->type))
  887. ath9k_reclaim_beacon(sc, vif);
  888. ath9k_calculate_summary_state(hw, NULL);
  889. mutex_unlock(&sc->mutex);
  890. ath9k_ps_restore(sc);
  891. }
  892. static void ath9k_enable_ps(struct ath_softc *sc)
  893. {
  894. struct ath_hw *ah = sc->sc_ah;
  895. struct ath_common *common = ath9k_hw_common(ah);
  896. sc->ps_enabled = true;
  897. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  898. if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
  899. ah->imask |= ATH9K_INT_TIM_TIMER;
  900. ath9k_hw_set_interrupts(ah);
  901. }
  902. ath9k_hw_setrxabort(ah, 1);
  903. }
  904. ath_dbg(common, PS, "PowerSave enabled\n");
  905. }
  906. static void ath9k_disable_ps(struct ath_softc *sc)
  907. {
  908. struct ath_hw *ah = sc->sc_ah;
  909. struct ath_common *common = ath9k_hw_common(ah);
  910. sc->ps_enabled = false;
  911. ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
  912. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  913. ath9k_hw_setrxabort(ah, 0);
  914. sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
  915. PS_WAIT_FOR_CAB |
  916. PS_WAIT_FOR_PSPOLL_DATA |
  917. PS_WAIT_FOR_TX_ACK);
  918. if (ah->imask & ATH9K_INT_TIM_TIMER) {
  919. ah->imask &= ~ATH9K_INT_TIM_TIMER;
  920. ath9k_hw_set_interrupts(ah);
  921. }
  922. }
  923. ath_dbg(common, PS, "PowerSave disabled\n");
  924. }
  925. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  926. {
  927. struct ath_softc *sc = hw->priv;
  928. struct ath_hw *ah = sc->sc_ah;
  929. struct ath_common *common = ath9k_hw_common(ah);
  930. struct ieee80211_conf *conf = &hw->conf;
  931. bool reset_channel = false;
  932. ath9k_ps_wakeup(sc);
  933. mutex_lock(&sc->mutex);
  934. if (changed & IEEE80211_CONF_CHANGE_IDLE) {
  935. sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
  936. if (sc->ps_idle) {
  937. ath_cancel_work(sc);
  938. ath9k_stop_btcoex(sc);
  939. } else {
  940. ath9k_start_btcoex(sc);
  941. /*
  942. * The chip needs a reset to properly wake up from
  943. * full sleep
  944. */
  945. reset_channel = ah->chip_fullsleep;
  946. }
  947. }
  948. /*
  949. * We just prepare to enable PS. We have to wait until our AP has
  950. * ACK'd our null data frame to disable RX otherwise we'll ignore
  951. * those ACKs and end up retransmitting the same null data frames.
  952. * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
  953. */
  954. if (changed & IEEE80211_CONF_CHANGE_PS) {
  955. unsigned long flags;
  956. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  957. if (conf->flags & IEEE80211_CONF_PS)
  958. ath9k_enable_ps(sc);
  959. else
  960. ath9k_disable_ps(sc);
  961. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  962. }
  963. if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
  964. if (conf->flags & IEEE80211_CONF_MONITOR) {
  965. ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
  966. sc->sc_ah->is_monitoring = true;
  967. } else {
  968. ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
  969. sc->sc_ah->is_monitoring = false;
  970. }
  971. }
  972. if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) {
  973. struct ieee80211_channel *curchan = hw->conf.channel;
  974. int pos = curchan->hw_value;
  975. int old_pos = -1;
  976. unsigned long flags;
  977. if (ah->curchan)
  978. old_pos = ah->curchan - &ah->channels[0];
  979. ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n",
  980. curchan->center_freq, conf->channel_type);
  981. /* update survey stats for the old channel before switching */
  982. spin_lock_irqsave(&common->cc_lock, flags);
  983. ath_update_survey_stats(sc);
  984. spin_unlock_irqrestore(&common->cc_lock, flags);
  985. /*
  986. * Preserve the current channel values, before updating
  987. * the same channel
  988. */
  989. if (ah->curchan && (old_pos == pos))
  990. ath9k_hw_getnf(ah, ah->curchan);
  991. ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
  992. curchan, conf->channel_type);
  993. /*
  994. * If the operating channel changes, change the survey in-use flags
  995. * along with it.
  996. * Reset the survey data for the new channel, unless we're switching
  997. * back to the operating channel from an off-channel operation.
  998. */
  999. if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
  1000. sc->cur_survey != &sc->survey[pos]) {
  1001. if (sc->cur_survey)
  1002. sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
  1003. sc->cur_survey = &sc->survey[pos];
  1004. memset(sc->cur_survey, 0, sizeof(struct survey_info));
  1005. sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
  1006. } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
  1007. memset(&sc->survey[pos], 0, sizeof(struct survey_info));
  1008. }
  1009. if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
  1010. ath_err(common, "Unable to set channel\n");
  1011. mutex_unlock(&sc->mutex);
  1012. ath9k_ps_restore(sc);
  1013. return -EINVAL;
  1014. }
  1015. /*
  1016. * The most recent snapshot of channel->noisefloor for the old
  1017. * channel is only available after the hardware reset. Copy it to
  1018. * the survey stats now.
  1019. */
  1020. if (old_pos >= 0)
  1021. ath_update_survey_nf(sc, old_pos);
  1022. }
  1023. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  1024. ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
  1025. sc->config.txpowlimit = 2 * conf->power_level;
  1026. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  1027. sc->config.txpowlimit, &sc->curtxpow);
  1028. }
  1029. mutex_unlock(&sc->mutex);
  1030. ath9k_ps_restore(sc);
  1031. return 0;
  1032. }
  1033. #define SUPPORTED_FILTERS \
  1034. (FIF_PROMISC_IN_BSS | \
  1035. FIF_ALLMULTI | \
  1036. FIF_CONTROL | \
  1037. FIF_PSPOLL | \
  1038. FIF_OTHER_BSS | \
  1039. FIF_BCN_PRBRESP_PROMISC | \
  1040. FIF_PROBE_REQ | \
  1041. FIF_FCSFAIL)
  1042. /* FIXME: sc->sc_full_reset ? */
  1043. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  1044. unsigned int changed_flags,
  1045. unsigned int *total_flags,
  1046. u64 multicast)
  1047. {
  1048. struct ath_softc *sc = hw->priv;
  1049. u32 rfilt;
  1050. changed_flags &= SUPPORTED_FILTERS;
  1051. *total_flags &= SUPPORTED_FILTERS;
  1052. sc->rx.rxfilter = *total_flags;
  1053. ath9k_ps_wakeup(sc);
  1054. rfilt = ath_calcrxfilter(sc);
  1055. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1056. ath9k_ps_restore(sc);
  1057. ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
  1058. rfilt);
  1059. }
  1060. static int ath9k_sta_add(struct ieee80211_hw *hw,
  1061. struct ieee80211_vif *vif,
  1062. struct ieee80211_sta *sta)
  1063. {
  1064. struct ath_softc *sc = hw->priv;
  1065. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1066. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1067. struct ieee80211_key_conf ps_key = { };
  1068. ath_node_attach(sc, sta, vif);
  1069. if (vif->type != NL80211_IFTYPE_AP &&
  1070. vif->type != NL80211_IFTYPE_AP_VLAN)
  1071. return 0;
  1072. an->ps_key = ath_key_config(common, vif, sta, &ps_key);
  1073. return 0;
  1074. }
  1075. static void ath9k_del_ps_key(struct ath_softc *sc,
  1076. struct ieee80211_vif *vif,
  1077. struct ieee80211_sta *sta)
  1078. {
  1079. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1080. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1081. struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
  1082. if (!an->ps_key)
  1083. return;
  1084. ath_key_delete(common, &ps_key);
  1085. }
  1086. static int ath9k_sta_remove(struct ieee80211_hw *hw,
  1087. struct ieee80211_vif *vif,
  1088. struct ieee80211_sta *sta)
  1089. {
  1090. struct ath_softc *sc = hw->priv;
  1091. ath9k_del_ps_key(sc, vif, sta);
  1092. ath_node_detach(sc, sta);
  1093. return 0;
  1094. }
  1095. static void ath9k_sta_notify(struct ieee80211_hw *hw,
  1096. struct ieee80211_vif *vif,
  1097. enum sta_notify_cmd cmd,
  1098. struct ieee80211_sta *sta)
  1099. {
  1100. struct ath_softc *sc = hw->priv;
  1101. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1102. if (!sta->ht_cap.ht_supported)
  1103. return;
  1104. switch (cmd) {
  1105. case STA_NOTIFY_SLEEP:
  1106. an->sleeping = true;
  1107. ath_tx_aggr_sleep(sta, sc, an);
  1108. break;
  1109. case STA_NOTIFY_AWAKE:
  1110. an->sleeping = false;
  1111. ath_tx_aggr_wakeup(sc, an);
  1112. break;
  1113. }
  1114. }
  1115. static int ath9k_conf_tx(struct ieee80211_hw *hw,
  1116. struct ieee80211_vif *vif, u16 queue,
  1117. const struct ieee80211_tx_queue_params *params)
  1118. {
  1119. struct ath_softc *sc = hw->priv;
  1120. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1121. struct ath_txq *txq;
  1122. struct ath9k_tx_queue_info qi;
  1123. int ret = 0;
  1124. if (queue >= WME_NUM_AC)
  1125. return 0;
  1126. txq = sc->tx.txq_map[queue];
  1127. ath9k_ps_wakeup(sc);
  1128. mutex_lock(&sc->mutex);
  1129. memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
  1130. qi.tqi_aifs = params->aifs;
  1131. qi.tqi_cwmin = params->cw_min;
  1132. qi.tqi_cwmax = params->cw_max;
  1133. qi.tqi_burstTime = params->txop;
  1134. ath_dbg(common, CONFIG,
  1135. "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1136. queue, txq->axq_qnum, params->aifs, params->cw_min,
  1137. params->cw_max, params->txop);
  1138. ret = ath_txq_update(sc, txq->axq_qnum, &qi);
  1139. if (ret)
  1140. ath_err(common, "TXQ Update failed\n");
  1141. if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
  1142. if (queue == WME_AC_BE && !ret)
  1143. ath_beaconq_config(sc);
  1144. mutex_unlock(&sc->mutex);
  1145. ath9k_ps_restore(sc);
  1146. return ret;
  1147. }
  1148. static int ath9k_set_key(struct ieee80211_hw *hw,
  1149. enum set_key_cmd cmd,
  1150. struct ieee80211_vif *vif,
  1151. struct ieee80211_sta *sta,
  1152. struct ieee80211_key_conf *key)
  1153. {
  1154. struct ath_softc *sc = hw->priv;
  1155. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1156. int ret = 0;
  1157. if (ath9k_modparam_nohwcrypt)
  1158. return -ENOSPC;
  1159. if ((vif->type == NL80211_IFTYPE_ADHOC ||
  1160. vif->type == NL80211_IFTYPE_MESH_POINT) &&
  1161. (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
  1162. key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
  1163. !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
  1164. /*
  1165. * For now, disable hw crypto for the RSN IBSS group keys. This
  1166. * could be optimized in the future to use a modified key cache
  1167. * design to support per-STA RX GTK, but until that gets
  1168. * implemented, use of software crypto for group addressed
  1169. * frames is a acceptable to allow RSN IBSS to be used.
  1170. */
  1171. return -EOPNOTSUPP;
  1172. }
  1173. mutex_lock(&sc->mutex);
  1174. ath9k_ps_wakeup(sc);
  1175. ath_dbg(common, CONFIG, "Set HW Key\n");
  1176. switch (cmd) {
  1177. case SET_KEY:
  1178. if (sta)
  1179. ath9k_del_ps_key(sc, vif, sta);
  1180. ret = ath_key_config(common, vif, sta, key);
  1181. if (ret >= 0) {
  1182. key->hw_key_idx = ret;
  1183. /* push IV and Michael MIC generation to stack */
  1184. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1185. if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
  1186. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1187. if (sc->sc_ah->sw_mgmt_crypto &&
  1188. key->cipher == WLAN_CIPHER_SUITE_CCMP)
  1189. key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
  1190. ret = 0;
  1191. }
  1192. break;
  1193. case DISABLE_KEY:
  1194. ath_key_delete(common, key);
  1195. break;
  1196. default:
  1197. ret = -EINVAL;
  1198. }
  1199. ath9k_ps_restore(sc);
  1200. mutex_unlock(&sc->mutex);
  1201. return ret;
  1202. }
  1203. static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  1204. {
  1205. struct ath_softc *sc = data;
  1206. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1207. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1208. struct ath_vif *avp = (void *)vif->drv_priv;
  1209. unsigned long flags;
  1210. /*
  1211. * Skip iteration if primary station vif's bss info
  1212. * was not changed
  1213. */
  1214. if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags))
  1215. return;
  1216. if (bss_conf->assoc) {
  1217. set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
  1218. avp->primary_sta_vif = true;
  1219. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1220. common->curaid = bss_conf->aid;
  1221. ath9k_hw_write_associd(sc->sc_ah);
  1222. ath_dbg(common, CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
  1223. bss_conf->aid, common->curbssid);
  1224. ath_beacon_config(sc, vif);
  1225. /*
  1226. * Request a re-configuration of Beacon related timers
  1227. * on the receipt of the first Beacon frame (i.e.,
  1228. * after time sync with the AP).
  1229. */
  1230. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  1231. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  1232. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  1233. /* Reset rssi stats */
  1234. sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
  1235. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  1236. ath_start_rx_poll(sc, 3);
  1237. if (!common->disable_ani) {
  1238. set_bit(SC_OP_ANI_RUN, &sc->sc_flags);
  1239. ath_start_ani(common);
  1240. }
  1241. }
  1242. }
  1243. static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif)
  1244. {
  1245. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1246. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1247. struct ath_vif *avp = (void *)vif->drv_priv;
  1248. if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
  1249. return;
  1250. /* Reconfigure bss info */
  1251. if (avp->primary_sta_vif && !bss_conf->assoc) {
  1252. ath_dbg(common, CONFIG, "Bss Info DISASSOC %d, bssid %pM\n",
  1253. common->curaid, common->curbssid);
  1254. clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
  1255. clear_bit(SC_OP_BEACONS, &sc->sc_flags);
  1256. avp->primary_sta_vif = false;
  1257. memset(common->curbssid, 0, ETH_ALEN);
  1258. common->curaid = 0;
  1259. }
  1260. ieee80211_iterate_active_interfaces_atomic(
  1261. sc->hw, ath9k_bss_iter, sc);
  1262. /*
  1263. * None of station vifs are associated.
  1264. * Clear bssid & aid
  1265. */
  1266. if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  1267. ath9k_hw_write_associd(sc->sc_ah);
  1268. clear_bit(SC_OP_ANI_RUN, &sc->sc_flags);
  1269. del_timer_sync(&common->ani.timer);
  1270. del_timer_sync(&sc->rx_poll_timer);
  1271. memset(&sc->caldata, 0, sizeof(sc->caldata));
  1272. }
  1273. }
  1274. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1275. struct ieee80211_vif *vif,
  1276. struct ieee80211_bss_conf *bss_conf,
  1277. u32 changed)
  1278. {
  1279. struct ath_softc *sc = hw->priv;
  1280. struct ath_hw *ah = sc->sc_ah;
  1281. struct ath_common *common = ath9k_hw_common(ah);
  1282. struct ath_vif *avp = (void *)vif->drv_priv;
  1283. int slottime;
  1284. ath9k_ps_wakeup(sc);
  1285. mutex_lock(&sc->mutex);
  1286. if (changed & BSS_CHANGED_ASSOC) {
  1287. ath9k_config_bss(sc, vif);
  1288. ath_dbg(common, CONFIG, "BSSID: %pM aid: 0x%x\n",
  1289. common->curbssid, common->curaid);
  1290. }
  1291. if (changed & BSS_CHANGED_IBSS) {
  1292. /* There can be only one vif available */
  1293. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1294. common->curaid = bss_conf->aid;
  1295. ath9k_hw_write_associd(sc->sc_ah);
  1296. if (bss_conf->ibss_joined) {
  1297. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  1298. if (!common->disable_ani) {
  1299. set_bit(SC_OP_ANI_RUN, &sc->sc_flags);
  1300. ath_start_ani(common);
  1301. }
  1302. } else {
  1303. clear_bit(SC_OP_ANI_RUN, &sc->sc_flags);
  1304. del_timer_sync(&common->ani.timer);
  1305. del_timer_sync(&sc->rx_poll_timer);
  1306. }
  1307. }
  1308. /*
  1309. * In case of AP mode, the HW TSF has to be reset
  1310. * when the beacon interval changes.
  1311. */
  1312. if ((changed & BSS_CHANGED_BEACON_INT) &&
  1313. (vif->type == NL80211_IFTYPE_AP))
  1314. set_bit(SC_OP_TSF_RESET, &sc->sc_flags);
  1315. /* Configure beaconing (AP, IBSS, MESH) */
  1316. if (ath9k_uses_beacons(vif->type) &&
  1317. ((changed & BSS_CHANGED_BEACON) ||
  1318. (changed & BSS_CHANGED_BEACON_ENABLED) ||
  1319. (changed & BSS_CHANGED_BEACON_INT))) {
  1320. ath9k_set_beaconing_status(sc, false);
  1321. if (bss_conf->enable_beacon)
  1322. ath_beacon_alloc(sc, vif);
  1323. else
  1324. avp->is_bslot_active = false;
  1325. ath_beacon_config(sc, vif);
  1326. ath9k_set_beaconing_status(sc, true);
  1327. }
  1328. if (changed & BSS_CHANGED_ERP_SLOT) {
  1329. if (bss_conf->use_short_slot)
  1330. slottime = 9;
  1331. else
  1332. slottime = 20;
  1333. if (vif->type == NL80211_IFTYPE_AP) {
  1334. /*
  1335. * Defer update, so that connected stations can adjust
  1336. * their settings at the same time.
  1337. * See beacon.c for more details
  1338. */
  1339. sc->beacon.slottime = slottime;
  1340. sc->beacon.updateslot = UPDATE;
  1341. } else {
  1342. ah->slottime = slottime;
  1343. ath9k_hw_init_global_settings(ah);
  1344. }
  1345. }
  1346. mutex_unlock(&sc->mutex);
  1347. ath9k_ps_restore(sc);
  1348. }
  1349. static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1350. {
  1351. struct ath_softc *sc = hw->priv;
  1352. u64 tsf;
  1353. mutex_lock(&sc->mutex);
  1354. ath9k_ps_wakeup(sc);
  1355. tsf = ath9k_hw_gettsf64(sc->sc_ah);
  1356. ath9k_ps_restore(sc);
  1357. mutex_unlock(&sc->mutex);
  1358. return tsf;
  1359. }
  1360. static void ath9k_set_tsf(struct ieee80211_hw *hw,
  1361. struct ieee80211_vif *vif,
  1362. u64 tsf)
  1363. {
  1364. struct ath_softc *sc = hw->priv;
  1365. mutex_lock(&sc->mutex);
  1366. ath9k_ps_wakeup(sc);
  1367. ath9k_hw_settsf64(sc->sc_ah, tsf);
  1368. ath9k_ps_restore(sc);
  1369. mutex_unlock(&sc->mutex);
  1370. }
  1371. static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1372. {
  1373. struct ath_softc *sc = hw->priv;
  1374. mutex_lock(&sc->mutex);
  1375. ath9k_ps_wakeup(sc);
  1376. ath9k_hw_reset_tsf(sc->sc_ah);
  1377. ath9k_ps_restore(sc);
  1378. mutex_unlock(&sc->mutex);
  1379. }
  1380. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1381. struct ieee80211_vif *vif,
  1382. enum ieee80211_ampdu_mlme_action action,
  1383. struct ieee80211_sta *sta,
  1384. u16 tid, u16 *ssn, u8 buf_size)
  1385. {
  1386. struct ath_softc *sc = hw->priv;
  1387. int ret = 0;
  1388. local_bh_disable();
  1389. switch (action) {
  1390. case IEEE80211_AMPDU_RX_START:
  1391. break;
  1392. case IEEE80211_AMPDU_RX_STOP:
  1393. break;
  1394. case IEEE80211_AMPDU_TX_START:
  1395. ath9k_ps_wakeup(sc);
  1396. ret = ath_tx_aggr_start(sc, sta, tid, ssn);
  1397. if (!ret)
  1398. ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1399. ath9k_ps_restore(sc);
  1400. break;
  1401. case IEEE80211_AMPDU_TX_STOP:
  1402. ath9k_ps_wakeup(sc);
  1403. ath_tx_aggr_stop(sc, sta, tid);
  1404. ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1405. ath9k_ps_restore(sc);
  1406. break;
  1407. case IEEE80211_AMPDU_TX_OPERATIONAL:
  1408. ath9k_ps_wakeup(sc);
  1409. ath_tx_aggr_resume(sc, sta, tid);
  1410. ath9k_ps_restore(sc);
  1411. break;
  1412. default:
  1413. ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
  1414. }
  1415. local_bh_enable();
  1416. return ret;
  1417. }
  1418. static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
  1419. struct survey_info *survey)
  1420. {
  1421. struct ath_softc *sc = hw->priv;
  1422. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1423. struct ieee80211_supported_band *sband;
  1424. struct ieee80211_channel *chan;
  1425. unsigned long flags;
  1426. int pos;
  1427. spin_lock_irqsave(&common->cc_lock, flags);
  1428. if (idx == 0)
  1429. ath_update_survey_stats(sc);
  1430. sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
  1431. if (sband && idx >= sband->n_channels) {
  1432. idx -= sband->n_channels;
  1433. sband = NULL;
  1434. }
  1435. if (!sband)
  1436. sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
  1437. if (!sband || idx >= sband->n_channels) {
  1438. spin_unlock_irqrestore(&common->cc_lock, flags);
  1439. return -ENOENT;
  1440. }
  1441. chan = &sband->channels[idx];
  1442. pos = chan->hw_value;
  1443. memcpy(survey, &sc->survey[pos], sizeof(*survey));
  1444. survey->channel = chan;
  1445. spin_unlock_irqrestore(&common->cc_lock, flags);
  1446. return 0;
  1447. }
  1448. static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
  1449. {
  1450. struct ath_softc *sc = hw->priv;
  1451. struct ath_hw *ah = sc->sc_ah;
  1452. mutex_lock(&sc->mutex);
  1453. ah->coverage_class = coverage_class;
  1454. ath9k_ps_wakeup(sc);
  1455. ath9k_hw_init_global_settings(ah);
  1456. ath9k_ps_restore(sc);
  1457. mutex_unlock(&sc->mutex);
  1458. }
  1459. static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
  1460. {
  1461. struct ath_softc *sc = hw->priv;
  1462. struct ath_hw *ah = sc->sc_ah;
  1463. struct ath_common *common = ath9k_hw_common(ah);
  1464. int timeout = 200; /* ms */
  1465. int i, j;
  1466. bool drain_txq;
  1467. mutex_lock(&sc->mutex);
  1468. cancel_delayed_work_sync(&sc->tx_complete_work);
  1469. if (ah->ah_flags & AH_UNPLUGGED) {
  1470. ath_dbg(common, ANY, "Device has been unplugged!\n");
  1471. mutex_unlock(&sc->mutex);
  1472. return;
  1473. }
  1474. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  1475. ath_dbg(common, ANY, "Device not present\n");
  1476. mutex_unlock(&sc->mutex);
  1477. return;
  1478. }
  1479. for (j = 0; j < timeout; j++) {
  1480. bool npend = false;
  1481. if (j)
  1482. usleep_range(1000, 2000);
  1483. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1484. if (!ATH_TXQ_SETUP(sc, i))
  1485. continue;
  1486. npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
  1487. if (npend)
  1488. break;
  1489. }
  1490. if (!npend)
  1491. break;
  1492. }
  1493. if (drop) {
  1494. ath9k_ps_wakeup(sc);
  1495. spin_lock_bh(&sc->sc_pcu_lock);
  1496. drain_txq = ath_drain_all_txq(sc, false);
  1497. spin_unlock_bh(&sc->sc_pcu_lock);
  1498. if (!drain_txq)
  1499. ath_reset(sc, false);
  1500. ath9k_ps_restore(sc);
  1501. ieee80211_wake_queues(hw);
  1502. }
  1503. ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
  1504. mutex_unlock(&sc->mutex);
  1505. }
  1506. static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
  1507. {
  1508. struct ath_softc *sc = hw->priv;
  1509. int i;
  1510. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1511. if (!ATH_TXQ_SETUP(sc, i))
  1512. continue;
  1513. if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
  1514. return true;
  1515. }
  1516. return false;
  1517. }
  1518. static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
  1519. {
  1520. struct ath_softc *sc = hw->priv;
  1521. struct ath_hw *ah = sc->sc_ah;
  1522. struct ieee80211_vif *vif;
  1523. struct ath_vif *avp;
  1524. struct ath_buf *bf;
  1525. struct ath_tx_status ts;
  1526. bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
  1527. int status;
  1528. vif = sc->beacon.bslot[0];
  1529. if (!vif)
  1530. return 0;
  1531. avp = (void *)vif->drv_priv;
  1532. if (!avp->is_bslot_active)
  1533. return 0;
  1534. if (!sc->beacon.tx_processed && !edma) {
  1535. tasklet_disable(&sc->bcon_tasklet);
  1536. bf = avp->av_bcbuf;
  1537. if (!bf || !bf->bf_mpdu)
  1538. goto skip;
  1539. status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
  1540. if (status == -EINPROGRESS)
  1541. goto skip;
  1542. sc->beacon.tx_processed = true;
  1543. sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
  1544. skip:
  1545. tasklet_enable(&sc->bcon_tasklet);
  1546. }
  1547. return sc->beacon.tx_last;
  1548. }
  1549. static int ath9k_get_stats(struct ieee80211_hw *hw,
  1550. struct ieee80211_low_level_stats *stats)
  1551. {
  1552. struct ath_softc *sc = hw->priv;
  1553. struct ath_hw *ah = sc->sc_ah;
  1554. struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
  1555. stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
  1556. stats->dot11RTSFailureCount = mib_stats->rts_bad;
  1557. stats->dot11FCSErrorCount = mib_stats->fcs_bad;
  1558. stats->dot11RTSSuccessCount = mib_stats->rts_good;
  1559. return 0;
  1560. }
  1561. static u32 fill_chainmask(u32 cap, u32 new)
  1562. {
  1563. u32 filled = 0;
  1564. int i;
  1565. for (i = 0; cap && new; i++, cap >>= 1) {
  1566. if (!(cap & BIT(0)))
  1567. continue;
  1568. if (new & BIT(0))
  1569. filled |= BIT(i);
  1570. new >>= 1;
  1571. }
  1572. return filled;
  1573. }
  1574. static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
  1575. {
  1576. struct ath_softc *sc = hw->priv;
  1577. struct ath_hw *ah = sc->sc_ah;
  1578. if (!rx_ant || !tx_ant)
  1579. return -EINVAL;
  1580. sc->ant_rx = rx_ant;
  1581. sc->ant_tx = tx_ant;
  1582. if (ah->caps.rx_chainmask == 1)
  1583. return 0;
  1584. /* AR9100 runs into calibration issues if not all rx chains are enabled */
  1585. if (AR_SREV_9100(ah))
  1586. ah->rxchainmask = 0x7;
  1587. else
  1588. ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
  1589. ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
  1590. ath9k_reload_chainmask_settings(sc);
  1591. return 0;
  1592. }
  1593. static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
  1594. {
  1595. struct ath_softc *sc = hw->priv;
  1596. *tx_ant = sc->ant_tx;
  1597. *rx_ant = sc->ant_rx;
  1598. return 0;
  1599. }
  1600. #ifdef CONFIG_ATH9K_DEBUGFS
  1601. /* Ethtool support for get-stats */
  1602. #define AMKSTR(nm) #nm "_BE", #nm "_BK", #nm "_VI", #nm "_VO"
  1603. static const char ath9k_gstrings_stats[][ETH_GSTRING_LEN] = {
  1604. "tx_pkts_nic",
  1605. "tx_bytes_nic",
  1606. "rx_pkts_nic",
  1607. "rx_bytes_nic",
  1608. AMKSTR(d_tx_pkts),
  1609. AMKSTR(d_tx_bytes),
  1610. AMKSTR(d_tx_mpdus_queued),
  1611. AMKSTR(d_tx_mpdus_completed),
  1612. AMKSTR(d_tx_mpdu_xretries),
  1613. AMKSTR(d_tx_aggregates),
  1614. AMKSTR(d_tx_ampdus_queued_hw),
  1615. AMKSTR(d_tx_ampdus_queued_sw),
  1616. AMKSTR(d_tx_ampdus_completed),
  1617. AMKSTR(d_tx_ampdu_retries),
  1618. AMKSTR(d_tx_ampdu_xretries),
  1619. AMKSTR(d_tx_fifo_underrun),
  1620. AMKSTR(d_tx_op_exceeded),
  1621. AMKSTR(d_tx_timer_expiry),
  1622. AMKSTR(d_tx_desc_cfg_err),
  1623. AMKSTR(d_tx_data_underrun),
  1624. AMKSTR(d_tx_delim_underrun),
  1625. "d_rx_decrypt_crc_err",
  1626. "d_rx_phy_err",
  1627. "d_rx_mic_err",
  1628. "d_rx_pre_delim_crc_err",
  1629. "d_rx_post_delim_crc_err",
  1630. "d_rx_decrypt_busy_err",
  1631. "d_rx_phyerr_radar",
  1632. "d_rx_phyerr_ofdm_timing",
  1633. "d_rx_phyerr_cck_timing",
  1634. };
  1635. #define ATH9K_SSTATS_LEN ARRAY_SIZE(ath9k_gstrings_stats)
  1636. static void ath9k_get_et_strings(struct ieee80211_hw *hw,
  1637. struct ieee80211_vif *vif,
  1638. u32 sset, u8 *data)
  1639. {
  1640. if (sset == ETH_SS_STATS)
  1641. memcpy(data, *ath9k_gstrings_stats,
  1642. sizeof(ath9k_gstrings_stats));
  1643. }
  1644. static int ath9k_get_et_sset_count(struct ieee80211_hw *hw,
  1645. struct ieee80211_vif *vif, int sset)
  1646. {
  1647. if (sset == ETH_SS_STATS)
  1648. return ATH9K_SSTATS_LEN;
  1649. return 0;
  1650. }
  1651. #define PR_QNUM(_n) (sc->tx.txq_map[_n]->axq_qnum)
  1652. #define AWDATA(elem) \
  1653. do { \
  1654. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].elem; \
  1655. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].elem; \
  1656. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].elem; \
  1657. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].elem; \
  1658. } while (0)
  1659. #define AWDATA_RX(elem) \
  1660. do { \
  1661. data[i++] = sc->debug.stats.rxstats.elem; \
  1662. } while (0)
  1663. static void ath9k_get_et_stats(struct ieee80211_hw *hw,
  1664. struct ieee80211_vif *vif,
  1665. struct ethtool_stats *stats, u64 *data)
  1666. {
  1667. struct ath_softc *sc = hw->priv;
  1668. int i = 0;
  1669. data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_pkts_all +
  1670. sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_pkts_all +
  1671. sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_pkts_all +
  1672. sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_pkts_all);
  1673. data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_bytes_all +
  1674. sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_bytes_all +
  1675. sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_bytes_all +
  1676. sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_bytes_all);
  1677. AWDATA_RX(rx_pkts_all);
  1678. AWDATA_RX(rx_bytes_all);
  1679. AWDATA(tx_pkts_all);
  1680. AWDATA(tx_bytes_all);
  1681. AWDATA(queued);
  1682. AWDATA(completed);
  1683. AWDATA(xretries);
  1684. AWDATA(a_aggr);
  1685. AWDATA(a_queued_hw);
  1686. AWDATA(a_queued_sw);
  1687. AWDATA(a_completed);
  1688. AWDATA(a_retries);
  1689. AWDATA(a_xretries);
  1690. AWDATA(fifo_underrun);
  1691. AWDATA(xtxop);
  1692. AWDATA(timer_exp);
  1693. AWDATA(desc_cfg_err);
  1694. AWDATA(data_underrun);
  1695. AWDATA(delim_underrun);
  1696. AWDATA_RX(decrypt_crc_err);
  1697. AWDATA_RX(phy_err);
  1698. AWDATA_RX(mic_err);
  1699. AWDATA_RX(pre_delim_crc_err);
  1700. AWDATA_RX(post_delim_crc_err);
  1701. AWDATA_RX(decrypt_busy_err);
  1702. AWDATA_RX(phy_err_stats[ATH9K_PHYERR_RADAR]);
  1703. AWDATA_RX(phy_err_stats[ATH9K_PHYERR_OFDM_TIMING]);
  1704. AWDATA_RX(phy_err_stats[ATH9K_PHYERR_CCK_TIMING]);
  1705. WARN_ON(i != ATH9K_SSTATS_LEN);
  1706. }
  1707. /* End of ethtool get-stats functions */
  1708. #endif
  1709. #ifdef CONFIG_PM_SLEEP
  1710. static void ath9k_wow_map_triggers(struct ath_softc *sc,
  1711. struct cfg80211_wowlan *wowlan,
  1712. u32 *wow_triggers)
  1713. {
  1714. if (wowlan->disconnect)
  1715. *wow_triggers |= AH_WOW_LINK_CHANGE |
  1716. AH_WOW_BEACON_MISS;
  1717. if (wowlan->magic_pkt)
  1718. *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN;
  1719. if (wowlan->n_patterns)
  1720. *wow_triggers |= AH_WOW_USER_PATTERN_EN;
  1721. sc->wow_enabled = *wow_triggers;
  1722. }
  1723. static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc)
  1724. {
  1725. struct ath_hw *ah = sc->sc_ah;
  1726. struct ath_common *common = ath9k_hw_common(ah);
  1727. struct ath9k_hw_capabilities *pcaps = &ah->caps;
  1728. int pattern_count = 0;
  1729. int i, byte_cnt;
  1730. u8 dis_deauth_pattern[MAX_PATTERN_SIZE];
  1731. u8 dis_deauth_mask[MAX_PATTERN_SIZE];
  1732. memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE);
  1733. memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE);
  1734. /*
  1735. * Create Dissassociate / Deauthenticate packet filter
  1736. *
  1737. * 2 bytes 2 byte 6 bytes 6 bytes 6 bytes
  1738. * +--------------+----------+---------+--------+--------+----
  1739. * + Frame Control+ Duration + DA + SA + BSSID +
  1740. * +--------------+----------+---------+--------+--------+----
  1741. *
  1742. * The above is the management frame format for disassociate/
  1743. * deauthenticate pattern, from this we need to match the first byte
  1744. * of 'Frame Control' and DA, SA, and BSSID fields
  1745. * (skipping 2nd byte of FC and Duration feild.
  1746. *
  1747. * Disassociate pattern
  1748. * --------------------
  1749. * Frame control = 00 00 1010
  1750. * DA, SA, BSSID = x:x:x:x:x:x
  1751. * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x
  1752. * | x:x:x:x:x:x -- 22 bytes
  1753. *
  1754. * Deauthenticate pattern
  1755. * ----------------------
  1756. * Frame control = 00 00 1100
  1757. * DA, SA, BSSID = x:x:x:x:x:x
  1758. * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x
  1759. * | x:x:x:x:x:x -- 22 bytes
  1760. */
  1761. /* Create Disassociate Pattern first */
  1762. byte_cnt = 0;
  1763. /* Fill out the mask with all FF's */
  1764. for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++)
  1765. dis_deauth_mask[i] = 0xff;
  1766. /* copy the first byte of frame control field */
  1767. dis_deauth_pattern[byte_cnt] = 0xa0;
  1768. byte_cnt++;
  1769. /* skip 2nd byte of frame control and Duration field */
  1770. byte_cnt += 3;
  1771. /*
  1772. * need not match the destination mac address, it can be a broadcast
  1773. * mac address or an unicast to this station
  1774. */
  1775. byte_cnt += 6;
  1776. /* copy the source mac address */
  1777. memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
  1778. byte_cnt += 6;
  1779. /* copy the bssid, its same as the source mac address */
  1780. memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
  1781. /* Create Disassociate pattern mask */
  1782. if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_EXACT) {
  1783. if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_DWORD) {
  1784. /*
  1785. * for AR9280, because of hardware limitation, the
  1786. * first 4 bytes have to be matched for all patterns.
  1787. * the mask for disassociation and de-auth pattern
  1788. * matching need to enable the first 4 bytes.
  1789. * also the duration field needs to be filled.
  1790. */
  1791. dis_deauth_mask[0] = 0xf0;
  1792. /*
  1793. * fill in duration field
  1794. FIXME: what is the exact value ?
  1795. */
  1796. dis_deauth_pattern[2] = 0xff;
  1797. dis_deauth_pattern[3] = 0xff;
  1798. } else {
  1799. dis_deauth_mask[0] = 0xfe;
  1800. }
  1801. dis_deauth_mask[1] = 0x03;
  1802. dis_deauth_mask[2] = 0xc0;
  1803. } else {
  1804. dis_deauth_mask[0] = 0xef;
  1805. dis_deauth_mask[1] = 0x3f;
  1806. dis_deauth_mask[2] = 0x00;
  1807. dis_deauth_mask[3] = 0xfc;
  1808. }
  1809. ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n");
  1810. ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
  1811. pattern_count, byte_cnt);
  1812. pattern_count++;
  1813. /*
  1814. * for de-authenticate pattern, only the first byte of the frame
  1815. * control field gets changed from 0xA0 to 0xC0
  1816. */
  1817. dis_deauth_pattern[0] = 0xC0;
  1818. ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
  1819. pattern_count, byte_cnt);
  1820. }
  1821. static void ath9k_wow_add_pattern(struct ath_softc *sc,
  1822. struct cfg80211_wowlan *wowlan)
  1823. {
  1824. struct ath_hw *ah = sc->sc_ah;
  1825. struct ath9k_wow_pattern *wow_pattern = NULL;
  1826. struct cfg80211_wowlan_trig_pkt_pattern *patterns = wowlan->patterns;
  1827. int mask_len;
  1828. s8 i = 0;
  1829. if (!wowlan->n_patterns)
  1830. return;
  1831. /*
  1832. * Add the new user configured patterns
  1833. */
  1834. for (i = 0; i < wowlan->n_patterns; i++) {
  1835. wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL);
  1836. if (!wow_pattern)
  1837. return;
  1838. /*
  1839. * TODO: convert the generic user space pattern to
  1840. * appropriate chip specific/802.11 pattern.
  1841. */
  1842. mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8);
  1843. memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE);
  1844. memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE);
  1845. memcpy(wow_pattern->pattern_bytes, patterns[i].pattern,
  1846. patterns[i].pattern_len);
  1847. memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len);
  1848. wow_pattern->pattern_len = patterns[i].pattern_len;
  1849. /*
  1850. * just need to take care of deauth and disssoc pattern,
  1851. * make sure we don't overwrite them.
  1852. */
  1853. ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes,
  1854. wow_pattern->mask_bytes,
  1855. i + 2,
  1856. wow_pattern->pattern_len);
  1857. kfree(wow_pattern);
  1858. }
  1859. }
  1860. static int ath9k_suspend(struct ieee80211_hw *hw,
  1861. struct cfg80211_wowlan *wowlan)
  1862. {
  1863. struct ath_softc *sc = hw->priv;
  1864. struct ath_hw *ah = sc->sc_ah;
  1865. struct ath_common *common = ath9k_hw_common(ah);
  1866. u32 wow_triggers_enabled = 0;
  1867. int ret = 0;
  1868. mutex_lock(&sc->mutex);
  1869. ath_cancel_work(sc);
  1870. del_timer_sync(&common->ani.timer);
  1871. del_timer_sync(&sc->rx_poll_timer);
  1872. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  1873. ath_dbg(common, ANY, "Device not present\n");
  1874. ret = -EINVAL;
  1875. goto fail_wow;
  1876. }
  1877. if (WARN_ON(!wowlan)) {
  1878. ath_dbg(common, WOW, "None of the WoW triggers enabled\n");
  1879. ret = -EINVAL;
  1880. goto fail_wow;
  1881. }
  1882. if (!device_can_wakeup(sc->dev)) {
  1883. ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n");
  1884. ret = 1;
  1885. goto fail_wow;
  1886. }
  1887. /*
  1888. * none of the sta vifs are associated
  1889. * and we are not currently handling multivif
  1890. * cases, for instance we have to seperately
  1891. * configure 'keep alive frame' for each
  1892. * STA.
  1893. */
  1894. if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  1895. ath_dbg(common, WOW, "None of the STA vifs are associated\n");
  1896. ret = 1;
  1897. goto fail_wow;
  1898. }
  1899. if (sc->nvifs > 1) {
  1900. ath_dbg(common, WOW, "WoW for multivif is not yet supported\n");
  1901. ret = 1;
  1902. goto fail_wow;
  1903. }
  1904. ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled);
  1905. ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n",
  1906. wow_triggers_enabled);
  1907. ath9k_ps_wakeup(sc);
  1908. ath9k_stop_btcoex(sc);
  1909. /*
  1910. * Enable wake up on recieving disassoc/deauth
  1911. * frame by default.
  1912. */
  1913. ath9k_wow_add_disassoc_deauth_pattern(sc);
  1914. if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN)
  1915. ath9k_wow_add_pattern(sc, wowlan);
  1916. spin_lock_bh(&sc->sc_pcu_lock);
  1917. /*
  1918. * To avoid false wake, we enable beacon miss interrupt only
  1919. * when we go to sleep. We save the current interrupt mask
  1920. * so we can restore it after the system wakes up
  1921. */
  1922. sc->wow_intr_before_sleep = ah->imask;
  1923. ah->imask &= ~ATH9K_INT_GLOBAL;
  1924. ath9k_hw_disable_interrupts(ah);
  1925. ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL;
  1926. ath9k_hw_set_interrupts(ah);
  1927. ath9k_hw_enable_interrupts(ah);
  1928. spin_unlock_bh(&sc->sc_pcu_lock);
  1929. /*
  1930. * we can now sync irq and kill any running tasklets, since we already
  1931. * disabled interrupts and not holding a spin lock
  1932. */
  1933. synchronize_irq(sc->irq);
  1934. tasklet_kill(&sc->intr_tq);
  1935. ath9k_hw_wow_enable(ah, wow_triggers_enabled);
  1936. ath9k_ps_restore(sc);
  1937. ath_dbg(common, ANY, "WoW enabled in ath9k\n");
  1938. atomic_inc(&sc->wow_sleep_proc_intr);
  1939. fail_wow:
  1940. mutex_unlock(&sc->mutex);
  1941. return ret;
  1942. }
  1943. static int ath9k_resume(struct ieee80211_hw *hw)
  1944. {
  1945. struct ath_softc *sc = hw->priv;
  1946. struct ath_hw *ah = sc->sc_ah;
  1947. struct ath_common *common = ath9k_hw_common(ah);
  1948. u32 wow_status;
  1949. mutex_lock(&sc->mutex);
  1950. ath9k_ps_wakeup(sc);
  1951. spin_lock_bh(&sc->sc_pcu_lock);
  1952. ath9k_hw_disable_interrupts(ah);
  1953. ah->imask = sc->wow_intr_before_sleep;
  1954. ath9k_hw_set_interrupts(ah);
  1955. ath9k_hw_enable_interrupts(ah);
  1956. spin_unlock_bh(&sc->sc_pcu_lock);
  1957. wow_status = ath9k_hw_wow_wakeup(ah);
  1958. if (atomic_read(&sc->wow_got_bmiss_intr) == 0) {
  1959. /*
  1960. * some devices may not pick beacon miss
  1961. * as the reason they woke up so we add
  1962. * that here for that shortcoming.
  1963. */
  1964. wow_status |= AH_WOW_BEACON_MISS;
  1965. atomic_dec(&sc->wow_got_bmiss_intr);
  1966. ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n");
  1967. }
  1968. atomic_dec(&sc->wow_sleep_proc_intr);
  1969. if (wow_status) {
  1970. ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n",
  1971. ath9k_hw_wow_event_to_string(wow_status), wow_status);
  1972. }
  1973. ath_restart_work(sc);
  1974. ath9k_start_btcoex(sc);
  1975. ath9k_ps_restore(sc);
  1976. mutex_unlock(&sc->mutex);
  1977. return 0;
  1978. }
  1979. static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
  1980. {
  1981. struct ath_softc *sc = hw->priv;
  1982. mutex_lock(&sc->mutex);
  1983. device_init_wakeup(sc->dev, 1);
  1984. device_set_wakeup_enable(sc->dev, enabled);
  1985. mutex_unlock(&sc->mutex);
  1986. }
  1987. #endif
  1988. struct ieee80211_ops ath9k_ops = {
  1989. .tx = ath9k_tx,
  1990. .start = ath9k_start,
  1991. .stop = ath9k_stop,
  1992. .add_interface = ath9k_add_interface,
  1993. .change_interface = ath9k_change_interface,
  1994. .remove_interface = ath9k_remove_interface,
  1995. .config = ath9k_config,
  1996. .configure_filter = ath9k_configure_filter,
  1997. .sta_add = ath9k_sta_add,
  1998. .sta_remove = ath9k_sta_remove,
  1999. .sta_notify = ath9k_sta_notify,
  2000. .conf_tx = ath9k_conf_tx,
  2001. .bss_info_changed = ath9k_bss_info_changed,
  2002. .set_key = ath9k_set_key,
  2003. .get_tsf = ath9k_get_tsf,
  2004. .set_tsf = ath9k_set_tsf,
  2005. .reset_tsf = ath9k_reset_tsf,
  2006. .ampdu_action = ath9k_ampdu_action,
  2007. .get_survey = ath9k_get_survey,
  2008. .rfkill_poll = ath9k_rfkill_poll_state,
  2009. .set_coverage_class = ath9k_set_coverage_class,
  2010. .flush = ath9k_flush,
  2011. .tx_frames_pending = ath9k_tx_frames_pending,
  2012. .tx_last_beacon = ath9k_tx_last_beacon,
  2013. .get_stats = ath9k_get_stats,
  2014. .set_antenna = ath9k_set_antenna,
  2015. .get_antenna = ath9k_get_antenna,
  2016. #ifdef CONFIG_PM_SLEEP
  2017. .suspend = ath9k_suspend,
  2018. .resume = ath9k_resume,
  2019. .set_wakeup = ath9k_set_wakeup,
  2020. #endif
  2021. #ifdef CONFIG_ATH9K_DEBUGFS
  2022. .get_et_sset_count = ath9k_get_et_sset_count,
  2023. .get_et_stats = ath9k_get_et_stats,
  2024. .get_et_strings = ath9k_get_et_strings,
  2025. #endif
  2026. };