pci.c 21 KB

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  1. /*
  2. * Copyright IBM Corp. 2012
  3. *
  4. * Author(s):
  5. * Jan Glauber <jang@linux.vnet.ibm.com>
  6. *
  7. * The System z PCI code is a rewrite from a prototype by
  8. * the following people (Kudoz!):
  9. * Alexander Schmidt
  10. * Christoph Raisch
  11. * Hannes Hering
  12. * Hoang-Nam Nguyen
  13. * Jan-Bernd Themann
  14. * Stefan Roscher
  15. * Thomas Klein
  16. */
  17. #define COMPONENT "zPCI"
  18. #define pr_fmt(fmt) COMPONENT ": " fmt
  19. #include <linux/kernel.h>
  20. #include <linux/slab.h>
  21. #include <linux/err.h>
  22. #include <linux/export.h>
  23. #include <linux/delay.h>
  24. #include <linux/irq.h>
  25. #include <linux/kernel_stat.h>
  26. #include <linux/seq_file.h>
  27. #include <linux/pci.h>
  28. #include <linux/msi.h>
  29. #include <asm/isc.h>
  30. #include <asm/airq.h>
  31. #include <asm/facility.h>
  32. #include <asm/pci_insn.h>
  33. #include <asm/pci_clp.h>
  34. #include <asm/pci_dma.h>
  35. #define DEBUG /* enable pr_debug */
  36. #define SIC_IRQ_MODE_ALL 0
  37. #define SIC_IRQ_MODE_SINGLE 1
  38. #define ZPCI_NR_DMA_SPACES 1
  39. #define ZPCI_NR_DEVICES CONFIG_PCI_NR_FUNCTIONS
  40. /* list of all detected zpci devices */
  41. LIST_HEAD(zpci_list);
  42. EXPORT_SYMBOL_GPL(zpci_list);
  43. DEFINE_MUTEX(zpci_list_lock);
  44. EXPORT_SYMBOL_GPL(zpci_list_lock);
  45. static void zpci_enable_irq(struct irq_data *data);
  46. static void zpci_disable_irq(struct irq_data *data);
  47. static struct irq_chip zpci_irq_chip = {
  48. .name = "zPCI",
  49. .irq_unmask = zpci_enable_irq,
  50. .irq_mask = zpci_disable_irq,
  51. };
  52. static struct pci_hp_callback_ops *hotplug_ops;
  53. static DECLARE_BITMAP(zpci_domain, ZPCI_NR_DEVICES);
  54. static DEFINE_SPINLOCK(zpci_domain_lock);
  55. static struct airq_iv *zpci_aisb_iv;
  56. static struct airq_iv *zpci_aibv[ZPCI_NR_DEVICES];
  57. /* Adapter interrupt definitions */
  58. static void zpci_irq_handler(struct airq_struct *airq);
  59. static struct airq_struct zpci_airq = {
  60. .handler = zpci_irq_handler,
  61. .isc = PCI_ISC,
  62. };
  63. /* I/O Map */
  64. static DEFINE_SPINLOCK(zpci_iomap_lock);
  65. static DECLARE_BITMAP(zpci_iomap, ZPCI_IOMAP_MAX_ENTRIES);
  66. struct zpci_iomap_entry *zpci_iomap_start;
  67. EXPORT_SYMBOL_GPL(zpci_iomap_start);
  68. static struct kmem_cache *zdev_fmb_cache;
  69. struct zpci_dev *get_zdev(struct pci_dev *pdev)
  70. {
  71. return (struct zpci_dev *) pdev->sysdata;
  72. }
  73. struct zpci_dev *get_zdev_by_fid(u32 fid)
  74. {
  75. struct zpci_dev *tmp, *zdev = NULL;
  76. mutex_lock(&zpci_list_lock);
  77. list_for_each_entry(tmp, &zpci_list, entry) {
  78. if (tmp->fid == fid) {
  79. zdev = tmp;
  80. break;
  81. }
  82. }
  83. mutex_unlock(&zpci_list_lock);
  84. return zdev;
  85. }
  86. bool zpci_fid_present(u32 fid)
  87. {
  88. return (get_zdev_by_fid(fid) != NULL) ? true : false;
  89. }
  90. static struct zpci_dev *get_zdev_by_bus(struct pci_bus *bus)
  91. {
  92. return (bus && bus->sysdata) ? (struct zpci_dev *) bus->sysdata : NULL;
  93. }
  94. int pci_domain_nr(struct pci_bus *bus)
  95. {
  96. return ((struct zpci_dev *) bus->sysdata)->domain;
  97. }
  98. EXPORT_SYMBOL_GPL(pci_domain_nr);
  99. int pci_proc_domain(struct pci_bus *bus)
  100. {
  101. return pci_domain_nr(bus);
  102. }
  103. EXPORT_SYMBOL_GPL(pci_proc_domain);
  104. /* Modify PCI: Register adapter interruptions */
  105. static int zpci_set_airq(struct zpci_dev *zdev)
  106. {
  107. u64 req = ZPCI_CREATE_REQ(zdev->fh, 0, ZPCI_MOD_FC_REG_INT);
  108. struct zpci_fib *fib;
  109. int rc;
  110. fib = (void *) get_zeroed_page(GFP_KERNEL);
  111. if (!fib)
  112. return -ENOMEM;
  113. fib->isc = PCI_ISC;
  114. fib->sum = 1; /* enable summary notifications */
  115. fib->noi = airq_iv_end(zdev->aibv);
  116. fib->aibv = (unsigned long) zdev->aibv->vector;
  117. fib->aibvo = 0; /* each zdev has its own interrupt vector */
  118. fib->aisb = (unsigned long) zpci_aisb_iv->vector + (zdev->aisb/64)*8;
  119. fib->aisbo = zdev->aisb & 63;
  120. rc = zpci_mod_fc(req, fib);
  121. pr_debug("%s mpcifc returned noi: %d\n", __func__, fib->noi);
  122. free_page((unsigned long) fib);
  123. return rc;
  124. }
  125. struct mod_pci_args {
  126. u64 base;
  127. u64 limit;
  128. u64 iota;
  129. u64 fmb_addr;
  130. };
  131. static int mod_pci(struct zpci_dev *zdev, int fn, u8 dmaas, struct mod_pci_args *args)
  132. {
  133. u64 req = ZPCI_CREATE_REQ(zdev->fh, dmaas, fn);
  134. struct zpci_fib *fib;
  135. int rc;
  136. /* The FIB must be available even if it's not used */
  137. fib = (void *) get_zeroed_page(GFP_KERNEL);
  138. if (!fib)
  139. return -ENOMEM;
  140. fib->pba = args->base;
  141. fib->pal = args->limit;
  142. fib->iota = args->iota;
  143. fib->fmb_addr = args->fmb_addr;
  144. rc = zpci_mod_fc(req, fib);
  145. free_page((unsigned long) fib);
  146. return rc;
  147. }
  148. /* Modify PCI: Register I/O address translation parameters */
  149. int zpci_register_ioat(struct zpci_dev *zdev, u8 dmaas,
  150. u64 base, u64 limit, u64 iota)
  151. {
  152. struct mod_pci_args args = { base, limit, iota, 0 };
  153. WARN_ON_ONCE(iota & 0x3fff);
  154. args.iota |= ZPCI_IOTA_RTTO_FLAG;
  155. return mod_pci(zdev, ZPCI_MOD_FC_REG_IOAT, dmaas, &args);
  156. }
  157. /* Modify PCI: Unregister I/O address translation parameters */
  158. int zpci_unregister_ioat(struct zpci_dev *zdev, u8 dmaas)
  159. {
  160. struct mod_pci_args args = { 0, 0, 0, 0 };
  161. return mod_pci(zdev, ZPCI_MOD_FC_DEREG_IOAT, dmaas, &args);
  162. }
  163. /* Modify PCI: Unregister adapter interruptions */
  164. static int zpci_clear_airq(struct zpci_dev *zdev)
  165. {
  166. struct mod_pci_args args = { 0, 0, 0, 0 };
  167. return mod_pci(zdev, ZPCI_MOD_FC_DEREG_INT, 0, &args);
  168. }
  169. /* Modify PCI: Set PCI function measurement parameters */
  170. int zpci_fmb_enable_device(struct zpci_dev *zdev)
  171. {
  172. struct mod_pci_args args = { 0, 0, 0, 0 };
  173. if (zdev->fmb)
  174. return -EINVAL;
  175. zdev->fmb = kmem_cache_zalloc(zdev_fmb_cache, GFP_KERNEL);
  176. if (!zdev->fmb)
  177. return -ENOMEM;
  178. WARN_ON((u64) zdev->fmb & 0xf);
  179. args.fmb_addr = virt_to_phys(zdev->fmb);
  180. return mod_pci(zdev, ZPCI_MOD_FC_SET_MEASURE, 0, &args);
  181. }
  182. /* Modify PCI: Disable PCI function measurement */
  183. int zpci_fmb_disable_device(struct zpci_dev *zdev)
  184. {
  185. struct mod_pci_args args = { 0, 0, 0, 0 };
  186. int rc;
  187. if (!zdev->fmb)
  188. return -EINVAL;
  189. /* Function measurement is disabled if fmb address is zero */
  190. rc = mod_pci(zdev, ZPCI_MOD_FC_SET_MEASURE, 0, &args);
  191. kmem_cache_free(zdev_fmb_cache, zdev->fmb);
  192. zdev->fmb = NULL;
  193. return rc;
  194. }
  195. #define ZPCI_PCIAS_CFGSPC 15
  196. static int zpci_cfg_load(struct zpci_dev *zdev, int offset, u32 *val, u8 len)
  197. {
  198. u64 req = ZPCI_CREATE_REQ(zdev->fh, ZPCI_PCIAS_CFGSPC, len);
  199. u64 data;
  200. int rc;
  201. rc = zpci_load(&data, req, offset);
  202. if (!rc) {
  203. data = data << ((8 - len) * 8);
  204. data = le64_to_cpu(data);
  205. *val = (u32) data;
  206. } else
  207. *val = 0xffffffff;
  208. return rc;
  209. }
  210. static int zpci_cfg_store(struct zpci_dev *zdev, int offset, u32 val, u8 len)
  211. {
  212. u64 req = ZPCI_CREATE_REQ(zdev->fh, ZPCI_PCIAS_CFGSPC, len);
  213. u64 data = val;
  214. int rc;
  215. data = cpu_to_le64(data);
  216. data = data >> ((8 - len) * 8);
  217. rc = zpci_store(data, req, offset);
  218. return rc;
  219. }
  220. static int zpci_msi_set_mask_bits(struct msi_desc *msi, u32 mask, u32 flag)
  221. {
  222. int offset, pos;
  223. u32 mask_bits;
  224. if (msi->msi_attrib.is_msix) {
  225. offset = msi->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
  226. PCI_MSIX_ENTRY_VECTOR_CTRL;
  227. msi->masked = readl(msi->mask_base + offset);
  228. writel(flag, msi->mask_base + offset);
  229. } else if (msi->msi_attrib.maskbit) {
  230. pos = (long) msi->mask_base;
  231. pci_read_config_dword(msi->dev, pos, &mask_bits);
  232. mask_bits &= ~(mask);
  233. mask_bits |= flag & mask;
  234. pci_write_config_dword(msi->dev, pos, mask_bits);
  235. } else
  236. return 0;
  237. msi->msi_attrib.maskbit = !!flag;
  238. return 1;
  239. }
  240. static void zpci_enable_irq(struct irq_data *data)
  241. {
  242. struct msi_desc *msi = irq_get_msi_desc(data->irq);
  243. zpci_msi_set_mask_bits(msi, 1, 0);
  244. }
  245. static void zpci_disable_irq(struct irq_data *data)
  246. {
  247. struct msi_desc *msi = irq_get_msi_desc(data->irq);
  248. zpci_msi_set_mask_bits(msi, 1, 1);
  249. }
  250. void pcibios_fixup_bus(struct pci_bus *bus)
  251. {
  252. }
  253. resource_size_t pcibios_align_resource(void *data, const struct resource *res,
  254. resource_size_t size,
  255. resource_size_t align)
  256. {
  257. return 0;
  258. }
  259. /* combine single writes by using store-block insn */
  260. void __iowrite64_copy(void __iomem *to, const void *from, size_t count)
  261. {
  262. zpci_memcpy_toio(to, from, count);
  263. }
  264. /* Create a virtual mapping cookie for a PCI BAR */
  265. void __iomem *pci_iomap(struct pci_dev *pdev, int bar, unsigned long max)
  266. {
  267. struct zpci_dev *zdev = get_zdev(pdev);
  268. u64 addr;
  269. int idx;
  270. if ((bar & 7) != bar)
  271. return NULL;
  272. idx = zdev->bars[bar].map_idx;
  273. spin_lock(&zpci_iomap_lock);
  274. zpci_iomap_start[idx].fh = zdev->fh;
  275. zpci_iomap_start[idx].bar = bar;
  276. spin_unlock(&zpci_iomap_lock);
  277. addr = ZPCI_IOMAP_ADDR_BASE | ((u64) idx << 48);
  278. return (void __iomem *) addr;
  279. }
  280. EXPORT_SYMBOL_GPL(pci_iomap);
  281. void pci_iounmap(struct pci_dev *pdev, void __iomem *addr)
  282. {
  283. unsigned int idx;
  284. idx = (((__force u64) addr) & ~ZPCI_IOMAP_ADDR_BASE) >> 48;
  285. spin_lock(&zpci_iomap_lock);
  286. zpci_iomap_start[idx].fh = 0;
  287. zpci_iomap_start[idx].bar = 0;
  288. spin_unlock(&zpci_iomap_lock);
  289. }
  290. EXPORT_SYMBOL_GPL(pci_iounmap);
  291. static int pci_read(struct pci_bus *bus, unsigned int devfn, int where,
  292. int size, u32 *val)
  293. {
  294. struct zpci_dev *zdev = get_zdev_by_bus(bus);
  295. int ret;
  296. if (!zdev || devfn != ZPCI_DEVFN)
  297. ret = -ENODEV;
  298. else
  299. ret = zpci_cfg_load(zdev, where, val, size);
  300. return ret;
  301. }
  302. static int pci_write(struct pci_bus *bus, unsigned int devfn, int where,
  303. int size, u32 val)
  304. {
  305. struct zpci_dev *zdev = get_zdev_by_bus(bus);
  306. int ret;
  307. if (!zdev || devfn != ZPCI_DEVFN)
  308. ret = -ENODEV;
  309. else
  310. ret = zpci_cfg_store(zdev, where, val, size);
  311. return ret;
  312. }
  313. static struct pci_ops pci_root_ops = {
  314. .read = pci_read,
  315. .write = pci_write,
  316. };
  317. static void zpci_irq_handler(struct airq_struct *airq)
  318. {
  319. unsigned long si, ai;
  320. struct airq_iv *aibv;
  321. int irqs_on = 0;
  322. inc_irq_stat(IRQIO_PCI);
  323. for (si = 0;;) {
  324. /* Scan adapter summary indicator bit vector */
  325. si = airq_iv_scan(zpci_aisb_iv, si, airq_iv_end(zpci_aisb_iv));
  326. if (si == -1UL) {
  327. if (irqs_on++)
  328. /* End of second scan with interrupts on. */
  329. break;
  330. /* First scan complete, reenable interrupts. */
  331. zpci_set_irq_ctrl(SIC_IRQ_MODE_SINGLE, NULL, PCI_ISC);
  332. si = 0;
  333. continue;
  334. }
  335. /* Scan the adapter interrupt vector for this device. */
  336. aibv = zpci_aibv[si];
  337. for (ai = 0;;) {
  338. ai = airq_iv_scan(aibv, ai, airq_iv_end(aibv));
  339. if (ai == -1UL)
  340. break;
  341. inc_irq_stat(IRQIO_MSI);
  342. airq_iv_lock(aibv, ai);
  343. generic_handle_irq(airq_iv_get_data(aibv, ai));
  344. airq_iv_unlock(aibv, ai);
  345. }
  346. }
  347. }
  348. int arch_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
  349. {
  350. struct zpci_dev *zdev = get_zdev(pdev);
  351. unsigned int hwirq, irq, msi_vecs;
  352. unsigned long aisb;
  353. struct msi_desc *msi;
  354. struct msi_msg msg;
  355. int rc;
  356. pr_debug("%s: requesting %d MSI-X interrupts...", __func__, nvec);
  357. if (type != PCI_CAP_ID_MSIX && type != PCI_CAP_ID_MSI)
  358. return -EINVAL;
  359. msi_vecs = min(nvec, ZPCI_MSI_VEC_MAX);
  360. msi_vecs = min_t(unsigned int, msi_vecs, CONFIG_PCI_NR_MSI);
  361. /* Allocate adapter summary indicator bit */
  362. rc = -EIO;
  363. aisb = airq_iv_alloc_bit(zpci_aisb_iv);
  364. if (aisb == -1UL)
  365. goto out;
  366. zdev->aisb = aisb;
  367. /* Create adapter interrupt vector */
  368. rc = -ENOMEM;
  369. zdev->aibv = airq_iv_create(msi_vecs, AIRQ_IV_DATA | AIRQ_IV_BITLOCK);
  370. if (!zdev->aibv)
  371. goto out_si;
  372. /* Wire up shortcut pointer */
  373. zpci_aibv[aisb] = zdev->aibv;
  374. /* Request MSI interrupts */
  375. hwirq = 0;
  376. list_for_each_entry(msi, &pdev->msi_list, list) {
  377. rc = -EIO;
  378. irq = irq_alloc_desc(0); /* Alloc irq on node 0 */
  379. if (irq == NO_IRQ)
  380. goto out_msi;
  381. rc = irq_set_msi_desc(irq, msi);
  382. if (rc)
  383. goto out_msi;
  384. irq_set_chip_and_handler(irq, &zpci_irq_chip,
  385. handle_simple_irq);
  386. msg.data = hwirq;
  387. msg.address_lo = zdev->msi_addr & 0xffffffff;
  388. msg.address_hi = zdev->msi_addr >> 32;
  389. write_msi_msg(irq, &msg);
  390. airq_iv_set_data(zdev->aibv, hwirq, irq);
  391. hwirq++;
  392. }
  393. /* Enable adapter interrupts */
  394. rc = zpci_set_airq(zdev);
  395. if (rc)
  396. goto out_msi;
  397. return (msi_vecs == nvec) ? 0 : msi_vecs;
  398. out_msi:
  399. list_for_each_entry(msi, &pdev->msi_list, list) {
  400. if (hwirq-- == 0)
  401. break;
  402. irq_set_msi_desc(msi->irq, NULL);
  403. irq_free_desc(msi->irq);
  404. msi->msg.address_lo = 0;
  405. msi->msg.address_hi = 0;
  406. msi->msg.data = 0;
  407. msi->irq = 0;
  408. }
  409. zpci_aibv[aisb] = NULL;
  410. airq_iv_release(zdev->aibv);
  411. out_si:
  412. airq_iv_free_bit(zpci_aisb_iv, aisb);
  413. out:
  414. dev_err(&pdev->dev, "register MSI failed with: %d\n", rc);
  415. return rc;
  416. }
  417. void arch_teardown_msi_irqs(struct pci_dev *pdev)
  418. {
  419. struct zpci_dev *zdev = get_zdev(pdev);
  420. struct msi_desc *msi;
  421. int rc;
  422. pr_info("%s: on pdev: %p\n", __func__, pdev);
  423. /* Disable adapter interrupts */
  424. rc = zpci_clear_airq(zdev);
  425. if (rc) {
  426. dev_err(&pdev->dev, "deregister MSI failed with: %d\n", rc);
  427. return;
  428. }
  429. /* Release MSI interrupts */
  430. list_for_each_entry(msi, &pdev->msi_list, list) {
  431. zpci_msi_set_mask_bits(msi, 1, 1);
  432. irq_set_msi_desc(msi->irq, NULL);
  433. irq_free_desc(msi->irq);
  434. msi->msg.address_lo = 0;
  435. msi->msg.address_hi = 0;
  436. msi->msg.data = 0;
  437. msi->irq = 0;
  438. }
  439. zpci_aibv[zdev->aisb] = NULL;
  440. airq_iv_release(zdev->aibv);
  441. airq_iv_free_bit(zpci_aisb_iv, zdev->aisb);
  442. }
  443. static void zpci_map_resources(struct zpci_dev *zdev)
  444. {
  445. struct pci_dev *pdev = zdev->pdev;
  446. resource_size_t len;
  447. int i;
  448. for (i = 0; i < PCI_BAR_COUNT; i++) {
  449. len = pci_resource_len(pdev, i);
  450. if (!len)
  451. continue;
  452. pdev->resource[i].start = (resource_size_t) pci_iomap(pdev, i, 0);
  453. pdev->resource[i].end = pdev->resource[i].start + len - 1;
  454. pr_debug("BAR%i: -> start: %Lx end: %Lx\n",
  455. i, pdev->resource[i].start, pdev->resource[i].end);
  456. }
  457. }
  458. static void zpci_unmap_resources(struct zpci_dev *zdev)
  459. {
  460. struct pci_dev *pdev = zdev->pdev;
  461. resource_size_t len;
  462. int i;
  463. for (i = 0; i < PCI_BAR_COUNT; i++) {
  464. len = pci_resource_len(pdev, i);
  465. if (!len)
  466. continue;
  467. pci_iounmap(pdev, (void *) pdev->resource[i].start);
  468. }
  469. }
  470. struct zpci_dev *zpci_alloc_device(void)
  471. {
  472. struct zpci_dev *zdev;
  473. /* Alloc memory for our private pci device data */
  474. zdev = kzalloc(sizeof(*zdev), GFP_KERNEL);
  475. return zdev ? : ERR_PTR(-ENOMEM);
  476. }
  477. void zpci_free_device(struct zpci_dev *zdev)
  478. {
  479. kfree(zdev);
  480. }
  481. /*
  482. * Too late for any s390 specific setup, since interrupts must be set up
  483. * already which requires DMA setup too and the pci scan will access the
  484. * config space, which only works if the function handle is enabled.
  485. */
  486. int pcibios_enable_device(struct pci_dev *pdev, int mask)
  487. {
  488. struct resource *res;
  489. u16 cmd;
  490. int i;
  491. pci_read_config_word(pdev, PCI_COMMAND, &cmd);
  492. for (i = 0; i < PCI_BAR_COUNT; i++) {
  493. res = &pdev->resource[i];
  494. if (res->flags & IORESOURCE_IO)
  495. return -EINVAL;
  496. if (res->flags & IORESOURCE_MEM)
  497. cmd |= PCI_COMMAND_MEMORY;
  498. }
  499. pci_write_config_word(pdev, PCI_COMMAND, cmd);
  500. return 0;
  501. }
  502. int pcibios_add_platform_entries(struct pci_dev *pdev)
  503. {
  504. return zpci_sysfs_add_device(&pdev->dev);
  505. }
  506. static int __init zpci_irq_init(void)
  507. {
  508. int rc;
  509. rc = register_adapter_interrupt(&zpci_airq);
  510. if (rc)
  511. goto out;
  512. /* Set summary to 1 to be called every time for the ISC. */
  513. *zpci_airq.lsi_ptr = 1;
  514. rc = -ENOMEM;
  515. zpci_aisb_iv = airq_iv_create(ZPCI_NR_DEVICES, AIRQ_IV_ALLOC);
  516. if (!zpci_aisb_iv)
  517. goto out_airq;
  518. zpci_set_irq_ctrl(SIC_IRQ_MODE_SINGLE, NULL, PCI_ISC);
  519. return 0;
  520. out_airq:
  521. unregister_adapter_interrupt(&zpci_airq);
  522. out:
  523. return rc;
  524. }
  525. static void zpci_irq_exit(void)
  526. {
  527. airq_iv_release(zpci_aisb_iv);
  528. unregister_adapter_interrupt(&zpci_airq);
  529. }
  530. static struct resource *zpci_alloc_bus_resource(unsigned long start, unsigned long size,
  531. unsigned long flags, int domain)
  532. {
  533. struct resource *r;
  534. char *name;
  535. int rc;
  536. r = kzalloc(sizeof(*r), GFP_KERNEL);
  537. if (!r)
  538. return ERR_PTR(-ENOMEM);
  539. r->start = start;
  540. r->end = r->start + size - 1;
  541. r->flags = flags;
  542. r->parent = &iomem_resource;
  543. name = kmalloc(18, GFP_KERNEL);
  544. if (!name) {
  545. kfree(r);
  546. return ERR_PTR(-ENOMEM);
  547. }
  548. sprintf(name, "PCI Bus: %04x:%02x", domain, ZPCI_BUS_NR);
  549. r->name = name;
  550. rc = request_resource(&iomem_resource, r);
  551. if (rc)
  552. pr_debug("request resource %pR failed\n", r);
  553. return r;
  554. }
  555. static int zpci_alloc_iomap(struct zpci_dev *zdev)
  556. {
  557. int entry;
  558. spin_lock(&zpci_iomap_lock);
  559. entry = find_first_zero_bit(zpci_iomap, ZPCI_IOMAP_MAX_ENTRIES);
  560. if (entry == ZPCI_IOMAP_MAX_ENTRIES) {
  561. spin_unlock(&zpci_iomap_lock);
  562. return -ENOSPC;
  563. }
  564. set_bit(entry, zpci_iomap);
  565. spin_unlock(&zpci_iomap_lock);
  566. return entry;
  567. }
  568. static void zpci_free_iomap(struct zpci_dev *zdev, int entry)
  569. {
  570. spin_lock(&zpci_iomap_lock);
  571. memset(&zpci_iomap_start[entry], 0, sizeof(struct zpci_iomap_entry));
  572. clear_bit(entry, zpci_iomap);
  573. spin_unlock(&zpci_iomap_lock);
  574. }
  575. int pcibios_add_device(struct pci_dev *pdev)
  576. {
  577. struct zpci_dev *zdev = get_zdev(pdev);
  578. zdev->pdev = pdev;
  579. zpci_debug_init_device(zdev);
  580. zpci_fmb_enable_device(zdev);
  581. zpci_map_resources(zdev);
  582. return 0;
  583. }
  584. void pcibios_release_device(struct pci_dev *pdev)
  585. {
  586. struct zpci_dev *zdev = get_zdev(pdev);
  587. zpci_unmap_resources(zdev);
  588. zpci_fmb_disable_device(zdev);
  589. zpci_debug_exit_device(zdev);
  590. zdev->pdev = NULL;
  591. }
  592. static int zpci_scan_bus(struct zpci_dev *zdev)
  593. {
  594. struct resource *res;
  595. LIST_HEAD(resources);
  596. int i;
  597. /* allocate mapping entry for each used bar */
  598. for (i = 0; i < PCI_BAR_COUNT; i++) {
  599. unsigned long addr, size, flags;
  600. int entry;
  601. if (!zdev->bars[i].size)
  602. continue;
  603. entry = zpci_alloc_iomap(zdev);
  604. if (entry < 0)
  605. return entry;
  606. zdev->bars[i].map_idx = entry;
  607. /* only MMIO is supported */
  608. flags = IORESOURCE_MEM;
  609. if (zdev->bars[i].val & 8)
  610. flags |= IORESOURCE_PREFETCH;
  611. if (zdev->bars[i].val & 4)
  612. flags |= IORESOURCE_MEM_64;
  613. addr = ZPCI_IOMAP_ADDR_BASE + ((u64) entry << 48);
  614. size = 1UL << zdev->bars[i].size;
  615. res = zpci_alloc_bus_resource(addr, size, flags, zdev->domain);
  616. if (IS_ERR(res)) {
  617. zpci_free_iomap(zdev, entry);
  618. return PTR_ERR(res);
  619. }
  620. pci_add_resource(&resources, res);
  621. }
  622. zdev->bus = pci_scan_root_bus(NULL, ZPCI_BUS_NR, &pci_root_ops,
  623. zdev, &resources);
  624. if (!zdev->bus)
  625. return -EIO;
  626. zdev->bus->max_bus_speed = zdev->max_bus_speed;
  627. return 0;
  628. }
  629. static int zpci_alloc_domain(struct zpci_dev *zdev)
  630. {
  631. spin_lock(&zpci_domain_lock);
  632. zdev->domain = find_first_zero_bit(zpci_domain, ZPCI_NR_DEVICES);
  633. if (zdev->domain == ZPCI_NR_DEVICES) {
  634. spin_unlock(&zpci_domain_lock);
  635. return -ENOSPC;
  636. }
  637. set_bit(zdev->domain, zpci_domain);
  638. spin_unlock(&zpci_domain_lock);
  639. return 0;
  640. }
  641. static void zpci_free_domain(struct zpci_dev *zdev)
  642. {
  643. spin_lock(&zpci_domain_lock);
  644. clear_bit(zdev->domain, zpci_domain);
  645. spin_unlock(&zpci_domain_lock);
  646. }
  647. int zpci_enable_device(struct zpci_dev *zdev)
  648. {
  649. int rc;
  650. rc = clp_enable_fh(zdev, ZPCI_NR_DMA_SPACES);
  651. if (rc)
  652. goto out;
  653. pr_info("Enabled fh: 0x%x fid: 0x%x\n", zdev->fh, zdev->fid);
  654. rc = zpci_dma_init_device(zdev);
  655. if (rc)
  656. goto out_dma;
  657. return 0;
  658. out_dma:
  659. clp_disable_fh(zdev);
  660. out:
  661. return rc;
  662. }
  663. EXPORT_SYMBOL_GPL(zpci_enable_device);
  664. int zpci_disable_device(struct zpci_dev *zdev)
  665. {
  666. zpci_dma_exit_device(zdev);
  667. return clp_disable_fh(zdev);
  668. }
  669. EXPORT_SYMBOL_GPL(zpci_disable_device);
  670. int zpci_create_device(struct zpci_dev *zdev)
  671. {
  672. int rc;
  673. rc = zpci_alloc_domain(zdev);
  674. if (rc)
  675. goto out;
  676. if (zdev->state == ZPCI_FN_STATE_CONFIGURED) {
  677. rc = zpci_enable_device(zdev);
  678. if (rc)
  679. goto out_free;
  680. zdev->state = ZPCI_FN_STATE_ONLINE;
  681. }
  682. rc = zpci_scan_bus(zdev);
  683. if (rc)
  684. goto out_disable;
  685. mutex_lock(&zpci_list_lock);
  686. list_add_tail(&zdev->entry, &zpci_list);
  687. if (hotplug_ops)
  688. hotplug_ops->create_slot(zdev);
  689. mutex_unlock(&zpci_list_lock);
  690. return 0;
  691. out_disable:
  692. if (zdev->state == ZPCI_FN_STATE_ONLINE)
  693. zpci_disable_device(zdev);
  694. out_free:
  695. zpci_free_domain(zdev);
  696. out:
  697. return rc;
  698. }
  699. void zpci_stop_device(struct zpci_dev *zdev)
  700. {
  701. zpci_dma_exit_device(zdev);
  702. /*
  703. * Note: SCLP disables fh via set-pci-fn so don't
  704. * do that here.
  705. */
  706. }
  707. EXPORT_SYMBOL_GPL(zpci_stop_device);
  708. static inline int barsize(u8 size)
  709. {
  710. return (size) ? (1 << size) >> 10 : 0;
  711. }
  712. static int zpci_mem_init(void)
  713. {
  714. zdev_fmb_cache = kmem_cache_create("PCI_FMB_cache", sizeof(struct zpci_fmb),
  715. 16, 0, NULL);
  716. if (!zdev_fmb_cache)
  717. goto error_zdev;
  718. /* TODO: use realloc */
  719. zpci_iomap_start = kzalloc(ZPCI_IOMAP_MAX_ENTRIES * sizeof(*zpci_iomap_start),
  720. GFP_KERNEL);
  721. if (!zpci_iomap_start)
  722. goto error_iomap;
  723. return 0;
  724. error_iomap:
  725. kmem_cache_destroy(zdev_fmb_cache);
  726. error_zdev:
  727. return -ENOMEM;
  728. }
  729. static void zpci_mem_exit(void)
  730. {
  731. kfree(zpci_iomap_start);
  732. kmem_cache_destroy(zdev_fmb_cache);
  733. }
  734. void zpci_register_hp_ops(struct pci_hp_callback_ops *ops)
  735. {
  736. mutex_lock(&zpci_list_lock);
  737. hotplug_ops = ops;
  738. mutex_unlock(&zpci_list_lock);
  739. }
  740. EXPORT_SYMBOL_GPL(zpci_register_hp_ops);
  741. void zpci_deregister_hp_ops(void)
  742. {
  743. mutex_lock(&zpci_list_lock);
  744. hotplug_ops = NULL;
  745. mutex_unlock(&zpci_list_lock);
  746. }
  747. EXPORT_SYMBOL_GPL(zpci_deregister_hp_ops);
  748. unsigned int s390_pci_probe;
  749. EXPORT_SYMBOL_GPL(s390_pci_probe);
  750. char * __init pcibios_setup(char *str)
  751. {
  752. if (!strcmp(str, "on")) {
  753. s390_pci_probe = 1;
  754. return NULL;
  755. }
  756. return str;
  757. }
  758. static int __init pci_base_init(void)
  759. {
  760. int rc;
  761. if (!s390_pci_probe)
  762. return 0;
  763. if (!test_facility(2) || !test_facility(69)
  764. || !test_facility(71) || !test_facility(72))
  765. return 0;
  766. pr_info("Probing PCI hardware: PCI:%d SID:%d AEN:%d\n",
  767. test_facility(69), test_facility(70),
  768. test_facility(71));
  769. rc = zpci_debug_init();
  770. if (rc)
  771. goto out;
  772. rc = zpci_mem_init();
  773. if (rc)
  774. goto out_mem;
  775. rc = zpci_irq_init();
  776. if (rc)
  777. goto out_irq;
  778. rc = zpci_dma_init();
  779. if (rc)
  780. goto out_dma;
  781. rc = clp_find_pci_devices();
  782. if (rc)
  783. goto out_find;
  784. return 0;
  785. out_find:
  786. zpci_dma_exit();
  787. out_dma:
  788. zpci_irq_exit();
  789. out_irq:
  790. zpci_mem_exit();
  791. out_mem:
  792. zpci_debug_exit();
  793. out:
  794. return rc;
  795. }
  796. subsys_initcall(pci_base_init);