mach-qt2410.c 9.2 KB

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  1. /* linux/arch/arm/mach-s3c2410/mach-qt2410.c
  2. *
  3. * Copyright (C) 2006 by OpenMoko, Inc.
  4. * Author: Harald Welte <laforge@openmoko.org>
  5. * All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. *
  22. */
  23. #include <linux/kernel.h>
  24. #include <linux/types.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/list.h>
  27. #include <linux/timer.h>
  28. #include <linux/init.h>
  29. #include <linux/sysdev.h>
  30. #include <linux/platform_device.h>
  31. #include <linux/serial_core.h>
  32. #include <linux/spi/spi.h>
  33. #include <linux/spi/spi_bitbang.h>
  34. #include <linux/mtd/mtd.h>
  35. #include <linux/mtd/nand.h>
  36. #include <linux/mtd/nand_ecc.h>
  37. #include <linux/mtd/partitions.h>
  38. #include <asm/mach/arch.h>
  39. #include <asm/mach/map.h>
  40. #include <asm/mach/irq.h>
  41. #include <asm/hardware.h>
  42. #include <asm/io.h>
  43. #include <asm/irq.h>
  44. #include <asm/mach-types.h>
  45. #include <asm/arch/regs-gpio.h>
  46. #include <asm/arch/leds-gpio.h>
  47. #include <asm/plat-s3c/regs-serial.h>
  48. #include <asm/arch/fb.h>
  49. #include <asm/plat-s3c/nand.h>
  50. #include <asm/plat-s3c24xx/udc.h>
  51. #include <asm/arch/spi.h>
  52. #include <asm/arch/spi-gpio.h>
  53. #include <asm/plat-s3c24xx/common-smdk.h>
  54. #include <asm/plat-s3c24xx/devs.h>
  55. #include <asm/plat-s3c24xx/cpu.h>
  56. #include <asm/plat-s3c24xx/pm.h>
  57. static struct map_desc qt2410_iodesc[] __initdata = {
  58. { 0xe0000000, __phys_to_pfn(S3C2410_CS3+0x01000000), SZ_1M, MT_DEVICE }
  59. };
  60. #define UCON S3C2410_UCON_DEFAULT
  61. #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
  62. #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
  63. static struct s3c2410_uartcfg smdk2410_uartcfgs[] = {
  64. [0] = {
  65. .hwport = 0,
  66. .flags = 0,
  67. .ucon = UCON,
  68. .ulcon = ULCON,
  69. .ufcon = UFCON,
  70. },
  71. [1] = {
  72. .hwport = 1,
  73. .flags = 0,
  74. .ucon = UCON,
  75. .ulcon = ULCON,
  76. .ufcon = UFCON,
  77. },
  78. [2] = {
  79. .hwport = 2,
  80. .flags = 0,
  81. .ucon = UCON,
  82. .ulcon = ULCON,
  83. .ufcon = UFCON,
  84. }
  85. };
  86. /* LCD driver info */
  87. static struct s3c2410fb_display qt2410_lcd_cfg[] __initdata = {
  88. {
  89. /* Configuration for 640x480 SHARP LQ080V3DG01 */
  90. .regs = {
  91. .lcdcon1 = S3C2410_LCDCON1_TFT16BPP |
  92. S3C2410_LCDCON1_TFT |
  93. S3C2410_LCDCON1_CLKVAL(0x01), /* HCLK/4 */
  94. .lcdcon2 = S3C2410_LCDCON2_VBPD(18) | /* 19 */
  95. S3C2410_LCDCON2_LINEVAL(479) |
  96. S3C2410_LCDCON2_VFPD(10) | /* 11 */
  97. S3C2410_LCDCON2_VSPW(14), /* 15 */
  98. .lcdcon3 = S3C2410_LCDCON3_HBPD(43) | /* 44 */
  99. S3C2410_LCDCON3_HOZVAL(639) | /* 640 */
  100. S3C2410_LCDCON3_HFPD(115), /* 116 */
  101. .lcdcon4 = S3C2410_LCDCON4_MVAL(0) |
  102. S3C2410_LCDCON4_HSPW(95), /* 96 */
  103. .lcdcon5 = S3C2410_LCDCON5_FRM565 |
  104. S3C2410_LCDCON5_INVVLINE |
  105. S3C2410_LCDCON5_INVVFRAME |
  106. S3C2410_LCDCON5_PWREN |
  107. S3C2410_LCDCON5_HWSWP,
  108. },
  109. .type = S3C2410_LCDCON1_TFT,
  110. .width = 640,
  111. .height = 480,
  112. .xres = 640,
  113. .yres = 480,
  114. .bpp = 16,
  115. .left_margin = 44,
  116. .right_margin = 116,
  117. },
  118. {
  119. /* Configuration for 480x640 toppoly TD028TTEC1 */
  120. .regs = {
  121. .lcdcon1 = S3C2410_LCDCON1_TFT16BPP |
  122. S3C2410_LCDCON1_TFT |
  123. S3C2410_LCDCON1_CLKVAL(0x01), /* HCLK/4 */
  124. .lcdcon2 = S3C2410_LCDCON2_VBPD(1) | /* 2 */
  125. S3C2410_LCDCON2_LINEVAL(639) |/* 640 */
  126. S3C2410_LCDCON2_VFPD(3) | /* 4 */
  127. S3C2410_LCDCON2_VSPW(1), /* 2 */
  128. .lcdcon3 = S3C2410_LCDCON3_HBPD(7) | /* 8 */
  129. S3C2410_LCDCON3_HOZVAL(479) | /* 479 */
  130. S3C2410_LCDCON3_HFPD(23), /* 24 */
  131. .lcdcon4 = S3C2410_LCDCON4_MVAL(0) |
  132. S3C2410_LCDCON4_HSPW(7), /* 8 */
  133. .lcdcon5 = S3C2410_LCDCON5_FRM565 |
  134. S3C2410_LCDCON5_INVVLINE |
  135. S3C2410_LCDCON5_INVVFRAME |
  136. S3C2410_LCDCON5_PWREN |
  137. S3C2410_LCDCON5_HWSWP,
  138. },
  139. .type = S3C2410_LCDCON1_TFT,
  140. .width = 480,
  141. .height = 640,
  142. .xres = 480,
  143. .yres = 640,
  144. .bpp = 16,
  145. .left_margin = 8,
  146. .right_margin = 24,
  147. },
  148. {
  149. /* Config for 240x320 LCD */
  150. .regs = {
  151. .lcdcon1 = S3C2410_LCDCON1_TFT16BPP |
  152. S3C2410_LCDCON1_TFT |
  153. S3C2410_LCDCON1_CLKVAL(0x04),
  154. .lcdcon2 = S3C2410_LCDCON2_VBPD(1) |
  155. S3C2410_LCDCON2_LINEVAL(319) |
  156. S3C2410_LCDCON2_VFPD(6) |
  157. S3C2410_LCDCON2_VSPW(3),
  158. .lcdcon3 = S3C2410_LCDCON3_HBPD(12) |
  159. S3C2410_LCDCON3_HOZVAL(239) |
  160. S3C2410_LCDCON3_HFPD(7),
  161. .lcdcon4 = S3C2410_LCDCON4_MVAL(0) |
  162. S3C2410_LCDCON4_HSPW(3),
  163. .lcdcon5 = S3C2410_LCDCON5_FRM565 |
  164. S3C2410_LCDCON5_INVVLINE |
  165. S3C2410_LCDCON5_INVVFRAME |
  166. S3C2410_LCDCON5_PWREN |
  167. S3C2410_LCDCON5_HWSWP,
  168. },
  169. .type = S3C2410_LCDCON1_TFT,
  170. .width = 240,
  171. .height = 320,
  172. .xres = 240,
  173. .yres = 320,
  174. .bpp = 16,
  175. .left_margin = 13,
  176. .right_margin = 8,
  177. },
  178. };
  179. static struct s3c2410fb_mach_info qt2410_fb_info __initdata = {
  180. .displays = qt2410_lcd_cfg,
  181. .num_displays = ARRAY_SIZE(qt2410_lcd_cfg),
  182. .default_display = 0,
  183. .lpcsel = ((0xCE6) & ~7) | 1<<4,
  184. };
  185. /* CS8900 */
  186. static struct resource qt2410_cs89x0_resources[] = {
  187. [0] = {
  188. .start = 0x19000000,
  189. .end = 0x19000000 + 16,
  190. .flags = IORESOURCE_MEM,
  191. },
  192. [1] = {
  193. .start = IRQ_EINT9,
  194. .end = IRQ_EINT9,
  195. .flags = IORESOURCE_IRQ,
  196. },
  197. };
  198. static struct platform_device qt2410_cs89x0 = {
  199. .name = "cirrus-cs89x0",
  200. .num_resources = ARRAY_SIZE(qt2410_cs89x0_resources),
  201. .resource = qt2410_cs89x0_resources,
  202. };
  203. /* LED */
  204. static struct s3c24xx_led_platdata qt2410_pdata_led = {
  205. .gpio = S3C2410_GPB0,
  206. .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
  207. .name = "led",
  208. .def_trigger = "timer",
  209. };
  210. static struct platform_device qt2410_led = {
  211. .name = "s3c24xx_led",
  212. .id = 0,
  213. .dev = {
  214. .platform_data = &qt2410_pdata_led,
  215. },
  216. };
  217. /* SPI */
  218. static void spi_gpio_cs(struct s3c2410_spigpio_info *spi, int cs)
  219. {
  220. switch (cs) {
  221. case BITBANG_CS_ACTIVE:
  222. s3c2410_gpio_setpin(S3C2410_GPB5, 0);
  223. break;
  224. case BITBANG_CS_INACTIVE:
  225. s3c2410_gpio_setpin(S3C2410_GPB5, 1);
  226. break;
  227. }
  228. }
  229. static struct s3c2410_spigpio_info spi_gpio_cfg = {
  230. .pin_clk = S3C2410_GPG7,
  231. .pin_mosi = S3C2410_GPG6,
  232. .pin_miso = S3C2410_GPG5,
  233. .chip_select = &spi_gpio_cs,
  234. };
  235. static struct platform_device qt2410_spi = {
  236. .name = "s3c24xx-spi-gpio",
  237. .id = 1,
  238. .dev = {
  239. .platform_data = &spi_gpio_cfg,
  240. },
  241. };
  242. /* Board devices */
  243. static struct platform_device *qt2410_devices[] __initdata = {
  244. &s3c_device_usb,
  245. &s3c_device_lcd,
  246. &s3c_device_wdt,
  247. &s3c_device_i2c,
  248. &s3c_device_iis,
  249. &s3c_device_sdi,
  250. &s3c_device_usbgadget,
  251. &qt2410_spi,
  252. &qt2410_cs89x0,
  253. &qt2410_led,
  254. };
  255. static struct mtd_partition qt2410_nand_part[] = {
  256. [0] = {
  257. .name = "U-Boot",
  258. .size = 0x30000,
  259. .offset = 0,
  260. },
  261. [1] = {
  262. .name = "U-Boot environment",
  263. .offset = 0x30000,
  264. .size = 0x4000,
  265. },
  266. [2] = {
  267. .name = "kernel",
  268. .offset = 0x34000,
  269. .size = SZ_2M,
  270. },
  271. [3] = {
  272. .name = "initrd",
  273. .offset = 0x234000,
  274. .size = SZ_4M,
  275. },
  276. [4] = {
  277. .name = "jffs2",
  278. .offset = 0x634000,
  279. .size = 0x39cc000,
  280. },
  281. };
  282. static struct s3c2410_nand_set qt2410_nand_sets[] = {
  283. [0] = {
  284. .name = "NAND",
  285. .nr_chips = 1,
  286. .nr_partitions = ARRAY_SIZE(qt2410_nand_part),
  287. .partitions = qt2410_nand_part,
  288. },
  289. };
  290. /* choose a set of timings which should suit most 512Mbit
  291. * chips and beyond.
  292. */
  293. static struct s3c2410_platform_nand qt2410_nand_info = {
  294. .tacls = 20,
  295. .twrph0 = 60,
  296. .twrph1 = 20,
  297. .nr_sets = ARRAY_SIZE(qt2410_nand_sets),
  298. .sets = qt2410_nand_sets,
  299. };
  300. /* UDC */
  301. static struct s3c2410_udc_mach_info qt2410_udc_cfg = {
  302. };
  303. static char tft_type = 's';
  304. static int __init qt2410_tft_setup(char *str)
  305. {
  306. tft_type = str[0];
  307. return 1;
  308. }
  309. __setup("tft=", qt2410_tft_setup);
  310. static void __init qt2410_map_io(void)
  311. {
  312. s3c24xx_init_io(qt2410_iodesc, ARRAY_SIZE(qt2410_iodesc));
  313. s3c24xx_init_clocks(12*1000*1000);
  314. s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
  315. }
  316. static void __init qt2410_machine_init(void)
  317. {
  318. s3c_device_nand.dev.platform_data = &qt2410_nand_info;
  319. switch (tft_type) {
  320. case 'p': /* production */
  321. qt2410_fb_info.default_display = 1;
  322. break;
  323. case 'b': /* big */
  324. qt2410_fb_info.default_display = 0;
  325. break;
  326. case 's': /* small */
  327. default:
  328. qt2410_fb_info.default_display = 2;
  329. break;
  330. }
  331. s3c24xx_fb_set_platdata(&qt2410_fb_info);
  332. s3c2410_gpio_cfgpin(S3C2410_GPB0, S3C2410_GPIO_OUTPUT);
  333. s3c2410_gpio_setpin(S3C2410_GPB0, 1);
  334. s3c24xx_udc_set_platdata(&qt2410_udc_cfg);
  335. s3c2410_gpio_cfgpin(S3C2410_GPB5, S3C2410_GPIO_OUTPUT);
  336. platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices));
  337. s3c2410_pm_init();
  338. }
  339. MACHINE_START(QT2410, "QT2410")
  340. .phys_io = S3C2410_PA_UART,
  341. .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
  342. .boot_params = S3C2410_SDRAM_PA + 0x100,
  343. .map_io = qt2410_map_io,
  344. .init_irq = s3c24xx_init_irq,
  345. .init_machine = qt2410_machine_init,
  346. .timer = &s3c24xx_timer,
  347. MACHINE_END