hda_intel.c 36 KB

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  1. /*
  2. *
  3. * hda_intel.c - Implementation of primary alsa driver code base for Intel HD Audio.
  4. *
  5. * Copyright(c) 2004 Intel Corporation. All rights reserved.
  6. *
  7. * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
  8. * PeiSen Hou <pshou@realtek.com.tw>
  9. *
  10. * This program is free software; you can redistribute it and/or modify it
  11. * under the terms of the GNU General Public License as published by the Free
  12. * Software Foundation; either version 2 of the License, or (at your option)
  13. * any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful, but WITHOUT
  16. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  18. * more details.
  19. *
  20. * You should have received a copy of the GNU General Public License along with
  21. * this program; if not, write to the Free Software Foundation, Inc., 59
  22. * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  23. *
  24. * CONTACTS:
  25. *
  26. * Matt Jared matt.jared@intel.com
  27. * Andy Kopp andy.kopp@intel.com
  28. * Dan Kogan dan.d.kogan@intel.com
  29. *
  30. * CHANGES:
  31. *
  32. * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
  33. *
  34. */
  35. #include <sound/driver.h>
  36. #include <asm/io.h>
  37. #include <linux/delay.h>
  38. #include <linux/interrupt.h>
  39. #include <linux/module.h>
  40. #include <linux/moduleparam.h>
  41. #include <linux/init.h>
  42. #include <linux/slab.h>
  43. #include <linux/pci.h>
  44. #include <sound/core.h>
  45. #include <sound/initval.h>
  46. #include "hda_codec.h"
  47. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  48. static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  49. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  50. static char *model[SNDRV_CARDS];
  51. module_param_array(index, int, NULL, 0444);
  52. MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  53. module_param_array(id, charp, NULL, 0444);
  54. MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  55. module_param_array(enable, bool, NULL, 0444);
  56. MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  57. module_param_array(model, charp, NULL, 0444);
  58. MODULE_PARM_DESC(model, "Use the given board model.");
  59. MODULE_LICENSE("GPL");
  60. MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
  61. "{Intel, ICH6M},"
  62. "{Intel, ICH7},"
  63. "{Intel, ESB2}}");
  64. MODULE_DESCRIPTION("Intel HDA driver");
  65. #define SFX "hda-intel: "
  66. /*
  67. * registers
  68. */
  69. #define ICH6_REG_GCAP 0x00
  70. #define ICH6_REG_VMIN 0x02
  71. #define ICH6_REG_VMAJ 0x03
  72. #define ICH6_REG_OUTPAY 0x04
  73. #define ICH6_REG_INPAY 0x06
  74. #define ICH6_REG_GCTL 0x08
  75. #define ICH6_REG_WAKEEN 0x0c
  76. #define ICH6_REG_STATESTS 0x0e
  77. #define ICH6_REG_GSTS 0x10
  78. #define ICH6_REG_INTCTL 0x20
  79. #define ICH6_REG_INTSTS 0x24
  80. #define ICH6_REG_WALCLK 0x30
  81. #define ICH6_REG_SYNC 0x34
  82. #define ICH6_REG_CORBLBASE 0x40
  83. #define ICH6_REG_CORBUBASE 0x44
  84. #define ICH6_REG_CORBWP 0x48
  85. #define ICH6_REG_CORBRP 0x4A
  86. #define ICH6_REG_CORBCTL 0x4c
  87. #define ICH6_REG_CORBSTS 0x4d
  88. #define ICH6_REG_CORBSIZE 0x4e
  89. #define ICH6_REG_RIRBLBASE 0x50
  90. #define ICH6_REG_RIRBUBASE 0x54
  91. #define ICH6_REG_RIRBWP 0x58
  92. #define ICH6_REG_RINTCNT 0x5a
  93. #define ICH6_REG_RIRBCTL 0x5c
  94. #define ICH6_REG_RIRBSTS 0x5d
  95. #define ICH6_REG_RIRBSIZE 0x5e
  96. #define ICH6_REG_IC 0x60
  97. #define ICH6_REG_IR 0x64
  98. #define ICH6_REG_IRS 0x68
  99. #define ICH6_IRS_VALID (1<<1)
  100. #define ICH6_IRS_BUSY (1<<0)
  101. #define ICH6_REG_DPLBASE 0x70
  102. #define ICH6_REG_DPUBASE 0x74
  103. #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
  104. /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
  105. enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
  106. /* stream register offsets from stream base */
  107. #define ICH6_REG_SD_CTL 0x00
  108. #define ICH6_REG_SD_STS 0x03
  109. #define ICH6_REG_SD_LPIB 0x04
  110. #define ICH6_REG_SD_CBL 0x08
  111. #define ICH6_REG_SD_LVI 0x0c
  112. #define ICH6_REG_SD_FIFOW 0x0e
  113. #define ICH6_REG_SD_FIFOSIZE 0x10
  114. #define ICH6_REG_SD_FORMAT 0x12
  115. #define ICH6_REG_SD_BDLPL 0x18
  116. #define ICH6_REG_SD_BDLPU 0x1c
  117. /* PCI space */
  118. #define ICH6_PCIREG_TCSEL 0x44
  119. /*
  120. * other constants
  121. */
  122. /* max number of SDs */
  123. #define MAX_ICH6_DEV 8
  124. /* max number of fragments - we may use more if allocating more pages for BDL */
  125. #define AZX_MAX_FRAG (PAGE_SIZE / (MAX_ICH6_DEV * 16))
  126. /* max buffer size - no h/w limit, you can increase as you like */
  127. #define AZX_MAX_BUF_SIZE (1024*1024*1024)
  128. /* max number of PCM devics per card */
  129. #define AZX_MAX_PCMS 8
  130. /* RIRB int mask: overrun[2], response[0] */
  131. #define RIRB_INT_RESPONSE 0x01
  132. #define RIRB_INT_OVERRUN 0x04
  133. #define RIRB_INT_MASK 0x05
  134. /* STATESTS int mask: SD2,SD1,SD0 */
  135. #define STATESTS_INT_MASK 0x07
  136. #define AZX_MAX_CODECS 3
  137. /* SD_CTL bits */
  138. #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
  139. #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
  140. #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
  141. #define SD_CTL_STREAM_TAG_SHIFT 20
  142. /* SD_CTL and SD_STS */
  143. #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
  144. #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
  145. #define SD_INT_COMPLETE 0x04 /* completion interrupt */
  146. #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|SD_INT_COMPLETE)
  147. /* SD_STS */
  148. #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
  149. /* INTCTL and INTSTS */
  150. #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
  151. #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
  152. #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
  153. /* GCTL reset bit */
  154. #define ICH6_GCTL_RESET (1<<0)
  155. /* CORB/RIRB control, read/write pointer */
  156. #define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
  157. #define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
  158. #define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
  159. /* below are so far hardcoded - should read registers in future */
  160. #define ICH6_MAX_CORB_ENTRIES 256
  161. #define ICH6_MAX_RIRB_ENTRIES 256
  162. /*
  163. * Use CORB/RIRB for communication from/to codecs.
  164. * This is the way recommended by Intel (see below).
  165. */
  166. #define USE_CORB_RIRB
  167. /*
  168. * Define this if use the position buffer instead of reading SD_LPIB
  169. * It's not used as default since SD_LPIB seems to give more accurate position
  170. */
  171. /* #define USE_POSBUF */
  172. /*
  173. */
  174. typedef struct snd_azx azx_t;
  175. typedef struct snd_azx_rb azx_rb_t;
  176. typedef struct snd_azx_dev azx_dev_t;
  177. struct snd_azx_dev {
  178. u32 *bdl; /* virtual address of the BDL */
  179. dma_addr_t bdl_addr; /* physical address of the BDL */
  180. volatile u32 *posbuf; /* position buffer pointer */
  181. unsigned int bufsize; /* size of the play buffer in bytes */
  182. unsigned int fragsize; /* size of each period in bytes */
  183. unsigned int frags; /* number for period in the play buffer */
  184. unsigned int fifo_size; /* FIFO size */
  185. void __iomem *sd_addr; /* stream descriptor pointer */
  186. u32 sd_int_sta_mask; /* stream int status mask */
  187. /* pcm support */
  188. snd_pcm_substream_t *substream; /* assigned substream, set in PCM open */
  189. unsigned int format_val; /* format value to be set in the controller and the codec */
  190. unsigned char stream_tag; /* assigned stream */
  191. unsigned char index; /* stream index */
  192. unsigned int opened: 1;
  193. unsigned int running: 1;
  194. };
  195. /* CORB/RIRB */
  196. struct snd_azx_rb {
  197. u32 *buf; /* CORB/RIRB buffer
  198. * Each CORB entry is 4byte, RIRB is 8byte
  199. */
  200. dma_addr_t addr; /* physical address of CORB/RIRB buffer */
  201. /* for RIRB */
  202. unsigned short rp, wp; /* read/write pointers */
  203. int cmds; /* number of pending requests */
  204. u32 res; /* last read value */
  205. };
  206. struct snd_azx {
  207. snd_card_t *card;
  208. struct pci_dev *pci;
  209. /* pci resources */
  210. unsigned long addr;
  211. void __iomem *remap_addr;
  212. int irq;
  213. /* locks */
  214. spinlock_t reg_lock;
  215. struct semaphore open_mutex;
  216. /* streams */
  217. azx_dev_t azx_dev[MAX_ICH6_DEV];
  218. /* PCM */
  219. unsigned int pcm_devs;
  220. snd_pcm_t *pcm[AZX_MAX_PCMS];
  221. /* HD codec */
  222. unsigned short codec_mask;
  223. struct hda_bus *bus;
  224. /* CORB/RIRB */
  225. azx_rb_t corb;
  226. azx_rb_t rirb;
  227. /* BDL, CORB/RIRB and position buffers */
  228. struct snd_dma_buffer bdl;
  229. struct snd_dma_buffer rb;
  230. struct snd_dma_buffer posbuf;
  231. };
  232. /*
  233. * macros for easy use
  234. */
  235. #define azx_writel(chip,reg,value) \
  236. writel(value, (chip)->remap_addr + ICH6_REG_##reg)
  237. #define azx_readl(chip,reg) \
  238. readl((chip)->remap_addr + ICH6_REG_##reg)
  239. #define azx_writew(chip,reg,value) \
  240. writew(value, (chip)->remap_addr + ICH6_REG_##reg)
  241. #define azx_readw(chip,reg) \
  242. readw((chip)->remap_addr + ICH6_REG_##reg)
  243. #define azx_writeb(chip,reg,value) \
  244. writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
  245. #define azx_readb(chip,reg) \
  246. readb((chip)->remap_addr + ICH6_REG_##reg)
  247. #define azx_sd_writel(dev,reg,value) \
  248. writel(value, (dev)->sd_addr + ICH6_REG_##reg)
  249. #define azx_sd_readl(dev,reg) \
  250. readl((dev)->sd_addr + ICH6_REG_##reg)
  251. #define azx_sd_writew(dev,reg,value) \
  252. writew(value, (dev)->sd_addr + ICH6_REG_##reg)
  253. #define azx_sd_readw(dev,reg) \
  254. readw((dev)->sd_addr + ICH6_REG_##reg)
  255. #define azx_sd_writeb(dev,reg,value) \
  256. writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
  257. #define azx_sd_readb(dev,reg) \
  258. readb((dev)->sd_addr + ICH6_REG_##reg)
  259. /* for pcm support */
  260. #define get_azx_dev(substream) (azx_dev_t*)(substream->runtime->private_data)
  261. /* Get the upper 32bit of the given dma_addr_t
  262. * Compiler should optimize and eliminate the code if dma_addr_t is 32bit
  263. */
  264. #define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0)
  265. /*
  266. * Interface for HD codec
  267. */
  268. #ifdef USE_CORB_RIRB
  269. /*
  270. * CORB / RIRB interface
  271. */
  272. static int azx_alloc_cmd_io(azx_t *chip)
  273. {
  274. int err;
  275. /* single page (at least 4096 bytes) must suffice for both ringbuffes */
  276. err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
  277. PAGE_SIZE, &chip->rb);
  278. if (err < 0) {
  279. snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
  280. return err;
  281. }
  282. return 0;
  283. }
  284. static void azx_init_cmd_io(azx_t *chip)
  285. {
  286. /* CORB set up */
  287. chip->corb.addr = chip->rb.addr;
  288. chip->corb.buf = (u32 *)chip->rb.area;
  289. azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
  290. azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr));
  291. /* set the corb write pointer to 0 */
  292. azx_writew(chip, CORBWP, 0);
  293. /* reset the corb hw read pointer */
  294. azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
  295. /* enable corb dma */
  296. azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
  297. /* RIRB set up */
  298. chip->rirb.addr = chip->rb.addr + 2048;
  299. chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
  300. azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
  301. azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr));
  302. /* reset the rirb hw write pointer */
  303. azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
  304. /* set N=1, get RIRB response interrupt for new entry */
  305. azx_writew(chip, RINTCNT, 1);
  306. /* enable rirb dma and response irq */
  307. #ifdef USE_CORB_RIRB
  308. azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
  309. #else
  310. azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN);
  311. #endif
  312. chip->rirb.rp = chip->rirb.cmds = 0;
  313. }
  314. static void azx_free_cmd_io(azx_t *chip)
  315. {
  316. /* disable ringbuffer DMAs */
  317. azx_writeb(chip, RIRBCTL, 0);
  318. azx_writeb(chip, CORBCTL, 0);
  319. }
  320. /* send a command */
  321. static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid, int direct,
  322. unsigned int verb, unsigned int para)
  323. {
  324. azx_t *chip = codec->bus->private_data;
  325. unsigned int wp;
  326. u32 val;
  327. val = (u32)(codec->addr & 0x0f) << 28;
  328. val |= (u32)direct << 27;
  329. val |= (u32)nid << 20;
  330. val |= verb << 8;
  331. val |= para;
  332. /* add command to corb */
  333. wp = azx_readb(chip, CORBWP);
  334. wp++;
  335. wp %= ICH6_MAX_CORB_ENTRIES;
  336. spin_lock_irq(&chip->reg_lock);
  337. chip->rirb.cmds++;
  338. chip->corb.buf[wp] = cpu_to_le32(val);
  339. azx_writel(chip, CORBWP, wp);
  340. spin_unlock_irq(&chip->reg_lock);
  341. return 0;
  342. }
  343. #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
  344. /* retrieve RIRB entry - called from interrupt handler */
  345. static void azx_update_rirb(azx_t *chip)
  346. {
  347. unsigned int rp, wp;
  348. u32 res, res_ex;
  349. wp = azx_readb(chip, RIRBWP);
  350. if (wp == chip->rirb.wp)
  351. return;
  352. chip->rirb.wp = wp;
  353. while (chip->rirb.rp != wp) {
  354. chip->rirb.rp++;
  355. chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
  356. rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
  357. res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
  358. res = le32_to_cpu(chip->rirb.buf[rp]);
  359. if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
  360. snd_hda_queue_unsol_event(chip->bus, res, res_ex);
  361. else if (chip->rirb.cmds) {
  362. chip->rirb.cmds--;
  363. chip->rirb.res = res;
  364. }
  365. }
  366. }
  367. /* receive a response */
  368. static unsigned int azx_get_response(struct hda_codec *codec)
  369. {
  370. azx_t *chip = codec->bus->private_data;
  371. int timeout = 50;
  372. while (chip->rirb.cmds) {
  373. if (! --timeout) {
  374. snd_printk(KERN_ERR "azx_get_response timeout\n");
  375. chip->rirb.rp = azx_readb(chip, RIRBWP);
  376. chip->rirb.cmds = 0;
  377. return -1;
  378. }
  379. msleep(1);
  380. }
  381. return chip->rirb.res; /* the last value */
  382. }
  383. #else
  384. /*
  385. * Use the single immediate command instead of CORB/RIRB for simplicity
  386. *
  387. * Note: according to Intel, this is not preferred use. The command was
  388. * intended for the BIOS only, and may get confused with unsolicited
  389. * responses. So, we shouldn't use it for normal operation from the
  390. * driver.
  391. * I left the codes, however, for debugging/testing purposes.
  392. */
  393. #define azx_alloc_cmd_io(chip) 0
  394. #define azx_init_cmd_io(chip)
  395. #define azx_free_cmd_io(chip)
  396. /* send a command */
  397. static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid, int direct,
  398. unsigned int verb, unsigned int para)
  399. {
  400. azx_t *chip = codec->bus->private_data;
  401. u32 val;
  402. int timeout = 50;
  403. val = (u32)(codec->addr & 0x0f) << 28;
  404. val |= (u32)direct << 27;
  405. val |= (u32)nid << 20;
  406. val |= verb << 8;
  407. val |= para;
  408. while (timeout--) {
  409. /* check ICB busy bit */
  410. if (! (azx_readw(chip, IRS) & ICH6_IRS_BUSY)) {
  411. /* Clear IRV valid bit */
  412. azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_VALID);
  413. azx_writel(chip, IC, val);
  414. azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_BUSY);
  415. return 0;
  416. }
  417. udelay(1);
  418. }
  419. snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n", azx_readw(chip, IRS), val);
  420. return -EIO;
  421. }
  422. /* receive a response */
  423. static unsigned int azx_get_response(struct hda_codec *codec)
  424. {
  425. azx_t *chip = codec->bus->private_data;
  426. int timeout = 50;
  427. while (timeout--) {
  428. /* check IRV busy bit */
  429. if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
  430. return azx_readl(chip, IR);
  431. udelay(1);
  432. }
  433. snd_printd(SFX "get_response timeout: IRS=0x%x\n", azx_readw(chip, IRS));
  434. return (unsigned int)-1;
  435. }
  436. #define azx_update_rirb(chip)
  437. #endif /* USE_CORB_RIRB */
  438. /* reset codec link */
  439. static int azx_reset(azx_t *chip)
  440. {
  441. int count;
  442. /* reset controller */
  443. azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
  444. count = 50;
  445. while (azx_readb(chip, GCTL) && --count)
  446. msleep(1);
  447. /* delay for >= 100us for codec PLL to settle per spec
  448. * Rev 0.9 section 5.5.1
  449. */
  450. msleep(1);
  451. /* Bring controller out of reset */
  452. azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
  453. count = 50;
  454. while (! azx_readb(chip, GCTL) && --count)
  455. msleep(1);
  456. /* Brent Chartrand said to wait >= 540us for codecs to intialize */
  457. msleep(1);
  458. /* check to see if controller is ready */
  459. if (! azx_readb(chip, GCTL)) {
  460. snd_printd("azx_reset: controller not ready!\n");
  461. return -EBUSY;
  462. }
  463. /* detect codecs */
  464. if (! chip->codec_mask) {
  465. chip->codec_mask = azx_readw(chip, STATESTS);
  466. snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
  467. }
  468. return 0;
  469. }
  470. /*
  471. * Lowlevel interface
  472. */
  473. /* enable interrupts */
  474. static void azx_int_enable(azx_t *chip)
  475. {
  476. /* enable controller CIE and GIE */
  477. azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
  478. ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
  479. }
  480. /* disable interrupts */
  481. static void azx_int_disable(azx_t *chip)
  482. {
  483. int i;
  484. /* disable interrupts in stream descriptor */
  485. for (i = 0; i < MAX_ICH6_DEV; i++) {
  486. azx_dev_t *azx_dev = &chip->azx_dev[i];
  487. azx_sd_writeb(azx_dev, SD_CTL,
  488. azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
  489. }
  490. /* disable SIE for all streams */
  491. azx_writeb(chip, INTCTL, 0);
  492. /* disable controller CIE and GIE */
  493. azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
  494. ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
  495. }
  496. /* clear interrupts */
  497. static void azx_int_clear(azx_t *chip)
  498. {
  499. int i;
  500. /* clear stream status */
  501. for (i = 0; i < MAX_ICH6_DEV; i++) {
  502. azx_dev_t *azx_dev = &chip->azx_dev[i];
  503. azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
  504. }
  505. /* clear STATESTS */
  506. azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
  507. /* clear rirb status */
  508. azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
  509. /* clear int status */
  510. azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
  511. }
  512. /* start a stream */
  513. static void azx_stream_start(azx_t *chip, azx_dev_t *azx_dev)
  514. {
  515. /* enable SIE */
  516. azx_writeb(chip, INTCTL,
  517. azx_readb(chip, INTCTL) | (1 << azx_dev->index));
  518. /* set DMA start and interrupt mask */
  519. azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
  520. SD_CTL_DMA_START | SD_INT_MASK);
  521. }
  522. /* stop a stream */
  523. static void azx_stream_stop(azx_t *chip, azx_dev_t *azx_dev)
  524. {
  525. /* stop DMA */
  526. azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
  527. ~(SD_CTL_DMA_START | SD_INT_MASK));
  528. azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
  529. /* disable SIE */
  530. azx_writeb(chip, INTCTL,
  531. azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
  532. }
  533. /*
  534. * initialize the chip
  535. */
  536. static void azx_init_chip(azx_t *chip)
  537. {
  538. unsigned char tcsel_reg;
  539. /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
  540. * TCSEL == Traffic Class Select Register, which sets PCI express QOS
  541. * Ensuring these bits are 0 clears playback static on some HD Audio codecs
  542. */
  543. pci_read_config_byte (chip->pci, ICH6_PCIREG_TCSEL, &tcsel_reg);
  544. pci_write_config_byte(chip->pci, ICH6_PCIREG_TCSEL, tcsel_reg & 0xf8);
  545. /* reset controller */
  546. azx_reset(chip);
  547. /* initialize interrupts */
  548. azx_int_clear(chip);
  549. azx_int_enable(chip);
  550. /* initialize the codec command I/O */
  551. azx_init_cmd_io(chip);
  552. #ifdef USE_POSBUF
  553. /* program the position buffer */
  554. azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
  555. azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr));
  556. #endif
  557. }
  558. /*
  559. * interrupt handler
  560. */
  561. static irqreturn_t azx_interrupt(int irq, void* dev_id, struct pt_regs *regs)
  562. {
  563. azx_t *chip = dev_id;
  564. azx_dev_t *azx_dev;
  565. u32 status;
  566. int i;
  567. spin_lock(&chip->reg_lock);
  568. status = azx_readl(chip, INTSTS);
  569. if (status == 0) {
  570. spin_unlock(&chip->reg_lock);
  571. return IRQ_NONE;
  572. }
  573. for (i = 0; i < MAX_ICH6_DEV; i++) {
  574. azx_dev = &chip->azx_dev[i];
  575. if (status & azx_dev->sd_int_sta_mask) {
  576. azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
  577. if (azx_dev->substream && azx_dev->running) {
  578. spin_unlock(&chip->reg_lock);
  579. snd_pcm_period_elapsed(azx_dev->substream);
  580. spin_lock(&chip->reg_lock);
  581. }
  582. }
  583. }
  584. /* clear rirb int */
  585. status = azx_readb(chip, RIRBSTS);
  586. if (status & RIRB_INT_MASK) {
  587. if (status & RIRB_INT_RESPONSE)
  588. azx_update_rirb(chip);
  589. azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
  590. }
  591. #if 0
  592. /* clear state status int */
  593. if (azx_readb(chip, STATESTS) & 0x04)
  594. azx_writeb(chip, STATESTS, 0x04);
  595. #endif
  596. spin_unlock(&chip->reg_lock);
  597. return IRQ_HANDLED;
  598. }
  599. /*
  600. * set up BDL entries
  601. */
  602. static void azx_setup_periods(azx_dev_t *azx_dev)
  603. {
  604. u32 *bdl = azx_dev->bdl;
  605. dma_addr_t dma_addr = azx_dev->substream->runtime->dma_addr;
  606. int idx;
  607. /* reset BDL address */
  608. azx_sd_writel(azx_dev, SD_BDLPL, 0);
  609. azx_sd_writel(azx_dev, SD_BDLPU, 0);
  610. /* program the initial BDL entries */
  611. for (idx = 0; idx < azx_dev->frags; idx++) {
  612. unsigned int off = idx << 2; /* 4 dword step */
  613. dma_addr_t addr = dma_addr + idx * azx_dev->fragsize;
  614. /* program the address field of the BDL entry */
  615. bdl[off] = cpu_to_le32((u32)addr);
  616. bdl[off+1] = cpu_to_le32(upper_32bit(addr));
  617. /* program the size field of the BDL entry */
  618. bdl[off+2] = cpu_to_le32(azx_dev->fragsize);
  619. /* program the IOC to enable interrupt when buffer completes */
  620. bdl[off+3] = cpu_to_le32(0x01);
  621. }
  622. }
  623. /*
  624. * set up the SD for streaming
  625. */
  626. static int azx_setup_controller(azx_t *chip, azx_dev_t *azx_dev)
  627. {
  628. unsigned char val;
  629. int timeout;
  630. /* make sure the run bit is zero for SD */
  631. azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & ~SD_CTL_DMA_START);
  632. /* reset stream */
  633. azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | SD_CTL_STREAM_RESET);
  634. udelay(3);
  635. timeout = 300;
  636. while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
  637. --timeout)
  638. ;
  639. val &= ~SD_CTL_STREAM_RESET;
  640. azx_sd_writeb(azx_dev, SD_CTL, val);
  641. udelay(3);
  642. timeout = 300;
  643. /* waiting for hardware to report that the stream is out of reset */
  644. while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
  645. --timeout)
  646. ;
  647. /* program the stream_tag */
  648. azx_sd_writel(azx_dev, SD_CTL,
  649. (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK) |
  650. (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
  651. /* program the length of samples in cyclic buffer */
  652. azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
  653. /* program the stream format */
  654. /* this value needs to be the same as the one programmed */
  655. azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
  656. /* program the stream LVI (last valid index) of the BDL */
  657. azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
  658. /* program the BDL address */
  659. /* lower BDL address */
  660. azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl_addr);
  661. /* upper BDL address */
  662. azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl_addr));
  663. #ifdef USE_POSBUF
  664. /* enable the position buffer */
  665. if (! (azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
  666. azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
  667. #endif
  668. /* set the interrupt enable bits in the descriptor control register */
  669. azx_sd_writel(azx_dev, SD_CTL, azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
  670. return 0;
  671. }
  672. /*
  673. * Codec initialization
  674. */
  675. static int __devinit azx_codec_create(azx_t *chip, const char *model)
  676. {
  677. struct hda_bus_template bus_temp;
  678. int c, codecs, err;
  679. memset(&bus_temp, 0, sizeof(bus_temp));
  680. bus_temp.private_data = chip;
  681. bus_temp.modelname = model;
  682. bus_temp.pci = chip->pci;
  683. bus_temp.ops.command = azx_send_cmd;
  684. bus_temp.ops.get_response = azx_get_response;
  685. if ((err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus)) < 0)
  686. return err;
  687. codecs = 0;
  688. for (c = 0; c < AZX_MAX_CODECS; c++) {
  689. if (chip->codec_mask & (1 << c)) {
  690. err = snd_hda_codec_new(chip->bus, c, NULL);
  691. if (err < 0)
  692. continue;
  693. codecs++;
  694. }
  695. }
  696. if (! codecs) {
  697. snd_printk(KERN_ERR SFX "no codecs initialized\n");
  698. return -ENXIO;
  699. }
  700. return 0;
  701. }
  702. /*
  703. * PCM support
  704. */
  705. /* assign a stream for the PCM */
  706. static inline azx_dev_t *azx_assign_device(azx_t *chip, int stream)
  707. {
  708. int dev, i;
  709. dev = stream == SNDRV_PCM_STREAM_PLAYBACK ? 4 : 0;
  710. for (i = 0; i < 4; i++, dev++)
  711. if (! chip->azx_dev[dev].opened) {
  712. chip->azx_dev[dev].opened = 1;
  713. return &chip->azx_dev[dev];
  714. }
  715. return NULL;
  716. }
  717. /* release the assigned stream */
  718. static inline void azx_release_device(azx_dev_t *azx_dev)
  719. {
  720. azx_dev->opened = 0;
  721. }
  722. static snd_pcm_hardware_t azx_pcm_hw = {
  723. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  724. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  725. SNDRV_PCM_INFO_MMAP_VALID |
  726. SNDRV_PCM_INFO_PAUSE |
  727. SNDRV_PCM_INFO_RESUME),
  728. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  729. .rates = SNDRV_PCM_RATE_48000,
  730. .rate_min = 48000,
  731. .rate_max = 48000,
  732. .channels_min = 2,
  733. .channels_max = 2,
  734. .buffer_bytes_max = AZX_MAX_BUF_SIZE,
  735. .period_bytes_min = 128,
  736. .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
  737. .periods_min = 2,
  738. .periods_max = AZX_MAX_FRAG,
  739. .fifo_size = 0,
  740. };
  741. struct azx_pcm {
  742. azx_t *chip;
  743. struct hda_codec *codec;
  744. struct hda_pcm_stream *hinfo[2];
  745. };
  746. static int azx_pcm_open(snd_pcm_substream_t *substream)
  747. {
  748. struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
  749. struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
  750. azx_t *chip = apcm->chip;
  751. azx_dev_t *azx_dev;
  752. snd_pcm_runtime_t *runtime = substream->runtime;
  753. unsigned long flags;
  754. int err;
  755. down(&chip->open_mutex);
  756. azx_dev = azx_assign_device(chip, substream->stream);
  757. if (azx_dev == NULL) {
  758. up(&chip->open_mutex);
  759. return -EBUSY;
  760. }
  761. runtime->hw = azx_pcm_hw;
  762. runtime->hw.channels_min = hinfo->channels_min;
  763. runtime->hw.channels_max = hinfo->channels_max;
  764. runtime->hw.formats = hinfo->formats;
  765. runtime->hw.rates = hinfo->rates;
  766. snd_pcm_limit_hw_rates(runtime);
  767. snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
  768. if ((err = hinfo->ops.open(hinfo, apcm->codec, substream)) < 0) {
  769. azx_release_device(azx_dev);
  770. up(&chip->open_mutex);
  771. return err;
  772. }
  773. spin_lock_irqsave(&chip->reg_lock, flags);
  774. azx_dev->substream = substream;
  775. azx_dev->running = 0;
  776. spin_unlock_irqrestore(&chip->reg_lock, flags);
  777. runtime->private_data = azx_dev;
  778. up(&chip->open_mutex);
  779. return 0;
  780. }
  781. static int azx_pcm_close(snd_pcm_substream_t *substream)
  782. {
  783. struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
  784. struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
  785. azx_t *chip = apcm->chip;
  786. azx_dev_t *azx_dev = get_azx_dev(substream);
  787. unsigned long flags;
  788. down(&chip->open_mutex);
  789. spin_lock_irqsave(&chip->reg_lock, flags);
  790. azx_dev->substream = NULL;
  791. azx_dev->running = 0;
  792. spin_unlock_irqrestore(&chip->reg_lock, flags);
  793. azx_release_device(azx_dev);
  794. hinfo->ops.close(hinfo, apcm->codec, substream);
  795. up(&chip->open_mutex);
  796. return 0;
  797. }
  798. static int azx_pcm_hw_params(snd_pcm_substream_t *substream, snd_pcm_hw_params_t *hw_params)
  799. {
  800. return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  801. }
  802. static int azx_pcm_hw_free(snd_pcm_substream_t *substream)
  803. {
  804. struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
  805. azx_dev_t *azx_dev = get_azx_dev(substream);
  806. struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
  807. /* reset BDL address */
  808. azx_sd_writel(azx_dev, SD_BDLPL, 0);
  809. azx_sd_writel(azx_dev, SD_BDLPU, 0);
  810. azx_sd_writel(azx_dev, SD_CTL, 0);
  811. hinfo->ops.cleanup(hinfo, apcm->codec, substream);
  812. return snd_pcm_lib_free_pages(substream);
  813. }
  814. static int azx_pcm_prepare(snd_pcm_substream_t *substream)
  815. {
  816. struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
  817. azx_t *chip = apcm->chip;
  818. azx_dev_t *azx_dev = get_azx_dev(substream);
  819. struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
  820. snd_pcm_runtime_t *runtime = substream->runtime;
  821. azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
  822. azx_dev->fragsize = snd_pcm_lib_period_bytes(substream);
  823. azx_dev->frags = azx_dev->bufsize / azx_dev->fragsize;
  824. azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
  825. runtime->channels,
  826. runtime->format,
  827. hinfo->maxbps);
  828. if (! azx_dev->format_val) {
  829. snd_printk(KERN_ERR SFX "invalid format_val, rate=%d, ch=%d, format=%d\n",
  830. runtime->rate, runtime->channels, runtime->format);
  831. return -EINVAL;
  832. }
  833. snd_printdd("azx_pcm_prepare: bufsize=0x%x, fragsize=0x%x, format=0x%x\n",
  834. azx_dev->bufsize, azx_dev->fragsize, azx_dev->format_val);
  835. azx_setup_periods(azx_dev);
  836. azx_setup_controller(chip, azx_dev);
  837. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  838. azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
  839. else
  840. azx_dev->fifo_size = 0;
  841. return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
  842. azx_dev->format_val, substream);
  843. }
  844. static int azx_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
  845. {
  846. struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
  847. azx_dev_t *azx_dev = get_azx_dev(substream);
  848. azx_t *chip = apcm->chip;
  849. int err = 0;
  850. spin_lock(&chip->reg_lock);
  851. switch (cmd) {
  852. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  853. case SNDRV_PCM_TRIGGER_RESUME:
  854. case SNDRV_PCM_TRIGGER_START:
  855. azx_stream_start(chip, azx_dev);
  856. azx_dev->running = 1;
  857. break;
  858. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  859. case SNDRV_PCM_TRIGGER_STOP:
  860. azx_stream_stop(chip, azx_dev);
  861. azx_dev->running = 0;
  862. break;
  863. default:
  864. err = -EINVAL;
  865. }
  866. spin_unlock(&chip->reg_lock);
  867. if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH ||
  868. cmd == SNDRV_PCM_TRIGGER_STOP) {
  869. int timeout = 5000;
  870. while (azx_sd_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START && --timeout)
  871. ;
  872. }
  873. return err;
  874. }
  875. static snd_pcm_uframes_t azx_pcm_pointer(snd_pcm_substream_t *substream)
  876. {
  877. azx_dev_t *azx_dev = get_azx_dev(substream);
  878. unsigned int pos;
  879. #ifdef USE_POSBUF
  880. /* use the position buffer */
  881. pos = *azx_dev->posbuf;
  882. #else
  883. /* read LPIB */
  884. pos = azx_sd_readl(azx_dev, SD_LPIB) + azx_dev->fifo_size;
  885. #endif
  886. if (pos >= azx_dev->bufsize)
  887. pos = 0;
  888. return bytes_to_frames(substream->runtime, pos);
  889. }
  890. static snd_pcm_ops_t azx_pcm_ops = {
  891. .open = azx_pcm_open,
  892. .close = azx_pcm_close,
  893. .ioctl = snd_pcm_lib_ioctl,
  894. .hw_params = azx_pcm_hw_params,
  895. .hw_free = azx_pcm_hw_free,
  896. .prepare = azx_pcm_prepare,
  897. .trigger = azx_pcm_trigger,
  898. .pointer = azx_pcm_pointer,
  899. };
  900. static void azx_pcm_free(snd_pcm_t *pcm)
  901. {
  902. kfree(pcm->private_data);
  903. }
  904. static int __devinit create_codec_pcm(azx_t *chip, struct hda_codec *codec,
  905. struct hda_pcm *cpcm, int pcm_dev)
  906. {
  907. int err;
  908. snd_pcm_t *pcm;
  909. struct azx_pcm *apcm;
  910. snd_assert(cpcm->stream[0].substreams || cpcm->stream[1].substreams, return -EINVAL);
  911. snd_assert(cpcm->name, return -EINVAL);
  912. err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
  913. cpcm->stream[0].substreams, cpcm->stream[1].substreams,
  914. &pcm);
  915. if (err < 0)
  916. return err;
  917. strcpy(pcm->name, cpcm->name);
  918. apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
  919. if (apcm == NULL)
  920. return -ENOMEM;
  921. apcm->chip = chip;
  922. apcm->codec = codec;
  923. apcm->hinfo[0] = &cpcm->stream[0];
  924. apcm->hinfo[1] = &cpcm->stream[1];
  925. pcm->private_data = apcm;
  926. pcm->private_free = azx_pcm_free;
  927. if (cpcm->stream[0].substreams)
  928. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
  929. if (cpcm->stream[1].substreams)
  930. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
  931. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  932. snd_dma_pci_data(chip->pci),
  933. 1024 * 64, 1024 * 128);
  934. chip->pcm[pcm_dev] = pcm;
  935. return 0;
  936. }
  937. static int __devinit azx_pcm_create(azx_t *chip)
  938. {
  939. struct list_head *p;
  940. struct hda_codec *codec;
  941. int c, err;
  942. int pcm_dev;
  943. if ((err = snd_hda_build_pcms(chip->bus)) < 0)
  944. return err;
  945. pcm_dev = 0;
  946. list_for_each(p, &chip->bus->codec_list) {
  947. codec = list_entry(p, struct hda_codec, list);
  948. for (c = 0; c < codec->num_pcms; c++) {
  949. if (pcm_dev >= AZX_MAX_PCMS) {
  950. snd_printk(KERN_ERR SFX "Too many PCMs\n");
  951. return -EINVAL;
  952. }
  953. err = create_codec_pcm(chip, codec, &codec->pcm_info[c], pcm_dev);
  954. if (err < 0)
  955. return err;
  956. pcm_dev++;
  957. }
  958. }
  959. return 0;
  960. }
  961. /*
  962. * mixer creation - all stuff is implemented in hda module
  963. */
  964. static int __devinit azx_mixer_create(azx_t *chip)
  965. {
  966. return snd_hda_build_controls(chip->bus);
  967. }
  968. /*
  969. * initialize SD streams
  970. */
  971. static int __devinit azx_init_stream(azx_t *chip)
  972. {
  973. int i;
  974. /* initialize each stream (aka device)
  975. * assign the starting bdl address to each stream (device) and initialize
  976. */
  977. for (i = 0; i < MAX_ICH6_DEV; i++) {
  978. unsigned int off = sizeof(u32) * (i * AZX_MAX_FRAG * 4);
  979. azx_dev_t *azx_dev = &chip->azx_dev[i];
  980. azx_dev->bdl = (u32 *)(chip->bdl.area + off);
  981. azx_dev->bdl_addr = chip->bdl.addr + off;
  982. #ifdef USE_POSBUF
  983. azx_dev->posbuf = (volatile u32 *)(chip->posbuf.area + i * 8);
  984. #endif
  985. /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
  986. azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
  987. /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
  988. azx_dev->sd_int_sta_mask = 1 << i;
  989. /* stream tag: must be non-zero and unique */
  990. azx_dev->index = i;
  991. azx_dev->stream_tag = i + 1;
  992. }
  993. return 0;
  994. }
  995. #ifdef CONFIG_PM
  996. /*
  997. * power management
  998. */
  999. static int azx_suspend(snd_card_t *card, pm_message_t state)
  1000. {
  1001. azx_t *chip = card->pm_private_data;
  1002. int i;
  1003. for (i = 0; i < chip->pcm_devs; i++)
  1004. if (chip->pcm[i])
  1005. snd_pcm_suspend_all(chip->pcm[i]);
  1006. snd_hda_suspend(chip->bus, state);
  1007. azx_free_cmd_io(chip);
  1008. pci_disable_device(chip->pci);
  1009. return 0;
  1010. }
  1011. static int azx_resume(snd_card_t *card)
  1012. {
  1013. azx_t *chip = card->pm_private_data;
  1014. pci_enable_device(chip->pci);
  1015. pci_set_master(chip->pci);
  1016. azx_init_chip(chip);
  1017. snd_hda_resume(chip->bus);
  1018. return 0;
  1019. }
  1020. #endif /* CONFIG_PM */
  1021. /*
  1022. * destructor
  1023. */
  1024. static int azx_free(azx_t *chip)
  1025. {
  1026. if (chip->remap_addr) {
  1027. int i;
  1028. for (i = 0; i < MAX_ICH6_DEV; i++)
  1029. azx_stream_stop(chip, &chip->azx_dev[i]);
  1030. /* disable interrupts */
  1031. azx_int_disable(chip);
  1032. azx_int_clear(chip);
  1033. /* disable CORB/RIRB */
  1034. azx_free_cmd_io(chip);
  1035. /* disable position buffer */
  1036. azx_writel(chip, DPLBASE, 0);
  1037. azx_writel(chip, DPUBASE, 0);
  1038. /* wait a little for interrupts to finish */
  1039. msleep(1);
  1040. iounmap(chip->remap_addr);
  1041. }
  1042. if (chip->irq >= 0)
  1043. free_irq(chip->irq, (void*)chip);
  1044. if (chip->bdl.area)
  1045. snd_dma_free_pages(&chip->bdl);
  1046. if (chip->rb.area)
  1047. snd_dma_free_pages(&chip->rb);
  1048. #ifdef USE_POSBUF
  1049. if (chip->posbuf.area)
  1050. snd_dma_free_pages(&chip->posbuf);
  1051. #endif
  1052. pci_release_regions(chip->pci);
  1053. pci_disable_device(chip->pci);
  1054. kfree(chip);
  1055. return 0;
  1056. }
  1057. static int azx_dev_free(snd_device_t *device)
  1058. {
  1059. return azx_free(device->device_data);
  1060. }
  1061. /*
  1062. * constructor
  1063. */
  1064. static int __devinit azx_create(snd_card_t *card, struct pci_dev *pci, azx_t **rchip)
  1065. {
  1066. azx_t *chip;
  1067. int err = 0;
  1068. static snd_device_ops_t ops = {
  1069. .dev_free = azx_dev_free,
  1070. };
  1071. *rchip = NULL;
  1072. if ((err = pci_enable_device(pci)) < 0)
  1073. return err;
  1074. chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
  1075. if (NULL == chip) {
  1076. snd_printk(KERN_ERR SFX "cannot allocate chip\n");
  1077. pci_disable_device(pci);
  1078. return -ENOMEM;
  1079. }
  1080. spin_lock_init(&chip->reg_lock);
  1081. init_MUTEX(&chip->open_mutex);
  1082. chip->card = card;
  1083. chip->pci = pci;
  1084. chip->irq = -1;
  1085. if ((err = pci_request_regions(pci, "ICH HD audio")) < 0) {
  1086. kfree(chip);
  1087. pci_disable_device(pci);
  1088. return err;
  1089. }
  1090. chip->addr = pci_resource_start(pci,0);
  1091. chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
  1092. if (chip->remap_addr == NULL) {
  1093. snd_printk(KERN_ERR SFX "ioremap error\n");
  1094. err = -ENXIO;
  1095. goto errout;
  1096. }
  1097. if (request_irq(pci->irq, azx_interrupt, SA_INTERRUPT|SA_SHIRQ,
  1098. "HDA Intel", (void*)chip)) {
  1099. snd_printk(KERN_ERR SFX "unable to grab IRQ %d\n", pci->irq);
  1100. err = -EBUSY;
  1101. goto errout;
  1102. }
  1103. chip->irq = pci->irq;
  1104. pci_set_master(pci);
  1105. synchronize_irq(chip->irq);
  1106. /* allocate memory for the BDL for each stream */
  1107. if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
  1108. PAGE_SIZE, &chip->bdl)) < 0) {
  1109. snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
  1110. goto errout;
  1111. }
  1112. #ifdef USE_POSBUF
  1113. /* allocate memory for the position buffer */
  1114. if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
  1115. MAX_ICH6_DEV * 8, &chip->posbuf)) < 0) {
  1116. snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
  1117. goto errout;
  1118. }
  1119. #endif
  1120. /* allocate CORB/RIRB */
  1121. if ((err = azx_alloc_cmd_io(chip)) < 0)
  1122. goto errout;
  1123. /* initialize streams */
  1124. azx_init_stream(chip);
  1125. /* initialize chip */
  1126. azx_init_chip(chip);
  1127. /* codec detection */
  1128. if (! chip->codec_mask) {
  1129. snd_printk(KERN_ERR SFX "no codecs found!\n");
  1130. err = -ENODEV;
  1131. goto errout;
  1132. }
  1133. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) <0) {
  1134. snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
  1135. goto errout;
  1136. }
  1137. *rchip = chip;
  1138. return 0;
  1139. errout:
  1140. azx_free(chip);
  1141. return err;
  1142. }
  1143. static int __devinit azx_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
  1144. {
  1145. static int dev;
  1146. snd_card_t *card;
  1147. azx_t *chip;
  1148. int err = 0;
  1149. if (dev >= SNDRV_CARDS)
  1150. return -ENODEV;
  1151. if (! enable[dev]) {
  1152. dev++;
  1153. return -ENOENT;
  1154. }
  1155. card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
  1156. if (NULL == card) {
  1157. snd_printk(KERN_ERR SFX "Error creating card!\n");
  1158. return -ENOMEM;
  1159. }
  1160. if ((err = azx_create(card, pci, &chip)) < 0) {
  1161. snd_card_free(card);
  1162. return err;
  1163. }
  1164. strcpy(card->driver, "HDA-Intel");
  1165. strcpy(card->shortname, "HDA Intel");
  1166. sprintf(card->longname, "%s at 0x%lx irq %i", card->shortname, chip->addr, chip->irq);
  1167. /* create codec instances */
  1168. if ((err = azx_codec_create(chip, model[dev])) < 0) {
  1169. snd_card_free(card);
  1170. return err;
  1171. }
  1172. /* create PCM streams */
  1173. if ((err = azx_pcm_create(chip)) < 0) {
  1174. snd_card_free(card);
  1175. return err;
  1176. }
  1177. /* create mixer controls */
  1178. if ((err = azx_mixer_create(chip)) < 0) {
  1179. snd_card_free(card);
  1180. return err;
  1181. }
  1182. snd_card_set_pm_callback(card, azx_suspend, azx_resume, chip);
  1183. snd_card_set_dev(card, &pci->dev);
  1184. if ((err = snd_card_register(card)) < 0) {
  1185. snd_card_free(card);
  1186. return err;
  1187. }
  1188. pci_set_drvdata(pci, card);
  1189. dev++;
  1190. return err;
  1191. }
  1192. static void __devexit azx_remove(struct pci_dev *pci)
  1193. {
  1194. snd_card_free(pci_get_drvdata(pci));
  1195. pci_set_drvdata(pci, NULL);
  1196. }
  1197. /* PCI IDs */
  1198. static struct pci_device_id azx_ids[] = {
  1199. { 0x8086, 0x2668, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ICH6 */
  1200. { 0x8086, 0x27d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ICH7 */
  1201. { 0x8086, 0x269a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ESB2 */
  1202. { 0, }
  1203. };
  1204. MODULE_DEVICE_TABLE(pci, azx_ids);
  1205. /* pci_driver definition */
  1206. static struct pci_driver driver = {
  1207. .name = "HDA Intel",
  1208. .id_table = azx_ids,
  1209. .probe = azx_probe,
  1210. .remove = __devexit_p(azx_remove),
  1211. SND_PCI_PM_CALLBACKS
  1212. };
  1213. static int __init alsa_card_azx_init(void)
  1214. {
  1215. return pci_module_init(&driver);
  1216. }
  1217. static void __exit alsa_card_azx_exit(void)
  1218. {
  1219. pci_unregister_driver(&driver);
  1220. }
  1221. module_init(alsa_card_azx_init)
  1222. module_exit(alsa_card_azx_exit)