mac53c94.c 16 KB

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  1. /*
  2. * SCSI low-level driver for the 53c94 SCSI bus adaptor found
  3. * on Power Macintosh computers, controlling the external SCSI chain.
  4. * We assume the 53c94 is connected to a DBDMA (descriptor-based DMA)
  5. * controller.
  6. *
  7. * Paul Mackerras, August 1996.
  8. * Copyright (C) 1996 Paul Mackerras.
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/delay.h>
  12. #include <linux/types.h>
  13. #include <linux/string.h>
  14. #include <linux/slab.h>
  15. #include <linux/blkdev.h>
  16. #include <linux/proc_fs.h>
  17. #include <linux/stat.h>
  18. #include <linux/spinlock.h>
  19. #include <linux/interrupt.h>
  20. #include <asm/dbdma.h>
  21. #include <asm/io.h>
  22. #include <asm/pgtable.h>
  23. #include <asm/prom.h>
  24. #include <asm/system.h>
  25. #include <asm/pci-bridge.h>
  26. #include <asm/macio.h>
  27. #include <scsi/scsi.h>
  28. #include <scsi/scsi_cmnd.h>
  29. #include <scsi/scsi_device.h>
  30. #include <scsi/scsi_host.h>
  31. #include "mac53c94.h"
  32. enum fsc_phase {
  33. idle,
  34. selecting,
  35. dataing,
  36. completing,
  37. busfreeing,
  38. };
  39. struct fsc_state {
  40. struct mac53c94_regs __iomem *regs;
  41. int intr;
  42. struct dbdma_regs __iomem *dma;
  43. int dmaintr;
  44. int clk_freq;
  45. struct Scsi_Host *host;
  46. struct scsi_cmnd *request_q;
  47. struct scsi_cmnd *request_qtail;
  48. struct scsi_cmnd *current_req; /* req we're currently working on */
  49. enum fsc_phase phase; /* what we're currently trying to do */
  50. struct dbdma_cmd *dma_cmds; /* space for dbdma commands, aligned */
  51. void *dma_cmd_space;
  52. struct pci_dev *pdev;
  53. dma_addr_t dma_addr;
  54. struct macio_dev *mdev;
  55. };
  56. static void mac53c94_init(struct fsc_state *);
  57. static void mac53c94_start(struct fsc_state *);
  58. static void mac53c94_interrupt(int, void *, struct pt_regs *);
  59. static irqreturn_t do_mac53c94_interrupt(int, void *, struct pt_regs *);
  60. static void cmd_done(struct fsc_state *, int result);
  61. static void set_dma_cmds(struct fsc_state *, struct scsi_cmnd *);
  62. static int mac53c94_queue(struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *))
  63. {
  64. struct fsc_state *state;
  65. #if 0
  66. if (cmd->sc_data_direction == DMA_TO_DEVICE) {
  67. int i;
  68. printk(KERN_DEBUG "mac53c94_queue %p: command is", cmd);
  69. for (i = 0; i < cmd->cmd_len; ++i)
  70. printk(" %.2x", cmd->cmnd[i]);
  71. printk("\n" KERN_DEBUG "use_sg=%d request_bufflen=%d request_buffer=%p\n",
  72. cmd->use_sg, cmd->request_bufflen, cmd->request_buffer);
  73. }
  74. #endif
  75. cmd->scsi_done = done;
  76. cmd->host_scribble = NULL;
  77. state = (struct fsc_state *) cmd->device->host->hostdata;
  78. if (state->request_q == NULL)
  79. state->request_q = cmd;
  80. else
  81. state->request_qtail->host_scribble = (void *) cmd;
  82. state->request_qtail = cmd;
  83. if (state->phase == idle)
  84. mac53c94_start(state);
  85. return 0;
  86. }
  87. static int mac53c94_abort(struct scsi_cmnd *cmd)
  88. {
  89. return FAILED;
  90. }
  91. static int mac53c94_host_reset(struct scsi_cmnd *cmd)
  92. {
  93. struct fsc_state *state = (struct fsc_state *) cmd->device->host->hostdata;
  94. struct mac53c94_regs __iomem *regs = state->regs;
  95. struct dbdma_regs __iomem *dma = state->dma;
  96. writel((RUN|PAUSE|FLUSH|WAKE) << 16, &dma->control);
  97. writeb(CMD_SCSI_RESET, &regs->command); /* assert RST */
  98. udelay(100); /* leave it on for a while (>= 25us) */
  99. writeb(CMD_RESET, &regs->command);
  100. udelay(20);
  101. mac53c94_init(state);
  102. writeb(CMD_NOP, &regs->command);
  103. return SUCCESS;
  104. }
  105. static void mac53c94_init(struct fsc_state *state)
  106. {
  107. struct mac53c94_regs __iomem *regs = state->regs;
  108. struct dbdma_regs __iomem *dma = state->dma;
  109. int x;
  110. writeb(state->host->this_id | CF1_PAR_ENABLE, &regs->config1);
  111. writeb(TIMO_VAL(250), &regs->sel_timeout); /* 250ms */
  112. writeb(CLKF_VAL(state->clk_freq), &regs->clk_factor);
  113. writeb(CF2_FEATURE_EN, &regs->config2);
  114. writeb(0, &regs->config3);
  115. writeb(0, &regs->sync_period);
  116. writeb(0, &regs->sync_offset);
  117. x = readb(&regs->interrupt);
  118. writel((RUN|PAUSE|FLUSH|WAKE) << 16, &dma->control);
  119. }
  120. /*
  121. * Start the next command for a 53C94.
  122. * Should be called with interrupts disabled.
  123. */
  124. static void mac53c94_start(struct fsc_state *state)
  125. {
  126. struct scsi_cmnd *cmd;
  127. struct mac53c94_regs __iomem *regs = state->regs;
  128. int i;
  129. if (state->phase != idle || state->current_req != NULL)
  130. panic("inappropriate mac53c94_start (state=%p)", state);
  131. if (state->request_q == NULL)
  132. return;
  133. state->current_req = cmd = state->request_q;
  134. state->request_q = (struct scsi_cmnd *) cmd->host_scribble;
  135. /* Off we go */
  136. writeb(0, &regs->count_lo);
  137. writeb(0, &regs->count_mid);
  138. writeb(0, &regs->count_hi);
  139. writeb(CMD_NOP + CMD_DMA_MODE, &regs->command);
  140. udelay(1);
  141. writeb(CMD_FLUSH, &regs->command);
  142. udelay(1);
  143. writeb(cmd->device->id, &regs->dest_id);
  144. writeb(0, &regs->sync_period);
  145. writeb(0, &regs->sync_offset);
  146. /* load the command into the FIFO */
  147. for (i = 0; i < cmd->cmd_len; ++i)
  148. writeb(cmd->cmnd[i], &regs->fifo);
  149. /* do select without ATN XXX */
  150. writeb(CMD_SELECT, &regs->command);
  151. state->phase = selecting;
  152. if (cmd->use_sg > 0 || cmd->request_bufflen != 0)
  153. set_dma_cmds(state, cmd);
  154. }
  155. static irqreturn_t do_mac53c94_interrupt(int irq, void *dev_id, struct pt_regs *ptregs)
  156. {
  157. unsigned long flags;
  158. struct Scsi_Host *dev = ((struct fsc_state *) dev_id)->current_req->device->host;
  159. spin_lock_irqsave(dev->host_lock, flags);
  160. mac53c94_interrupt(irq, dev_id, ptregs);
  161. spin_unlock_irqrestore(dev->host_lock, flags);
  162. return IRQ_HANDLED;
  163. }
  164. static void mac53c94_interrupt(int irq, void *dev_id, struct pt_regs *ptregs)
  165. {
  166. struct fsc_state *state = (struct fsc_state *) dev_id;
  167. struct mac53c94_regs __iomem *regs = state->regs;
  168. struct dbdma_regs __iomem *dma = state->dma;
  169. struct scsi_cmnd *cmd = state->current_req;
  170. int nb, stat, seq, intr;
  171. static int mac53c94_errors;
  172. /*
  173. * Apparently, reading the interrupt register unlatches
  174. * the status and sequence step registers.
  175. */
  176. seq = readb(&regs->seqstep);
  177. stat = readb(&regs->status);
  178. intr = readb(&regs->interrupt);
  179. #if 0
  180. printk(KERN_DEBUG "mac53c94_intr, intr=%x stat=%x seq=%x phase=%d\n",
  181. intr, stat, seq, state->phase);
  182. #endif
  183. if (intr & INTR_RESET) {
  184. /* SCSI bus was reset */
  185. printk(KERN_INFO "external SCSI bus reset detected\n");
  186. writeb(CMD_NOP, &regs->command);
  187. writel(RUN << 16, &dma->control); /* stop dma */
  188. cmd_done(state, DID_RESET << 16);
  189. return;
  190. }
  191. if (intr & INTR_ILL_CMD) {
  192. printk(KERN_ERR "53c94: invalid cmd, intr=%x stat=%x seq=%x phase=%d\n",
  193. intr, stat, seq, state->phase);
  194. cmd_done(state, DID_ERROR << 16);
  195. return;
  196. }
  197. if (stat & STAT_ERROR) {
  198. #if 0
  199. /* XXX these seem to be harmless? */
  200. printk("53c94: bad error, intr=%x stat=%x seq=%x phase=%d\n",
  201. intr, stat, seq, state->phase);
  202. #endif
  203. ++mac53c94_errors;
  204. writeb(CMD_NOP + CMD_DMA_MODE, &regs->command);
  205. }
  206. if (cmd == 0) {
  207. printk(KERN_DEBUG "53c94: interrupt with no command active?\n");
  208. return;
  209. }
  210. if (stat & STAT_PARITY) {
  211. printk(KERN_ERR "mac53c94: parity error\n");
  212. cmd_done(state, DID_PARITY << 16);
  213. return;
  214. }
  215. switch (state->phase) {
  216. case selecting:
  217. if (intr & INTR_DISCONNECT) {
  218. /* selection timed out */
  219. cmd_done(state, DID_BAD_TARGET << 16);
  220. return;
  221. }
  222. if (intr != INTR_BUS_SERV + INTR_DONE) {
  223. printk(KERN_DEBUG "got intr %x during selection\n", intr);
  224. cmd_done(state, DID_ERROR << 16);
  225. return;
  226. }
  227. if ((seq & SS_MASK) != SS_DONE) {
  228. printk(KERN_DEBUG "seq step %x after command\n", seq);
  229. cmd_done(state, DID_ERROR << 16);
  230. return;
  231. }
  232. writeb(CMD_NOP, &regs->command);
  233. /* set DMA controller going if any data to transfer */
  234. if ((stat & (STAT_MSG|STAT_CD)) == 0
  235. && (cmd->use_sg > 0 || cmd->request_bufflen != 0)) {
  236. nb = cmd->SCp.this_residual;
  237. if (nb > 0xfff0)
  238. nb = 0xfff0;
  239. cmd->SCp.this_residual -= nb;
  240. writeb(nb, &regs->count_lo);
  241. writeb(nb >> 8, &regs->count_mid);
  242. writeb(CMD_DMA_MODE + CMD_NOP, &regs->command);
  243. writel(virt_to_phys(state->dma_cmds), &dma->cmdptr);
  244. writel((RUN << 16) | RUN, &dma->control);
  245. writeb(CMD_DMA_MODE + CMD_XFER_DATA, &regs->command);
  246. state->phase = dataing;
  247. break;
  248. } else if ((stat & STAT_PHASE) == STAT_CD + STAT_IO) {
  249. /* up to status phase already */
  250. writeb(CMD_I_COMPLETE, &regs->command);
  251. state->phase = completing;
  252. } else {
  253. printk(KERN_DEBUG "in unexpected phase %x after cmd\n",
  254. stat & STAT_PHASE);
  255. cmd_done(state, DID_ERROR << 16);
  256. return;
  257. }
  258. break;
  259. case dataing:
  260. if (intr != INTR_BUS_SERV) {
  261. printk(KERN_DEBUG "got intr %x before status\n", intr);
  262. cmd_done(state, DID_ERROR << 16);
  263. return;
  264. }
  265. if (cmd->SCp.this_residual != 0
  266. && (stat & (STAT_MSG|STAT_CD)) == 0) {
  267. /* Set up the count regs to transfer more */
  268. nb = cmd->SCp.this_residual;
  269. if (nb > 0xfff0)
  270. nb = 0xfff0;
  271. cmd->SCp.this_residual -= nb;
  272. writeb(nb, &regs->count_lo);
  273. writeb(nb >> 8, &regs->count_mid);
  274. writeb(CMD_DMA_MODE + CMD_NOP, &regs->command);
  275. writeb(CMD_DMA_MODE + CMD_XFER_DATA, &regs->command);
  276. break;
  277. }
  278. if ((stat & STAT_PHASE) != STAT_CD + STAT_IO) {
  279. printk(KERN_DEBUG "intr %x before data xfer complete\n", intr);
  280. }
  281. writel(RUN << 16, &dma->control); /* stop dma */
  282. if (cmd->use_sg != 0) {
  283. pci_unmap_sg(state->pdev,
  284. (struct scatterlist *)cmd->request_buffer,
  285. cmd->use_sg, cmd->sc_data_direction);
  286. } else {
  287. pci_unmap_single(state->pdev, state->dma_addr,
  288. cmd->request_bufflen, cmd->sc_data_direction);
  289. }
  290. /* should check dma status */
  291. writeb(CMD_I_COMPLETE, &regs->command);
  292. state->phase = completing;
  293. break;
  294. case completing:
  295. if (intr != INTR_DONE) {
  296. printk(KERN_DEBUG "got intr %x on completion\n", intr);
  297. cmd_done(state, DID_ERROR << 16);
  298. return;
  299. }
  300. cmd->SCp.Status = readb(&regs->fifo);
  301. cmd->SCp.Message = readb(&regs->fifo);
  302. cmd->result = CMD_ACCEPT_MSG;
  303. writeb(CMD_ACCEPT_MSG, &regs->command);
  304. state->phase = busfreeing;
  305. break;
  306. case busfreeing:
  307. if (intr != INTR_DISCONNECT) {
  308. printk(KERN_DEBUG "got intr %x when expected disconnect\n", intr);
  309. }
  310. cmd_done(state, (DID_OK << 16) + (cmd->SCp.Message << 8)
  311. + cmd->SCp.Status);
  312. break;
  313. default:
  314. printk(KERN_DEBUG "don't know about phase %d\n", state->phase);
  315. }
  316. }
  317. static void cmd_done(struct fsc_state *state, int result)
  318. {
  319. struct scsi_cmnd *cmd;
  320. cmd = state->current_req;
  321. if (cmd != 0) {
  322. cmd->result = result;
  323. (*cmd->scsi_done)(cmd);
  324. state->current_req = NULL;
  325. }
  326. state->phase = idle;
  327. mac53c94_start(state);
  328. }
  329. /*
  330. * Set up DMA commands for transferring data.
  331. */
  332. static void set_dma_cmds(struct fsc_state *state, struct scsi_cmnd *cmd)
  333. {
  334. int i, dma_cmd, total;
  335. struct scatterlist *scl;
  336. struct dbdma_cmd *dcmds;
  337. dma_addr_t dma_addr;
  338. u32 dma_len;
  339. dma_cmd = cmd->sc_data_direction == DMA_TO_DEVICE ?
  340. OUTPUT_MORE : INPUT_MORE;
  341. dcmds = state->dma_cmds;
  342. if (cmd->use_sg > 0) {
  343. int nseg;
  344. total = 0;
  345. scl = (struct scatterlist *) cmd->buffer;
  346. nseg = pci_map_sg(state->pdev, scl, cmd->use_sg,
  347. cmd->sc_data_direction);
  348. for (i = 0; i < nseg; ++i) {
  349. dma_addr = sg_dma_address(scl);
  350. dma_len = sg_dma_len(scl);
  351. if (dma_len > 0xffff)
  352. panic("mac53c94: scatterlist element >= 64k");
  353. total += dma_len;
  354. st_le16(&dcmds->req_count, dma_len);
  355. st_le16(&dcmds->command, dma_cmd);
  356. st_le32(&dcmds->phy_addr, dma_addr);
  357. dcmds->xfer_status = 0;
  358. ++scl;
  359. ++dcmds;
  360. }
  361. } else {
  362. total = cmd->request_bufflen;
  363. if (total > 0xffff)
  364. panic("mac53c94: transfer size >= 64k");
  365. dma_addr = pci_map_single(state->pdev, cmd->request_buffer,
  366. total, cmd->sc_data_direction);
  367. state->dma_addr = dma_addr;
  368. st_le16(&dcmds->req_count, total);
  369. st_le32(&dcmds->phy_addr, dma_addr);
  370. dcmds->xfer_status = 0;
  371. ++dcmds;
  372. }
  373. dma_cmd += OUTPUT_LAST - OUTPUT_MORE;
  374. st_le16(&dcmds[-1].command, dma_cmd);
  375. st_le16(&dcmds->command, DBDMA_STOP);
  376. cmd->SCp.this_residual = total;
  377. }
  378. static struct scsi_host_template mac53c94_template = {
  379. .proc_name = "53c94",
  380. .name = "53C94",
  381. .queuecommand = mac53c94_queue,
  382. .eh_abort_handler = mac53c94_abort,
  383. .eh_host_reset_handler = mac53c94_host_reset,
  384. .can_queue = 1,
  385. .this_id = 7,
  386. .sg_tablesize = SG_ALL,
  387. .cmd_per_lun = 1,
  388. .use_clustering = DISABLE_CLUSTERING,
  389. };
  390. static int mac53c94_probe(struct macio_dev *mdev, const struct of_match *match)
  391. {
  392. struct device_node *node = macio_get_of_node(mdev);
  393. struct pci_dev *pdev = macio_get_pci_dev(mdev);
  394. struct fsc_state *state;
  395. struct Scsi_Host *host;
  396. void *dma_cmd_space;
  397. unsigned char *clkprop;
  398. int proplen;
  399. if (macio_resource_count(mdev) != 2 || macio_irq_count(mdev) != 2) {
  400. printk(KERN_ERR "mac53c94: expected 2 addrs and intrs (got %d/%d)\n",
  401. node->n_addrs, node->n_intrs);
  402. return -ENODEV;
  403. }
  404. if (macio_request_resources(mdev, "mac53c94") != 0) {
  405. printk(KERN_ERR "mac53c94: unable to request memory resources");
  406. return -EBUSY;
  407. }
  408. host = scsi_host_alloc(&mac53c94_template, sizeof(struct fsc_state));
  409. if (host == NULL) {
  410. printk(KERN_ERR "mac53c94: couldn't register host");
  411. goto out_release;
  412. }
  413. state = (struct fsc_state *) host->hostdata;
  414. macio_set_drvdata(mdev, state);
  415. state->host = host;
  416. state->pdev = pdev;
  417. state->mdev = mdev;
  418. state->regs = (struct mac53c94_regs __iomem *)
  419. ioremap(macio_resource_start(mdev, 0), 0x1000);
  420. state->intr = macio_irq(mdev, 0);
  421. state->dma = (struct dbdma_regs __iomem *)
  422. ioremap(macio_resource_start(mdev, 1), 0x1000);
  423. state->dmaintr = macio_irq(mdev, 1);
  424. if (state->regs == NULL || state->dma == NULL) {
  425. printk(KERN_ERR "mac53c94: ioremap failed for %s\n",
  426. node->full_name);
  427. goto out_free;
  428. }
  429. clkprop = get_property(node, "clock-frequency", &proplen);
  430. if (clkprop == NULL || proplen != sizeof(int)) {
  431. printk(KERN_ERR "%s: can't get clock frequency, "
  432. "assuming 25MHz\n", node->full_name);
  433. state->clk_freq = 25000000;
  434. } else
  435. state->clk_freq = *(int *)clkprop;
  436. /* Space for dma command list: +1 for stop command,
  437. * +1 to allow for aligning.
  438. * XXX FIXME: Use DMA consistent routines
  439. */
  440. dma_cmd_space = kmalloc((host->sg_tablesize + 2) *
  441. sizeof(struct dbdma_cmd), GFP_KERNEL);
  442. if (dma_cmd_space == 0) {
  443. printk(KERN_ERR "mac53c94: couldn't allocate dma "
  444. "command space for %s\n", node->full_name);
  445. goto out_free;
  446. }
  447. state->dma_cmds = (struct dbdma_cmd *)DBDMA_ALIGN(dma_cmd_space);
  448. memset(state->dma_cmds, 0, (host->sg_tablesize + 1)
  449. * sizeof(struct dbdma_cmd));
  450. state->dma_cmd_space = dma_cmd_space;
  451. mac53c94_init(state);
  452. if (request_irq(state->intr, do_mac53c94_interrupt, 0, "53C94", state)) {
  453. printk(KERN_ERR "mac53C94: can't get irq %d for %s\n",
  454. state->intr, node->full_name);
  455. goto out_free_dma;
  456. }
  457. /* XXX FIXME: handle failure */
  458. scsi_add_host(host, &mdev->ofdev.dev);
  459. scsi_scan_host(host);
  460. return 0;
  461. out_free_dma:
  462. kfree(state->dma_cmd_space);
  463. out_free:
  464. if (state->dma != NULL)
  465. iounmap(state->dma);
  466. if (state->regs != NULL)
  467. iounmap(state->regs);
  468. scsi_host_put(host);
  469. out_release:
  470. macio_release_resources(mdev);
  471. return -ENODEV;
  472. }
  473. static int mac53c94_remove(struct macio_dev *mdev)
  474. {
  475. struct fsc_state *fp = (struct fsc_state *)macio_get_drvdata(mdev);
  476. struct Scsi_Host *host = fp->host;
  477. scsi_remove_host(host);
  478. free_irq(fp->intr, fp);
  479. if (fp->regs)
  480. iounmap((void *) fp->regs);
  481. if (fp->dma)
  482. iounmap((void *) fp->dma);
  483. kfree(fp->dma_cmd_space);
  484. scsi_host_put(host);
  485. macio_release_resources(mdev);
  486. return 0;
  487. }
  488. static struct of_match mac53c94_match[] =
  489. {
  490. {
  491. .name = "53c94",
  492. .type = OF_ANY_MATCH,
  493. .compatible = OF_ANY_MATCH
  494. },
  495. {},
  496. };
  497. static struct macio_driver mac53c94_driver =
  498. {
  499. .name = "mac53c94",
  500. .match_table = mac53c94_match,
  501. .probe = mac53c94_probe,
  502. .remove = mac53c94_remove,
  503. };
  504. static int __init init_mac53c94(void)
  505. {
  506. return macio_register_driver(&mac53c94_driver);
  507. }
  508. static void __exit exit_mac53c94(void)
  509. {
  510. return macio_unregister_driver(&mac53c94_driver);
  511. }
  512. module_init(init_mac53c94);
  513. module_exit(exit_mac53c94);
  514. MODULE_DESCRIPTION("PowerMac 53c94 SCSI driver");
  515. MODULE_AUTHOR("Paul Mackerras <paulus@samba.org>");
  516. MODULE_LICENSE("GPL");