video1394.c 42 KB

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  1. /*
  2. * video1394.c - video driver for OHCI 1394 boards
  3. * Copyright (C)1999,2000 Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>
  4. * Peter Schlaile <udbz@rz.uni-karlsruhe.de>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software Foundation,
  18. * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19. *
  20. * NOTES:
  21. *
  22. * jds -- add private data to file to keep track of iso contexts associated
  23. * with each open -- so release won't kill all iso transfers.
  24. *
  25. * Damien Douxchamps: Fix failure when the number of DMA pages per frame is
  26. * one.
  27. *
  28. * ioctl return codes:
  29. * EFAULT is only for invalid address for the argp
  30. * EINVAL for out of range values
  31. * EBUSY when trying to use an already used resource
  32. * ESRCH when trying to free/stop a not used resource
  33. * EAGAIN for resource allocation failure that could perhaps succeed later
  34. * ENOTTY for unsupported ioctl request
  35. *
  36. */
  37. #include <linux/config.h>
  38. #include <linux/kernel.h>
  39. #include <linux/list.h>
  40. #include <linux/slab.h>
  41. #include <linux/interrupt.h>
  42. #include <linux/wait.h>
  43. #include <linux/errno.h>
  44. #include <linux/module.h>
  45. #include <linux/init.h>
  46. #include <linux/pci.h>
  47. #include <linux/fs.h>
  48. #include <linux/poll.h>
  49. #include <linux/smp_lock.h>
  50. #include <linux/delay.h>
  51. #include <linux/devfs_fs_kernel.h>
  52. #include <linux/bitops.h>
  53. #include <linux/types.h>
  54. #include <linux/vmalloc.h>
  55. #include <linux/timex.h>
  56. #include <linux/mm.h>
  57. #include <linux/ioctl32.h>
  58. #include <linux/compat.h>
  59. #include <linux/cdev.h>
  60. #include "ieee1394.h"
  61. #include "ieee1394_types.h"
  62. #include "hosts.h"
  63. #include "ieee1394_core.h"
  64. #include "highlevel.h"
  65. #include "video1394.h"
  66. #include "nodemgr.h"
  67. #include "dma.h"
  68. #include "ohci1394.h"
  69. #define ISO_CHANNELS 64
  70. #ifndef virt_to_page
  71. #define virt_to_page(x) MAP_NR(x)
  72. #endif
  73. #ifndef vmalloc_32
  74. #define vmalloc_32(x) vmalloc(x)
  75. #endif
  76. struct it_dma_prg {
  77. struct dma_cmd begin;
  78. quadlet_t data[4];
  79. struct dma_cmd end;
  80. quadlet_t pad[4]; /* FIXME: quick hack for memory alignment */
  81. };
  82. struct dma_iso_ctx {
  83. struct ti_ohci *ohci;
  84. int type; /* OHCI_ISO_TRANSMIT or OHCI_ISO_RECEIVE */
  85. struct ohci1394_iso_tasklet iso_tasklet;
  86. int channel;
  87. int ctx;
  88. int last_buffer;
  89. int * next_buffer; /* For ISO Transmit of video packets
  90. to write the correct SYT field
  91. into the next block */
  92. unsigned int num_desc;
  93. unsigned int buf_size;
  94. unsigned int frame_size;
  95. unsigned int packet_size;
  96. unsigned int left_size;
  97. unsigned int nb_cmd;
  98. struct dma_region dma;
  99. struct dma_prog_region *prg_reg;
  100. struct dma_cmd **ir_prg;
  101. struct it_dma_prg **it_prg;
  102. unsigned int *buffer_status;
  103. struct timeval *buffer_time; /* time when the buffer was received */
  104. unsigned int *last_used_cmd; /* For ISO Transmit with
  105. variable sized packets only ! */
  106. int ctrlClear;
  107. int ctrlSet;
  108. int cmdPtr;
  109. int ctxMatch;
  110. wait_queue_head_t waitq;
  111. spinlock_t lock;
  112. unsigned int syt_offset;
  113. int flags;
  114. struct list_head link;
  115. };
  116. struct file_ctx {
  117. struct ti_ohci *ohci;
  118. struct list_head context_list;
  119. struct dma_iso_ctx *current_ctx;
  120. };
  121. #ifdef CONFIG_IEEE1394_VERBOSEDEBUG
  122. #define VIDEO1394_DEBUG
  123. #endif
  124. #ifdef DBGMSG
  125. #undef DBGMSG
  126. #endif
  127. #ifdef VIDEO1394_DEBUG
  128. #define DBGMSG(card, fmt, args...) \
  129. printk(KERN_INFO "video1394_%d: " fmt "\n" , card , ## args)
  130. #else
  131. #define DBGMSG(card, fmt, args...)
  132. #endif
  133. /* print general (card independent) information */
  134. #define PRINT_G(level, fmt, args...) \
  135. printk(level "video1394: " fmt "\n" , ## args)
  136. /* print card specific information */
  137. #define PRINT(level, card, fmt, args...) \
  138. printk(level "video1394_%d: " fmt "\n" , card , ## args)
  139. static void wakeup_dma_ir_ctx(unsigned long l);
  140. static void wakeup_dma_it_ctx(unsigned long l);
  141. static struct hpsb_highlevel video1394_highlevel;
  142. static int free_dma_iso_ctx(struct dma_iso_ctx *d)
  143. {
  144. int i;
  145. DBGMSG(d->ohci->host->id, "Freeing dma_iso_ctx %d", d->ctx);
  146. ohci1394_stop_context(d->ohci, d->ctrlClear, NULL);
  147. if (d->iso_tasklet.link.next != NULL)
  148. ohci1394_unregister_iso_tasklet(d->ohci, &d->iso_tasklet);
  149. dma_region_free(&d->dma);
  150. if (d->prg_reg) {
  151. for (i = 0; i < d->num_desc; i++)
  152. dma_prog_region_free(&d->prg_reg[i]);
  153. kfree(d->prg_reg);
  154. }
  155. if (d->ir_prg)
  156. kfree(d->ir_prg);
  157. if (d->it_prg)
  158. kfree(d->it_prg);
  159. if (d->buffer_status)
  160. kfree(d->buffer_status);
  161. if (d->buffer_time)
  162. kfree(d->buffer_time);
  163. if (d->last_used_cmd)
  164. kfree(d->last_used_cmd);
  165. if (d->next_buffer)
  166. kfree(d->next_buffer);
  167. list_del(&d->link);
  168. kfree(d);
  169. return 0;
  170. }
  171. static struct dma_iso_ctx *
  172. alloc_dma_iso_ctx(struct ti_ohci *ohci, int type, int num_desc,
  173. int buf_size, int channel, unsigned int packet_size)
  174. {
  175. struct dma_iso_ctx *d;
  176. int i;
  177. d = kmalloc(sizeof(struct dma_iso_ctx), GFP_KERNEL);
  178. if (d == NULL) {
  179. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma_iso_ctx");
  180. return NULL;
  181. }
  182. memset(d, 0, sizeof *d);
  183. d->ohci = ohci;
  184. d->type = type;
  185. d->channel = channel;
  186. d->num_desc = num_desc;
  187. d->frame_size = buf_size;
  188. d->buf_size = PAGE_ALIGN(buf_size);
  189. d->last_buffer = -1;
  190. INIT_LIST_HEAD(&d->link);
  191. init_waitqueue_head(&d->waitq);
  192. /* Init the regions for easy cleanup */
  193. dma_region_init(&d->dma);
  194. if (dma_region_alloc(&d->dma, d->num_desc * d->buf_size, ohci->dev,
  195. PCI_DMA_BIDIRECTIONAL)) {
  196. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma buffer");
  197. free_dma_iso_ctx(d);
  198. return NULL;
  199. }
  200. if (type == OHCI_ISO_RECEIVE)
  201. ohci1394_init_iso_tasklet(&d->iso_tasklet, type,
  202. wakeup_dma_ir_ctx,
  203. (unsigned long) d);
  204. else
  205. ohci1394_init_iso_tasklet(&d->iso_tasklet, type,
  206. wakeup_dma_it_ctx,
  207. (unsigned long) d);
  208. if (ohci1394_register_iso_tasklet(ohci, &d->iso_tasklet) < 0) {
  209. PRINT(KERN_ERR, ohci->host->id, "no free iso %s contexts",
  210. type == OHCI_ISO_RECEIVE ? "receive" : "transmit");
  211. free_dma_iso_ctx(d);
  212. return NULL;
  213. }
  214. d->ctx = d->iso_tasklet.context;
  215. d->prg_reg = kmalloc(d->num_desc * sizeof(struct dma_prog_region),
  216. GFP_KERNEL);
  217. if (d->prg_reg == NULL) {
  218. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate ir prg regs");
  219. free_dma_iso_ctx(d);
  220. return NULL;
  221. }
  222. /* Makes for easier cleanup */
  223. for (i = 0; i < d->num_desc; i++)
  224. dma_prog_region_init(&d->prg_reg[i]);
  225. if (type == OHCI_ISO_RECEIVE) {
  226. d->ctrlSet = OHCI1394_IsoRcvContextControlSet+32*d->ctx;
  227. d->ctrlClear = OHCI1394_IsoRcvContextControlClear+32*d->ctx;
  228. d->cmdPtr = OHCI1394_IsoRcvCommandPtr+32*d->ctx;
  229. d->ctxMatch = OHCI1394_IsoRcvContextMatch+32*d->ctx;
  230. d->ir_prg = kmalloc(d->num_desc * sizeof(struct dma_cmd *),
  231. GFP_KERNEL);
  232. if (d->ir_prg == NULL) {
  233. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma ir prg");
  234. free_dma_iso_ctx(d);
  235. return NULL;
  236. }
  237. memset(d->ir_prg, 0, d->num_desc * sizeof(struct dma_cmd *));
  238. d->nb_cmd = d->buf_size / PAGE_SIZE + 1;
  239. d->left_size = (d->frame_size % PAGE_SIZE) ?
  240. d->frame_size % PAGE_SIZE : PAGE_SIZE;
  241. for (i = 0;i < d->num_desc; i++) {
  242. if (dma_prog_region_alloc(&d->prg_reg[i], d->nb_cmd *
  243. sizeof(struct dma_cmd), ohci->dev)) {
  244. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma ir prg");
  245. free_dma_iso_ctx(d);
  246. return NULL;
  247. }
  248. d->ir_prg[i] = (struct dma_cmd *)d->prg_reg[i].kvirt;
  249. }
  250. } else { /* OHCI_ISO_TRANSMIT */
  251. d->ctrlSet = OHCI1394_IsoXmitContextControlSet+16*d->ctx;
  252. d->ctrlClear = OHCI1394_IsoXmitContextControlClear+16*d->ctx;
  253. d->cmdPtr = OHCI1394_IsoXmitCommandPtr+16*d->ctx;
  254. d->it_prg = kmalloc(d->num_desc * sizeof(struct it_dma_prg *),
  255. GFP_KERNEL);
  256. if (d->it_prg == NULL) {
  257. PRINT(KERN_ERR, ohci->host->id,
  258. "Failed to allocate dma it prg");
  259. free_dma_iso_ctx(d);
  260. return NULL;
  261. }
  262. memset(d->it_prg, 0, d->num_desc*sizeof(struct it_dma_prg *));
  263. d->packet_size = packet_size;
  264. if (PAGE_SIZE % packet_size || packet_size>4096) {
  265. PRINT(KERN_ERR, ohci->host->id,
  266. "Packet size %d (page_size: %ld) "
  267. "not yet supported\n",
  268. packet_size, PAGE_SIZE);
  269. free_dma_iso_ctx(d);
  270. return NULL;
  271. }
  272. d->nb_cmd = d->frame_size / d->packet_size;
  273. if (d->frame_size % d->packet_size) {
  274. d->nb_cmd++;
  275. d->left_size = d->frame_size % d->packet_size;
  276. } else
  277. d->left_size = d->packet_size;
  278. for (i = 0; i < d->num_desc; i++) {
  279. if (dma_prog_region_alloc(&d->prg_reg[i], d->nb_cmd *
  280. sizeof(struct it_dma_prg), ohci->dev)) {
  281. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma it prg");
  282. free_dma_iso_ctx(d);
  283. return NULL;
  284. }
  285. d->it_prg[i] = (struct it_dma_prg *)d->prg_reg[i].kvirt;
  286. }
  287. }
  288. d->buffer_status = kmalloc(d->num_desc * sizeof(unsigned int),
  289. GFP_KERNEL);
  290. d->buffer_time = kmalloc(d->num_desc * sizeof(struct timeval),
  291. GFP_KERNEL);
  292. d->last_used_cmd = kmalloc(d->num_desc * sizeof(unsigned int),
  293. GFP_KERNEL);
  294. d->next_buffer = kmalloc(d->num_desc * sizeof(int),
  295. GFP_KERNEL);
  296. if (d->buffer_status == NULL) {
  297. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate buffer_status");
  298. free_dma_iso_ctx(d);
  299. return NULL;
  300. }
  301. if (d->buffer_time == NULL) {
  302. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate buffer_time");
  303. free_dma_iso_ctx(d);
  304. return NULL;
  305. }
  306. if (d->last_used_cmd == NULL) {
  307. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate last_used_cmd");
  308. free_dma_iso_ctx(d);
  309. return NULL;
  310. }
  311. if (d->next_buffer == NULL) {
  312. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate next_buffer");
  313. free_dma_iso_ctx(d);
  314. return NULL;
  315. }
  316. memset(d->buffer_status, 0, d->num_desc * sizeof(unsigned int));
  317. memset(d->buffer_time, 0, d->num_desc * sizeof(struct timeval));
  318. memset(d->last_used_cmd, 0, d->num_desc * sizeof(unsigned int));
  319. memset(d->next_buffer, -1, d->num_desc * sizeof(int));
  320. spin_lock_init(&d->lock);
  321. PRINT(KERN_INFO, ohci->host->id, "Iso %s DMA: %d buffers "
  322. "of size %d allocated for a frame size %d, each with %d prgs",
  323. (type == OHCI_ISO_RECEIVE) ? "receive" : "transmit",
  324. d->num_desc, d->buf_size, d->frame_size, d->nb_cmd);
  325. return d;
  326. }
  327. static void reset_ir_status(struct dma_iso_ctx *d, int n)
  328. {
  329. int i;
  330. d->ir_prg[n][0].status = cpu_to_le32(4);
  331. d->ir_prg[n][1].status = cpu_to_le32(PAGE_SIZE-4);
  332. for (i = 2; i < d->nb_cmd - 1; i++)
  333. d->ir_prg[n][i].status = cpu_to_le32(PAGE_SIZE);
  334. d->ir_prg[n][i].status = cpu_to_le32(d->left_size);
  335. }
  336. static void initialize_dma_ir_prg(struct dma_iso_ctx *d, int n, int flags)
  337. {
  338. struct dma_cmd *ir_prg = d->ir_prg[n];
  339. struct dma_prog_region *ir_reg = &d->prg_reg[n];
  340. unsigned long buf = (unsigned long)d->dma.kvirt + n * d->buf_size;
  341. int i;
  342. /* the first descriptor will read only 4 bytes */
  343. ir_prg[0].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  344. DMA_CTL_BRANCH | 4);
  345. /* set the sync flag */
  346. if (flags & VIDEO1394_SYNC_FRAMES)
  347. ir_prg[0].control |= cpu_to_le32(DMA_CTL_WAIT);
  348. ir_prg[0].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, buf -
  349. (unsigned long)d->dma.kvirt));
  350. ir_prg[0].branchAddress = cpu_to_le32((dma_prog_region_offset_to_bus(ir_reg,
  351. 1 * sizeof(struct dma_cmd)) & 0xfffffff0) | 0x1);
  352. /* If there is *not* only one DMA page per frame (hence, d->nb_cmd==2) */
  353. if (d->nb_cmd > 2) {
  354. /* The second descriptor will read PAGE_SIZE-4 bytes */
  355. ir_prg[1].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  356. DMA_CTL_BRANCH | (PAGE_SIZE-4));
  357. ir_prg[1].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, (buf + 4) -
  358. (unsigned long)d->dma.kvirt));
  359. ir_prg[1].branchAddress = cpu_to_le32((dma_prog_region_offset_to_bus(ir_reg,
  360. 2 * sizeof(struct dma_cmd)) & 0xfffffff0) | 0x1);
  361. for (i = 2; i < d->nb_cmd - 1; i++) {
  362. ir_prg[i].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  363. DMA_CTL_BRANCH | PAGE_SIZE);
  364. ir_prg[i].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  365. (buf+(i-1)*PAGE_SIZE) -
  366. (unsigned long)d->dma.kvirt));
  367. ir_prg[i].branchAddress =
  368. cpu_to_le32((dma_prog_region_offset_to_bus(ir_reg,
  369. (i + 1) * sizeof(struct dma_cmd)) & 0xfffffff0) | 0x1);
  370. }
  371. /* The last descriptor will generate an interrupt */
  372. ir_prg[i].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  373. DMA_CTL_IRQ | DMA_CTL_BRANCH | d->left_size);
  374. ir_prg[i].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  375. (buf+(i-1)*PAGE_SIZE) -
  376. (unsigned long)d->dma.kvirt));
  377. } else {
  378. /* Only one DMA page is used. Read d->left_size immediately and */
  379. /* generate an interrupt as this is also the last page. */
  380. ir_prg[1].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  381. DMA_CTL_IRQ | DMA_CTL_BRANCH | (d->left_size-4));
  382. ir_prg[1].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  383. (buf + 4) - (unsigned long)d->dma.kvirt));
  384. }
  385. }
  386. static void initialize_dma_ir_ctx(struct dma_iso_ctx *d, int tag, int flags)
  387. {
  388. struct ti_ohci *ohci = (struct ti_ohci *)d->ohci;
  389. int i;
  390. d->flags = flags;
  391. ohci1394_stop_context(ohci, d->ctrlClear, NULL);
  392. for (i=0;i<d->num_desc;i++) {
  393. initialize_dma_ir_prg(d, i, flags);
  394. reset_ir_status(d, i);
  395. }
  396. /* reset the ctrl register */
  397. reg_write(ohci, d->ctrlClear, 0xf0000000);
  398. /* Set bufferFill */
  399. reg_write(ohci, d->ctrlSet, 0x80000000);
  400. /* Set isoch header */
  401. if (flags & VIDEO1394_INCLUDE_ISO_HEADERS)
  402. reg_write(ohci, d->ctrlSet, 0x40000000);
  403. /* Set the context match register to match on all tags,
  404. sync for sync tag, and listen to d->channel */
  405. reg_write(ohci, d->ctxMatch, 0xf0000000|((tag&0xf)<<8)|d->channel);
  406. /* Set up isoRecvIntMask to generate interrupts */
  407. reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1<<d->ctx);
  408. }
  409. /* find which context is listening to this channel */
  410. static struct dma_iso_ctx *
  411. find_ctx(struct list_head *list, int type, int channel)
  412. {
  413. struct dma_iso_ctx *ctx;
  414. list_for_each_entry(ctx, list, link) {
  415. if (ctx->type == type && ctx->channel == channel)
  416. return ctx;
  417. }
  418. return NULL;
  419. }
  420. static void wakeup_dma_ir_ctx(unsigned long l)
  421. {
  422. struct dma_iso_ctx *d = (struct dma_iso_ctx *) l;
  423. int i;
  424. spin_lock(&d->lock);
  425. for (i = 0; i < d->num_desc; i++) {
  426. if (d->ir_prg[i][d->nb_cmd-1].status & cpu_to_le32(0xFFFF0000)) {
  427. reset_ir_status(d, i);
  428. d->buffer_status[i] = VIDEO1394_BUFFER_READY;
  429. do_gettimeofday(&d->buffer_time[i]);
  430. }
  431. }
  432. spin_unlock(&d->lock);
  433. if (waitqueue_active(&d->waitq))
  434. wake_up_interruptible(&d->waitq);
  435. }
  436. static inline void put_timestamp(struct ti_ohci *ohci, struct dma_iso_ctx * d,
  437. int n)
  438. {
  439. unsigned char* buf = d->dma.kvirt + n * d->buf_size;
  440. u32 cycleTimer;
  441. u32 timeStamp;
  442. if (n == -1) {
  443. return;
  444. }
  445. cycleTimer = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
  446. timeStamp = ((cycleTimer & 0x0fff) + d->syt_offset); /* 11059 = 450 us */
  447. timeStamp = (timeStamp % 3072 + ((timeStamp / 3072) << 12)
  448. + (cycleTimer & 0xf000)) & 0xffff;
  449. buf[6] = timeStamp >> 8;
  450. buf[7] = timeStamp & 0xff;
  451. /* if first packet is empty packet, then put timestamp into the next full one too */
  452. if ( (le32_to_cpu(d->it_prg[n][0].data[1]) >>16) == 0x008) {
  453. buf += d->packet_size;
  454. buf[6] = timeStamp >> 8;
  455. buf[7] = timeStamp & 0xff;
  456. }
  457. /* do the next buffer frame too in case of irq latency */
  458. n = d->next_buffer[n];
  459. if (n == -1) {
  460. return;
  461. }
  462. buf = d->dma.kvirt + n * d->buf_size;
  463. timeStamp += (d->last_used_cmd[n] << 12) & 0xffff;
  464. buf[6] = timeStamp >> 8;
  465. buf[7] = timeStamp & 0xff;
  466. /* if first packet is empty packet, then put timestamp into the next full one too */
  467. if ( (le32_to_cpu(d->it_prg[n][0].data[1]) >>16) == 0x008) {
  468. buf += d->packet_size;
  469. buf[6] = timeStamp >> 8;
  470. buf[7] = timeStamp & 0xff;
  471. }
  472. #if 0
  473. printk("curr: %d, next: %d, cycleTimer: %08x timeStamp: %08x\n",
  474. curr, n, cycleTimer, timeStamp);
  475. #endif
  476. }
  477. static void wakeup_dma_it_ctx(unsigned long l)
  478. {
  479. struct dma_iso_ctx *d = (struct dma_iso_ctx *) l;
  480. struct ti_ohci *ohci = d->ohci;
  481. int i;
  482. spin_lock(&d->lock);
  483. for (i = 0; i < d->num_desc; i++) {
  484. if (d->it_prg[i][d->last_used_cmd[i]].end.status &
  485. cpu_to_le32(0xFFFF0000)) {
  486. int next = d->next_buffer[i];
  487. put_timestamp(ohci, d, next);
  488. d->it_prg[i][d->last_used_cmd[i]].end.status = 0;
  489. d->buffer_status[i] = VIDEO1394_BUFFER_READY;
  490. }
  491. }
  492. spin_unlock(&d->lock);
  493. if (waitqueue_active(&d->waitq))
  494. wake_up_interruptible(&d->waitq);
  495. }
  496. static void initialize_dma_it_prg(struct dma_iso_ctx *d, int n, int sync_tag)
  497. {
  498. struct it_dma_prg *it_prg = d->it_prg[n];
  499. struct dma_prog_region *it_reg = &d->prg_reg[n];
  500. unsigned long buf = (unsigned long)d->dma.kvirt + n * d->buf_size;
  501. int i;
  502. d->last_used_cmd[n] = d->nb_cmd - 1;
  503. for (i=0;i<d->nb_cmd;i++) {
  504. it_prg[i].begin.control = cpu_to_le32(DMA_CTL_OUTPUT_MORE |
  505. DMA_CTL_IMMEDIATE | 8) ;
  506. it_prg[i].begin.address = 0;
  507. it_prg[i].begin.status = 0;
  508. it_prg[i].data[0] = cpu_to_le32(
  509. (IEEE1394_SPEED_100 << 16)
  510. | (/* tag */ 1 << 14)
  511. | (d->channel << 8)
  512. | (TCODE_ISO_DATA << 4));
  513. if (i==0) it_prg[i].data[0] |= cpu_to_le32(sync_tag);
  514. it_prg[i].data[1] = cpu_to_le32(d->packet_size << 16);
  515. it_prg[i].data[2] = 0;
  516. it_prg[i].data[3] = 0;
  517. it_prg[i].end.control = cpu_to_le32(DMA_CTL_OUTPUT_LAST |
  518. DMA_CTL_BRANCH);
  519. it_prg[i].end.address =
  520. cpu_to_le32(dma_region_offset_to_bus(&d->dma, (buf+i*d->packet_size) -
  521. (unsigned long)d->dma.kvirt));
  522. if (i<d->nb_cmd-1) {
  523. it_prg[i].end.control |= cpu_to_le32(d->packet_size);
  524. it_prg[i].begin.branchAddress =
  525. cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) *
  526. sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3);
  527. it_prg[i].end.branchAddress =
  528. cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) *
  529. sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3);
  530. } else {
  531. /* the last prg generates an interrupt */
  532. it_prg[i].end.control |= cpu_to_le32(DMA_CTL_UPDATE |
  533. DMA_CTL_IRQ | d->left_size);
  534. /* the last prg doesn't branch */
  535. it_prg[i].begin.branchAddress = 0;
  536. it_prg[i].end.branchAddress = 0;
  537. }
  538. it_prg[i].end.status = 0;
  539. }
  540. }
  541. static void initialize_dma_it_prg_var_packet_queue(
  542. struct dma_iso_ctx *d, int n, unsigned int * packet_sizes,
  543. struct ti_ohci *ohci)
  544. {
  545. struct it_dma_prg *it_prg = d->it_prg[n];
  546. struct dma_prog_region *it_reg = &d->prg_reg[n];
  547. int i;
  548. #if 0
  549. if (n != -1) {
  550. put_timestamp(ohci, d, n);
  551. }
  552. #endif
  553. d->last_used_cmd[n] = d->nb_cmd - 1;
  554. for (i = 0; i < d->nb_cmd; i++) {
  555. unsigned int size;
  556. if (packet_sizes[i] > d->packet_size) {
  557. size = d->packet_size;
  558. } else {
  559. size = packet_sizes[i];
  560. }
  561. it_prg[i].data[1] = cpu_to_le32(size << 16);
  562. it_prg[i].end.control = cpu_to_le32(DMA_CTL_OUTPUT_LAST | DMA_CTL_BRANCH);
  563. if (i < d->nb_cmd-1 && packet_sizes[i+1] != 0) {
  564. it_prg[i].end.control |= cpu_to_le32(size);
  565. it_prg[i].begin.branchAddress =
  566. cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) *
  567. sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3);
  568. it_prg[i].end.branchAddress =
  569. cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) *
  570. sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3);
  571. } else {
  572. /* the last prg generates an interrupt */
  573. it_prg[i].end.control |= cpu_to_le32(DMA_CTL_UPDATE |
  574. DMA_CTL_IRQ | size);
  575. /* the last prg doesn't branch */
  576. it_prg[i].begin.branchAddress = 0;
  577. it_prg[i].end.branchAddress = 0;
  578. d->last_used_cmd[n] = i;
  579. break;
  580. }
  581. }
  582. }
  583. static void initialize_dma_it_ctx(struct dma_iso_ctx *d, int sync_tag,
  584. unsigned int syt_offset, int flags)
  585. {
  586. struct ti_ohci *ohci = (struct ti_ohci *)d->ohci;
  587. int i;
  588. d->flags = flags;
  589. d->syt_offset = (syt_offset == 0 ? 11000 : syt_offset);
  590. ohci1394_stop_context(ohci, d->ctrlClear, NULL);
  591. for (i=0;i<d->num_desc;i++)
  592. initialize_dma_it_prg(d, i, sync_tag);
  593. /* Set up isoRecvIntMask to generate interrupts */
  594. reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1<<d->ctx);
  595. }
  596. static inline unsigned video1394_buffer_state(struct dma_iso_ctx *d,
  597. unsigned int buffer)
  598. {
  599. unsigned long flags;
  600. unsigned int ret;
  601. spin_lock_irqsave(&d->lock, flags);
  602. ret = d->buffer_status[buffer];
  603. spin_unlock_irqrestore(&d->lock, flags);
  604. return ret;
  605. }
  606. static int __video1394_ioctl(struct file *file,
  607. unsigned int cmd, unsigned long arg)
  608. {
  609. struct file_ctx *ctx = (struct file_ctx *)file->private_data;
  610. struct ti_ohci *ohci = ctx->ohci;
  611. unsigned long flags;
  612. void __user *argp = (void __user *)arg;
  613. switch(cmd)
  614. {
  615. case VIDEO1394_IOC_LISTEN_CHANNEL:
  616. case VIDEO1394_IOC_TALK_CHANNEL:
  617. {
  618. struct video1394_mmap v;
  619. u64 mask;
  620. struct dma_iso_ctx *d;
  621. int i;
  622. if (copy_from_user(&v, argp, sizeof(v)))
  623. return -EFAULT;
  624. /* if channel < 0, find lowest available one */
  625. if (v.channel < 0) {
  626. mask = (u64)0x1;
  627. for (i=0; ; i++) {
  628. if (i == ISO_CHANNELS) {
  629. PRINT(KERN_ERR, ohci->host->id,
  630. "No free channel found");
  631. return EAGAIN;
  632. }
  633. if (!(ohci->ISO_channel_usage & mask)) {
  634. v.channel = i;
  635. PRINT(KERN_INFO, ohci->host->id, "Found free channel %d", i);
  636. break;
  637. }
  638. mask = mask << 1;
  639. }
  640. } else if (v.channel >= ISO_CHANNELS) {
  641. PRINT(KERN_ERR, ohci->host->id,
  642. "Iso channel %d out of bounds", v.channel);
  643. return -EINVAL;
  644. } else {
  645. mask = (u64)0x1<<v.channel;
  646. }
  647. PRINT(KERN_INFO, ohci->host->id, "mask: %08X%08X usage: %08X%08X\n",
  648. (u32)(mask>>32),(u32)(mask&0xffffffff),
  649. (u32)(ohci->ISO_channel_usage>>32),
  650. (u32)(ohci->ISO_channel_usage&0xffffffff));
  651. if (ohci->ISO_channel_usage & mask) {
  652. PRINT(KERN_ERR, ohci->host->id,
  653. "Channel %d is already taken", v.channel);
  654. return -EBUSY;
  655. }
  656. if (v.buf_size == 0 || v.buf_size > VIDEO1394_MAX_SIZE) {
  657. PRINT(KERN_ERR, ohci->host->id,
  658. "Invalid %d length buffer requested",v.buf_size);
  659. return -EINVAL;
  660. }
  661. if (v.nb_buffers == 0 || v.nb_buffers > VIDEO1394_MAX_SIZE) {
  662. PRINT(KERN_ERR, ohci->host->id,
  663. "Invalid %d buffers requested",v.nb_buffers);
  664. return -EINVAL;
  665. }
  666. if (v.nb_buffers * v.buf_size > VIDEO1394_MAX_SIZE) {
  667. PRINT(KERN_ERR, ohci->host->id,
  668. "%d buffers of size %d bytes is too big",
  669. v.nb_buffers, v.buf_size);
  670. return -EINVAL;
  671. }
  672. if (cmd == VIDEO1394_IOC_LISTEN_CHANNEL) {
  673. d = alloc_dma_iso_ctx(ohci, OHCI_ISO_RECEIVE,
  674. v.nb_buffers, v.buf_size,
  675. v.channel, 0);
  676. if (d == NULL) {
  677. PRINT(KERN_ERR, ohci->host->id,
  678. "Couldn't allocate ir context");
  679. return -EAGAIN;
  680. }
  681. initialize_dma_ir_ctx(d, v.sync_tag, v.flags);
  682. ctx->current_ctx = d;
  683. v.buf_size = d->buf_size;
  684. list_add_tail(&d->link, &ctx->context_list);
  685. PRINT(KERN_INFO, ohci->host->id,
  686. "iso context %d listen on channel %d",
  687. d->ctx, v.channel);
  688. }
  689. else {
  690. d = alloc_dma_iso_ctx(ohci, OHCI_ISO_TRANSMIT,
  691. v.nb_buffers, v.buf_size,
  692. v.channel, v.packet_size);
  693. if (d == NULL) {
  694. PRINT(KERN_ERR, ohci->host->id,
  695. "Couldn't allocate it context");
  696. return -EAGAIN;
  697. }
  698. initialize_dma_it_ctx(d, v.sync_tag,
  699. v.syt_offset, v.flags);
  700. ctx->current_ctx = d;
  701. v.buf_size = d->buf_size;
  702. list_add_tail(&d->link, &ctx->context_list);
  703. PRINT(KERN_INFO, ohci->host->id,
  704. "Iso context %d talk on channel %d", d->ctx,
  705. v.channel);
  706. }
  707. if (copy_to_user((void *)arg, &v, sizeof(v))) {
  708. /* FIXME : free allocated dma resources */
  709. return -EFAULT;
  710. }
  711. ohci->ISO_channel_usage |= mask;
  712. return 0;
  713. }
  714. case VIDEO1394_IOC_UNLISTEN_CHANNEL:
  715. case VIDEO1394_IOC_UNTALK_CHANNEL:
  716. {
  717. int channel;
  718. u64 mask;
  719. struct dma_iso_ctx *d;
  720. if (copy_from_user(&channel, argp, sizeof(int)))
  721. return -EFAULT;
  722. if (channel < 0 || channel >= ISO_CHANNELS) {
  723. PRINT(KERN_ERR, ohci->host->id,
  724. "Iso channel %d out of bound", channel);
  725. return -EINVAL;
  726. }
  727. mask = (u64)0x1<<channel;
  728. if (!(ohci->ISO_channel_usage & mask)) {
  729. PRINT(KERN_ERR, ohci->host->id,
  730. "Channel %d is not being used", channel);
  731. return -ESRCH;
  732. }
  733. /* Mark this channel as unused */
  734. ohci->ISO_channel_usage &= ~mask;
  735. if (cmd == VIDEO1394_IOC_UNLISTEN_CHANNEL)
  736. d = find_ctx(&ctx->context_list, OHCI_ISO_RECEIVE, channel);
  737. else
  738. d = find_ctx(&ctx->context_list, OHCI_ISO_TRANSMIT, channel);
  739. if (d == NULL) return -ESRCH;
  740. PRINT(KERN_INFO, ohci->host->id, "Iso context %d "
  741. "stop talking on channel %d", d->ctx, channel);
  742. free_dma_iso_ctx(d);
  743. return 0;
  744. }
  745. case VIDEO1394_IOC_LISTEN_QUEUE_BUFFER:
  746. {
  747. struct video1394_wait v;
  748. struct dma_iso_ctx *d;
  749. if (copy_from_user(&v, argp, sizeof(v)))
  750. return -EFAULT;
  751. d = find_ctx(&ctx->context_list, OHCI_ISO_RECEIVE, v.channel);
  752. if (d == NULL) return -EFAULT;
  753. if ((v.buffer<0) || (v.buffer>d->num_desc)) {
  754. PRINT(KERN_ERR, ohci->host->id,
  755. "Buffer %d out of range",v.buffer);
  756. return -EINVAL;
  757. }
  758. spin_lock_irqsave(&d->lock,flags);
  759. if (d->buffer_status[v.buffer]==VIDEO1394_BUFFER_QUEUED) {
  760. PRINT(KERN_ERR, ohci->host->id,
  761. "Buffer %d is already used",v.buffer);
  762. spin_unlock_irqrestore(&d->lock,flags);
  763. return -EBUSY;
  764. }
  765. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_QUEUED;
  766. if (d->last_buffer>=0)
  767. d->ir_prg[d->last_buffer][d->nb_cmd-1].branchAddress =
  768. cpu_to_le32((dma_prog_region_offset_to_bus(&d->prg_reg[v.buffer], 0)
  769. & 0xfffffff0) | 0x1);
  770. d->last_buffer = v.buffer;
  771. d->ir_prg[d->last_buffer][d->nb_cmd-1].branchAddress = 0;
  772. spin_unlock_irqrestore(&d->lock,flags);
  773. if (!(reg_read(ohci, d->ctrlSet) & 0x8000))
  774. {
  775. DBGMSG(ohci->host->id, "Starting iso DMA ctx=%d",d->ctx);
  776. /* Tell the controller where the first program is */
  777. reg_write(ohci, d->cmdPtr,
  778. dma_prog_region_offset_to_bus(&d->prg_reg[v.buffer], 0) | 0x1);
  779. /* Run IR context */
  780. reg_write(ohci, d->ctrlSet, 0x8000);
  781. }
  782. else {
  783. /* Wake up dma context if necessary */
  784. if (!(reg_read(ohci, d->ctrlSet) & 0x400)) {
  785. PRINT(KERN_INFO, ohci->host->id,
  786. "Waking up iso dma ctx=%d", d->ctx);
  787. reg_write(ohci, d->ctrlSet, 0x1000);
  788. }
  789. }
  790. return 0;
  791. }
  792. case VIDEO1394_IOC_LISTEN_WAIT_BUFFER:
  793. case VIDEO1394_IOC_LISTEN_POLL_BUFFER:
  794. {
  795. struct video1394_wait v;
  796. struct dma_iso_ctx *d;
  797. int i;
  798. if (copy_from_user(&v, argp, sizeof(v)))
  799. return -EFAULT;
  800. d = find_ctx(&ctx->context_list, OHCI_ISO_RECEIVE, v.channel);
  801. if (d == NULL) return -EFAULT;
  802. if ((v.buffer<0) || (v.buffer>d->num_desc)) {
  803. PRINT(KERN_ERR, ohci->host->id,
  804. "Buffer %d out of range",v.buffer);
  805. return -EINVAL;
  806. }
  807. /*
  808. * I change the way it works so that it returns
  809. * the last received frame.
  810. */
  811. spin_lock_irqsave(&d->lock, flags);
  812. switch(d->buffer_status[v.buffer]) {
  813. case VIDEO1394_BUFFER_READY:
  814. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_FREE;
  815. break;
  816. case VIDEO1394_BUFFER_QUEUED:
  817. if (cmd == VIDEO1394_IOC_LISTEN_POLL_BUFFER) {
  818. /* for polling, return error code EINTR */
  819. spin_unlock_irqrestore(&d->lock, flags);
  820. return -EINTR;
  821. }
  822. spin_unlock_irqrestore(&d->lock, flags);
  823. wait_event_interruptible(d->waitq,
  824. video1394_buffer_state(d, v.buffer) ==
  825. VIDEO1394_BUFFER_READY);
  826. if (signal_pending(current))
  827. return -EINTR;
  828. spin_lock_irqsave(&d->lock, flags);
  829. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_FREE;
  830. break;
  831. default:
  832. PRINT(KERN_ERR, ohci->host->id,
  833. "Buffer %d is not queued",v.buffer);
  834. spin_unlock_irqrestore(&d->lock, flags);
  835. return -ESRCH;
  836. }
  837. /* set time of buffer */
  838. v.filltime = d->buffer_time[v.buffer];
  839. // printk("Buffer %d time %d\n", v.buffer, (d->buffer_time[v.buffer]).tv_usec);
  840. /*
  841. * Look ahead to see how many more buffers have been received
  842. */
  843. i=0;
  844. while (d->buffer_status[(v.buffer+1)%d->num_desc]==
  845. VIDEO1394_BUFFER_READY) {
  846. v.buffer=(v.buffer+1)%d->num_desc;
  847. i++;
  848. }
  849. spin_unlock_irqrestore(&d->lock, flags);
  850. v.buffer=i;
  851. if (copy_to_user(argp, &v, sizeof(v)))
  852. return -EFAULT;
  853. return 0;
  854. }
  855. case VIDEO1394_IOC_TALK_QUEUE_BUFFER:
  856. {
  857. struct video1394_wait v;
  858. unsigned int *psizes = NULL;
  859. struct dma_iso_ctx *d;
  860. if (copy_from_user(&v, argp, sizeof(v)))
  861. return -EFAULT;
  862. d = find_ctx(&ctx->context_list, OHCI_ISO_TRANSMIT, v.channel);
  863. if (d == NULL) return -EFAULT;
  864. if ((v.buffer<0) || (v.buffer>d->num_desc)) {
  865. PRINT(KERN_ERR, ohci->host->id,
  866. "Buffer %d out of range",v.buffer);
  867. return -EINVAL;
  868. }
  869. if (d->flags & VIDEO1394_VARIABLE_PACKET_SIZE) {
  870. int buf_size = d->nb_cmd * sizeof(unsigned int);
  871. struct video1394_queue_variable __user *p = argp;
  872. unsigned int __user *qv;
  873. if (get_user(qv, &p->packet_sizes))
  874. return -EFAULT;
  875. psizes = kmalloc(buf_size, GFP_KERNEL);
  876. if (!psizes)
  877. return -ENOMEM;
  878. if (copy_from_user(psizes, qv, buf_size)) {
  879. kfree(psizes);
  880. return -EFAULT;
  881. }
  882. }
  883. spin_lock_irqsave(&d->lock,flags);
  884. if (d->buffer_status[v.buffer]!=VIDEO1394_BUFFER_FREE) {
  885. PRINT(KERN_ERR, ohci->host->id,
  886. "Buffer %d is already used",v.buffer);
  887. spin_unlock_irqrestore(&d->lock,flags);
  888. if (psizes)
  889. kfree(psizes);
  890. return -EBUSY;
  891. }
  892. if (d->flags & VIDEO1394_VARIABLE_PACKET_SIZE) {
  893. initialize_dma_it_prg_var_packet_queue(
  894. d, v.buffer, psizes,
  895. ohci);
  896. }
  897. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_QUEUED;
  898. if (d->last_buffer >= 0) {
  899. d->it_prg[d->last_buffer]
  900. [ d->last_used_cmd[d->last_buffer] ].end.branchAddress =
  901. cpu_to_le32((dma_prog_region_offset_to_bus(&d->prg_reg[v.buffer],
  902. 0) & 0xfffffff0) | 0x3);
  903. d->it_prg[d->last_buffer]
  904. [ d->last_used_cmd[d->last_buffer] ].begin.branchAddress =
  905. cpu_to_le32((dma_prog_region_offset_to_bus(&d->prg_reg[v.buffer],
  906. 0) & 0xfffffff0) | 0x3);
  907. d->next_buffer[d->last_buffer] = v.buffer;
  908. }
  909. d->last_buffer = v.buffer;
  910. d->next_buffer[d->last_buffer] = -1;
  911. d->it_prg[d->last_buffer][d->last_used_cmd[d->last_buffer]].end.branchAddress = 0;
  912. spin_unlock_irqrestore(&d->lock,flags);
  913. if (!(reg_read(ohci, d->ctrlSet) & 0x8000))
  914. {
  915. DBGMSG(ohci->host->id, "Starting iso transmit DMA ctx=%d",
  916. d->ctx);
  917. put_timestamp(ohci, d, d->last_buffer);
  918. /* Tell the controller where the first program is */
  919. reg_write(ohci, d->cmdPtr,
  920. dma_prog_region_offset_to_bus(&d->prg_reg[v.buffer], 0) | 0x3);
  921. /* Run IT context */
  922. reg_write(ohci, d->ctrlSet, 0x8000);
  923. }
  924. else {
  925. /* Wake up dma context if necessary */
  926. if (!(reg_read(ohci, d->ctrlSet) & 0x400)) {
  927. PRINT(KERN_INFO, ohci->host->id,
  928. "Waking up iso transmit dma ctx=%d",
  929. d->ctx);
  930. put_timestamp(ohci, d, d->last_buffer);
  931. reg_write(ohci, d->ctrlSet, 0x1000);
  932. }
  933. }
  934. if (psizes)
  935. kfree(psizes);
  936. return 0;
  937. }
  938. case VIDEO1394_IOC_TALK_WAIT_BUFFER:
  939. {
  940. struct video1394_wait v;
  941. struct dma_iso_ctx *d;
  942. if (copy_from_user(&v, argp, sizeof(v)))
  943. return -EFAULT;
  944. d = find_ctx(&ctx->context_list, OHCI_ISO_TRANSMIT, v.channel);
  945. if (d == NULL) return -EFAULT;
  946. if ((v.buffer<0) || (v.buffer>d->num_desc)) {
  947. PRINT(KERN_ERR, ohci->host->id,
  948. "Buffer %d out of range",v.buffer);
  949. return -EINVAL;
  950. }
  951. switch(d->buffer_status[v.buffer]) {
  952. case VIDEO1394_BUFFER_READY:
  953. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_FREE;
  954. return 0;
  955. case VIDEO1394_BUFFER_QUEUED:
  956. wait_event_interruptible(d->waitq,
  957. (d->buffer_status[v.buffer] == VIDEO1394_BUFFER_READY));
  958. if (signal_pending(current))
  959. return -EINTR;
  960. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_FREE;
  961. return 0;
  962. default:
  963. PRINT(KERN_ERR, ohci->host->id,
  964. "Buffer %d is not queued",v.buffer);
  965. return -ESRCH;
  966. }
  967. }
  968. default:
  969. return -ENOTTY;
  970. }
  971. }
  972. static long video1394_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
  973. {
  974. int err;
  975. lock_kernel();
  976. err = __video1394_ioctl(file, cmd, arg);
  977. unlock_kernel();
  978. return err;
  979. }
  980. /*
  981. * This maps the vmalloced and reserved buffer to user space.
  982. *
  983. * FIXME:
  984. * - PAGE_READONLY should suffice!?
  985. * - remap_pfn_range is kind of inefficient for page by page remapping.
  986. * But e.g. pte_alloc() does not work in modules ... :-(
  987. */
  988. static int video1394_mmap(struct file *file, struct vm_area_struct *vma)
  989. {
  990. struct file_ctx *ctx = (struct file_ctx *)file->private_data;
  991. int res = -EINVAL;
  992. lock_kernel();
  993. if (ctx->current_ctx == NULL) {
  994. PRINT(KERN_ERR, ctx->ohci->host->id, "Current iso context not set");
  995. } else
  996. res = dma_region_mmap(&ctx->current_ctx->dma, file, vma);
  997. unlock_kernel();
  998. return res;
  999. }
  1000. static int video1394_open(struct inode *inode, struct file *file)
  1001. {
  1002. int i = ieee1394_file_to_instance(file);
  1003. struct ti_ohci *ohci;
  1004. struct file_ctx *ctx;
  1005. ohci = hpsb_get_hostinfo_bykey(&video1394_highlevel, i);
  1006. if (ohci == NULL)
  1007. return -EIO;
  1008. ctx = kmalloc(sizeof(struct file_ctx), GFP_KERNEL);
  1009. if (ctx == NULL) {
  1010. PRINT(KERN_ERR, ohci->host->id, "Cannot malloc file_ctx");
  1011. return -ENOMEM;
  1012. }
  1013. memset(ctx, 0, sizeof(struct file_ctx));
  1014. ctx->ohci = ohci;
  1015. INIT_LIST_HEAD(&ctx->context_list);
  1016. ctx->current_ctx = NULL;
  1017. file->private_data = ctx;
  1018. return 0;
  1019. }
  1020. static int video1394_release(struct inode *inode, struct file *file)
  1021. {
  1022. struct file_ctx *ctx = (struct file_ctx *)file->private_data;
  1023. struct ti_ohci *ohci = ctx->ohci;
  1024. struct list_head *lh, *next;
  1025. u64 mask;
  1026. lock_kernel();
  1027. list_for_each_safe(lh, next, &ctx->context_list) {
  1028. struct dma_iso_ctx *d;
  1029. d = list_entry(lh, struct dma_iso_ctx, link);
  1030. mask = (u64) 1 << d->channel;
  1031. if (!(ohci->ISO_channel_usage & mask))
  1032. PRINT(KERN_ERR, ohci->host->id, "On release: Channel %d "
  1033. "is not being used", d->channel);
  1034. else
  1035. ohci->ISO_channel_usage &= ~mask;
  1036. PRINT(KERN_INFO, ohci->host->id, "On release: Iso %s context "
  1037. "%d stop listening on channel %d",
  1038. d->type == OHCI_ISO_RECEIVE ? "receive" : "transmit",
  1039. d->ctx, d->channel);
  1040. free_dma_iso_ctx(d);
  1041. }
  1042. kfree(ctx);
  1043. file->private_data = NULL;
  1044. unlock_kernel();
  1045. return 0;
  1046. }
  1047. #ifdef CONFIG_COMPAT
  1048. static long video1394_compat_ioctl(struct file *f, unsigned cmd, unsigned long arg);
  1049. #endif
  1050. static struct cdev video1394_cdev;
  1051. static struct file_operations video1394_fops=
  1052. {
  1053. .owner = THIS_MODULE,
  1054. .unlocked_ioctl = video1394_ioctl,
  1055. #ifdef CONFIG_COMPAT
  1056. .compat_ioctl = video1394_compat_ioctl,
  1057. #endif
  1058. .mmap = video1394_mmap,
  1059. .open = video1394_open,
  1060. .release = video1394_release
  1061. };
  1062. /*** HOTPLUG STUFF **********************************************************/
  1063. /*
  1064. * Export information about protocols/devices supported by this driver.
  1065. */
  1066. static struct ieee1394_device_id video1394_id_table[] = {
  1067. {
  1068. .match_flags = IEEE1394_MATCH_SPECIFIER_ID | IEEE1394_MATCH_VERSION,
  1069. .specifier_id = CAMERA_UNIT_SPEC_ID_ENTRY & 0xffffff,
  1070. .version = CAMERA_SW_VERSION_ENTRY & 0xffffff
  1071. },
  1072. {
  1073. .match_flags = IEEE1394_MATCH_SPECIFIER_ID | IEEE1394_MATCH_VERSION,
  1074. .specifier_id = CAMERA_UNIT_SPEC_ID_ENTRY & 0xffffff,
  1075. .version = (CAMERA_SW_VERSION_ENTRY + 1) & 0xffffff
  1076. },
  1077. {
  1078. .match_flags = IEEE1394_MATCH_SPECIFIER_ID | IEEE1394_MATCH_VERSION,
  1079. .specifier_id = CAMERA_UNIT_SPEC_ID_ENTRY & 0xffffff,
  1080. .version = (CAMERA_SW_VERSION_ENTRY + 2) & 0xffffff
  1081. },
  1082. { }
  1083. };
  1084. MODULE_DEVICE_TABLE(ieee1394, video1394_id_table);
  1085. static struct hpsb_protocol_driver video1394_driver = {
  1086. .name = "1394 Digital Camera Driver",
  1087. .id_table = video1394_id_table,
  1088. .driver = {
  1089. .name = VIDEO1394_DRIVER_NAME,
  1090. .bus = &ieee1394_bus_type,
  1091. },
  1092. };
  1093. static void video1394_add_host (struct hpsb_host *host)
  1094. {
  1095. struct ti_ohci *ohci;
  1096. int minor;
  1097. /* We only work with the OHCI-1394 driver */
  1098. if (strcmp(host->driver->name, OHCI1394_DRIVER_NAME))
  1099. return;
  1100. ohci = (struct ti_ohci *)host->hostdata;
  1101. if (!hpsb_create_hostinfo(&video1394_highlevel, host, 0)) {
  1102. PRINT(KERN_ERR, ohci->host->id, "Cannot allocate hostinfo");
  1103. return;
  1104. }
  1105. hpsb_set_hostinfo(&video1394_highlevel, host, ohci);
  1106. hpsb_set_hostinfo_key(&video1394_highlevel, host, ohci->host->id);
  1107. minor = IEEE1394_MINOR_BLOCK_VIDEO1394 * 16 + ohci->host->id;
  1108. class_simple_device_add(hpsb_protocol_class, MKDEV(
  1109. IEEE1394_MAJOR, minor),
  1110. NULL, "%s-%d", VIDEO1394_DRIVER_NAME, ohci->host->id);
  1111. devfs_mk_cdev(MKDEV(IEEE1394_MAJOR, minor),
  1112. S_IFCHR | S_IRUSR | S_IWUSR,
  1113. "%s/%d", VIDEO1394_DRIVER_NAME, ohci->host->id);
  1114. }
  1115. static void video1394_remove_host (struct hpsb_host *host)
  1116. {
  1117. struct ti_ohci *ohci = hpsb_get_hostinfo(&video1394_highlevel, host);
  1118. if (ohci) {
  1119. class_simple_device_remove(MKDEV(IEEE1394_MAJOR,
  1120. IEEE1394_MINOR_BLOCK_VIDEO1394 * 16 + ohci->host->id));
  1121. devfs_remove("%s/%d", VIDEO1394_DRIVER_NAME, ohci->host->id);
  1122. }
  1123. return;
  1124. }
  1125. static struct hpsb_highlevel video1394_highlevel = {
  1126. .name = VIDEO1394_DRIVER_NAME,
  1127. .add_host = video1394_add_host,
  1128. .remove_host = video1394_remove_host,
  1129. };
  1130. MODULE_AUTHOR("Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>");
  1131. MODULE_DESCRIPTION("driver for digital video on OHCI board");
  1132. MODULE_SUPPORTED_DEVICE(VIDEO1394_DRIVER_NAME);
  1133. MODULE_LICENSE("GPL");
  1134. #ifdef CONFIG_COMPAT
  1135. #define VIDEO1394_IOC32_LISTEN_QUEUE_BUFFER \
  1136. _IOW ('#', 0x12, struct video1394_wait32)
  1137. #define VIDEO1394_IOC32_LISTEN_WAIT_BUFFER \
  1138. _IOWR('#', 0x13, struct video1394_wait32)
  1139. #define VIDEO1394_IOC32_TALK_WAIT_BUFFER \
  1140. _IOW ('#', 0x17, struct video1394_wait32)
  1141. #define VIDEO1394_IOC32_LISTEN_POLL_BUFFER \
  1142. _IOWR('#', 0x18, struct video1394_wait32)
  1143. struct video1394_wait32 {
  1144. u32 channel;
  1145. u32 buffer;
  1146. struct compat_timeval filltime;
  1147. };
  1148. static int video1394_wr_wait32(struct file *file, unsigned int cmd, unsigned long arg)
  1149. {
  1150. struct video1394_wait32 __user *argp = (void __user *)arg;
  1151. struct video1394_wait32 wait32;
  1152. struct video1394_wait wait;
  1153. mm_segment_t old_fs;
  1154. int ret;
  1155. if (copy_from_user(&wait32, argp, sizeof(wait32)))
  1156. return -EFAULT;
  1157. wait.channel = wait32.channel;
  1158. wait.buffer = wait32.buffer;
  1159. wait.filltime.tv_sec = (time_t)wait32.filltime.tv_sec;
  1160. wait.filltime.tv_usec = (suseconds_t)wait32.filltime.tv_usec;
  1161. old_fs = get_fs();
  1162. set_fs(KERNEL_DS);
  1163. if (cmd == VIDEO1394_IOC32_LISTEN_WAIT_BUFFER)
  1164. ret = video1394_ioctl(file,
  1165. VIDEO1394_IOC_LISTEN_WAIT_BUFFER,
  1166. (unsigned long) &wait);
  1167. else
  1168. ret = video1394_ioctl(file,
  1169. VIDEO1394_IOC_LISTEN_POLL_BUFFER,
  1170. (unsigned long) &wait);
  1171. set_fs(old_fs);
  1172. if (!ret) {
  1173. wait32.channel = wait.channel;
  1174. wait32.buffer = wait.buffer;
  1175. wait32.filltime.tv_sec = (int)wait.filltime.tv_sec;
  1176. wait32.filltime.tv_usec = (int)wait.filltime.tv_usec;
  1177. if (copy_to_user(argp, &wait32, sizeof(wait32)))
  1178. ret = -EFAULT;
  1179. }
  1180. return ret;
  1181. }
  1182. static int video1394_w_wait32(struct file *file, unsigned int cmd, unsigned long arg)
  1183. {
  1184. struct video1394_wait32 wait32;
  1185. struct video1394_wait wait;
  1186. mm_segment_t old_fs;
  1187. int ret;
  1188. if (copy_from_user(&wait32, (void __user *)arg, sizeof(wait32)))
  1189. return -EFAULT;
  1190. wait.channel = wait32.channel;
  1191. wait.buffer = wait32.buffer;
  1192. wait.filltime.tv_sec = (time_t)wait32.filltime.tv_sec;
  1193. wait.filltime.tv_usec = (suseconds_t)wait32.filltime.tv_usec;
  1194. old_fs = get_fs();
  1195. set_fs(KERNEL_DS);
  1196. if (cmd == VIDEO1394_IOC32_LISTEN_QUEUE_BUFFER)
  1197. ret = video1394_ioctl(file,
  1198. VIDEO1394_IOC_LISTEN_QUEUE_BUFFER,
  1199. (unsigned long) &wait);
  1200. else
  1201. ret = video1394_ioctl(file,
  1202. VIDEO1394_IOC_TALK_WAIT_BUFFER,
  1203. (unsigned long) &wait);
  1204. set_fs(old_fs);
  1205. return ret;
  1206. }
  1207. static int video1394_queue_buf32(struct file *file, unsigned int cmd, unsigned long arg)
  1208. {
  1209. return -EFAULT; /* ??? was there before. */
  1210. return video1394_ioctl(file,
  1211. VIDEO1394_IOC_TALK_QUEUE_BUFFER, arg);
  1212. }
  1213. static long video1394_compat_ioctl(struct file *f, unsigned cmd, unsigned long arg)
  1214. {
  1215. switch (cmd) {
  1216. case VIDEO1394_IOC_LISTEN_CHANNEL:
  1217. case VIDEO1394_IOC_UNLISTEN_CHANNEL:
  1218. case VIDEO1394_IOC_TALK_CHANNEL:
  1219. case VIDEO1394_IOC_UNTALK_CHANNEL:
  1220. return video1394_ioctl(f, cmd, arg);
  1221. case VIDEO1394_IOC32_LISTEN_QUEUE_BUFFER:
  1222. return video1394_w_wait32(f, cmd, arg);
  1223. case VIDEO1394_IOC32_LISTEN_WAIT_BUFFER:
  1224. return video1394_wr_wait32(f, cmd, arg);
  1225. case VIDEO1394_IOC_TALK_QUEUE_BUFFER:
  1226. return video1394_queue_buf32(f, cmd, arg);
  1227. case VIDEO1394_IOC32_TALK_WAIT_BUFFER:
  1228. return video1394_w_wait32(f, cmd, arg);
  1229. case VIDEO1394_IOC32_LISTEN_POLL_BUFFER:
  1230. return video1394_wr_wait32(f, cmd, arg);
  1231. default:
  1232. return -ENOIOCTLCMD;
  1233. }
  1234. }
  1235. #endif /* CONFIG_COMPAT */
  1236. static void __exit video1394_exit_module (void)
  1237. {
  1238. hpsb_unregister_protocol(&video1394_driver);
  1239. hpsb_unregister_highlevel(&video1394_highlevel);
  1240. devfs_remove(VIDEO1394_DRIVER_NAME);
  1241. cdev_del(&video1394_cdev);
  1242. PRINT_G(KERN_INFO, "Removed " VIDEO1394_DRIVER_NAME " module");
  1243. }
  1244. static int __init video1394_init_module (void)
  1245. {
  1246. int ret;
  1247. cdev_init(&video1394_cdev, &video1394_fops);
  1248. video1394_cdev.owner = THIS_MODULE;
  1249. kobject_set_name(&video1394_cdev.kobj, VIDEO1394_DRIVER_NAME);
  1250. ret = cdev_add(&video1394_cdev, IEEE1394_VIDEO1394_DEV, 16);
  1251. if (ret) {
  1252. PRINT_G(KERN_ERR, "video1394: unable to get minor device block");
  1253. return ret;
  1254. }
  1255. devfs_mk_dir(VIDEO1394_DRIVER_NAME);
  1256. hpsb_register_highlevel(&video1394_highlevel);
  1257. ret = hpsb_register_protocol(&video1394_driver);
  1258. if (ret) {
  1259. PRINT_G(KERN_ERR, "video1394: failed to register protocol");
  1260. hpsb_unregister_highlevel(&video1394_highlevel);
  1261. devfs_remove(VIDEO1394_DRIVER_NAME);
  1262. cdev_del(&video1394_cdev);
  1263. return ret;
  1264. }
  1265. PRINT_G(KERN_INFO, "Installed " VIDEO1394_DRIVER_NAME " module");
  1266. return 0;
  1267. }
  1268. module_init(video1394_init_module);
  1269. module_exit(video1394_exit_module);
  1270. MODULE_ALIAS_CHARDEV(IEEE1394_MAJOR, IEEE1394_MINOR_BLOCK_VIDEO1394 * 16);